Gallium oxide epitaxial wafer and method for manufacturing the same

Abstract

A gallium oxide epitaxial wafer and a manufacturing method thereof, the gallium oxide epitaxial wafer comprising, from bottom to top, a gallium oxide substrate, a non-intentionally doped pressure transition grown gallium oxide buffer layer, a stack structure, and a second doped gallium oxide epitaxial layer; wherein the stack structure comprises a group of stacks or a plurality of groups of stacks arranged in a stack, and each group of stacks comprises, from bottom to top, a first doped gallium oxide layer and a non-intentionally doped gallium oxide layer. The application can effectively solve the problem of the peak value of doped atoms between the gallium oxide substrate and the gallium oxide epitaxial layer, significantly improve the large leakage current phenomenon of the gallium oxide-based device, greatly reduce the failure risk of the gallium oxide-based device, and provide a solid guarantee for preparing a high-performance and high-stability gallium oxide-based device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a gallium oxide epitaxial wafer and a method for manufacturing the same. Background Technology

[0002] In the field of semiconductor materials, fourth-generation β-Ga2O3 ultrawide bandgap semiconductor materials have shown great application potential in high-voltage power devices and solar-blind photodetectors due to their superior performance. It possesses an ultrawide bandgap of approximately 4.9 eV and a bandwidth of approximately 100-300 cm⁻¹. 2 It exhibits an electron mobility of / Vs (300K), a breakdown field strength of 8MV / cm, a high Baliga value of 3214, and good chemical stability.

[0003] To leverage the material properties of β-Ga2O3 and apply it to ultra-high voltage power devices, the first step is to epitaxially grow high-quality epitaxial wafers with low defect density, low background doping concentration, and high electron mobility on β-Ga2O3 substrates. The second step is to process the prepared epitaxial wafers into products using device fabrication and packaging processes.

[0004] Currently, there are various methods for epitaxial growth of β-Ga2O3, including MOCVD (metal-organic chemical vapor deposition), MBE (molecular beam epitaxy), and HVPE (hydride vapor phase epitaxy). However, MBE technology suffers from slow epitaxial growth rates, resulting in low efficiency for large-scale production and making it difficult to meet industrialization needs. While HVPE technology has certain advantages, it suffers from poor uniformity in epitaxial layer thickness, poor doping uniformity, and poor surface roughness, which severely limit its application in industrial production. In contrast, MOCVD technology offers significant advantages such as fast growth rate, relatively low cost per wafer, good epitaxial layer uniformity, and the ability to achieve large-scale mass production, making it the ideal choice for β-Ga2O3 epitaxial growth.

[0005] However, to apply MOCVD-grown epitaxial wafers to horizontal devices, a key challenge must be solved—the Si atom peak problem at the interface between the gallium oxide substrate and the β-Ga2O3 epitaxial layer. This problem leads to excessive leakage current in the device, ultimately causing device failure and severely hindering the development and application of related technologies. Summary of the Invention

[0006] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To address the existing problems, this application provides a gallium oxide epitaxial wafer, which, from bottom to top, comprises: a gallium oxide substrate, an unintentionally doped gallium oxide buffer layer grown under transformer conditions, a stacked structure, and a second doped gallium oxide epitaxial layer;

[0008] The stacked structure includes a set of stacked layers or multiple sets of stacked layers, each set of stacked layers including a first doped gallium oxide layer and an unintentionally doped gallium oxide layer arranged from bottom to top.

[0009] In some embodiments of this application, when the stacked structure includes multiple sets of the stacked layers,

[0010] Along the bottom-up direction, the doping concentration of the first doped atom in the first doped gallium oxide layer of the later stack decreases compared to the doping concentration of the first doped atom in the first doped gallium oxide layer of the previous stack.

[0011] In some embodiments of this application, when the stacked structure includes multiple sets of the stacked layers,

[0012] Along the bottom-up direction, the thickness of the first doped gallium oxide layer in the later stack decreases compared to the thickness of the first doped gallium oxide layer in the previous stack.

[0013] In some embodiments of this application, when the stacked structure includes multiple sets of the stacked layers,

[0014] Along the bottom-up direction, the thickness of the unintentionally doped gallium oxide layer in the later stack increases compared to the thickness of the unintentionally doped gallium oxide layer in the previous stack.

[0015] In some embodiments of this application, the first doping includes nitrogen doping, and the second doping includes silicon doping.

[0016] In some embodiments of this application, the thickness of the gallium oxide buffer layer is 200 nm to 500 nm.

[0017] In another aspect, the present invention provides a method for manufacturing a gallium oxide epitaxial wafer, the method comprising:

[0018] Provide gallium oxide substrate;

[0019] An unintentionally doped, voltage-grown gallium oxide buffer layer is formed on the gallium oxide substrate;

[0020] A stacked structure is formed on the gallium oxide buffer layer; wherein the stacked structure includes a set of stacked layers or multiple sets of stacked layers, each set of stacked layers including a first doped gallium oxide layer and an unintentionally doped gallium oxide layer disposed from bottom to top;

[0021] A second doped gallium oxide epitaxial layer is formed on the stacked structure.

[0022] In some embodiments of this application, the gallium oxide buffer layer is formed using a first vapor deposition method, wherein the first vapor deposition method includes:

[0023] The pressure and temperature of the reaction chamber are set to a first pressure range and a first temperature range, respectively. A carrier gas, an oxygen source, and a gallium source are introduced into the reaction chamber. Vapor deposition is performed in a gradient pressure manner within the first pressure range to grow the gallium oxide buffer layer on the gallium oxide substrate.

[0024] The thickness of the gallium oxide buffer layer is 200nm to 500nm.

[0025] In some embodiments of this application, a second vapor deposition method is used multiple times to sequentially form each of the first doped gallium oxide layers in a plurality of sets of the stacked layers in a bottom-up direction;

[0026] The second vapor deposition method includes: setting the pressure of the reaction chamber to a second pressure range and the temperature to a second temperature range, introducing a carrier gas, an oxygen source, a gallium source and a first doping source into the reaction chamber, and performing vapor deposition to grow the first doped gallium oxide layer in the stack.

[0027] In this context, along the bottom-up direction, the doping concentration of the first doped gallium oxide layer in the first doped gallium oxide layer of the later stack is lower than the doping concentration of the first doped gallium oxide layer in the first stack, and / or the thickness of the first doped gallium oxide layer in the later stack is lower than the thickness of the first doped gallium oxide layer in the first stack.

[0028] In some embodiments of this application, a third vapor deposition method is used multiple times to sequentially form each of the unintentionally doped gallium oxide layers in multiple sets of the stack in a bottom-up direction;

[0029] The third vapor deposition method includes: setting the pressure of the reaction chamber to a third pressure range and the temperature to a third temperature range, introducing a carrier gas, an oxygen source and a gallium source into the reaction chamber, and performing vapor deposition to grow the unintentionally doped gallium oxide layer in the stack.

[0030] In this context, along the bottom-up direction, the thickness of the unintentionally doped gallium oxide layer in the later stack increases compared to the thickness of the unintentionally doped gallium oxide layer in the previous stack.

[0031] In some embodiments of this application, a fourth vapor deposition method is used to form the second-doped gallium oxide epitaxial layer, the fourth vapor deposition method comprising:

[0032] The pressure in the reaction chamber is set to a fourth pressure range and the temperature to a fourth temperature range. A carrier gas, an oxygen source, a gallium source, and a second doping source are introduced into the reaction chamber to perform vapor deposition in order to grow the second doped gallium oxide epitaxial layer.

[0033] The gallium oxide epitaxial wafer and its manufacturing method disclosed in this application, by setting an unintentionally doped gallium oxide buffer layer and a stacked structure between the gallium oxide substrate and the second doped gallium oxide epitaxial layer, wherein the stacked structure includes a set of stacked layers or multiple sets of stacked layers, each set of stacked layers including a first doped gallium oxide layer and an unintentionally doped gallium oxide layer arranged from bottom to top, can effectively solve the problem of doping atom peaks between the gallium oxide substrate and the gallium oxide epitaxial layer, significantly improve the phenomenon of large leakage current in gallium oxide-based devices, greatly reduce the failure risk of gallium oxide-based devices, and provide a solid guarantee for the preparation of high-performance and high-stability gallium oxide-based devices. Attached Figure Description

[0034] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0035] In the attached image:

[0036] Figure 1 A flowchart illustrating a method for manufacturing a gallium oxide epitaxial wafer according to a specific embodiment of this application is shown;

[0037] Figure 2A-2D This illustration shows a cross-sectional schematic diagram of a gallium oxide epitaxial wafer obtained by sequentially implementing a method for manufacturing a gallium oxide epitaxial wafer according to a specific embodiment of this application.

[0038] Figure 3 The diagram shows the pressure gradient variation during the first vapor deposition process. Detailed Implementation

[0039] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0040] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] In related technologies, there is a certain concentration of doped atom (e.g., Si atoms) peak at the interface between the gallium oxide substrate and the gallium oxide epitaxial layer. This can easily lead to excessive leakage current in gallium oxide-based devices, resulting in failure.

[0045] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing gallium oxide epitaxial wafers, such as... Figure 1 As shown, it mainly includes the following steps:

[0046] Step S1, provide a gallium oxide substrate;

[0047] Step S2: An unintentionally doped gallium oxide buffer layer grown by transformer is formed on the gallium oxide substrate;

[0048] Step S3: A stacked structure is formed on the gallium oxide buffer layer; wherein the stacked structure includes a set of stacked layers or multiple sets of stacked layers, each set of stacked layers including a first doped gallium oxide layer and an unintentionally doped gallium oxide layer disposed from bottom to top;

[0049] Step S4: A second doped gallium oxide epitaxial layer is formed on the stacked structure.

[0050] In this embodiment, an unintentionally doped GaO buffer layer and a stacked structure are formed between the GaO substrate and the second doped GaO epitaxial layer. The stacked structure includes a set of stacked layers or multiple sets of stacked layers. Each set of stacked layers includes a first doped GaO layer and an unintentionally doped GaO layer arranged from bottom to top. This effectively solves the problem of doping atom peaks between the GaO substrate and the GaO epitaxial layer, significantly improves the phenomenon of large leakage current in GaO-based devices, greatly reduces the failure risk of GaO-based devices, and provides a solid guarantee for the preparation of high-performance and high-stability GaO-based devices.

[0051] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0052] Example 1

[0053] Below, for reference Figure 1 , Figure 2A-2D The method for manufacturing gallium oxide epitaxial wafers according to this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for manufacturing a gallium oxide epitaxial wafer according to a specific embodiment of this application is shown; Figure 2A-2D This illustration shows a cross-sectional schematic diagram of a gallium oxide epitaxial wafer obtained by sequentially implementing a method for manufacturing a gallium oxide epitaxial wafer according to a specific embodiment of this application.

[0054] Exemplarily, the method for manufacturing a gallium oxide epitaxial wafer according to this application includes the following steps:

[0055] First, execute step S1, as follows: Figure 2A As shown, a gallium oxide substrate 210 is provided.

[0056] The gallium oxide substrate 210 can be any suitable crystal phase, such as β-Ga₂O₃, α-Ga₂O₃, γ-Ga₂O₃, and δ-Ga₂O₃, and is not limited thereto. Exemplarily, a gallium oxide substrate 210 with a β-Ga₂O₃ crystal phase is preferred. The β-Ga₂O₃ crystal phase is the most stable crystal phase of gallium oxide, possessing advantages such as high breakdown electric field strength, wide bandgap, and good chemical stability. Devices fabricated based on the β-Ga₂O₃ crystal phase gallium oxide substrate 210 can operate under extreme conditions such as high voltage, high power, and high temperature, exhibiting excellent performance and reliability.

[0057] For example, the gallium oxide substrate 210 can be a gallium oxide substrate with an Fe-doped semi-insulating (010) surface.

[0058] In some embodiments, prior to forming the gallium oxide buffer layer 220 on the gallium oxide substrate 210 as described below, a repair step on the gallium oxide substrate 210 is included. This repair step aims to eliminate mechanical damage to the gallium oxide substrate 210 generated during the processing and to remove organic contaminants from its surface, providing a higher quality substrate basis for subsequent epitaxial growth.

[0059] In some embodiments, repairing the gallium oxide substrate 210 may include the following steps S11 to S13:

[0060] Step S11: Place the gallium oxide substrate 210 in deionized water for ultrasonic treatment.

[0061] Ultrasonic treatment can remove particulate contaminants and residual dirt from the gallium oxide substrate 210 surface, which is beneficial for the subsequent epitaxial growth of the gallium oxide epitaxial layer 240. The duration of ultrasonic treatment of the gallium oxide substrate 210 in deionized water can be determined according to the actual situation and is not limited thereto. For example, the ultrasonic treatment time can be 10 min to 20 min.

[0062] Step S12: Dry the gallium oxide substrate 210 after ultrasonic treatment.

[0063] Specifically, the gallium oxide substrate 210 can be dried in a dust-free environment to prevent the surface of the gallium oxide substrate 210 from being contaminated with dust from the environment again, thus ensuring the cleanliness of the gallium oxide substrate 210 in subsequent processing.

[0064] Step S13: Place the dried gallium oxide substrate 210 in the reaction chamber, set the pressure of the reaction chamber to the fifth pressure range and the temperature to the fifth temperature range, and introduce a mixed gas of N2 and O2 into the reaction chamber to repair the gallium oxide substrate 210.

[0065] In actual operation, the gallium oxide substrate 210 can be placed in the reaction chamber of an MOCVD machine (different models of MOCVD machines can be selected to produce gallium oxide epitaxial wafers of different sizes, such as 6-inch, 8-inch, and 12-inch gallium oxide epitaxial wafers, depending on the diversity of actual needs). The temperature of the reaction chamber is raised to 900℃~1100℃, and the pressure of the reaction chamber is adjusted to 200mbar~500mbar. At the same time, a mixture of N2 and O2 gas is introduced into the reaction chamber, with the N2 to O2 flow rate ratio controlled between 5% and 30%. The purpose of this process is to repair mechanical damage caused during substrate processing and to remove organic contaminants from the substrate surface, creating favorable conditions for subsequent epitaxial processes.

[0066] Next, proceed to step S2, as follows: Figure 2B As shown, an unintentionally doped, voltage-grown gallium oxide buffer layer 220 is formed on a gallium oxide substrate 210.

[0067] In some embodiments, a first vapor deposition method may be used to form the gallium oxide buffer layer 220, wherein the first vapor deposition method includes:

[0068] The pressure and temperature of the reaction chamber are set to a first pressure range and a first temperature range, respectively. A carrier gas, an oxygen source, and a gallium source are introduced into the reaction chamber. Vapor deposition is performed in a gradient pressure manner within the first pressure range to grow a gallium oxide buffer layer 220 on the gallium oxide substrate 210.

[0069] The first pressure range can be 130 mbar to 480 mbar, the first temperature range can be 600℃ to 800℃, and the carrier gas can be high-purity nitrogen. 2、 The source gas can be high-purity Ar or a mixture of both, the oxygen source can be high-purity O2, and the gallium source can be trimethylgallium (TMGa) or triethylgallium (TEGa). The ratio of oxygen to gallium source can be 350–750, and the pressure interval of the gradient pressurization can be 50 mbar or any other suitable pressure value. For example, Figure 3 The diagram shows the pressure gradient variation with a pressure increase interval of 50 mbar.

[0070] In this embodiment, a gallium oxide buffer layer 220 with excellent crystal quality and unintentionally doped variable voltage growth can be formed using a gradient boosting method. This structure differs somewhat from the crystal structures of the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, creating an effect similar to an "isolation layer." Due to the unique crystal structure of the gallium oxide buffer layer 220, the diffusion coefficient of the second doped atoms therein is significantly different from that in the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240. This greatly reduces the diffusion efficiency of the second doped atoms between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, effectively reducing the aggregation of the second doped atoms at the interface and solving the problem of the peak value of the second doped atoms between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240.

[0071] In some embodiments, the thickness of the gallium oxide buffer layer 220 grown unintentionally by transformer is within a preset thickness range.

[0072] The gallium oxide buffer layer 220, with a predetermined thickness, plays a crucial role as a physical barrier. When dopants in the gallium oxide epitaxial layer 240 tend to diffuse towards the gallium oxide substrate 210, they need to cross this gallium oxide buffer layer 220 with a specific thickness. If the gallium oxide buffer layer 220 is too thin, it cannot effectively block the diffusion of dopants from the gallium oxide epitaxial layer 240 towards the gallium oxide substrate 210, making it difficult to resolve the dopant peak problem between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, ultimately affecting the electrical performance and stability of the device. Conversely, if the gallium oxide buffer layer 220 is too thick, it will introduce additional stress into the gallium oxide epitaxial layer 240. This stress will damage the crystal structure of the gallium oxide epitaxial layer 240, causing cracking and severely degrading the crystal quality, which is also detrimental to improving device performance. The buffer layer within the predetermined thickness range can significantly increase the difficulty of dopant diffusion and lengthen its diffusion path. In this process, the diffusion rate of most doped atoms will be greatly reduced, making it difficult for them to accumulate in large quantities and form peaks between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, thus effectively solving the doped atom peak problem.

[0073] In some embodiments, the preset thickness range is set to 200 nm to 500 nm. This means that in the structural design of gallium oxide epitaxial growth, an unintentionally doped gallium oxide buffer layer 220 with a thickness of 200 nm to 500 nm can be constructed between the gallium oxide substrate 210 and the second doped gallium oxide epitaxial layer 240. Of course, in practical applications, considering different process requirements, equipment conditions, and expected device performance, the thickness of the gallium oxide buffer layer 220 is not limited to this, and other suitable values ​​may exist, which are not explicitly limited here.

[0074] In this application, a gallium oxide buffer layer 220 with a preset thickness is grown by unintentional doping and pressure variation growth. The resulting gallium oxide buffer layer 220 has a high-quality crystal structure, and the half width of its crystal quality XRD rocking curve (RC) can be as small as less than 30 arcsec. In addition, the growth method with pressure from low to high also forms a good interface connection for the subsequent first doped gallium oxide layer, which is beneficial to the two-dimensional growth of the first doped gallium oxide layer.

[0075] Next, proceed to step S3, such as... Figure 2C As shown, a stacked structure 230 is formed on the gallium oxide buffer layer 220; wherein, the stacked structure 230 includes a set of stacked layers 231 or multiple sets of stacked layers 231 stacked together, each set of stacked layers 231 including a first doped gallium oxide layer and an unintentionally doped gallium oxide layer disposed from bottom to top.

[0076] In some embodiments, a second vapor deposition method may be used to form the first doped gallium oxide layer in the stack 231, wherein the second vapor deposition method includes:

[0077] The pressure and temperature of the reaction chamber are set to a second pressure range and a second temperature range, respectively. A carrier gas, an oxygen source, a gallium source, and a first doped source are introduced into the reaction chamber to perform vapor deposition in order to grow the first doped gallium oxide layer in the stack 231.

[0078] The second pressure range can be 250 mbar to 450 mbar, the second temperature range can be 700℃ to 1000℃, and the carrier gas can be high-purity nitrogen. 2、 High-purity Ar or a mixture of both gases can be used. The oxygen source can be high-purity O2, and the gallium source can be trimethylgallium (TMGa) or triethylgallium (TEGa). The ratio of oxygen source to gallium source can be 300 to 800. Taking N-type doping as an example, the first doping source can be N2O, etc.

[0079] When it is only necessary to form a stacked structure 230 including a set of stacked layers 231 on the gallium oxide buffer layer 220, the second vapor deposition method can be performed only once to form the first doped gallium oxide layer in the stacked layer 231; when it is necessary to form a stacked structure 230 including multiple sets of stacked layers 231 on the gallium oxide buffer layer 220, the second vapor deposition method can be performed multiple times to sequentially form each first doped gallium oxide layer in the multiple sets of stacked layers 231 in a bottom-up direction.

[0080] In some embodiments, an unintentionally doped gallium oxide layer in the stack 231 may be formed using a third vapor deposition method, wherein the third vapor deposition method includes:

[0081] The pressure and temperature of the reaction chamber are set to the third pressure range and the third temperature range, respectively. Carrier gas, oxygen source and gallium source are introduced into the reaction chamber to perform vapor deposition in order to grow an unintentionally doped gallium oxide layer in the stack 231.

[0082] The third pressure range can be 30 mbar to 100 mbar, the third temperature range can be 700℃ to 1000℃, and the carrier gas can be high-purity nitrogen. 2、 The oxygen source can be high-purity Ar or a mixture of the two gases, and the gallium source can be high-purity O2, etc. The ratio of oxygen source to gallium source can be 250 to 900.

[0083] When it is only necessary to form a stacked structure 230 including a set of stacked layers 231 on the gallium oxide buffer layer 220, the third vapor deposition method can be performed only once to form the unintentionally doped gallium oxide layer in the stacked layer 231; when it is necessary to form a stacked structure 230 including multiple sets of stacked layers 231 on the gallium oxide buffer layer 220, the third vapor deposition method can be performed multiple times to sequentially form each unintentionally doped gallium oxide layer in the multiple sets of stacked layers in a bottom-up direction.

[0084] By forming a stacked structure 230, which includes a set of stacked layers 231 or multiple sets of stacked layers 231, each set of stacked layers 231 includes a first doped gallium oxide layer and an unintentionally doped gallium oxide layer arranged from bottom to top. The first doped gallium oxide layer can serve as a compensation center to introduce a certain barrier height in the energy band, which can further solve the problem of the peak value of the second doped atom between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240 and the diffusion problem of the second doped atom in the subsequent barrier layer. Moreover, the design of the staggered stacking of the first doped gallium oxide layer and the unintentionally doped gallium oxide layer can form more interfaces to reduce the defect density and improve the crystal quality.

[0085] Taking a common material system as an example, when the gallium oxide substrate 210 is a β-Ga₂O₃ substrate, the unintentionally doped voltage-grown gallium oxide buffer layer 220 is specifically an unintentionally doped voltage-grown β-Ga₂O₃ buffer layer, the first doped gallium oxide layer in the stack 231 is a nitrogen (N) doped β-Ga₂O₃ layer, the unintentionally doped gallium oxide layer in the stack 231 is an unintentionally doped β-Ga₂O₃ layer, and the second doped gallium oxide epitaxial layer 240 is an N-type doped β-Ga₂O₃ epitaxial layer, and the second doped atom is a silicon (Si) atom, then an unintentionally doped voltage-grown β-Ga₂O₃ buffer layer and a silicon (Si) doped β-Ga₂O₃ epitaxial layer are set between the β-Ga₂O₃ substrate and the Si-doped β-Ga₂O₃ epitaxial layer. In the stacked structure 230, the β-Ga2O3 buffer layer can effectively block the diffusion of Si atoms from the N-type doped β-Ga2O3 epitaxial layer toward the β-Ga2O3 substrate, solving the problem of Si atom peaks between the substrate and the epitaxial layer. The nitrogen-doped β-Ga2O3 layer in the stacked structure 230 can act as a compensation center to introduce a barrier height of about 1.3 eV in the energy band, which can further solve the problem of Si atom peaks between the substrate and the epitaxial layer and the diffusion problem of Si atoms in the subsequent barrier layer. Moreover, the design of alternating stacking of nitrogen-doped β-Ga2O3 layers and unintentionally doped β-Ga2O3 layers in the stacked structure 230 can form more interfaces to reduce defect density and improve crystal quality.

[0086] In some embodiments, when the stacked structure 230 includes multiple stacked layers 231, the doping concentration of the first doped atom in the first doped gallium oxide layer of the later stacked layer 231 decreases compared to the doping concentration of the first doped atom in the first doped gallium oxide layer of the previous stacked layer 231 in the direction from bottom to top.

[0087] On the one hand, in this embodiment, by making the doping concentration of the first doped atoms in the multiple first doped gallium oxide layers in the stacked structure 230 decrease from bottom to top, a suitable potential barrier can be formed at different positions, which can more accurately suppress the influence of the second doped atoms, reduce device leakage current, and improve device reliability.

[0088] On the other hand, the gradient-decreasing doping concentration and the alternating growth of unintentionally doped layers result in more interfaces in the stacked structure 230. These interfaces can disperse and accommodate defects, thereby reducing the overall defect density of the epitaxial layer and improving crystal quality. For example, at the interface between the first doped gallium oxide layer with different doping concentrations and the unintentionally doped gallium oxide layer, the difference in atomic arrangement can alleviate lattice stress, reduce the generation and propagation of defects such as dislocations, and make the crystal structure of the epitaxial wafer more complete, which is beneficial to the realization of subsequent device characteristics.

[0089] On the other hand, the design of decreasing doping concentration of the first dopant atom from bottom to top can also optimize the band structure and carrier distribution. As the doping concentration of the first dopant atom decreases along the growth direction, the band structure changes accordingly. This change helps to adjust the carrier distribution, making the carrier concentration and migration characteristics in different regions more in line with the device's operating requirements. In regions close to the substrate, a higher nitrogen doping concentration can provide sufficient electrons to compensate for defects and impurities at the substrate-epitaxy layer interface, while in regions far from the substrate, a lower nitrogen doping concentration can reduce scattering effects on carrier migration, improve electron mobility, and thus enhance the device's electrical performance.

[0090] In some embodiments, when the stacked structure 230 includes multiple stacked layers 231, the thickness of the first doped gallium oxide layer in the later stacked layer 231 decreases compared to the thickness of the first doped gallium oxide layer in the previous stacked layer 231 in the direction from bottom to top.

[0091] On the one hand, by making the thickness of the multiple first-doped gallium oxide layers in the stacked structure 230 decrease from bottom to top, the thicker first-doped gallium oxide layer near the substrate can provide enough first-doped atoms to form a higher potential barrier to effectively block the diffusion of second-doped atoms at the interface between the substrate and the epitaxial layer; and as the growth direction advances, the subsequent thinner first-doped gallium oxide layer can still block the further diffusion of first-doped atoms to a certain extent, while avoiding the negative impact of overdoping on device performance.

[0092] On the other hand, the design of the multiple first-doped gallium oxide layers in the stacked structure 230, with their thickness decreasing from bottom to top, allows for the adjustment of carrier concentration and distribution. A thicker first-doped gallium oxide layer provides more carriers in the early stages of growth, meeting the carrier concentration requirements of specific regions. As growth progresses, the gradually decreasing thickness of the first-doped gallium oxide layers allows for fine-tuning of carrier distribution, resulting in a more rational distribution of carriers throughout the structure and optimizing the device's electrical performance. For example, in regions near the epitaxial layer, a thinner first-doped gallium oxide layer can reduce scattering of carrier migration in the channel, improving electron mobility and thus enhancing the device's switching speed and operating efficiency.

[0093] On the other hand, the thicker first-doped gallium oxide layer can withstand and release greater lattice stress in the early stages of growth. As the thickness gradually decreases, the stress accumulation between subsequent layers is relatively small, which helps the overall structure to better adapt to lattice changes, reduce the generation and propagation of crystal defects such as dislocations, and improve the crystal quality of the epitaxial layer.

[0094] In some embodiments, when the stacked structure 230 includes multiple stacked layers 231, the thickness of the unintentionally doped gallium oxide layer in the later stacked layer 231 increases relative to the thickness of the unintentionally doped gallium oxide layer in the previous stacked layer 231 in the bottom-up direction.

[0095] On the one hand, the design of increasing thickness of multiple unintentionally doped gallium oxide layers in the stacked structure 230 from bottom to top is beneficial for releasing lattice stress and promoting high-quality growth of gallium oxide epitaxial wafers. During epitaxial growth, lattice mismatch generates stress, which may lead to defects such as dislocations. The design of increasing thickness of multiple unintentionally doped gallium oxide layers can provide a larger buffer space for the structure to release stress in the later stages of growth, reduce defect generation and propagation, and improve crystal quality. Moreover, thicker unintentionally doped gallium oxide layers can provide a more stable interface and environment for subsequent layer growth. It allows atoms more time to diffuse and align on the surface, forming a more regular crystal structure, promoting high-quality growth of epitaxial layers, and making the epitaxial wafer surface smoother and more uniform.

[0096] On the other hand, the design of increasing thickness of multiple unintentionally doped gallium oxide layers in the stacked structure 230 from bottom to top is beneficial to improving carrier distribution. As the growth direction advances, thicker unintentionally doped gallium oxide layers can provide a wider impurity-free migration space for carriers. In the region near the epitaxial layer, thicker unintentionally doped gallium oxide layers can reduce impurity scattering, improve carrier mobility, enable faster device switching speed and higher operating efficiency, and achieve fine control of device electrical performance.

[0097] For example, Figure 2C The document provides a stacked structure 230 consisting of four sets of stacked layers 231. From bottom to top, the stacked structure 230 comprises, sequentially, a first doped gallium oxide layer 2311, an unintentionally doped first gallium oxide layer 2312, a first doped second gallium oxide layer 2313, an unintentionally doped second gallium oxide layer 2314, a first doped third gallium oxide layer 2315, an unintentionally doped third gallium oxide layer 2316, a first doped fourth gallium oxide layer 2317, and an unintentionally doped fourth gallium oxide layer 2318. The nitrogen doping concentration in the first doped gallium oxide layer 2311 is 1–5E+21 atoms / cm³. 3 The nitrogen doping concentration in the first doped gallium oxide layer 2313 is 1–5E+19 atoms / cm². 3 The nitrogen doping concentration in the first doped third gallium oxide 2315 layer is 1–5E+17 atoms / cm². 3 The nitrogen doping concentration in the first doped fourth gallium oxide layer 2317 is (1~5E+15 atoms / cm). 3)~(1~5E+16atoms / cm 3 This results in the doping concentration of the first doped atoms in the multiple first-doped gallium oxide layers in the stacked structure 230 decreasing along the growth direction; the thickness of the first doped gallium oxide layer 2311 can be 1.0 μm to 1.5 μm, with a preferred thickness of 1.25 μm; the thickness of the first doped second gallium oxide layer 2313 can be 0.75 μm to 1.25 μm, with a preferred thickness of 1.0 μm; the thickness of the first doped third gallium oxide layer 2315 can be 0.5 μm to 1.0 μm, with a preferred thickness of 0.75 μm; and the thickness of the first doped fourth gallium oxide layer 2317 can be 0.25 μm to 0.75 μm, with a preferred thickness of 0.5 μm, resulting in the doping concentration of the multiple first doped gallium oxide layers in the stacked structure 230 decreasing along the growth direction; the thickness of the first doped first gallium oxide layer 2311 can be 1.0 μm to 1.0 μm, with a preferred thickness of 0.75 μm; the thickness of the first doped fourth gallium oxide layer 2317 can be 0.25 μm to 0.75 μm, with a preferred thickness of 0.5 μm, resulting in the doping concentration of the multiple first doped gallium oxide layers in the stacked structure 230 decreasing along the growth direction. The thickness of the first doped gallium oxide layer decreases along the growth direction; the thickness of the unintentionally doped first gallium oxide layer 2312 can be 0.1um to 0.5um, with a preferred thickness of 0.3um; the thickness of the unintentionally doped second gallium oxide layer 2314 can be 0.35um to 0.75um, with a preferred thickness of 0.5um; the thickness of the unintentionally doped third gallium oxide layer 2316 can be 0.6um to 1.0um, with a preferred thickness of 0.8um; and the thickness of the unintentionally doped fourth gallium oxide layer 2318 can be 0.85um to 1.25um, with a preferred thickness of 1.0um, so that the thickness of the multiple unintentionally doped gallium oxide layers in the stacked structure 230 increases along the growth direction.

[0098] Next, proceed to step S4, such as... Figure 2D As shown, a second doped gallium oxide epitaxial layer 240 is formed on the stacked structure 230.

[0099] In some embodiments, a fourth vapor deposition method may be used to form the second doped gallium oxide epitaxial layer 240, wherein the fourth vapor deposition method includes:

[0100] The pressure in the reaction chamber is set to the fourth pressure range and the temperature to the fourth temperature range. A carrier gas, an oxygen source, a gallium source, and a second doped source are introduced into the reaction chamber to perform vapor deposition in order to grow a second doped gallium oxide epitaxial layer 240.

[0101] The fourth pressure range can be 30 mbar to 80 mbar, the fourth temperature range can be 700℃ to 900℃, the carrier gas can be high-purity N2, high-purity Ar or a mixture of the two, the oxygen source can be high-purity O2, the gallium source can be trimethylgallium (TMGa) or triethylgallium (TEGa), the ratio of oxygen source to gallium source can be 200 to 600, and taking N-type doping as an example, the second doping source can be TEOS or SiH4.

[0102] In some embodiments, the thickness of the gallium oxide epitaxial layer 240 grown by the second vapor deposition method can range from 0.5 μm to 1.5 μm, with a more preferred thickness of 1.0 μm. The Si atom doping concentration in the gallium oxide epitaxial layer 240 can be 5E+15 atoms / cm². 3 ~2E+16 atoms / cm 3 The preferred doping concentration of Si atoms is 8E+15 atoms / cm². 3 .

[0103] After growth is complete, the temperature of the reaction chamber is lowered to below 150°C to end the entire epitaxial growth process.

[0104] This concludes the description of the key steps in the method for manufacturing gallium oxide epitaxial wafers according to this application. The complete method for manufacturing gallium oxide epitaxial wafers may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0105] In summary, the manufacturing method of this application embodiment forms an unintentionally doped gallium oxide buffer layer 220 and a stacked structure 230 between the gallium oxide substrate 210 and the second doped gallium oxide epitaxial layer 240. The stacked structure 230 includes a set of stacked layers 231 or multiple sets of stacked layers 231 stacked together. Each set of stacked layers 231 includes a first doped gallium oxide layer and an unintentionally doped gallium oxide layer disposed from bottom to top. This effectively solves the problem of doping atom peaks between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, significantly improves the phenomenon of large leakage current in gallium oxide-based devices, greatly reduces the failure risk of gallium oxide-based devices, and provides a solid guarantee for the preparation of high-performance and high-stability gallium oxide-based devices.

[0106] Example 2

[0107] This application also provides a gallium oxide epitaxial wafer, as described below, with reference to... Figure 2D This application provides a detailed description and explanation of the gallium oxide epitaxial wafer.

[0108] Specifically, such as Figure 2D As shown, the gallium oxide epitaxial wafer includes, from bottom to top: a gallium oxide substrate 210, an unintentionally doped gallium oxide buffer layer 220 grown under transformer pressure, a stacked structure 230, and a second doped gallium oxide epitaxial layer 240; wherein, the stacked structure 230 includes a set of stacked layers 231 or multiple sets of stacked layers 231 stacked together, and each set of stacked layers 231 includes a first doped gallium oxide layer and an unintentionally doped gallium oxide layer disposed from bottom to top.

[0109] In this embodiment, by forming an unintentionally doped GaO buffer layer 220 and a stacked structure 230 between the GaO substrate 210 and the second doped GaO epitaxial layer 240, the stacked structure 230 includes a set of stacked layers 231 or multiple sets of stacked layers 231 stacked together. Each set of stacked layers 231 includes a first doped GaO layer and an unintentionally doped GaO layer arranged from bottom to top. This can effectively solve the problem of the second doped atom peak between the GaO substrate 210 and the GaO epitaxial layer 240, and avoid the situation where the leakage current of the GaO-based device is too large or even fails due to the poor distribution of doped atoms.

[0110] On the one hand, the gallium oxide buffer layer 220 grown unintentionally using transformers forms a structure with excellent crystal quality during the growth process. This structure differs somewhat from the crystal structures of the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, creating an effect similar to an "isolation layer." Due to the unique crystal structure of the gallium oxide buffer layer 220, the diffusion coefficient of the second doped atoms therein is significantly different from that in the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240. This greatly reduces the diffusion efficiency of the second doped atoms between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, effectively reducing the aggregation of the second doped atoms at the interface and solving the problem of the peak value of the second doped atoms between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240.

[0111] On the other hand, by setting up a stacked structure 230, which includes a set of stacked layers 231 or multiple sets of stacked layers 231 stacked together, each set of stacked layers 231 includes a first doped gallium oxide layer and an unintentionally doped gallium oxide layer arranged from bottom to top. The first doped gallium oxide layer can serve as a compensation center to introduce a certain barrier height in the energy band, which can further solve the problem of the peak value of the second doped atom between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240 and the diffusion problem of the second doped atom in the subsequent barrier layer. Moreover, the design of the staggered stacking of the first doped gallium oxide layer and the unintentionally doped gallium oxide layer can form more interfaces to reduce the defect density and improve the crystal quality.

[0112] Taking a common material system as an example, when the gallium oxide substrate 210 is a β-Ga₂O₃ substrate, the unintentionally doped voltage-grown gallium oxide buffer layer 220 is specifically an unintentionally doped voltage-grown β-Ga₂O₃ buffer layer, the first doped gallium oxide layer in the stack 231 is a nitrogen (N) doped β-Ga₂O₃ layer, the unintentionally doped gallium oxide layer in the stack 231 is an unintentionally doped β-Ga₂O₃ layer, and the second doped gallium oxide epitaxial layer 240 is an N-type doped β-Ga₂O₃ epitaxial layer, and the second doped atom is a silicon (Si) atom, then an unintentionally doped voltage-grown β-Ga₂O₃ buffer layer and a silicon (Si) doped β-Ga₂O₃ epitaxial layer are set between the β-Ga₂O₃ substrate and the Si-doped β-Ga₂O₃ epitaxial layer. In the stacked structure 230, the β-Ga2O3 buffer layer can effectively block the diffusion of Si atoms from the N-type doped β-Ga2O3 epitaxial layer toward the β-Ga2O3 substrate, solving the problem of Si atom peaks between the substrate and the epitaxial layer. The nitrogen-doped β-Ga2O3 layer in the stacked structure 230 can act as a compensation center to introduce a barrier height of about 1.3 eV in the energy band, which can further solve the problem of Si atom peaks between the substrate and the epitaxial layer and the diffusion problem of Si atoms in the subsequent barrier layer. Moreover, the design of alternating stacking of nitrogen-doped β-Ga2O3 layers and unintentionally doped β-Ga2O3 layers in the stacked structure 230 can form more interfaces to reduce defect density and improve crystal quality.

[0113] In some embodiments, during the gallium oxide epitaxial growth process, different crystal planes on the gallium oxide substrate 210 have a significant impact on the lattice matching degree between the gallium oxide epitaxial layer 240 and the substrate. A higher lattice matching degree means a lower defect density in the gallium oxide epitaxial layer 240 and higher crystal quality. Exemplarily, the crystal planes on the gallium oxide substrate 210 can be 010 crystal planes, etc., and are not limited thereto. Exemplarily, the gallium oxide substrate 210 can be an Fe-doped semi-insulating (010) plane gallium oxide substrate.

[0114] In some embodiments, the thickness of the gallium oxide buffer layer 220 grown unintentionally by transformer is within a preset thickness range.

[0115] The gallium oxide buffer layer 220, with a predetermined thickness, plays a crucial role as a physical barrier. When dopants in the gallium oxide epitaxial layer 240 tend to diffuse towards the gallium oxide substrate 210, they need to cross this gallium oxide buffer layer 220 with a specific thickness. If the gallium oxide buffer layer 220 is too thin, it cannot effectively block the diffusion of dopants from the gallium oxide epitaxial layer 240 towards the gallium oxide substrate 210, making it difficult to resolve the dopant peak problem between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, ultimately affecting the electrical performance and stability of the device. Conversely, if the gallium oxide buffer layer 220 is too thick, it will introduce additional stress into the gallium oxide epitaxial layer 240. This stress will damage the crystal structure of the gallium oxide epitaxial layer 240, causing cracking and severely degrading the crystal quality, which is also detrimental to improving device performance. The buffer layer within the predetermined thickness range can significantly increase the difficulty of dopant diffusion and lengthen its diffusion path. In this process, the diffusion rate of most doped atoms will be greatly reduced, making it difficult for them to accumulate in large quantities and form peaks between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, thus effectively solving the doped atom peak problem.

[0116] In some embodiments, the preset thickness range is set to 200 nm to 500 nm. This means that in the structural design of gallium oxide epitaxial growth, an unintentionally doped, transformer-grown gallium oxide buffer layer 220 with a thickness in the range of 200 nm to 500 nm can be constructed between the gallium oxide substrate 210 and the second doped gallium oxide epitaxial layer 240. Of course, in practical applications, considering different process requirements, equipment conditions, and expected device performance, the thickness of the gallium oxide buffer layer 220 is not limited to this, and other suitable values ​​may exist, which are not explicitly limited here.

[0117] In this application, a gallium oxide buffer layer 220 with a preset thickness is grown by unintentional doping and pressure variation growth. The resulting gallium oxide buffer layer 220 has a high-quality crystal structure, and the half width of its crystal quality XRD rocking curve (RC) can be as small as less than 30 arcsec. In addition, the growth method with pressure from low to high also forms a good interface connection for the subsequent first doped gallium oxide layer, which is beneficial to the two-dimensional growth of the first doped gallium oxide layer.

[0118] In some embodiments, when the stacked structure 230 includes multiple stacked layers 231, the doping concentration of the first doped atom in the first doped gallium oxide layer of the later stacked layer 231 decreases compared to the doping concentration of the first doped atom in the first doped gallium oxide layer of the previous stacked layer 231 in the direction from bottom to top.

[0119] On the one hand, in this embodiment, by making the doping concentration of the first doped atoms in the multiple first doped gallium oxide layers in the stacked structure 230 decrease from bottom to top, a suitable potential barrier can be formed at different positions, which can more accurately suppress the influence of the second doped atoms, reduce device leakage current, and improve device reliability.

[0120] On the other hand, the gradient-decreasing doping concentration and the alternating growth of unintentionally doped layers result in more interfaces in the stacked structure 230. These interfaces can disperse and accommodate defects, thereby reducing the overall defect density of the epitaxial layer and improving crystal quality. For example, at the interface between the first doped gallium oxide layer with different doping concentrations and the unintentionally doped gallium oxide layer, the difference in atomic arrangement can alleviate lattice stress, reduce the generation and propagation of defects such as dislocations, and make the crystal structure of the epitaxial wafer more complete, which is beneficial to the realization of subsequent device characteristics.

[0121] On the other hand, the design of decreasing doping concentration of the first dopant atom from bottom to top can also optimize the band structure and carrier distribution. As the doping concentration of the first dopant atom decreases along the growth direction, the band structure changes accordingly. This change helps to adjust the carrier distribution, making the carrier concentration and migration characteristics in different regions more in line with the device's operating requirements. In regions close to the substrate, a higher nitrogen doping concentration can provide sufficient electrons to compensate for defects and impurities at the substrate-epitaxy layer interface, while in regions far from the substrate, a lower nitrogen doping concentration can reduce scattering effects on carrier migration, improve electron mobility, and thus enhance the device's electrical performance.

[0122] In some embodiments, when the stacked structure 230 includes multiple stacked layers 231, the thickness of the first doped gallium oxide layer in the later stacked layer 231 decreases compared to the thickness of the first doped gallium oxide layer in the previous stacked layer 231 in the direction from bottom to top.

[0123] On the one hand, by making the thickness of the multiple first-doped gallium oxide layers in the stacked structure 230 decrease from bottom to top, the thicker first-doped gallium oxide layer near the substrate can provide enough first-doped atoms to form a higher potential barrier to effectively block the diffusion of second-doped atoms at the interface between the substrate and the epitaxial layer; and as the growth direction advances, the subsequent thinner first-doped gallium oxide layer can still block the further diffusion of first-doped atoms to a certain extent, while avoiding the negative impact of overdoping on device performance.

[0124] On the other hand, the design of the multiple first-doped gallium oxide layers in the stacked structure 230, with their thickness decreasing from bottom to top, allows for the adjustment of carrier concentration and distribution. A thicker first-doped gallium oxide layer provides more carriers in the early stages of growth, meeting the carrier concentration requirements of specific regions. As growth progresses, the gradually decreasing thickness of the first-doped gallium oxide layers allows for fine-tuning of carrier distribution, resulting in a more rational distribution of carriers throughout the structure and optimizing the device's electrical performance. For example, in regions near the epitaxial layer, a thinner first-doped gallium oxide layer can reduce scattering of carrier migration in the channel, improving electron mobility and thus enhancing the device's switching speed and operating efficiency.

[0125] On the other hand, the thicker first-doped gallium oxide layer can withstand and release greater lattice stress in the early stages of growth. As the thickness gradually decreases, the stress accumulation between subsequent layers is relatively small, which helps the overall structure to better adapt to lattice changes, reduce the generation and propagation of crystal defects such as dislocations, and improve the crystal quality of the epitaxial layer.

[0126] In some embodiments, when the stacked structure 230 includes multiple stacked layers 231, the thickness of the unintentionally doped gallium oxide layer in the later stacked layer 231 increases relative to the thickness of the unintentionally doped gallium oxide layer in the previous stacked layer 231 in the bottom-up direction.

[0127] On the one hand, the design of increasing thickness of multiple unintentionally doped gallium oxide layers in the stacked structure 230 from bottom to top is beneficial for releasing lattice stress and promoting high-quality growth of gallium oxide epitaxial wafers. During epitaxial growth, lattice mismatch generates stress, which may lead to defects such as dislocations. The design of increasing thickness of multiple unintentionally doped gallium oxide layers can provide a larger buffer space for the structure to release stress in the later stages of growth, reduce defect generation and propagation, and improve crystal quality. Moreover, thicker unintentionally doped gallium oxide layers can provide a more stable interface and environment for subsequent layer growth. It allows atoms more time to diffuse and align on the surface, forming a more regular crystal structure, promoting high-quality growth of epitaxial layers, and making the epitaxial wafer surface smoother and more uniform.

[0128] On the other hand, the design of increasing thickness of multiple unintentionally doped gallium oxide layers in the stacked structure 230 from bottom to top is beneficial to improving carrier distribution. As the growth direction advances, thicker unintentionally doped gallium oxide layers can provide a wider impurity-free migration space for carriers. In the region near the epitaxial layer, thicker unintentionally doped gallium oxide layers can reduce impurity scattering, improve carrier mobility, enable faster device switching speed and higher operating efficiency, and achieve fine control of device electrical performance.

[0129] For example, Figure 2CThe document provides a stacked structure 230 consisting of four sets of stacked layers 231. From bottom to top, the stacked structure 230 comprises, sequentially, a first doped gallium oxide layer 2311, an unintentionally doped first gallium oxide layer 2312, a first doped second gallium oxide layer 2313, an unintentionally doped second gallium oxide layer 2314, a first doped third gallium oxide layer 2315, an unintentionally doped third gallium oxide layer 2316, a first doped fourth gallium oxide layer 2317, and an unintentionally doped fourth gallium oxide layer 2318. The nitrogen doping concentration in the first doped gallium oxide layer 2311 is 1–5E+21 atoms / cm³. 3 The nitrogen doping concentration in the first doped gallium oxide layer 2313 is 1–5E+19 atoms / cm². 3 The nitrogen doping concentration in the first doped third gallium oxide 2315 layer is 1–5E+17 atoms / cm². 3 The nitrogen doping concentration in the first doped fourth gallium oxide layer 2317 is (1~5E+15 atoms / cm). 3 )~(1~5E+16atoms / cm 3 This results in the doping concentration of the first doped atoms in the multiple first-doped gallium oxide layers in the stacked structure 230 decreasing along the growth direction; the thickness of the first doped gallium oxide layer 2311 can be 1.0 μm to 1.5 μm, with a preferred thickness of 1.25 μm; the thickness of the first doped second gallium oxide layer 2313 can be 0.75 μm to 1.25 μm, with a preferred thickness of 1.0 μm; the thickness of the first doped third gallium oxide layer 2315 can be 0.5 μm to 1.0 μm, with a preferred thickness of 0.75 μm; and the thickness of the first doped fourth gallium oxide layer 2317 can be 0.25 μm to 0.75 μm, with a preferred thickness of 0.5 μm, resulting in the doping concentration of the multiple first doped gallium oxide layers in the stacked structure 230 decreasing along the growth direction; the thickness of the first doped first gallium oxide layer 2311 can be 1.0 μm to 1.0 μm, with a preferred thickness of 0.75 μm; the thickness of the first doped fourth gallium oxide layer 2317 can be 0.25 μm to 0.75 μm, with a preferred thickness of 0.5 μm, resulting in the doping concentration of the multiple first doped gallium oxide layers in the stacked structure 230 decreasing along the growth direction. The thickness of the first doped gallium oxide layer decreases along the growth direction; the thickness of the unintentionally doped first gallium oxide layer 2312 can be 0.1um to 0.5um, with a preferred thickness of 0.3um; the thickness of the unintentionally doped second gallium oxide layer 2314 can be 0.35um to 0.75um, with a preferred thickness of 0.5um; the thickness of the unintentionally doped third gallium oxide layer 2316 can be 0.6um to 1.0um, with a preferred thickness of 0.8um; and the thickness of the unintentionally doped fourth gallium oxide layer 2318 can be 0.85um to 1.25um, with a preferred thickness of 1.0um, so that the thickness of the multiple unintentionally doped gallium oxide layers in the stacked structure 230 increases along the growth direction.

[0130] It is understood that the gallium oxide epitaxial wafer in this embodiment can be manufactured by the method in the aforementioned embodiment one. In order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment one. For specific explanations and descriptions, please refer to the description in embodiment one.

[0131] According to the gallium oxide epitaxial wafer of this application, by setting an unintentionally doped gallium oxide buffer layer 220 and a stacked structure 230 between the gallium oxide substrate 210 and the second doped gallium oxide epitaxial layer 240, the stacked structure 230 includes a set of stacked layers 231 or multiple sets of stacked layers 231 stacked together. Each set of stacked layers 231 includes a first doped gallium oxide layer and an unintentionally doped gallium oxide layer arranged from bottom to top, thereby effectively solving the problem of doping atom peaks between the gallium oxide substrate 210 and the gallium oxide epitaxial layer 240, significantly improving the phenomenon of large leakage current in gallium oxide-based devices, greatly reducing the failure risk of gallium oxide-based devices, and providing a solid guarantee for the preparation of high-performance and high-stability gallium oxide-based devices.

[0132] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A gallium oxide epitaxial wafer, characterized in that, From bottom to top, it includes: gallium oxide substrate, gallium oxide buffer layer grown by unintentional doping under transformer, stacked structure, and second-doped gallium oxide epitaxial layer; The stacked structure includes a set of stacked layers or multiple sets of stacked layers, each set of stacked layers including a first doped gallium oxide layer and an unintentionally doped gallium oxide layer arranged from bottom to top.

2. The gallium oxide epitaxial wafer as described in claim 1, characterized in that, When the stacked structure includes multiple sets of stacked layers... Along the bottom-up direction, the doping concentration of the first doped atom in the first doped gallium oxide layer of the later stack decreases compared to the doping concentration of the first doped atom in the first doped gallium oxide layer of the previous stack.

3. The gallium oxide epitaxial wafer as described in claim 1, characterized in that, When the stacked structure includes multiple sets of stacked layers... Along the bottom-up direction, the thickness of the first doped gallium oxide layer in the later stack decreases compared to the thickness of the first doped gallium oxide layer in the previous stack.

4. The gallium oxide epitaxial wafer as described in claim 1, characterized in that, When the stacked structure includes multiple sets of stacked layers... Along the bottom-up direction, the thickness of the unintentionally doped gallium oxide layer in the later stack increases compared to the thickness of the unintentionally doped gallium oxide layer in the previous stack.

5. The gallium oxide epitaxial wafer as described in claim 1, characterized in that, The first doping includes nitrogen doping, and the second doping includes silicon doping.

6. A method for manufacturing a gallium oxide epitaxial wafer, characterized in that, The manufacturing method includes: Provide gallium oxide substrate; An unintentionally doped, voltage-grown gallium oxide buffer layer is formed on the gallium oxide substrate; A stacked structure is formed on the gallium oxide buffer layer; wherein the stacked structure includes a set of stacked layers or multiple sets of stacked layers, each set of stacked layers including a first doped gallium oxide layer and an unintentionally doped gallium oxide layer disposed from bottom to top; A second doped gallium oxide epitaxial layer is formed on the stacked structure.

7. The method for manufacturing a gallium oxide epitaxial wafer as described in claim 6, characterized in that, The gallium oxide buffer layer is formed using a first vapor deposition method, wherein the first vapor deposition method includes: The pressure and temperature of the reaction chamber are set to a first pressure range and a first temperature range, respectively. A carrier gas, an oxygen source, and a gallium source are introduced into the reaction chamber. Vapor deposition is performed in a gradient pressure manner within the first pressure range to grow the gallium oxide buffer layer on the gallium oxide substrate. The thickness of the gallium oxide buffer layer is 200nm to 500nm.

8. The method for manufacturing a gallium oxide epitaxial wafer as described in claim 6, characterized in that, The second vapor deposition method is used multiple times to sequentially form each of the first doped gallium oxide layers in multiple sets of the stack in a bottom-up direction; The second vapor deposition method includes: setting the pressure of the reaction chamber to a second pressure range and the temperature to a second temperature range, introducing a carrier gas, an oxygen source, a gallium source and a first doping source into the reaction chamber, and performing vapor deposition to grow the first doped gallium oxide layer in the stack. In this context, along the bottom-up direction, the doping concentration of the first doped gallium oxide layer in the first doped gallium oxide layer of the later stack is lower than the doping concentration of the first doped gallium oxide layer in the first stack, and / or the thickness of the first doped gallium oxide layer in the later stack is lower than the thickness of the first doped gallium oxide layer in the first stack.

9. The method for manufacturing a gallium oxide epitaxial wafer as described in claim 6, characterized in that, The third vapor deposition method is used multiple times to sequentially form each of the unintentionally doped gallium oxide layers in multiple sets of the stack in a bottom-up direction; The third vapor deposition method includes: setting the pressure of the reaction chamber to a third pressure range and the temperature to a third temperature range, introducing a carrier gas, an oxygen source and a gallium source into the reaction chamber, and performing vapor deposition to grow the unintentionally doped gallium oxide layer in the stack. In this context, along the bottom-up direction, the thickness of the unintentionally doped gallium oxide layer in the later stack increases compared to the thickness of the unintentionally doped gallium oxide layer in the previous stack.

10. The method for manufacturing a gallium oxide epitaxial wafer as described in claim 6, characterized in that, The second-doped gallium oxide epitaxial layer is formed using a fourth vapor deposition method, the fourth vapor deposition method comprising: The pressure in the reaction chamber is set to a fourth pressure range and the temperature to a fourth temperature range. A carrier gas, an oxygen source, a gallium source, and a second doping source are introduced into the reaction chamber to perform vapor deposition in order to grow the second doped gallium oxide epitaxial layer.

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