High-precision wafer capacitive thickness measurement integrated system

Abstract

The application discloses a high-precision wafer capacitive thickness measurement integrated system, and relates to the technical fields of semiconductor advanced manufacturing equipment, micro-nano precision nondestructive testing and capacitive sensing, measurement and control cross technology, and comprises a shielded differential parallel plate capacitive sensing unit, a multi-channel low-noise differential signal demodulation module, a five-dimensional dynamic error compensation operation unit, a three-axis high-precision servo partition scanning motion platform and a control data interaction unit. The sensing unit adopts upper and lower symmetrical differential detection plates and a ring-shaped grounding shielding ring to suppress the edge stray electric field. The demodulation module adopts a double-path differential synchronous sampling architecture to collect capacitive signals and generate thickness original readings. The compensation unit corrects the thickness original readings in real time through a calibration fitting correction model, and generates encrypted sampling instructions in the gradient super-threshold value region. The motion platform receives the instructions and switches to a smaller step or a higher sampling frequency. The control unit coordinates the process and outputs data, and realizes non-contact high-precision full-automatic wafer thickness detection.

Description

Technical Field

[0001] This invention relates to the fields of advanced semiconductor manufacturing equipment, micro-nano precision non-destructive testing, and capacitive sensing and control, and more specifically to a high-precision wafer capacitive thickness measurement integrated system. Background Technology

[0002] Currently, wafer thickness measurement solutions fall into three categories: optical interferometric thickness gauges, mechanical probe contact thickness measurement stages, and simple single-plate capacitance thickness measurement devices. Each has its own limitations and technical shortcomings, lacking a complete integrated compensation and zone scanning solution. The objective defects in each dimension are as follows:

[0003] 1. Defects in spectral or laser interferometric optical thickness measurement equipment 1) Poor signal robustness: Relying on thin film reflection spectrum analysis, microparticles, water stains, oxidation color difference, and destructive interference of multilayer composite films on the wafer surface will cause thickness jump drift, with repeatability of only ±0.4~0.6μm, which cannot meet the TTV≤0.1μm control requirements; 2) Strict environmental constraints: Temperature change ≥1℃ will cause optical path drift. Fluctuations in workshop fan airflow and cleanroom illuminance directly interfere with the measurement. Manual optical path calibration is required every 4 hours, making it impossible to operate continuously for 24 hours in mass production. 3) Limited substrate compatibility: Dark polycrystalline silicon, thick metal films, and high-absorption dielectric layers have no effective reflection spectrum, making it impossible to complete thickness detection; the overall optical path module is large in size, making it difficult to embed into vacuum wafer transmission production lines.

[0004] 2. Defects in mechanical contact thickness testers 1) Irreversible wafer damage exists: Pressurized contact of ultrathin wafers with hard diamond probes easily causes localized deformation, surface scratches, and lattice dislocations, resulting in a scrap rate of >3% for 50–150μm ultrathin wafers. 2) Accumulated mechanical errors: Long-term wear of the probe, Z-axis lead screw backlash, and superposition of minute vibrations of the marble stage result in a single-point repeatability error of ±0.8~1.2μm; full-domain grid scanning of a single wafer takes ≥60s, resulting in extremely low mass production efficiency; 3) Only single-point numerical output is provided, without global thickness cloud map or edge warping quantification data, which cannot support the traceability of process defects.

[0005] 3. Traditional single-plate capacitor thickness measurement device 1) Electric field edge effect not suppressed: without shielding ring structure, stray capacitance around the electrode accounts for 12%~20% of the total signal, and the measurement error in the edge area of ​​the 12-inch wafer is amplified to ±0.35μm; 2) The signal acquisition architecture is rudimentary: single-ended signal amplification, no differential anti-interference design, and electromagnetic interference from workshop frequency converters and robotic arms directly causes capacitor sampling noise, with a resolution of only 0.05μm; 3) Lack of compensation mechanism: Only a simple fixed temperature correction coefficient is used, without synchronous compensation for humidity, air pressure, platform micro-displacement, and zero-point temperature drift; when the ambient temperature fluctuates by ±2℃, the thickness drift can reach 0.2μm; 4) Split-type without automated integration: The sensor, motion platform and signal acquisition box are independent of each other, requiring manual loading and unloading, manual positioning and single-point sampling. It does not have automatic vacuum adsorption, wafer pre-alignment, partition scanning and MES data uploading functions. 5) Single detection strategy: uniform step size and uniform sampling frequency scanning across the entire area. If a high-precision small step size is used across the entire area, the detection time will double. If the step size is increased, areas with sudden changes in wafer thickness will be missed. It is impossible to balance accuracy and efficiency.

[0006] Therefore, how to provide a capacitive thickness measurement system-level solution that meets submicron level accuracy, non-destructive testing, efficient partitioned scanning, environmental adaptive compensation, and fully automated production line integration is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of the above problems, the present invention is proposed to provide a high-precision wafer capacitive thickness measurement integrated system that overcomes or at least partially solves the above problems.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, embodiments of the present invention provide a high-precision wafer capacitive thickness measurement integrated system, comprising: Shielded differential parallel plate capacitive sensing unit: includes differential detection plates symmetrically arranged at the top and bottom and an annular grounded shielding ring disposed around the differential detection plates. The differential detection plates are used to form a detection capacitor with the wafer, and the annular grounded shielding ring is used to suppress stray electric fields at the edges. Multi-channel low-noise differential signal demodulation module: connected to the shielded differential parallel plate capacitance sensing unit, it adopts a dual-channel differential synchronous sampling architecture to acquire and demodulate the signal of the sensing capacitor, and generate the raw wafer thickness reading. Five-dimensional dynamic error compensation calculation unit: connected to the multi-channel low-noise differential signal demodulation module, it corrects the original wafer thickness reading in real time through calibration fitting correction model, and generates encrypted sampling instructions in the region where the wafer thickness gradient change rate exceeds the preset threshold based on the corrected original wafer thickness reading. Three-axis high-precision servo partition scanning motion platform: connected to a five-dimensional dynamic error compensation calculation unit, it receives encrypted sampling instructions and automatically switches to small scanning step size or high sampling frequency in the corresponding area; Embedded integrated control and data interaction unit: It is connected to the multi-channel low-noise differential signal demodulation module, the five-dimensional dynamic error compensation calculation unit and the three-axis high-precision servo partition scanning motion platform respectively, to control the detection process and output detection data.

[0009] Furthermore, the differential detection electrode plate is made of alumina ceramic substrate and is polished at the nanoscale. The surface of the electrode plate has a gold-plated conductive layer. The differential detection plates are installed using flexible, heat-insulated mounting brackets. The flexible heat-insulating fixing base is filled with an aerogel heat insulation layer.

[0010] Furthermore, the multi-channel low-noise differential signal demodulation module includes: a preamplifier, a multi-stage LC active filter unit, a high-precision AC capacitor demodulation chip, an analog-to-digital converter, and a hardware real-time zero-point clearing circuit; The preamplifier is connected to the differential detection plates arranged symmetrically on the top and bottom to receive the differential signal, which is used to amplify the differential signal with high common-mode rejection ratio. The multi-stage LC active filter unit is connected to the output of the preamplifier to filter out high-frequency interference noise above the cutoff frequency in the single-ended signal and retain the effective thickness signal bandwidth. The high-precision AC capacitor demodulation chip is connected to the output of the multi-stage LC active filter unit to convert the capacitance change in the effective thickness signal frequency band into an analog voltage signal that corresponds linearly to it. The analog-to-digital converter (ADC) is connected to the output of a high-precision AC capacitor demodulation chip to convert analog voltage signals into raw wafer thickness readings. The hardware real-time zero-point clearing circuit is connected to a high-precision AC capacitor demodulation chip to automatically perform zero-point calibration before each wafer is inspected.

[0011] Furthermore, the calibration and fitting correction model specifically corrects the original wafer thickness reading in real time as follows: The five-dimensional dynamic error compensation calculation unit has a built-in embedded real-time compensation algorithm and simultaneously collects five types of parameters: temperature, humidity, air pressure, Z-axis platform micro-displacement, and electrode zero-point drift, and establishes a correction formula: T 校正 =T 原始 K t ΔT K h ΔH K p ΔP K z ΔZ C 漂移 Where T 校正 The original reading for the corrected wafer thickness; T 原始 This is the raw reading of the wafer thickness; Kt K is the temperature correction factor. h K is the humidity correction factor. p K is the pressure correction factor. z ΔT is the Z-axis platform micro-displacement correction coefficient; ΔT is the difference between real-time temperature and calibrated temperature; ΔH is the difference between real-time relative humidity and calibrated humidity; ΔP is the difference between real-time air pressure and calibrated air pressure; ΔZ is the Z-axis platform micro-displacement; C 漂移 is the zero-point drift constant of the electrode.

[0012] Furthermore, the three-axis high-precision servo partition scanning motion platform also includes: It is connected to the multi-channel low-noise differential signal demodulation module via a synchronous sampling trigger unit; The synchronous sampling trigger unit enables the displacement of the three-axis high-precision servo partition scanning motion platform to be synchronously phase-locked with the capacitive sampling of the multi-channel low-noise differential signal demodulation module.

[0013] Furthermore, the corresponding areas are specifically as follows: The three-axis high-precision servo partition scanning motion platform divides the wafer inspection area into three inspection zones: the central standardized inspection zone, the transition gradient zone, and the edge critical high-precision zone. The scanning step size of the central standard detection area is greater than that of the transition gradient area, and the scanning step size of the transition gradient area is greater than that of the edge critical high-precision area. The sampling frequency in the edge critical high-precision zone is higher than that in the transition gradient zone, and the sampling frequency in the transition gradient zone is higher than that in the center standardized detection zone.

[0014] Furthermore, the embedded integrated control and data interaction unit adopts a dual-core real-time computing architecture of ARM and FPGA, with dual storage units of local caching and cloud upload, and built-in thickness cloud map generation algorithm, total thickness deviation (TTV) calculation algorithm, warpage fitting algorithm, and out-of-tolerance coordinate marking algorithm.

[0015] Furthermore, the embedded integrated control and data interaction unit includes: a standardized Ethernet interface, a SECS protocol interface, and a GEM protocol interface, used to interface with the production line MES system to automatically upload inspection data; and supports automatic audible and visual alarms for thickness deviations and locking of the wafer ID.

[0016] The beneficial effects of the above-described technical solutions provided in the embodiments of the present invention include at least the following: 1. This invention addresses the technical bottlenecks of traditional capacitance thickness measurement equipment, such as stray electric field at the edges, low measurement accuracy, and insufficient resolution. Existing single-plate unshielded structures have edge errors exceeding 0.3μm. This invention employs a differential shielded plate structure, coupled with a 24-bit high-resolution demodulation circuit, to reduce the basic repeatability accuracy to ±0.05μm and the resolution to 0.01μm, meeting the TTV control requirements of advanced processes while avoiding spectral interference from optical equipment and wafer damage defects from contact-type equipment.

[0017] 2) Addressing industry pain points such as poor environmental adaptability of existing testing equipment and severe data drift during long-term operation. Existing equipment only provides static temperature compensation, and fluctuations in temperature, humidity, air pressure, and mechanical displacement can all cause measurement drift. This invention uses a five-dimensional real-time dynamic compensation algorithm with multiple sensors to collect and correct data simultaneously. Even under conditions of significant fluctuations in workshop temperature and humidity and continuous 24-hour operation of the equipment, the thickness drift is controlled within 0.03μm, eliminating the need for frequent manual calibration and significantly reducing production line maintenance time.

[0018] 3) Overcoming the inherent contradiction between high precision and detection efficiency. Traditional equipment options are either one or the other: high-precision detection with small step size across the entire area takes too long, while fast detection with large step size misses wafer edge defects; the present invention uses a zoned differentiated gradient scanning strategy, with fast sampling with large step size in the central area and ultra-high density sampling with extremely small step size at the edges, improving detection efficiency by more than 40%, balancing mass production cycle time and edge defect detection accuracy.

[0019] 4) Address the shortcomings of existing thickness measuring devices, such as being fragmented, having low automation levels, and being unable to be integrated online for mass production. Traditional equipment separates sensors, motion tables, and data acquisition boxes, requiring manual loading and unloading and positioning. This system integrates visual alignment, vacuum adsorption, automatic scanning, and data uploading, supporting automatic loading and unloading of FOUP wafer boxes to connect with semiconductor mass production lines. The entire process is unmanned and adaptable to automated production lines in factories with 28nm and below.

[0020] 5) Solve the quality problems of easy deformation and surface damage leading to scrapping of ultrathin wafers in contact inspection. The entire process is non-contact capacitive electric field detection, without any mechanical probes or pressure contact. It can detect 50μm ultrathin silicon wafers and fragile epitaxial wafers without scratches or lattice damage, reducing the scrap rate to 0 and significantly improving the yield of high-end wafer products. At the same time, it is compatible with high-absorption dark film layers, making up for the shortcomings of optical thickness measurement substrate compatibility. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 This is a diagram of the overall system structure provided in an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] This invention discloses a high-precision wafer capacitive thickness measurement integrated system, such as... Figure 1 As shown, it includes: Shielded differential parallel plate capacitive sensing unit: includes differential detection plates symmetrically arranged at the top and bottom and an annular grounded shielding ring disposed around the differential detection plates. The differential detection plates are used to form a detection capacitor with the wafer, and the annular grounded shielding ring is used to suppress stray electric fields at the edges. Multi-channel low-noise differential signal demodulation module: connected to the shielded differential parallel plate capacitance sensing unit, it adopts a dual-channel differential synchronous sampling architecture to acquire and demodulate the signal of the sensing capacitor, and generate the raw wafer thickness reading. Five-dimensional dynamic error compensation calculation unit: connected to the multi-channel low-noise differential signal demodulation module, it corrects the original wafer thickness reading in real time through calibration fitting correction model, and generates encrypted sampling instructions in the region where the wafer thickness gradient change rate exceeds the preset threshold based on the corrected original wafer thickness reading. Three-axis high-precision servo partition scanning motion platform: connected to a five-dimensional dynamic error compensation calculation unit, it receives encrypted sampling instructions and automatically switches to a smaller scanning step or a higher sampling frequency in the corresponding area; Embedded integrated control and data interaction unit: It is connected to the multi-channel low-noise differential signal demodulation module, the five-dimensional dynamic error compensation calculation unit and the three-axis high-precision servo partition scanning motion platform respectively, to control the detection process and output detection data.

[0025] The specific implementation of this invention is as follows: Abandoning the traditional single-plate structure, it adopts a composite structure of upper and lower symmetrical differential detection plates and an outer ring grounding shield to eliminate stray electric fields at the edges; the plates are made of alumina ceramic substrate, nano-level planar polishing, and the parallelism of the plates is strictly controlled, and a heat-insulating and shock-absorbing flexible fixing seat is used to isolate the plate offset caused by frame deformation and temperature change.

[0026] Upper and lower detection plate dimensions: diameter φ12mm, annular shielding ring width 3mm, gap between shielding ring and plate 0.2mm, grounded throughout to shield stray electric field; The flatness of the ceramic substrate is ≤0.01μm, and the parallelism error of the upper and lower plates is ≤0.02mm; The gold-plated conductive layer on the electrode surface has a thickness of 0.8 μm and a surface roughness Ra≤5 nm; The Z-axis reference spacing of the electrode plates is fixed at 200μm, and the reference value of the calibration capacitor of the factory standard sheet is C0=4.2pF; The flexible heat-insulating fixing seat is filled with an aerogel heat insulation layer to isolate the internal heat source of the equipment from the conduction to the electrode plate, and the temperature fluctuation of the electrode plate is controlled within ±0.3℃.

[0027] The proportion of stray capacitance at the edge of the electrode plate has been reduced from the current 12%~20% to ≤1.8%, and the measurement error in the wafer edge region has been reduced from ±0.35μm to ≤0.04μm.

[0028] A dual-channel differential synchronous sampling architecture is adopted to cancel industrial common-mode electromagnetic interference; a preamplifier, multi-stage LC active filter and high-precision AC capacitor demodulation chip are used for hierarchical processing; hardware synchronous sampling trigger is set, and the movement of the motion platform is synchronized with the capacitor sampling to eliminate motion noise.

[0029] Signal sampling channels: Dual-channel differential synchronous acquisition, sampling frequency 1000Hz; Circuit input noise ≤0.08nV / √Hz, demodulation capacitor detection range 0–20pF, capacitance resolution 0.0001pF, corresponding thickness physical resolution 0.01μm; Filtering frequency band: cutoff frequency 120Hz, high-frequency interference from servo motors and radio frequency equipment in the filtration workshop; The analog-to-digital converter has a bit depth of 24 bits, and the linearity error of the thickness signal is ≤0.2%FS. The hardware real-time zero-point reset circuit automatically performs a 300ms zero-point calibration before each wafer is inspected.

[0030] When the frequency converter and the robotic arm are working simultaneously, the sampling noise is reduced by 75%, and there is no random thickness jump phenomenon.

[0031] Unlike existing single-temperature static compensation, it has a built-in embedded real-time compensation algorithm that simultaneously collects five types of parameters: temperature, humidity, air pressure, Z-axis platform micro-displacement, and electrode zero-point drift. It corrects the original thickness reading in real time through calibration and fitting correction model, which is an active dynamic compensation rather than a post-data correction.

[0032] Hardware sensor parameters: High-precision temperature sensor: accuracy ±0.05℃, sampling period 1s; Humidity sensor: accuracy ±1%RH; Barometric pressure sensor: accuracy ±0.1hPa; Z-axis grating displacement sensor with positioning accuracy of ±0.01μm, real-time acquisition of minute settlement displacement of the platform; Compensation Algorithm Implementation Example Calibration Model: Establish a five-variable linear correction formula: T 校正 =T 原始 K t ΔT K h ΔH K p ΔP K z ΔZ C 漂移 Where T 校正 The original reading for the corrected wafer thickness; T 原始 This is the raw reading of the wafer thickness; K t K is the temperature correction factor. h K is the humidity correction factor. p K is the pressure correction factor. z ΔT is the Z-axis platform micro-displacement correction coefficient; ΔT is the difference between real-time temperature and calibrated temperature; ΔH is the difference between real-time relative humidity and calibrated humidity; ΔP is the difference between real-time air pressure and calibrated air pressure; ΔZ is the Z-axis platform micro-displacement; C 漂移 is the zero-point drift constant of the electrode.

[0033] Under cleanroom conditions with temperature fluctuations of ±3℃ and humidity fluctuations of 40%–60%RH, the maximum thickness drift of the same standard wafer was measured continuously for 24 hours and was ≤0.03μm.

[0034] Equipped with a visual pre-alignment unit: The actual position of the silicon wafer is acquired through machine vision, the features are extracted and the deviation from the theoretical position is calculated, and the result is sent to the motion platform for position compensation, aligning the silicon wafer coordinate system with the capacitance measurement coordinate system.

[0035] Vacuum adsorption ceramic stage: It relies on negative pressure to create an atmospheric pressure difference, so that the silicon wafer is evenly attached to the suction cup stage surface; the core is the zoned and controllable negative pressure, which avoids the ultra-thin silicon wafer from being forcibly stretched and deformed.

[0036] The motion platform automatically divides the wafer inspection area into three zones: the central standard inspection zone, the transition gradient zone, and the edge critical high-precision zone. The scanning step size and sampling frequency are independently configured for each zone to achieve differentiated gradient scanning.

[0037] Key parameter thresholds (8 / 12-inch general platform) X / Y axis servo linear motor positioning accuracy ±0.01mm, repeatability ±0.005mm; Z axis grating positioning accuracy ±0.01μm; The flatness of the vacuum ceramic stage is ≤0.03μm, and the vacuum adsorption negative pressure is [not specified]. 85 kPa, ultra-thin wafers exhibit no adsorption deformation; The visual pre-alignment camera has a recognition accuracy of ±0.02mm and automatically corrects wafer eccentricity and deflection. Partition scan strategy parameters: Central region (wafer radius 0~40mm): scanning step size 2mm, sampling frequency 500Hz; Transition zone (40mm~55mm): scanning step size 1mm, sampling frequency 800Hz; Edge critical region (55mm to wafer outer edge): scan step size 0.2mm, sampling frequency 1000Hz; The total time for full-area complete grid inspection of a 12-inch wafer is 32s, which is 42.8% more efficient than the uniform 0.2mm small step size scan (56s). No abrupt changes in wafer edge thickness or warping defects were missed.

[0038] The industrial ARM+FPGA dual-core real-time computing architecture features dual storage with local caching and cloud upload; it incorporates algorithms for thickness cloud map generation, TTV calculation, warpage fitting, and out-of-tolerance coordinate marking; and it connects to the production line MES system via standardized Ethernet / SECS / GEM protocols, automatically uploading inspection reports.

[0039] Functional parameter thresholds: Single-wafer inspection data storage capacity ≥ 10 years of local retention; The thickness out-of-tolerance warning threshold can be customized. By default, if TTV > 0.1μm, an automatic audible and visual alarm will be triggered and the wafer ID will be locked. The output dataset includes: single-point coordinates-thickness table, two-dimensional color thickness contour map, wafer thickness range, average thickness, edge warpage height, and list of out-of-tolerance points; Supports offline USB drive export, real-time upload to factory database, and automatic generation of test report PDFs.

[0040] Shockproof and dustproof frame structure: The base is made of natural marble and has a three-level silicone shock-absorbing pad, which isolates the workshop floor from vibration, with a vibration suppression efficiency of ≥90%. The entire unit features a fully enclosed positive pressure dustproof chamber with a cleanliness level of Class 100, preventing dust from falling onto the wafers and sensor plates. The cavity has a constant temperature insulation interlayer, and the internal temperature change rate is controlled to ≤0.2℃ / h.

[0041] As shown in Table 1, the existing best simple capacitance thickness measurement device and optical interferometric thickness gauge are selected as comparative examples, and their key indicators are compared with those of the system of the present invention: Table 1

[0042] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the systems disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the system section description.

[0043] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-precision wafer capacitive thickness measurement integrated system, characterized in that, include: Shielded differential parallel plate capacitive sensing unit: includes differential detection plates symmetrically arranged vertically and an annular grounded shielding ring disposed around the differential detection plates. The differential detection plates are used to form a detection capacitor with the wafer, and the annular grounded shielding ring is used to suppress stray electric fields at the edges. Multi-channel low-noise differential signal demodulation module: connected to the shielded differential parallel plate capacitor sensing unit, it uses a dual-channel differential synchronous sampling architecture to acquire and demodulate the signal of the detection capacitor, and generates the raw wafer thickness reading. Five-dimensional dynamic error compensation calculation unit: connected to the multi-channel low-noise differential signal demodulation module, it corrects the original wafer thickness reading in real time through calibration fitting correction model, and generates encrypted sampling instructions in the region where the wafer thickness gradient change rate exceeds the preset threshold based on the corrected original wafer thickness reading; Three-axis high-precision servo partition scanning motion platform: connected to the five-dimensional dynamic error compensation calculation unit, receiving the encrypted sampling command and automatically switching to small scanning step size or high sampling frequency in the corresponding area; Embedded integrated control and data interaction unit: connected to the multi-channel low-noise differential signal demodulation module, the five-dimensional dynamic error compensation calculation unit and the three-axis high-precision servo partition scanning motion platform respectively, controlling the detection process and outputting detection data.

2. The system as described in claim 1, characterized in that, include: The differential detection electrode plate is made of alumina ceramic substrate and is polished at the nanoscale. The surface of the electrode plate has a gold-plated conductive layer. The differential detection electrode plate is installed via a flexible heat-insulating fixing base; The flexible heat-insulating fixing base is filled with an aerogel heat-insulating layer.

3. The system as described in claim 1, characterized in that, The multi-channel low-noise differential signal demodulation module includes: a preamplifier, a multi-stage LC active filter unit, a high-precision AC capacitor demodulation chip, an analog-to-digital converter, and a hardware real-time zero-point clearing circuit. The preamplifier is connected to the differential detection plates arranged symmetrically on the upper and lower sides to receive differential signals and is used to amplify the differential signals with high common-mode rejection ratio. The multi-stage LC active filter unit is connected to the output of the preamplifier and is used to filter out high-frequency interference noise above the cutoff frequency in the single-ended signal, while retaining the effective thickness signal bandwidth. The high-precision AC capacitor demodulation chip is connected to the output of the multi-stage LC active filter unit and is used to convert the capacitance change in the effective thickness signal frequency band into an analog voltage signal that corresponds linearly to it. The analog-to-digital converter is connected to the output of the high-precision AC capacitor demodulation chip and is used to convert the analog voltage signal into the raw reading of the wafer thickness. The hardware real-time zero-point clearing circuit is connected to the high-precision AC capacitor demodulation chip and is used to automatically perform zero-point calibration before each wafer is inspected.

4. The system as described in claim 1, characterized in that, The calibration fitting correction model specifically corrects the original wafer thickness reading in real time as follows: The five-dimensional dynamic error compensation calculation unit has a built-in embedded real-time compensation algorithm and simultaneously collects five types of parameters: temperature, humidity, air pressure, Z-axis platform micro-displacement, and electrode zero-point drift, and establishes a correction formula: T 校正 =T 原始 K t ΔT K h ΔH K p ΔP K z ΔZ C 漂移 Where T 校正 The original reading for the corrected wafer thickness; T 原始 This is the raw reading of the wafer thickness; K t K is the temperature correction factor. h K is the humidity correction factor. p K is the pressure correction factor. z ΔT is the Z-axis platform micro-displacement correction coefficient; ΔT is the difference between real-time temperature and calibrated temperature; ΔH is the difference between real-time relative humidity and calibrated humidity; ΔP is the difference between real-time air pressure and calibrated air pressure; ΔZ is the Z-axis platform micro-displacement; C 漂移 is the zero-point drift constant of the electrode.

5. The system as described in claim 1, characterized in that, The three-axis high-precision servo partition scanning motion platform also includes: It is connected to the multi-channel low-noise differential signal demodulation module via a synchronous sampling trigger unit; The synchronous sampling trigger unit enables the displacement of the three-axis high-precision servo partition scanning motion platform to be synchronously phase-locked with the capacitive sampling of the multi-channel low-noise differential signal demodulation module.

6. The system as described in claim 1, characterized in that, The corresponding region is specifically: The three-axis high-precision servo partition scanning motion platform divides the wafer inspection area into three inspection zones: the central standardized inspection zone, the transition gradient zone, and the edge critical high-precision zone. The scanning step size of the central standard detection area is greater than the scanning step size of the transition gradient area, and the scanning step size of the transition gradient area is greater than the scanning step size of the edge critical high-precision area; The sampling frequency of the edge critical high-precision zone is higher than that of the transition gradient zone, and the sampling frequency of the transition gradient zone is higher than that of the center standardized detection zone.

7. The system as described in claim 1, characterized in that, The embedded integrated control and data interaction unit adopts a dual-core real-time computing architecture of ARM and FPGA, and has dual storage units of local caching and cloud upload. It has built-in thickness cloud map generation algorithm, total thickness deviation (TTV) calculation algorithm, warpage fitting algorithm and out-of-tolerance coordinate marking algorithm.

8. The system as described in claim 1, characterized in that, The embedded integrated control and data interaction unit includes a standardized Ethernet interface, a SECS protocol interface, and a GEM protocol interface, which are used to interface with the production line MES system and automatically upload the detection data; and support automatic audible and visual alarms for thickness deviations and locking the wafer ID.

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