A method for measuring bonding energy of a D2W and D2D hybrid bonding interface

Abstract

The present application relates to a kind of bonding energy measurement method suitable for D2W and D2D mixed bonding interface, belong to interface bonding energy measurement technical field, at least one of the problems such as interface damage, interface bonding energy measurement inaccuracy and measurement unit difficult to convert in existing measurement method is solved.The present application provides a kind of bonding energy measurement method suitable for D2W and D2D mixed bonding interface, by applying load on the upper material layer to obtain scratch, the critical load of interface failure is measured by real-time monitoring the mutation point of load-displacement curve, and then the bonding energy of bonding interface is calculated.The measurement method is less destructive to bonding interface, can be measured multiple times to average, high accuracy and easy to repeat verification;For the adaptability of sample size, it can be applied to the bonding energy measurement of different bonding interfaces of multilayer chip;And the method can give quantitative detection results in the form of energy density, unit is J / m 2 , it is convenient for direct comparison.

Description

Technical Field

[0001] This invention relates to the field of interfacial bonding energy measurement technology, and in particular to a method for measuring the bonding energy of D2W and D2D hybrid bonding interfaces. Background Technology

[0002] With the increasing demand for chip integration, 3D integration technology has become a crucial core technology for breaking Moore's Law. Hybrid bonding processes can effectively achieve higher interconnect density and integration, playing a significant role in promoting heterogeneous integration and advanced processes. Die-to-Wafer Hybrid Bonding (D2W) greatly improves integration density and chip performance through 3D stacking, while simultaneously reducing power consumption, shrinking package size, and improving reliability. D2W hybrid bonding is a technology that directly bonds individual chips (dies) to wafers, achieving both mechanical and electrical interconnections. Unlike traditional soldering or bump bonding technologies, hybrid bonding achieves high-density interconnects by directly bonding dielectric and metal layers, with interconnect spacing down to the micrometer or even submicrometer level.

[0003] Compared to wafer-to-wafer (W2W) hybrid bonding technology, bonding energy measurement methods for die-to-wafer (D2W) hybrid bonding are still under development. In W2W bonding, the blade method is often used to measure wafer bonding energy, a key parameter for evaluating bonding quality. However, due to the smaller chip size, larger number of bonding layers, and difficulty in separating the bonding interfaces in D2W hybrid bonding, the blade method cannot be directly used for bonding energy measurement. Although C-mode scanning acoustic microscopy (C-SAM) can be used to scan the void distribution at the D2W hybrid bonding interface, the void distribution does not fully reflect the actual bonding energy intensity. The bonding mechanism of D2D hybrid bonding interfaces is similar to that of D2W bonding, and existing D2D hybrid bonding interface bonding energy measurement techniques also suffer from similar shortcomings.

[0004] Therefore, developing a quantitative measurement method for bonding energy applicable to D2W and D2D hybrid bonding interfaces to accurately characterize the interfacial bonding energy is of great significance for evaluating actual bonding quality. Summary of the Invention

[0005] In view of the above analysis, the present invention aims to provide a bonding energy measurement method suitable for D2W and D2D hybrid bonding interfaces, so as to solve at least one of the problems of existing bonding energy measurement methods for D2W and D2D hybrid bonding interfaces, such as large interface damage, inaccurate interface bonding energy measurement, and difficulty in converting measurement units.

[0006] This invention provides a method for measuring the bonding energy of hybrid D2W and D2D bonding interfaces, specifically including the following steps:

[0007] S1: Expose the upper material layer of the bonding interface to be tested, apply a load and create scratches on the upper surface of the upper material layer using a scratch probe, and monitor the longitudinal load-horizontal displacement curve of the probe tip in real time.

[0008] The longitudinal load at the needle tip refers to the load in the vertical direction detected by the sensor at the needle tip; the horizontal load at the needle tip is not considered.

[0009] S2: Determine the critical load based on the abrupt change point of the longitudinal load-horizontal displacement curve of the needle tip. The abrupt change point corresponds to the interface failure of the bonding interface to be tested. The bonding energy of the bonding interface to be tested is obtained by calculation.

[0010] The D2W and D2D hybrid bonding interface includes a single-layer or multi-layer chip D2W or D2D hybrid bonding interface.

[0011] Specifically, the bonding interface to be tested is the interface between the upper material layer and the lower material layer;

[0012] The upper material layer is a chip layer, which is one or more of the following: pure dielectric, pure metal, pure silicon chip, and composite material with silicon as substrate covered by dielectric.

[0013] The lower material layer is a chip layer or a wafer layer, and the chip layer is one or more of the following: pure dielectric, pure metal, pure silicon chip, and composite material with silicon as substrate covered by dielectric.

[0014] When the underlying material layer is a chip layer, the bonding interface under test is a D2D hybrid bonding interface; when the underlying material layer is a wafer layer, the bonding interface under test is a D2W hybrid bonding interface.

[0015] For example, when both the upper and lower material layers are silicon-based composite materials covered with a dielectric, the bonding interface to be tested generally refers to the interface between the dielectric layer of the upper material layer and the substrate layer of the lower material layer (e.g., ...). Figure 3 (As shown).

[0016] Furthermore, in step S1, after exposing the upper material layer, a thinning operation is performed. The thickness of the thinned upper material layer is 0.1µm to 10µm. The upper material layer can be thinned by dry etching, wet etching, mechanical polishing, ion beam etching, etc. After thinning, the area left by the upper material layer is only the bonding material layer or the bonding material and the substrate composite layer, so that the load applied by the probe can be effectively applied to the bonding interface to be tested.

[0017] For example, when the upper material layer is a composite material covered with a dielectric based on silicon, the thinned thickness refers to the total thickness of the substrate layer (Si) and the dielectric layer of the composite material; when the upper material layer is a pure substance (such as a pure dielectric, pure metal or pure silicon chip), the thinned thickness refers to the thickness of the upper material layer (the thickness of the pure substance).

[0018] It is worth noting that for multilayer chips, the upper and lower material layers are relative. The lower material layer measured in this measurement may be used as the upper material layer in the next measurement; that is, the entire upper material layer measured in this measurement will be removed when performing the next bonding interface bonding energy measurement (e.g., ...). Figure 3 As shown in the figure, the lower material layer measured in this measurement will be used as the upper material layer for the next measurement and thinning operation will be performed.

[0019] Optionally, step S1 uses a scratch probe with a wedge-shaped or conical needle from a micro-scratch tester.

[0020] Optionally, the load applied in step S1 can be either a progressive loading mode or a constant loading mode.

[0021] Among them, the progressive loading mode refers to the probe's vertical load increasing linearly from zero to a preset maximum value; the constant loading mode refers to the probe being subjected to a fixed downward load.

[0022] The load application mode refers to the mode in which the indenter of the scratch-free tester applies the load.

[0023] Specifically, the method for calculating the bonding energy of the bonding interface to be tested in step S2 is as follows:

[0024] Observe the abrupt change point of the longitudinal load-horizontal displacement curve at the needle tip, mark the critical load L, which is the load at which the interface begins to delaminate, and use the following formula to measure the bonding energy between the bonding interfaces:

[0025]

[0026] Among them, G C It is the bonding energy, and the unit is J / m. 2 E C t is the Young's modulus of the upper material layer after thinning, in GPa; t is the thickness of the upper bonding layer material at the bonding interface to be tested, in m; L is the critical load of the scratch, in N; d is the scratch width at the critical load point, in m.

[0027] Wherein, when the upper material layer is a composite material with silicon as the substrate and covered with a medium, t is the thickness of the composite material medium layer, which is generally ≤2μm; when the upper material layer is a pure substance (such as pure medium, pure metal or pure silicon chip), t is the total thickness of the upper material layer after thinning.

[0028] Furthermore, at least one area on the upper material layer is selected for scratch testing. Each area is set up as a test group, and each test group includes 1 to 20 scratches, each scratch having the same specifications.

[0029] Preferably, the scratches in each test group are distributed along a straight line, and the straight line is the baseline for the scratch distribution of the test group;

[0030] The baselines for scratch distribution in different test groups are set to coincide or parallel.

[0031] If the baselines for scratch distribution in adjacent test groups do not coincide, then the distance between the corresponding baselines for scratch distribution is greater than three times the length of a single scratch.

[0032] Specifically, the pressure applied by the probe tip is 0–3000 mN; the scratch length is 20–1000 μm; the speed is 0.05–20 μm / s; the scratching time is 0.5–200 s; the scratch width is 5–100 μm; the scratch depth is 0.05–5 μm; and the scratch direction is straight, obtained by the probe tip unidirectionally scratching along the surface of the upper material layer.

[0033] Preferably, after the measurement is completed, the scratch morphology is observed using SEM, AFM or confocal microscope to confirm the failure mode of the bonding interface to be tested. If the failure occurs inside the upper material layer and / or the lower material layer rather than the interface, the test parameters need to be adjusted and the measurement repeated.

[0034] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0035] 1. The measurement method provided by this invention has minimal destructive impact on the interface, allowing for repeated measurements and averaging to improve the accuracy of bonding energy measurement. Furthermore, since it only causes minor damage to the interface, different areas can be selected for scratch measurement, which can be used to detect whether the bonding energy is uniform in different areas of the bonding interface (indirectly reflecting the presence of voids, weak connections, etc.).

[0036] Meanwhile, the measurement method does not require pre-creating cracks at the bonding interface using FIB or etching methods. It can directly measure the interfacial bonding energy by applying a load to the upper material layer using a micro-scratch tester, thus avoiding the problem of inaccurate testing caused by pre-created cracks failing to break along the bonding interface during peeling.

[0037] 2. The measurement method provided by this invention can provide quantitative bond energy test results, and the calculated bond energy is expressed as energy density (J / m³). 2The unit used is consistent with the W2W blade method, facilitating direct comparison. In contrast, traditional direct pull or shear methods can only obtain the interfacial force (N) or pressure (MPa), which cannot be directly compared with energy units.

[0038] Furthermore, experimental verification shows that the interfacial bonding energy obtained by the measurement method has an error of less than 5% compared with the more ideal results obtained by existing technologies (test results without special cases such as uncontrolled fracture direction of pre-cracks). The measurement results are accurate and reliable.

[0039] 3. The measurement method provided by this invention has a testing range from nanometers to micrometers, and is suitable for testing the bonding energy of D2W and D2D hybrid bonding interfaces of chips of various sizes. Traditional blade bonding requires inserting a blade into the bonding interface, which can damage the bonding interface due to the small size and thinness of the chip, making it impossible to accurately measure the true interface bonding energy.

[0040] Furthermore, the measurement method is also applicable to the measurement of bonding energy at different bonding interfaces in D2W and D2D mixed-bonded samples in multilayer chips.

[0041] 4. The measurement method provided by this invention has strong adaptability to sample size and can realize bond energy measurement without special processing molds;

[0042] Preferably, the upper material layer is rectangular (common specification), with a length of 1mm-50mm and a width of 1mm-50mm, and the thickness of the upper material layer before thinning is 10um-900um; the total number of bonding layers of the chip under test (single or multi-layer) is 1-10.

[0043] If the lower substrate layer is a wafer, and since standard wafer sizes are 2 inches to 12 inches, to facilitate small-size measurements, the lower wafer can be cut into rectangular, square, triangular, or other polygonal shapes, with a cut area of ​​1 mm². 2 -10000 mm 2 Length 1mm-100mm. Width 1mm-100mm.

[0044] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0045] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0046] Figure 1a A top view illustrating an implementation of a bonding energy measurement method suitable for hybrid D2W and D2D bonding interfaces;

[0047] Figure 1b A schematic front view of an implementation method for measuring bonding energy of D2W and D2D hybrid bonding interfaces;

[0048] Figure 2 A schematic diagram illustrating a bonding energy measurement method applicable to D2W and D2D hybrid bonding interfaces for single-layer chip measurement;

[0049] Figure 3 A schematic diagram illustrating a bonding energy measurement method applicable to D2W and D2D hybrid bonding interfaces for multilayer chip measurement;

[0050] Figure 4 This refers to the test group and scratch distribution within the group in Example 1;

[0051] Figure 5 This is an image showing the longitudinal load and horizontal displacement of the needle tip for scratch No. 3 in Example 1.

[0052] Figure label:

[0053] 1-Wafer; 2-Chip; 3-Scratch; 4-Probe. Detailed Implementation

[0054] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0055] This invention provides a method for measuring the bonding energy of hybrid D2W and D2D bonding interfaces, specifically including the following steps:

[0056] S1: Expose the upper material layer of the bonding interface to be tested, apply a load and create scratches on the upper surface of the upper material layer using a scratch probe, and monitor the longitudinal load-horizontal displacement curve of the probe tip in real time.

[0057] The longitudinal load at the needle tip refers to the load in the vertical direction detected by the sensor at the needle tip; the horizontal load at the needle tip is not considered.

[0058] S2: Determine the critical load based on the abrupt change point of the longitudinal load-horizontal displacement curve of the needle tip. The abrupt change point corresponds to the interface failure of the bonding interface to be tested. The bonding energy of the bonding interface to be tested is obtained by calculation.

[0059] The D2W and D2D hybrid bonding interface includes a single-layer or multi-layer chip D2W or D2D hybrid bonding interface.

[0060] It is worth noting that the exposed surface / upper surface of the upper material layer and the bonding interface to be tested should be kept as horizontal as possible (i.e., parallel to each other) so that the scratch probe is perpendicular to the upper surface of the upper material layer; otherwise, the accuracy of this measurement method will be affected.

[0061] Specifically, the bonding interface to be tested is the interface between the upper material layer and the lower material layer;

[0062] The upper material layer is a chip layer, which is one or more of the following: pure dielectric, pure metal, pure silicon chip, and composite material with silicon as substrate covered by dielectric.

[0063] The lower material layer is a chip layer or a wafer layer, and the chip layer is one or more of the following: pure dielectric, pure metal, pure silicon chip, and composite material with silicon as substrate covered by dielectric.

[0064] When the underlying material layer is a chip layer, the bonding interface under test is a D2D hybrid bonding interface; when the underlying material layer is a wafer layer, the bonding interface under test is a D2W hybrid bonding interface. In other words, the measurement method can be used to measure the bonding energy of interfaces between chip layers and wafer layers, as well as the bonding energy of interfaces between different chip layers.

[0065] For example, when both the upper and lower material layers are silicon-based composite materials covered with a dielectric, the bonding interface to be tested generally refers to the interface between the dielectric layer of the upper material layer and the substrate layer of the lower material layer (e.g., ...). Figure 3 As shown, this is the interface between the dielectric layer of chip 1 and the substrate layer of chip 2.

[0066] Furthermore, in step S1, after exposing the upper material layer, a thinning operation is performed. The thickness of the thinned upper material layer is 0.1µm to 10µm. The upper material layer can be thinned by dry etching, wet etching, mechanical polishing, ion beam etching, etc. After thinning, the area left by the upper material layer is only the bonding material layer or the bonding material and the substrate composite layer, so that the load applied by the probe can be effectively applied to the bonding interface to be tested.

[0067] For example, when the upper material layer is a composite material covered with a dielectric based on silicon, the thinned thickness refers to the total thickness of the substrate layer (Si) and the dielectric layer of the composite material; when the upper material layer is a pure substance (such as a pure dielectric, pure metal or pure silicon chip), the thinned thickness refers to the thickness of the upper material layer (the thickness of the pure substance).

[0068] It is worth noting that for multilayer chips, the upper and lower material layers are relative. The lower material layer measured in this measurement may be used as the upper material layer in the next measurement; that is, the entire upper material layer measured in this measurement will be removed when performing the next bonding interface bonding energy measurement (e.g., ...). Figure 3 As shown in the figure, the lower material layer measured in this measurement will be used as the upper material layer for the next measurement and thinning operation will be performed.

[0069] Optionally, step S1 uses a scratch probe with a wedge-shaped or conical needle from a micro-scratch tester.

[0070] Optionally, the load applied in step S1 can be either a progressive loading mode or a constant loading mode.

[0071] Among them, the progressive loading mode refers to the probe's vertical load increasing linearly from zero to a preset maximum value; the constant loading mode refers to the probe being subjected to a fixed downward load.

[0072] The load application mode refers to the mode in which the indenter of the scratch-free tester applies the load. The load applied by the indenter is not directly equal to the longitudinal load measured by the probe tip. For example, when the vertical load applied by the probe is x, the longitudinal load detected by the sensor at the tip is ≤x, such as... Figure 5 As shown, the pressure applied by the indenter actually increases continuously, but when interface failure occurs, the longitudinal load detected by the sensor at the needle tip drops rapidly. This point of sudden change corresponds to the critical load point.

[0073] Specifically, the method for calculating the bonding energy of the bonding interface to be tested in step S2 is as follows:

[0074] Observe the abrupt change point of the longitudinal load-horizontal displacement curve at the needle tip, mark the critical load L, which is the load at which the interface begins to delaminate, and use the following formula to measure the bonding energy between the bonding interfaces:

[0075]

[0076] Among them, G C It is the bonding energy, and the unit is J / m. 2 E C t is the Young's modulus of the upper material layer after thinning, in GPa; t is the thickness of the upper bonding layer material at the bonding interface to be tested, in m; L is the critical load of the scratch, in N; d is the scratch width at the critical load point, in m.

[0077] Wherein, when the upper material layer is a composite material with silicon as the substrate and covered with a medium, t is the thickness of the composite material medium layer, which is generally ≤2μm; when the upper material layer is a pure substance (such as pure medium, pure metal or pure silicon chip), t is the total thickness of the upper material layer after thinning.

[0078] Furthermore, at least one area on the upper material layer is selected for scratch testing. Each area is set up as a test group, and each test group includes 1 to 20 scratches, each with the same specifications. The bonding energy of the corresponding area is obtained by averaging the bonding energy measured by the scratches in each test group. Furthermore, the bonding energy of the entire bonding interface is obtained by averaging the average bonding energy measured by different test groups (corresponding to different areas).

[0079] For example, taking a rectangular chip under test / upper material layer as an example, such as Figure 4 As shown, several areas can be selected at the center and near the edge of the upper material layer for scratch testing. Each area is set up as a test group. Preferably, each test group includes 5 to 10 scratches. The above number can ensure the accuracy of the measurement (by taking the average value) and avoid excessive scratches that would complicate the process.

[0080] Preferably, the scratches in each test group are distributed along a straight line, and the straight line is the baseline for the scratch distribution of that test group;

[0081] The baselines for scratch distribution in different test groups are set to coincide or parallel.

[0082] If the baselines for scratch distribution in adjacent test groups do not coincide, then the distance between the corresponding baselines for scratch distribution is greater than three times the length of a single scratch.

[0083] It is worth noting that the above test group (scratch distribution baseline) distribution method helps to avoid the interface failure caused by the earlier scratch test affecting the scratch test results of the later one.

[0084] If the scratches in a single test group are not on the same baseline, they may interfere with each other. Moreover, the operation process is cumbersome (the direction of probe scratching needs to be adjusted repeatedly), and the average value of the interface bonding energy test value in a single test group will lose its reference value or the reference value will be reduced.

[0085] Furthermore, if there are baselines for scratches within each test group, but these baselines are not parallel or coincident but overlap at random angles (including in-plane perpendicularity, etc.), it will cause the scratch test results of different test groups to interfere with each other, especially since scratching earlier may affect the accuracy of scratch test results of later scratches.

[0086] Specifically, the pressure applied by the probe tip is 0–3000 mN; the scratch length is 20–1000 μm; the speed is 0.05–20 μm / s; the scratching time is 0.5–200 s; the scratch length = probe moving speed * scratching time (single scratch);

[0087] The scratch depth ranges from 0.05 to 5 μm, and the maximum scratch depth does not exceed the thickness of the upper material layer after thinning.

[0088] Setting parameters according to the above range can meet the measurement needs of interfacial bonding energy of most materials, and the resulting scratch width range is 5 to 100 μm.

[0089] The scratches are straight lines, obtained by the probe tip making a unidirectional scratch along the surface of the upper material layer.

[0090] Depending on the material of the chip layer / wafer layer, different test parameters can be selected according to the actual implementation needs. The parameter settings should be such that the interfacial bonding energy can be accurately measured without damaging the internal structure of the material. That is, the abrupt change point of the longitudinal load of the tip and the horizontal displacement of the tip should correspond to the occurrence of interfacial failure rather than the destruction of the internal structure of the material.

[0091] Preferably, after the measurement is completed, the scratch morphology is observed using SEM, AFM or confocal microscope to confirm the failure mode of the bond interface to be tested. If the failure occurs in the upper material layer and / or the lower material layer rather than the interface, it indicates that the measured interface bond values ​​are inaccurate and the test parameters need to be adjusted and the measurement repeated.

[0092] Example 1

[0093] The bonding energy of the bonding interface of a single-layer chip is tested using the measurement method provided in this invention (e.g., Figure 2 As shown in the figure, the bonding interface to be tested in this embodiment is the interface between chip layers, not the interface between a chip layer and a wafer layer. The scratch sampling method is as follows. Figure 4 As shown, each test group has 5 scratches, for a total of 5 test groups and 25 scratches. The scratches are numbered 1 to 25 from top to bottom and left to right, and the distance between the baselines of adjacent test groups is ≥200um.

[0094] The upper material layer is a SiCN composite chip (with silicon as the substrate and a SiCN thin film covering the surface), and the lower material layer is a wafer layer with a D2W bonding interface. The SiCN composite chip is a 6*11mm rectangular chip with an initial wafer size of 12 inches. The sample under test is diced, and the wafer layer size after dicing is 8*15mm.

[0095] (1) In order to ensure that the scratch probe can destroy the bonding interface under test when the load is applied, the scratch contact surface / upper surface of the upper material layer needs to be thinned; dry etching is used to thin the chip to 5um, which is in line with the maximum load-bearing thickness of the high load probe of the scratch instrument.

[0096] (2) A progressive loading mode load is applied to the upper surface of the thinned upper material layer using a scratching probe with a conical needle tip, ranging from 0 mN to 2 N. The scratch length is 50 μm, the speed is 5 μm / s, the scratching time is 10 s (single scratch), the scratch width ranges from 5 to 100 μm, and the maximum scratch depth is 3 μm (since the base layer of the thinned upper material layer in this embodiment is about 3.2 μm and the dielectric layer is 1.8 μm, the maximum scratch depth is preferably ≤3.2 μm). The five sets of longitudinal load-horizontal displacement curves of the scratching probe tip are monitored in real time to realize the failure of the bonding interface to be tested.

[0097] (3) Analyze the displacement load curve to obtain the critical load value of the curve change point and confirm the scratch position (i.e. the critical load) corresponding to the change point. By combining multiple measurement methods such as AFM or SEM, the scratch width corresponding to the critical load is obtained.

[0098] (4) The bonding energy of the D2W hybrid bonded sample interface was obtained by substituting into the calculation formula. For the sample in this embodiment (except for the inherent material properties, all other measured values ​​are the average of 25 scratches), the critical load is 0.19 N, the critical load scratch width is 5.8 μm, the Young's modulus of the dielectric layer is 72.29 GPa, and the dielectric layer thickness is 1.8 μm. The calculated average bonding energy of the interface is 2.58 J / m. 2 .

[0099] The interfacial bonding energy of the same sample was measured using the traditional blade method (the interface is destroyed after a single measurement), and the value was 2.47 J / m. 2 .

[0100] Example 2

[0101] In this embodiment, SiO2 composite material was selected as the upper layer material, and other operations and parameters were the same as in Example 1. The critical load was measured to be 0.15 N, the critical load scratch width was 6 μm, the Young's modulus of the dielectric layer was 68.78 GPa, the dielectric layer thickness was 1.8 μm, and the calculated average interfacial bonding energy was 1.47 J / m. 2 .

[0102] The interfacial bonding energy of the same sample was measured using the traditional blade method (the interface is destroyed after a single measurement), and the value was 1.42 J / m. 2 .

[0103] In summary, the measurement method provided by this invention causes minimal damage to the interface, improves measurement accuracy by averaging multiple measurements, and can be used to preliminarily characterize the interfacial bonding energy distribution in different regions of the interface, thus aiding in the determination of defects such as bonding voids. Verification has shown that the bonding energy values ​​obtained by the measurement method provided by this invention are quite close to those obtained by the traditional blade method, with a difference of ≤5%. Theoretically, the bonding energy values ​​measured by this invention should be more accurate than those obtained by the blade method.

[0104] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for measuring the bonding energy of hybrid D2W and D2D bonding interfaces, characterized in that, Specifically, the following steps are included: S1: Expose the upper material layer of the bonding interface to be tested, apply a load and create scratches on the upper surface of the upper material layer using a scratch probe, and monitor the longitudinal load-horizontal displacement curve of the probe tip in real time. The longitudinal load at the needle tip refers to the load in the vertical direction detected by the sensor at the needle tip; the horizontal load at the needle tip is not considered. S2: Determine the critical load based on the abrupt change point of the longitudinal load-horizontal displacement curve of the needle tip. The abrupt change point corresponds to the interface failure of the bonding interface to be tested. The bonding energy of the bonding interface to be tested is obtained by calculation. The D2W and D2D hybrid bonding interface includes a single-layer or multi-layer chip D2W or D2D hybrid bonding interface.

2. The measurement method according to claim 1, characterized in that, The bonding interface to be tested is the interface between the upper material layer and the lower material layer; The upper material layer is a chip layer, which is one or more of the following: pure dielectric, pure metal, pure silicon chip, and composite material with silicon as substrate covered by dielectric. The lower material layer is a chip layer or a wafer layer, and the chip layer is one or more of the following: pure dielectric, pure metal, pure silicon chip, and composite material with silicon as substrate covered by dielectric.

3. The measurement method according to claim 1, characterized in that, In step S1, after the upper material layer is exposed, a thinning operation is performed, and the thickness of the thinned upper material layer is 0.1um to 10um.

4. The measurement method according to claim 1, characterized in that, In step S1, a scratch probe with a wedge-shaped or conical needle tip is used in a micro-scratch tester.

5. The measurement method according to claim 1, characterized in that, The load applied in step S1 is either a progressive loading mode or a constant loading mode. Among them, the progressive loading mode refers to the probe's vertical load increasing linearly from zero to a preset maximum value; the constant loading mode refers to the probe being subjected to a fixed downward load. The load application mode refers to the mode in which the indenter of the scratch-free tester applies the load.

6. The measurement method according to claim 1, characterized in that, The method for calculating the bonding energy of the bonding interface to be tested in step S2 is as follows: Observe the abrupt change point of the longitudinal load-horizontal displacement curve at the needle tip, mark the critical load L, which is the load at which the interface begins to delaminate, and use the following formula to measure the bonding energy between the bonding interfaces: Among them, G C It is the bonding energy, and the unit is J / m. 2 E C t is the Young's modulus of the upper material layer after thinning, in GPa; t is the thickness of the upper bonding layer material at the bonding interface to be tested, in m; L is the critical load of the scratch, in N; d is the scratch width at the critical load point, in m.

7. The measurement method according to claim 1, characterized in that, At least one area on the upper material layer is selected for scratch testing. Each area is set up as a test group, and each test group includes 1 to 20 scratches, with each scratch having the same specifications.

8. The measurement method according to claim 7, characterized in that, The scratches in each test group are distributed along a straight line, which serves as the baseline for the scratch distribution of that test group. The baselines for scratch distribution in different test groups are set to coincide or parallel. If the baselines for scratch distribution in adjacent test groups do not coincide, then the distance between the corresponding baselines for scratch distribution is greater than three times the length of a single scratch.

9. The measurement method according to claim 1, characterized in that, The pressure applied by the probe tip is 0–3000 mN; the scratch length is 20–1000 μm; the speed is 0.05–20 μm / s; the scratching time is 0.5–200 s; the scratch width is 5–100 μm; the scratch depth is 0.05–5 μm; the scratch direction is straight and is obtained by the probe tip unidirectionally scratching along the surface of the upper material layer.

10. The measurement method according to any one of claims 1 to 9, characterized in that, After the measurement is completed, use SEM, AFM or confocal microscope to observe the scratch morphology and confirm the failure mode of the bond interface to be tested. If the failure occurs in the upper material layer and / or the lower material layer rather than the interface, the test parameters need to be adjusted and the measurement repeated.

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