A method for testing bonding energy of d2w hybrid bonding

Abstract

The application relates to a D2W mixed bonding bonding energy test method, and belongs to the field of semiconductor device detection. At least one of the problems that the D2W mixed bonding bonding energy test method has a large bonding interface damage, poor applicability and compatibility, poor measurement precision, and cannot directly obtain an energy unit is solved. The test method comprises the following steps: providing a D2W mixed bonding sample; thinning a chip located above a to-be-detected bonding interface to a target thickness; applying pressure on the surface of the thinned chip by using a conical nano-probe head; measuring the radius of a delamination cavity area by using a focused ion beam-scanning electron microscope technology or AFM; and calculating the bonding energy. The application realizes high-precision measurement of the bonding energy of different bonding interfaces in D2W mixed bonding, the test method is non-destructive, is suitable for various D2W samples, has good compatibility, and the measurement result is expressed in an energy unit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, and in particular to a method for testing the bonding energy of D2W hybrid bonding. Background Technology

[0002] Under the constraints of Moore's Law, hybrid bonding technology is a crucial core process for achieving higher interconnect density and integration of chips. Die-to-wafer (D2W) hybrid bonding technology typically employs bumpless interconnects between a dielectric layer and Cu-Cu metal to achieve high-density, low-power 3D integration. Bond energy is a vital indicator of bond quality. By measuring bond energy, the strength of the bond interface can be determined, preventing contact failures caused by low bond energy. Good bond energy generally translates to stronger mechanical and electrical connections, ensuring that the chip is less prone to peeling, breakage, or performance degradation in subsequent processes.

[0003] Compared to wafer-to-wafer (W2W) hybrid bonding technology, the bonding energy measurement technology for D2W hybrid bonding is not yet mature. Traditional W2W bonding typically uses the blade method (also known as the crack propagation diffusion method) to measure wafer bonding energy. However, in D2W hybrid bonding technology, due to the smaller chip size, more bonding layers, and difficulty in separating the bonding interfaces, it is impossible to measure the bonding energy using the blade method as in W2W hybrid bonding. Although ultrasonic microscopy (C-SAM) can usually be used to scan and obtain the void distribution at the D2W hybrid bonding interface, interface voids cannot fully reflect the actual bonding energy intensity. Therefore, a method suitable for D2W hybrid bonding is still needed to quantitatively test the interface bonding energy to characterize the actual bonding quality. Summary of the Invention

[0004] In view of the above analysis, the present invention aims to provide a bonding energy testing method for D2W hybrid bonding, in order to solve at least one of the problems existing in the bonding energy testing method for D2W hybrid bonding, such as large destructiveness of the bonding interface, poor measurement accuracy, poor applicability and compatibility, and inability to directly obtain energy units.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] This invention provides a method for testing the bonding energy of D2W hybrid bonding, comprising:

[0007] A D2W hybrid bonding sample is provided, comprising a wafer and chips located on the wafer, wherein the chips are single-layer chips or multi-layer chips, and multi-layer chips are composed of multiple chips stacked in multiple layers; the D2W hybrid bonding sample includes one or more bonding interfaces to be tested, wherein the bonding interface to be tested is the interface between adjacent chips or the interface between adjacent chips and the wafer.

[0008] The bonding energy test for each of the bonding interfaces to be tested includes:

[0009] (a) Thin the chip located above the bonding interface to be tested to the target thickness to ensure that there are no other bonding interfaces between the thinned chip surface and the bonding interface to be tested.

[0010] (b) Apply pressure to the thinned chip surface using a conical nanoprobe indenter. This will create nanoindentations on the thinned chip surface and simultaneously form a layered cavity region at the bonding interface to be tested. Stop applying pressure when the nanoprobe indentation depth reaches the termination threshold p.

[0011] (c) The radius r of the layered cavity region is measured using focused ion beam scanning electron microscopy (FIB-SEM) or AFM; the bonding energy is calculated according to formula (1);

[0012]

[0013] Among them, G c Bond energy, measured in J / m 2 E f t is the Young's modulus of the area contacted by the nanoprobe indenter, in Pa; h is the thickness of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip, in meters; t is the depth of the nanoindentation, in meters; θ is the cone angle of the nanoprobe indenter, in degrees; and r is the radius of the layered cavity region caused by the nanoindentation, in meters.

[0014] Furthermore, the target thickness is H, and H is between 0.1 μm and 10 μm; based on the target thickness H, the requirement for the termination threshold p is divided into two intervals:

[0015] First interval: When 0.1μm≤H≤1.0μm, the termination threshold p≤10%H;

[0016] Second interval: When 1.0μm < H ≤ 10μm, the termination threshold p ≤ 5%H.

[0017] Furthermore, when the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip is ≥5%, the target thickness H and the termination threshold p are selected from the first interval.

[0018] When the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip is <5%, the target thickness H and the termination threshold p are selected from the second interval.

[0019] Furthermore, the measurement of the radius r of the layered cavity region using focused ion beam scanning electron microscopy includes: vertically cutting the chip surface at the center of the nanoindentation using a focused ion beam to expose the longitudinal section of the layered cavity region, and measuring and determining the radius r of the cavity region; and / or,

[0020] In step (c), the bonding energy of the bonding interface to be tested is determined by taking the average value of the bonding energy at multiple points on the thinned chip surface.

[0021] Furthermore, the nanoindentation center region extends radially outward from the indentation center, and the extension distance r0 ≤ 10%D; D is the maximum diameter of the nanoindentation on the chip surface.

[0022] Furthermore, the multi-point measurement includes: selecting M measurement areas on the thinned chip surface, and selecting N test points in each measurement area;

[0023] Where M≥3, N≥3, and the minimum distance between test points within each test area is ≥10×p max p max This represents the maximum depth of the nanoprobe.

[0024] Furthermore, the bonding interface under test has at least two layers; the minimum distance between the measurement areas of each bonding interface under test along the chip surface is ≥20×p. max p max This represents the maximum depth of the nanoprobe.

[0025] Furthermore, the chip also includes multiple metal pads, which are arranged in an array on the thinned chip surface, with dielectric material between the metal pads;

[0026] The bonding energy of the bonding interface to be tested includes: metal-metal bonding energy, dielectric-dielectric bonding energy, and metal-dielectric mixed bonding energy.

[0027] Furthermore, regarding the dielectric-dielectric bonding energy, the target thickness H is 1μm-5μm, and the pressure applied to the thinned chip surface includes: a downward pressure of 5mN-100mN, and a termination threshold p of 1%H to 5%H; or,

[0028] For metal-metal bonding energy, the target thickness H is 200nm-1μm, and the pressure applied to the thinned chip surface includes: a downward pressure of 1mN-50mN and a termination threshold p of 2%H-10%H.

[0029] Furthermore, when the elongation of the material of the chip under test after thinning is <5%, M is 3-8 and N is 5-10; or,

[0030] When the elongation of the material of the chip under test after thinning is ≥5%, M is 3-5 and N is 3-5.

[0031] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0032] This invention proposes a test method for measuring the bonding energy of D2W hybrid bonding in three-dimensional integration technology using nanoindentation. The method involves applying pressure to the thinned chip surface using a conical probe indenter. Compared to other indenters, the nanoindentation and layered cavities formed by the conical indenter are more regular, facilitating subsequent analysis of the layered cavities. The radius of the layered cavities is measured with high precision using FIB-SEM or AFM, and the bonding energy at the bonding interface is accurately calculated using a formula. Based on this test method, the beneficial effects of this invention include:

[0033] (1) The present invention effectively avoids the damage problem caused by the traditional blade method of inserting into the bonding interface. By applying nanoindentation to the surface of the D2W bonded sample, the critical energy required for interface damage is obtained, and the bonding energy of the bonding interface is calculated.

[0034] (2) The nanoindentation method of the present invention has a testing range in the nanometer or micrometer range, and can be compatible with the bonding energy test of D2W hybrid bonding of chips of various sizes. In particular, it can accurately measure the bonding energy of dielectric-dielectric bonding, metal-metal bonding, and metal-dielectric hybrid bonding on the chip.

[0035] (3) The test method of the present invention is a non-destructive test. The measurement process has a small impact on the bonding interface of the D2W sample. In some embodiments, the same sample can be measured multiple times, which is convenient for repeated verification.

[0036] (4) The test method of the present invention is highly adaptable to the size of D2W samples and can measure the bonding energy without special processing molds.

[0037] (5) The test method of the present invention is compatible with multilayer chips and can effectively measure the bonding energy between different bonding interfaces of multilayer chip D2W hybrid bonding samples.

[0038] (6) The D2W bonding energy calculated by the test method of this invention is expressed in units of energy density (J / m³). 2 The test units are consistent with those of the W2W blade method, allowing for comparison. Traditional direct pull and shear methods can only obtain the interfacial force (N) or pressure (MPa), which cannot be directly compared with energy units.

[0039] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0040] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0041] Figure 1 This is a schematic diagram illustrating the effect of nanoindentation on the bonding interface according to an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram showing the point at which the nanoprobe pressure depth reaches the termination threshold in an embodiment of the present invention.

[0043] Figure 3 This is a schematic diagram of the bonding energy testing process for D2W bonding of multilayer chips according to an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of the bonding energy testing process for single-layer chip D2W bonding according to an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram illustrating the testing of metal-metal bonding energy and dielectric-dielectric bonding energy in D2W hybrid bonding according to an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram illustrating the testing of metal-dielectric hybrid bonding energy in D2W hybrid bonding according to an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of a sampling method for measuring bonding energy using nanoindentation, according to an embodiment of the present invention.

[0048] Figure 8 This is a schematic diagram of a longitudinal FIB cutting method for measuring bonding energy using nanoindentation, as described in an embodiment of the present invention.

[0049] Figure label:

[0050] 1-Nano probe indenter; 2-Thinned chip; 3-Layered cavity; 10-First chip; 20-Second chip; 30-Third chip; 40-First wafer; 101-First substrate layer; 102-First dielectric layer; 201-Second substrate layer; 202-Second dielectric layer; 301-Third substrate layer; 302-Third dielectric layer; 10'-Thinned first chip; 20'-Thinned second chip; 30'-Thinned third chip; 101'-Surface of thinned first chip; 201'-Surface of thinned second chip; 301'-Surface of thinned third chip; a-First thinning; b-Second thinning; c-Third thinning; 50-Fourth chip; 60-Second wafer; 501-Fourth substrate layer ; 502 - Fourth dielectric layer; 50' - Thinned fourth chip; 501' - Thinned fourth chip surface; 70a - Third wafer; 80a' - Thinned fifth chip; 70b - Fourth wafer; 80b' - Thinned sixth chip; 81 - Metal pad; 90 - Test point; 901 - First nanoindentation for measuring metal-metal bonding energy; 902 - Second nanoindentation for measuring dielectric-dielectric bonding energy; 903 - Third nanoindentation for measuring metal-dielectric mixed bonding energy; 70c - Fifth wafer; 80c' - Thinned seventh chip; 70d - Sixth wafer; 80d' - Thinned eighth chip; A - Sampling area; B - Nanoindentation; C - Cutting area; p - Nanoprobe indentation depth. Detailed Implementation

[0051] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0052] Wafer-to-wafer (W2W) bonding is relatively easy to test due to its fewer bonding layers, larger wafer size, and regular surface and shape. For example, the traditional blade bonding method can effectively evaluate its bond strength. However, chip-to-wafer (D2W) bonding presents several challenges for bond energy testing due to the following characteristics:

[0053] (a) Small chip size and many layers: In D2W bonding, the chip size is much smaller than the wafer and there are many layers, which increases the complexity of the bonding interface.

[0054] (b) Different chip shapes and layers: The different chip shapes and layers in different regions of the wafer increase the complexity of bonding energy testing.

[0055] (c) Higher bond strength: D2W bond strength is usually higher than W2W, making the bond interface difficult to separate.

[0056] These factors combined make D2W bonding energy testing far more difficult than W2W bonding. The blade bonding method commonly used in traditional W2W bonding is not suitable for D2W bonding. The blade bonding method can only roughly measure the bonding energy of interfaces with basically the same structure on both sides, and cannot achieve targeted measurement of the bonding energy between different chip layers or between the chip and the wafer in D2W.

[0057] To address the difficulty in measuring D2W bonding energy in existing technologies, the inventors, after research, conceived of using nanoindentation technology to measure the bonding energy of D2W hybrid bonds. The measurement principle is as follows: the upper chip layer of the D2W hybrid bond sample at the bonding interface to be measured is thinned. Pressure is then applied to the thinned chip layer 2 using the nanoprobe indenter 1 to create a nanoindentation. When the pressure load reaches a certain level, a layered cavity 3 with a ring indentation is formed between the thinned upper chip layer and the lower chip layer or the wafer bonding interface. Figure 1 As shown, the bonding interface of the D2W hybrid bond is destroyed. The bonding energy of the D2W hybrid bond sample is obtained by calculating the amount of energy required to destroy the bonding interface.

[0058] However, in practical measurements, due to factors such as the small chip size and numerous layers in D2W bonding, achieving accurate measurement of the bonding energy at each interface layer is challenging. To overcome these challenges and achieve accurate measurement of the D2W bonding energy, the inventors, after in-depth research, proposed the following technical solution based on the aforementioned measurement principle:

[0059] This invention provides a method for testing the bonding energy of D2W hybrid bonding, comprising:

[0060] A D2W hybrid bonding sample is provided, comprising a wafer and chips located on the wafer, wherein the chips are single-layer chips or multi-layer chips, and multi-layer chips are composed of multiple chips stacked in multiple layers; the D2W hybrid bonding sample includes one or more bonding interfaces to be tested, wherein the bonding interface to be tested is the interface between adjacent chips or the interface between adjacent chips and the wafer.

[0061] The bonding energy test for each bonding interface to be tested includes:

[0062] (a) Thin the chip located above the bonding interface to be tested to the target thickness to ensure that there are no other bonding interfaces between the thinned chip surface and the bonding interface to be tested.

[0063] (b) Apply pressure to the thinned chip surface using a conical nanoprobe indenter. This will create nanoindentations on the thinned chip surface and simultaneously form a layered cavity region at the bonding interface to be tested. Stop applying pressure when the nanoprobe indentation depth reaches the termination threshold p.

[0064] (c) The radius r of the layered cavity region is measured using focused ion beam scanning electron microscopy (FIB-SEM) or AFM; the bonding energy is calculated according to formula (1);

[0065]

[0066] Among them, G c Bond energy, measured in J / m 2 E f t is the Young's modulus of the area contacted by the nanoprobe indenter, in Pa; h is the thickness of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip, in meters; t is the depth of the nanoindentation, in meters; θ is the cone angle of the nanoprobe indenter, in degrees; and r is the radius of the layered cavity region caused by the nanoindentation, in meters.

[0067] Specifically, the Young's modulus E of the area contacted by the nanoprobe indenter f The Young's modulus of thin film materials is obtained by means of existing technology. For example, the nanoindentation method is used, in which pressure is applied to the sample surface by a probe, and the deformation response of the sample is measured to obtain the Young's modulus of the area in contact with the nanoprobe indenter. The area in contact includes a medium, a metal or a combination thereof.

[0068] Specifically, the depth t of the nanoindentation is the depth of the nanoindentation formed on the thinned chip surface. The depth of the nanoindentation can be measured by SEM in FIB-SEM or AFM (atomic force microscopy).

[0069] Specifically, the nanoprobe indentation depth p is the probe indentation depth set by the nanoindenter.

[0070] Specifically, each of the chips comprises one or more layers. For chips with a multilayer structure, the layer directly adjacent to the bonding interface under test is defined as the bonding material layer, while all other layers above the bonding material layer are collectively referred to as the substrate layer.

[0071] Compared with existing technologies, this invention proposes a test method for measuring the bonding energy of D2W hybrid bonding in three-dimensional integration technology using nanoindentation. This test method applies pressure to the thinned chip surface using a conical probe indenter. Compared to other indenters, the nanoindentation and layered cavities formed by the conical indenter are relatively more regular, facilitating subsequent analysis of the layered cavities. The radius of the layered cavities is measured with high precision using FIB-SEM or AFM, and the bonding energy at the bonding interface is accurately calculated using formulas. Based on this test method, the beneficial effects of this invention include:

[0072] (1) The present invention effectively avoids the damage problem caused by the traditional blade method of inserting into the bonding interface. By applying nanoindentation to the surface of the D2W bonded sample, the critical energy required for interface damage is obtained, and the bonding energy of the bonding interface is calculated.

[0073] (2) The nanoindentation method of this invention has a testing range in the nanometer or micrometer range, and is compatible with the bonding energy testing of D2W hybrid bonding on chips of various sizes. In particular, it can precisely measure the dielectric-dielectric bonding energy, metal-metal bonding energy, and metal-dielectric hybrid bonding energy on the chip, such as... Figure 5 and Figure 6 As shown.

[0074] (3) The test method of the present invention is a non-destructive test, and the measurement process has a small impact on the bonding interface of the D2W sample; in some embodiments, the same sample can be measured multiple times, which is convenient for repeated verification.

[0075] (4) The test method of the present invention is highly adaptable to the size of D2W samples and can measure the bonding energy without special processing molds.

[0076] (5) The test method of the present invention is compatible with multilayer chips and can effectively measure the bonding energy between different bonding interfaces of multilayer chip D2W hybrid bonding samples.

[0077] (6) The D2W bonding energy calculated by the test method of this invention is expressed in units of energy density (J / m³). 2 The test units are consistent with those of the W2W blade method, allowing for comparison. Traditional direct pull and shear methods can only obtain the interfacial force (N) or pressure (MPa), which cannot be directly compared with energy units.

[0078] In some embodiments, the testing method of the present invention can be applied to the interfacial bonding energy testing of single-layer or multi-layer chip D2W hybrid bonding samples. The single-layer chip D2W hybrid bonding testing method is to directly measure the bonding energy using a nanoindenter after thinning the chip. When measuring multi-layer chip D2W hybrid bonding, the bonding energy of different bonding interfaces can be measured separately.

[0079] In some embodiments, the multilayer chip D2W hybrid bonding sample includes a wafer and multiple chips stacked on the wafer, each chip including one or more layers of structure. The multilayer chip D2W hybrid bonding sample includes one or more bonding interfaces to be tested. For example, in order of distance from the wafer, it includes the first bonding interface to be tested, the second bonding interface to be tested, the third bonding interface to be tested, ..., the (N-1)th bonding interface to be tested, and the Nth bonding interface to be tested; N≥1. The bonding energy is tested layer by layer from the first bonding interface to the Nth bonding interface to be tested.

[0080] For example, such as Figure 3 The multilayer chip D2W hybrid bonding sample includes a first wafer 40 and three chips stacked on the first wafer 40, arranged from farthest to closest to the first wafer 40 as a first chip 10, a second chip 20, and a third chip 30. The first chip 10 includes a first substrate layer 101 and a first dielectric layer 102; the second chip 20 includes a second substrate layer 201 and a second dielectric layer 202; and the third chip 30 includes a third substrate layer 301 and a third dielectric layer 302. The testing process includes:

[0081] (1) By first thinning a, the first chip 10 is thinned to the target thickness. A nano probe indenter is used to apply pressure to the surface 101' of the thinned first chip. When the pressure depth reaches the termination threshold, the pressure is stopped. Then the radius r of the layered cavity region is measured, and the bonding energy of the first layer bonding interface to be tested (i.e. the bonding interface between the first chip 10 and the second chip 20) is calculated.

[0082] (2) By the second thinning b, the second chip 20 is thinned to the target thickness. A nano probe indenter is used to apply pressure to the surface 201' of the thinned second chip. When the indentation depth reaches the termination threshold, the pressure is stopped. Then the radius r of the layered cavity region is measured, and the bonding energy of the second layer bonding interface to be tested (i.e. the bonding interface between the second chip 20 and the third chip 30) is calculated.

[0083] (3) By thinning the third chip c, the third chip 30 is thinned to the target thickness. A nano probe is used to apply pressure to the surface 301' of the thinned third chip. When the pressure depth reaches the termination threshold, the pressure is stopped. Then the radius r of the layered cavity region is measured, and the bonding energy of the third bonding interface to be tested (i.e. the bonding interface between the third chip 30 and the first wafer 40) is calculated.

[0084] In some embodiments, the monolayer chip D2W hybrid bonding sample includes a wafer and a monolayer chip located on the wafer, the monolayer chip comprising one or more layers of structure.

[0085] For example, such as Figure 4 The single-layer chip D2W hybrid bonding sample includes a second wafer 60 and a single-layer chip, namely a fourth chip 50, located on the second wafer 60. According to the distance from the second wafer 60 from far to near, the fourth chip 50 includes a fourth substrate layer 501 and a fourth dielectric layer 502. The testing process includes: thinning the fourth chip 50 to the target thickness, applying pressure to the surface 501' of the thinned fourth chip with a nanoprobe indenter, stopping the application of pressure when the indentation depth reaches the termination threshold, and then measuring the radius r of the layered cavity region to calculate the bonding energy of the bonding interface to be tested (i.e., the bonding interface between the fourth chip 50 and the second wafer 60).

[0086] In some embodiments, the thickness of the chip is 10μm-900μm.

[0087] Before testing, the chip located above the bonding interface to be tested is thinned to a target thickness, H, which is 0.1 μm-10 μm. It can be understood that the target thickness H is the vertical distance between the thinned chip surface and the bonding interface to be tested.

[0088] The chip's layer structure material is selected from dielectric, metal, and two-dimensional materials.

[0089] The dielectric is selected from at least one of semiconductors, ceramics, and polymers; wherein the semiconductor includes Si, SiCN, and SiO2. The ceramic includes Al2O3. The polymer includes polymethyl methacrylate (PMMA) and polydimethylsiloxane (PDMS).

[0090] The two-dimensional material includes graphene. The metal includes copper and aluminum.

[0091] The inventors comprehensively considered the material characteristics and deformation behavior of the thinned chip subjected to the nanoprobe indentation. To ensure the accuracy and reliability of bonding energy testing under different materials, preferably, the termination threshold p requirement is divided into two intervals based on the target thickness H:

[0092] First interval: When 0.1μm≤H≤1.0μm, the termination threshold p≤10%H;

[0093] Second interval: When 1.0μm < H ≤ 10μm, the termination threshold p ≤ 5%H.

[0094] Furthermore, based on the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip, the corresponding range is selected:

[0095] Preferably, when the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip is ≥5%, the target thickness H and the termination threshold p are selected from the first interval.

[0096] When the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip is <5%, the target thickness H and the termination threshold p are selected from the second interval.

[0097] It should be noted that the elongation of the bonding material layer directly adjacent to the bonding interface under test in the thinned chip (e.g., Figure 3When the brittleness of 102, 202, or 302 is low (elongation ≥ 5%), in order to ensure measurement accuracy and avoid substrate effect, a thinner target thickness (0.1 μm ≤ H ≤ 1.0 μm) is preferred, and the termination threshold of the pressing depth is not greater than 10% of the target thickness; the above preferred settings can further improve measurement accuracy.

[0098] When the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip (e.g., Figure 3 When the 102, 202, or 302 alloys used in the test have high brittleness (elongation < 5%), in order to ensure measurement accuracy and avoid boundary effects, a thicker target thickness (1.0 μm < H ≤ 10 μm) is preferred, and the termination threshold of the pressing depth should not be greater than 5% of the target thickness; the above preferred settings can further improve measurement accuracy.

[0099] It is understandable that by controlling the target thickness and pressing depth according to the material characteristics of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip, it is beneficial to improve the adaptability of the test method to test the more complex different types of bonding interfaces in D2W, and to ensure the accuracy of the test.

[0100] It should be noted that determining the radius r of the layered cavity region in formula (1) is one of the key steps to ensure the accuracy and reliability of the measurement results. In actual measurements, when the nanoprobe indenter applies pressure to the thinned chip surface, the layered cavity does not strictly follow a regular ring shape, especially for materials with high brittleness. To improve the reliability of the test results, it is preferable to improve accuracy by averaging multiple points and regions. Preferably, the measurement of the radius r of the layered cavity region using focused ion beam scanning electron microscopy includes: using a focused ion beam to vertically cut the central region of the nanoindentation on the chip surface to expose the longitudinal section of the layered cavity region, and measuring and determining the radius r of the cavity region.

[0101] It should be noted that focused ion beam (FIB) technology is used to perform precise vertical cutting in the central region of the nanoindentation. This method allows for accurate measurement of the radius of the longitudinal section of the layered cavity. This measurement accurately reflects the actual area of ​​the layered cavity, ensuring that the calculated bonding energy more accurately represents the critical energy for interface failure. Such precise measurement and calculation are crucial for adapting to the complex interface energy testing of different types of bonding in D2W (chip-to-wafer) bonding, while also ensuring the accuracy of the testing.

[0102] It is understood that in the vertical cutting, a focused ion beam (FIB) is used to perform longitudinal cutting along a direction perpendicular to the chip surface. Preferably, the depth of the longitudinal cut is equal to the target thickness to ensure that the bonding interface to be tested on the underlying layer is not affected. Preferably, the longitudinal cutting region C is rectangular, forming a rectangular groove after the longitudinal cut.

[0103] In some embodiments, the vertical cut is performed once or multiple times. In particular, when the vertical cut exposes an irregular layered cavity, it is preferable that the vertical cut is performed multiple times; in this case, the radius value of the layered cavity region exposed by each vertical cut is measured separately; then, the radius values ​​of the multiple layered cavity regions corresponding to the multiple vertical cuts are averaged to obtain the radius r of the layered cavity region formed by the bonding interface under test after applying pressure at the measurement point.

[0104] Furthermore, during focused ion beam (FIB) cutting, a well-designed nanoindentation center region helps ensure that the measurement results more closely approximate the actual bonding energy of the bonding interface. Preferably, the nanoindentation center region extends radially outward from the indentation center, with an extension distance r0 ≤ 10%D; where D is the maximum diameter of the nanoindentation on the chip surface. Layered cavities typically form near the indentation center. By limiting the cutting area to the vicinity of the indentation center and not exceeding 10% of the maximum diameter, it can be ensured that the cut profile accurately reflects the actual situation of the layered cavities of the bonding interface, improving measurement accuracy. This standardized cutting area setting not only reduces measurement errors but also improves the repeatability and comparability of multi-region, multi-point measurement results.

[0105] For example, a vertical cut is made in the central region of the nanoindentation on the chip surface. The cut region C is rectangular, and it is ensured that both long sides of the rectangle intersect with the central region of the nanoindentation.

[0106] In some embodiments, in step (c), in order to more comprehensively reflect the true situation of the bonding interface and reduce the influence of random errors, the bonding energy of the bonding interface to be tested is determined by taking the average value of the bonding energy of the multiple points by performing multi-point measurements on the thinned chip surface.

[0107] Preferably, the multi-point measurement includes: selecting M measurement areas on the thinned chip surface, and selecting N test points in each measurement area;

[0108] Where M≥3, N≥3, and the minimum distance between test points within each test area is ≥10×p max p max This represents the maximum depth of the nanoprobe. This requirement ensures the independence between test points, avoids stress overlap, and ensures that the measurement results of each test point are not affected by adjacent test points, thereby improving the accuracy of the measurement.

[0109] It should be noted that the maximum indentation depth of the nanoprobe refers to the maximum indentation depth of the nanoprobe among all measurement points on the D2W hybrid bonded sample during measurement. This depth value is controlled by the nanoindenter according to preset parameters during the indentation process. For example, M is 3 to 20, and N is 1 to 30.

[0110] In some embodiments, the bonding interface under test has at least two layers; preferably, the minimum distance between the measurement areas of each bonding interface under test along the chip surface is ≥20×p. max p max This represents the maximum depth of the nanoprobe. This requirement ensures the independence and reliability of measurement results between different bonding interfaces, effectively avoids mutual interference between different bonding interfaces, and ensures that the measurement results of each bonding interface are not affected by other interfaces. This improves the accuracy of multilayer bonding interface measurements and enhances the adaptability of the test method to test more complex and different types of bonding interfaces in D2W, while also ensuring test accuracy.

[0111] In some embodiments, the chip further includes multiple metal pads arranged in an array on the thinned chip surface, with dielectric material between the metal pads; the bonding energy of the bonding interface under test includes: metal-metal bonding energy, dielectric-dielectric bonding energy, and metal-dielectric hybrid bonding energy. The metal pads realize the vertical interconnection of the chip in D2W hybrid bonding.

[0112] like Figure 5 The D2W hybrid bonding sample includes a third wafer 70a and a multilayer stacked chip on the third wafer 70a. When the first nanoindentation 901 is located on the metal pad 81 on the surface of the thinned fifth chip 80a', the metal-metal bonding energy is measured. When the second nanoindentation 902 is located on the dielectric on the surface of the thinned fifth chip 80a', the dielectric-dielectric bonding energy is measured.

[0113] like Figure 6 The D2W hybrid bonding sample includes a fourth wafer 70b and a multilayer stacked chip on the fourth wafer 70b. When the contact area between the third nanoindentation 903 and the surface of the thinned sixth chip 80b' includes both metal pads and dielectric, the metal-dielectric hybrid bonding energy is measured.

[0114] In one embodiment, such as Figure 7 The D2W hybrid bonding sample includes a fifth wafer 70c and a thinned seventh chip 80c' surface located on the fifth wafer 70c. The sampling area A (i.e., the measurement area) consists of 5 points, and each sampling area (i.e., the measurement area) includes 5 test points 90.

[0115] Optionally, the pressing pressure of the nanoprobe indenter is 1mN-2000mN, and the pressing time is 1-200s. Exemplarily, the pressing pressure is 1mN, 20mN, 50mN, 80mN, 100mN, 150mN, 300mN, 500mN, or 1000mN. The pressing time is 1s, 2s, 5s, 10s, 20s, 50s, or 100s. Preferably, the pressing pressure is 1mN-500mN, and the pressing time is 5s-15s.

[0116] In some preferred embodiments, for dielectric-dielectric bonding energy, the target thickness H is 1μm-5μm, and the pressure applied to the thinned chip surface includes: a downward pressure of 5mN-100mN and a termination threshold p of 1%H to 5%H.

[0117] In some preferred embodiments, for metal-metal bonding energy, the target thickness H is 200 nm-1 μm, and the pressure applied to the thinned chip surface includes: a downward pressure of 1 mN-50 mN and a termination threshold p of 2% H to 10% H.

[0118] In some preferred embodiments, when the elongation of the material of the chip under test after thinning is <5% (e.g., Si, SiCN, SiO2), M is 3-8 and N is 5-10; M is the number of measurement areas selected for the same bonding interface under test, and N is the number of test points in each measurement area.

[0119] In some preferred embodiments, when the elongation of the material of the chip under test after thinning is ≥5% (e.g., Cu, Al, PDMS), M is 3-5 and N is 3-5; M is the number of measurement areas selected for the same bonding interface under test, and N is the number of test points in each measurement area.

[0120] It is understandable that, based on the material characteristics of the area contacted by the nanoprobe indenter, by controlling the downward pressure and termination conditions, and based on the material characteristics of the thinned chip, by controlling the measurement area and the number of test points in each measurement area, it is beneficial to improve the adaptability of the test method to the more complex different types of bonding interfaces in D2W, and to ensure the accuracy of the test while taking into account the efficiency of the measurement.

[0121] Optionally, the thinning method includes dry etching, wet etching, mechanical polishing, and ion beam etching. Considering measurement accuracy, ease of operation, and minimizing the impact of testing the upper bonding interface on the lower bonding interface, the preferred thinning method is dry etching or wet etching.

[0122] In some embodiments, the dry etching step includes:

[0123] (1) Coat the chip surface to be thinned with photoresist, expose and develop it to define the area to be etched;

[0124] Before applying photoresist, the process also includes cleaning the chip surface to be thinned; the cleaning includes washing the chip surface with deionized water and / or organic solvents.

[0125] (2) Dry etching is performed on the area to be etched;

[0126] The gas used for dry etching is selected from at least one of SF6, CF4, and O2;

[0127] The equipment used for the dry etching process is either reactive ion etching (RIE) or inductively coupled plasma (ICP) etching.

[0128] The parameters for the dry etching method include: power of 100-500W; gas pressure of 10-100 mTorr; gas flow rate of 10-100 sccm; and etching time of 1 min to 60 min, with the specific etching time set according to the thickness to be reduced. For example, power can be 200W, 250W, 300W, 350W, or 400W; gas pressure can be 20 mTorr, 40 mTorr, 60 mTorr, or 80 mTorr; gas flow rate can be 20 sccm, 40 sccm, 60 sccm, or 80 sccm; and etching time can be 2 min, 5 min, 10 min, 15 min, 20 min, 30 min, 40 min, or 50 min.

[0129] Preferably, the gas used for dry etching is SF6; the power is 250-350W; the gas pressure is 40-60mTorr; the gas flow rate is 40-60sccm; and the etching time is 5-15min.

[0130] (3) After etching, remove the photoresist and clean the thinned chip surface; for example, use oxygen plasma or photoresist remover to remove the photoresist.

[0131] In some embodiments, the wet etching step includes:

[0132] (1) Coat the chip surface to be thinned with photoresist, expose and develop it to define the area to be etched;

[0133] Before applying photoresist, the process also includes cleaning the chip surface to be thinned; the cleaning includes washing the chip surface with deionized water and / or organic solvents.

[0134] (2) Perform wet etching on the area to be etched;

[0135] The etching solution used in the wet etching process includes at least one of KOH, TMAH, and HF.

[0136] Preferably, the concentration of KOH is 20%–40%, the concentration of TMAH is 5%–25%, and the concentration of HF is 1%–10%. Exemplarily, the concentrations of KOH are 25%, 27%, 30%, 32%, and 35%. Preferably, the concentration of KOH is 27%–32%.

[0137] Preferably, the etching temperature for KOH and TMAH is 50–80°C. Exemplarily, the etching temperatures are 60°C, 65°C, 70°C, and 75°C. More preferably, the etching temperature is 65°C–75°C.

[0138] Preferably, for HF, the etching temperature is room temperature.

[0139] Optionally, the etching time for the wet etching process is 1 min to 10 h; the specific etching time is set according to the thickness reduction. For example, the etching times are 10 min, 15 min, 20 min, 30 min, 40 min, 50 min, 1 h, 3 h, and 5 h. Preferably, the etching time is 20 to 40 min.

[0140] (3) After etching, remove the photoresist and clean the thinned chip surface; for example, use a photoresist remover to remove the photoresist.

[0141] It should be noted that the above-mentioned preferred etching parameters help ensure uniform etching, avoid local over-etching or under-etching, and effectively control and reduce the impact of upper-layer chip thinning on the lower-layer bonding interface, thereby ensuring measurement accuracy.

[0142] In some embodiments, step (c) above, the step of measuring the radius r of the layered cavity region using focused ion beam scanning electron microscopy (FIB-SEM), includes:

[0143] (1) SEM positioning of the indentation area;

[0144] Specifically, the sample surface is scanned using a low-magnification mode of SEM to determine the location of the nanoindentations, and the nanoindentations are marked with markers; for example, the markers include FIB-deposited platinum (Pt);

[0145] (2) FIB cutting and sample preparation;

[0146] Specifically, FIB was used to vertically cut the sample surface in the central region of the nanoindentation to expose the longitudinal section of the layered cavity region;

[0147] Preferably, during cutting, a first current of 1-10nA is used for coarse cutting, and then a second current of 100-500pA is used for fine polishing to reduce the damage to the sample surface caused by cutting.

[0148] (3) SEM is used to image the longitudinal section of the layered cavity region;

[0149] After the FIB cutting is completed, switch to SEM mode to perform high-resolution imaging of the longitudinal section of the layered cavity region and obtain an image of the longitudinal section of the layered cavity region.

[0150] In imaging, the accelerating voltage is set to 1–5 kV and the working distance is set to 4–6 mm to obtain images with high contrast and resolution.

[0151] (4) Measure the radius r of the layered cavity region;

[0152] Specifically, the longitudinal section images of the obtained layered cavity region are processed using FIB-SEM software or image analysis tools (such as ImageJ);

[0153] For example, the boundary of the layered cavity region is determined based on the image contrast. The center point of the cavity is selected on the image, and the distance from the center point to the boundary is measured, which is the radius r of the layered cavity region.

[0154] Specifically, in step (1), before locating the indentation area in the SEM, sample preparation is also included: cleaning the sample surface with a cleaning agent and fixing the sample on the FIB-SEM sample stage. In some embodiments, the sample preparation further includes: after cleaning, if the sample is not conductive, spraying a thin layer of gold or carbon film onto the surface of the chip under test to avoid charge accumulation.

[0155] Specifically, during the FIB-SEM testing process, ensure that the sample is in a high vacuum environment to avoid contamination and interference.

[0156] In some embodiments, step (c) above, measuring the radius r of the layered cavity region using AFM (atomic force microscopy), includes:

[0157] (1) Place the sample in the cavity of the AFM, scan it, and export the morphology image;

[0158] Specifically, before placing the sample, purge the sample surface with an inert gas (such as nitrogen) to clean it; firmly attach the sample to the AFM sample stage, ensuring the surface is flat (use conductive adhesive or double-sided tape if necessary); mark the target area: if the location of the layered cavity is known, it can be pre-positioned using an optical microscope; if unknown, a large-area scan is required for positioning.

[0159] (2) Based on the topography map, the radius r of the layered cavity region is obtained;

[0160] Specifically, using AFM software (such as NanoScope Analysis) or third-party tools (such as Gwyddion, ImageJ), a cross-sectional line spanning the cavity center is drawn on the topography image. The edge points of the layered cavity region are determined using a threshold method or derivative method. The distance D between the two edge points is measured, and the radius r = D / 2. If the cavity edge is not circular, the average value of the radius r in multiple directions is taken. During AFM scanning, the probe is preferably in tapping mode, the scanning resolution is at least 512×512, the scanning range covers at least twice the area of ​​the layered cavity, and the scanning frequency is 0.5-1Hz.

[0161] The aforementioned "sample" refers to the D2W hybrid bonding sample after the nanoprobe indenter has applied pressure to the thinned chip surface.

[0162] In some embodiments, in the D2W hybrid bonding sample of the present invention, the area of ​​the chip on the wafer is 1 mm². 2 -2500mm 2 For example, the chip area is 4mm². 2 9mm 2 16mm 2 25mm 2 36mm 2 49mm 2 64mm 2 100mm 2 400mm 2 900mm 2 1600mm 2 For example, the chip on the wafer is rectangular, with a length of 1mm to 50mm and a width of 1mm to 50mm. The chip includes bonded single-layer or multi-layer chips, wherein the thickness of each chip layer is 10μm to 900μm, and the number of bonding layers is 1 to 20. For example, the thickness of each chip layer is 20μm, 40μm, 60μm, 80μm, 100μm, 150μm, 200μm, 500μm, or 700μm. For example, the number of bonding layers is 5, 10, or 15.

[0163] In some embodiments, in the D2W hybrid bonding samples of the present invention, the wafer size before dicing is 2 inches to 12 inches. To facilitate small-size measurements in the laboratory, the wafer is diced into rectangles, squares, triangles, or other shapes, and the area of ​​the wafer after dicing is 1 mm². 2 -10000mm 2 For example, the wafer is cut into a rectangle or square with a length of 1mm-100mm and a width of 1mm-100mm.

[0164] The testing method described in this invention can be flexibly applied in both laboratories and FABs (semiconductor manufacturing plants) for mass production. In laboratory measurements, the wafer is often cut to a smaller size for measurement due to the potentially limited space of the nanoindenter chamber. However, in mass-production FABs, wafer cutting is unnecessary, and testing can be performed directly. This is primarily because industrial-grade nanoindenters typically have larger and more flexible chambers and testing platforms than laboratory equipment, capable of accommodating an entire wafer. Compared to traditional blade or tensile testing methods, this invention offers greater flexibility and testing accuracy, meeting both the needs of laboratory research on D2W material properties and the requirements of efficient, non-destructive testing in mass production, thus demonstrating broad application prospects.

[0165] The technical solution of the present invention will be further described in detail below with reference to specific embodiments and comparative examples.

[0166] Example 1:

[0167] This embodiment provides a method for testing the bonding energy of D2W hybrid bonding, including the following steps:

[0168] S1. Provide a D2W hybrid bonding sample, which includes a first wafer 40 and a three-layer bonded chip located on the first wafer 40, from top to bottom, including a first chip 10, a second chip 20 and a third chip 30; wherein, the first chip 10 includes a first substrate layer 101 and a first dielectric layer 102; the second chip 20 includes a second substrate layer 201 and a second dielectric layer 202; the third chip 30 includes a third substrate layer 301 and a third dielectric layer 302.

[0169] The first substrate layer 101, the second substrate layer 201 and the third substrate layer 301 are made of Si, and the first dielectric layer 102, the second dielectric layer 202 and the third dielectric layer 302 are made of SiCN.

[0170] The first wafer 40 is square after being cut, with a length and width of 20 mm. The chip on the first wafer 40 is square, with a length and width of 5 mm. The thickness of each chip layer is 50 μm, wherein the thickness of the first dielectric layer 102, the second dielectric layer 202 and the third dielectric layer 302 is 15 nm.

[0171] S2. The bonding energy test of the first layer bonding interface to be tested (the bonding interface between adjacent first chip 10 and second chip 20) includes:

[0172] (a) The first chip 10 is thinned to a target thickness of 4 μm using dry etching. Specifically, the surface of the first substrate layer 101 is cleaned, photoresist is coated on the cleaned surface of the first substrate layer 101, exposed and developed to define the area to be etched. The area to be etched is dry etched using an inductively coupled plasma (ICP) etching machine. The gas used for dry etching is SF6, the power is 300W, the gas pressure is 50 mTorr, the gas flow rate is 50 sccm, and the etching time is 10 min.

[0173] (b) Apply pressure to the thinned first chip surface 101' using a conical nanoprobe indenter. The pressure is 25 mN. Stop applying pressure when the indentation depth reaches the termination threshold p = 0.5 μm.

[0174] (c) The radius r of the layered cavity region was measured using focused ion beam scanning electron microscopy (FIB-SEM), including:

[0175] (1) SEM positioning of the indentation area;

[0176] Specifically, the sample surface was scanned using a low-magnification mode of SEM to determine the location of the nanoindentations, and platinum (Pt) was deposited using FIB to mark the nanoindentations.

[0177] (2) FIB cutting and sample preparation;

[0178] Specifically, the sample surface is vertically cut in the central region of the nanoindentation using FIB to expose the longitudinal section of the layered cavity region; the central region of the nanoindentation extends radially outward from the center of the indentation, and the extension distance r0 = 10%D; D is the maximum diameter of the nanoindentation; during cutting, a first current of 5nA is used for coarse cutting, and a second current of 250pA is used for fine polishing.

[0179] (3) SEM is used to image the longitudinal section of the layered cavity region;

[0180] After the FIB cutting is completed, switch to SEM mode to perform high-resolution imaging of the longitudinal section of the layered cavity region and obtain an image of the longitudinal section of the layered cavity region; during imaging, the accelerating voltage is set to 2.5kV and the working distance is set to 5mm.

[0181] (4) Measure the radius r of the layered cavity region;

[0182] Specifically, the longitudinal section image of the obtained layered cavity region is processed using FIB-SEM software; based on the image contrast, the boundary of the layered cavity region is determined, the center point of the cavity is selected on the image, and the distance from the center point to the boundary is measured, which is the radius r of the layered cavity region.

[0183] Taking one of the test points as an example, E f =78.65Gpa, h=15nm, t=0.5μm, r=1.8μm, θ=60°, the bonding energy G is calculated according to formula (1). c =1.56J / m 2 .

[0184] like Figure 7 As shown, steps (a) to (c) were repeated. Five measurement regions were selected on the thinned first chip surface 101', and five test points were selected in each measurement region. The bonding energy of the 25 test points was averaged to determine the bonding energy result of the first layer of the bonding interface under test, and the result was recorded in Table 1. The minimum distance between the measurement regions of each bonding interface under test parallel to the chip surface was ≥20 μm, and the minimum distance between the test points in each measurement region was ≥10 μm.

[0185] Repeat step S2 to determine the bonding energy of the second bonding interface to be tested (the bonding interface between the second chip 20 and the third chip 30) and the bonding energy of the third bonding interface to be tested (the bonding interface between the third chip 30 and the first wafer 40) in sequence, and record them in Table 1.

[0186] Table 1. Bonding energy test results of Example 1

[0187]

[0188]

[0189] Example 2

[0190] The difference between this embodiment and Embodiment 1 is that the first dielectric layer 102, the second dielectric layer 202, and the third dielectric layer 302 are made of SiO2; and the three-layer chip also includes multiple arrayed copper pads that penetrate the three layers, forming vertical interconnects and being arranged in a horizontal array, such as... Figure 5 and Figure 6 In step S2, the pressure area of ​​the nanoprobe indenter is limited to the dielectric, limited to the copper pads, or includes the dielectric and four copper pads. Steps (a) to (c) are repeated to obtain the SiO2 / SiO2 bonding energy, Cu / Cu bonding energy, and Cu / SiO2 mixed bonding energy, respectively. The remaining steps and parameters are similar to those in Example 1.

[0191] Table 2 shows the bonding energy test results of the first bonding interface in Example 2.

[0192]

[0193] Effect verification:

[0194] The bonding energy of a silicon dioxide bonding interface with copper pads (where both the copper pads and the silicon dioxide layer are relatively large) was tested using the traditional blade method, and the mixed bonding energy was found to be 2.51 J / m. 2 The Cu / SiO2 bonding energy measured using the test method of this invention (2.53 J / m) is compared with that in Table 2. 2 The degree of agreement is relatively high. Blade method: A blade is inserted into the bonding interface, the interface crack length is measured using C-SAM, and the bonding energy is calculated by substituting the measured length into the formula.

[0195] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for testing the bonding energy of D2W hybrid bonding, characterized in that, include: A D2W hybrid bonding sample is provided, comprising a wafer and chips located on the wafer, wherein the chips are single-layer chips or multi-layer chips, and multi-layer chips are composed of multiple chips stacked in multiple layers; the D2W hybrid bonding sample includes one or more bonding interfaces to be tested, wherein the bonding interface to be tested is the interface between adjacent chips or the interface between adjacent chips and the wafer. The bonding energy test for each of the bonding interfaces to be tested includes: (a) Thin the chip located above the bonding interface to be tested to the target thickness to ensure that there are no other bonding interfaces between the thinned chip surface and the bonding interface to be tested. (b) Apply pressure to the thinned chip surface using a conical nanoprobe indenter. This will create nanoindentations on the thinned chip surface and simultaneously form a layered cavity region at the bonding interface to be tested. Stop applying pressure when the nanoprobe indentation depth reaches the termination threshold p. (c) The radius r of the layered cavity region is measured using focused ion beam scanning electron microscopy (FIB-SEM) or AFM; the bonding energy is calculated according to formula (1); Among them, G c Bonding energy, measured in J / m 2 E f t is the Young's modulus of the area contacted by the nanoprobe indenter, in Pa; h is the thickness of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip, in meters; t is the depth of the nanoindentation, in meters; θ is the cone angle of the nanoprobe indenter, in degrees; and r is the radius of the layered cavity region caused by the nanoindentation, in meters.

2. The bonding energy testing method according to claim 1, characterized in that, The target thickness is H, and H is between 0.1 μm and 10 μm; based on the target thickness H, the required termination threshold p is divided into two intervals: First interval: When 0.1μm≤H≤1.0μm, the termination threshold p≤10%H; Second interval: When 1.0μm < H ≤ 10μm, the termination threshold p ≤ 5%H.

3. The bonding energy testing method according to claim 2, characterized in that, When the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip is ≥5%, the target thickness H and the termination threshold p are selected from the first interval. When the elongation of the bonding material layer directly adjacent to the bonding interface to be tested in the thinned chip is <5%, the target thickness H and the termination threshold p are selected from the second interval.

4. The bonding energy testing method according to claim 1, characterized in that, The method of measuring the radius r of the layered cavity region using focused ion beam scanning electron microscopy includes: making a vertical cut in the center region of the nanoindentation on the chip surface using a focused ion beam to expose the longitudinal section of the layered cavity region, and measuring and determining the radius r of the cavity region; and / or, In step (c), the bonding energy of the bonding interface to be tested is determined by taking the average value of the bonding energy at multiple points on the thinned chip surface.

5. The bonding energy testing method according to claim 4, characterized in that, The nanoindentation center region extends radially outward from the indentation center, with an extension distance r0 ≤ 10%D; D is the maximum diameter of the nanoindentation on the chip surface.

6. The bonding energy testing method according to claim 4, characterized in that, The multi-point measurement includes: selecting M measurement areas on the thinned chip surface, and selecting N test points in each measurement area; Where M≥3, N≥3, and the minimum distance between test points within each test area is ≥10×p max p max This represents the maximum depth of the nanoprobe.

7. The bonding energy testing method according to claim 6, characterized in that, The bonding interface to be tested has at least two layers; the minimum distance between the measurement areas of each bonding interface to be tested along the chip surface is ≥20×p. max p max This represents the maximum depth of the nanoprobe.

8. The bonding energy testing method according to claim 1, characterized in that, The chip also includes multiple metal pads, which are arranged in an array on the thinned chip surface, with dielectric material between the metal pads. The bonding energy of the bonding interface to be tested includes: metal-metal bonding energy, dielectric-dielectric bonding energy, and metal-dielectric mixed bonding energy.

9. The bonding energy testing method according to claim 8, characterized in that, For dielectric-dielectric bonding energy, the target thickness H is 1μm-5μm, and the pressure applied to the thinned chip surface includes: a downward pressure of 5mN-100mN, and a termination threshold p of 1%H-5%H; or... For metal-metal bonding energy, the target thickness H is 200nm-1μm, and the pressure applied to the thinned chip surface includes: a downward pressure of 1mN-50mN and a termination threshold p of 2%H-10%H.

10. The bonding energy testing method according to claim 6, characterized in that, When the elongation of the material of the chip under test after thinning is <5%, M is 3-8 and N is 5-10; or... When the elongation of the material of the chip under test after thinning is ≥5%, M is 3-5 and N is 3-5.

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