Xrt three-dimensional quantitative detection method for slip line defect depth of epitaxial silicon wafer

Abstract

The present application relates to a kind of XRT three-dimensional quantitative detection methods of slip line defect depth of epitaxial silicon wafer, the semiconductor silicon wafer precision detection technical field belongs to, including the nondestructive cleaning pretreatment of the silicon wafer to be detected;Adopt X-ray transmission mode to carry out full domain two-dimensional imaging, automatically locate slip line defect plane coordinate area;The incident light beam is adjusted to be parallel to the ultrathin sheet X-ray beam of silicon wafer surface, switch to layered slice scanning mode;Control stage is stepped along the thickness direction of silicon wafer, and multiple cross-section diffraction images are collected;Finally, three-dimensional reconstruction is carried out, the defect starting and ending depth layer is extracted, the total depth is calculated and quantitative parameter is output.Solve the problem that the existing detection means is strong, cannot three-dimensional quantitative measurement depth and detection efficiency is low.The nondestructive detection of silicon wafer and the micron level accurate quantification of slip line defect depth are realized, artificial subjective error is eliminated, detection efficiency and production line quality control consistency are improved, suitable for semiconductor silicon wafer large-scale industrialization full detection demand.

Description

Technical Field

[0001] This invention relates to the field of precision inspection technology for semiconductor silicon wafers, specifically to an XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers. Background Technology

[0002] Slip lines on silicon wafers are high-density dislocation bundle defects formed during the crystal growth, heat treatment, wafer fabrication, and epitaxial processes of single-crystal silicon under thermal or mechanical stress, resulting in plastic slippage of the crystal lattice along specific crystal planes. In semiconductor manufacturing, native lattice defects in the silicon substrate easily become stress release trigger sites for slip lines in epitaxial processes, while the epitaxial heating / cooling rates and thermal stress caused by intra-wafer temperature differences are the direct driving forces for slip line propagation. Slip lines form nanoscale lattice steps within the silicon wafer, leading to deterioration of the active region flatness of subsequent chip devices, increased reverse leakage current, and a significant decrease in chip yield, severely reducing the long-term operational reliability of semiconductor devices.

[0003] Currently, the industry mainstream uses two types of detection schemes to quantitatively characterize the depth and spatial distribution of slip line defects on silicon wafers, but both have unavoidable shortcomings in industrial application: I. Copper-embellished selective etching method: This method involves embellishing defects with copper ions, followed by chemical etching and magnification, and then manual observation. Its drawbacks are: it can only qualitatively observe planar morphology and cannot obtain three-dimensional depth data of slip lines penetrating the silicon wafer; it relies on manual experience, resulting in high detection dispersion and difficulty in standardizing quality control; it is a semi-destructive test, as the silicon wafer cannot be reflowed after etching, leading to significant material loss; and it is inefficient and unsuitable for full inspection.

[0004] II. TEM (Transmission Electron Microscopy) Inspection Method: This method involves cutting and thinning the sample before observing the cross-section. Its drawbacks include: it is a completely destructive inspection, resulting in the scrapping of high-value epitaxial wafers; the observation field is only at the micrometer level, making it impossible to screen the entire wafer and easily missing edge defects; sample preparation is cumbersome and time-consuming, with a long cycle, extremely low production capacity, and high cost.

[0005] 3. Conventional two-dimensional X-ray morphology (XRT): It can only output a two-dimensional projection contrast map of the full thickness of the silicon wafer. The depth information is mixed up, and it also cannot achieve quantitative measurement of the depth of defects. Summary of the Invention

[0006] This invention addresses the shortcomings of existing technologies by providing a three-dimensional quantitative XRT method for detecting slip line defects in epitaxial silicon wafers. This method overcomes the problems of high destructiveness, inability to quantitatively measure depth in three dimensions, and low efficiency of existing detection methods. It achieves non-destructive testing of silicon wafers and precise micron-level quantification of slip line defect depth, eliminating subjective human error, improving detection efficiency and production line quality control consistency, and is suitable for the large-scale industrial-scale full inspection requirements of semiconductor silicon wafers.

[0007] The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions: A three-dimensional quantitative XRT method for detecting the depth of slip line defects in epitaxial silicon wafers includes the following steps: Step 1: Perform non-destructive surface cleaning on the silicon wafer to be inspected to remove surface interference.

[0008] Step 2: Place the silicon wafer horizontally on a high-precision stage and perform optical path, angle, and intensity calibration.

[0009] Step 3: Use X-ray transmission mode to perform two-dimensional global imaging of the entire silicon wafer. Based on the high brightness contrast of the complete lattice and the dark pattern characteristics of the slip line defect area, identify and automatically mark the planar coordinates of the slip line defect area.

[0010] Step 4: Move the marked defect area on the silicon wafer to the center of the optical path, adjust the incident beam to an ultra-thin sheet-like X-ray beam parallel to the surface of the silicon wafer, and switch to the layered slicing scanning mode.

[0011] Step 5: Control the stage to perform step scanning along the thickness direction of the silicon wafer, i.e., the Z-axis. For each preset step, acquire a two-dimensional cross-sectional diffraction image of the thin layer at that fixed depth. Continuously acquire multiple images until the slip line defect covers the entire depth range from the surface to the bulk.

[0012] Step 6: Perform three-dimensional reconstruction on the acquired multi-layer cross-sectional images, extract the starting depth layer and ending depth layer of the slip line defect, and calculate the total depth of the slip line defect.

[0013] As a preferred option, standard RCA cleaning or low-frequency ultrasonic cleaning is used, and the entire process involves no cutting, thinning, chemical corrosion, or coating operations, achieving non-destructive pretreatment of silicon wafers.

[0014] As a preferred method, the X-ray beam is compressed into an ultrathin parallel sheet beam with a thickness of 1~5μm through a high-precision slit, and the incident angle is adjusted to the Bragg angle of the Si (400) crystal plane so that the ultrathin sheet beam only excites a single fixed-depth thin-layer lattice of silicon wafer to generate Bragg diffraction, and no diffraction signal is generated in other depth layers.

[0015] Preferably, a Mo target X-ray source with a characteristic energy of 50keV is used, the pixel size of the detector is ≤15μm, and the horizontal calibration accuracy of the sample stage when the silicon wafer is placed is ≤±0.01°.

[0016] Preferably, the repeatability of the XYZ three-dimensional moving stage is ≤ ±0.1μm, and the Z-axis scanning step size is set to 1~2μm.

[0017] As a preferred method, the three-dimensional reconstruction includes image registration, noise filtering, threshold segmentation, and volume rendering to reconstruct the X / Y / Z three-dimensional model of the slip line defect and simultaneously output quantitative parameters such as the length, width, surface density, and spatial distribution location of the defect.

[0018] As a preferred option, the formula for calculating the total depth of the slip line defect is: Total Defect Depth = Termination Depth − Starting Depth, with a defect depth measurement accuracy of ±1μm.

[0019] Preferably, the system also includes matching the calculated total defect depth, areal density, and distribution area with production line quality control standards to automatically determine the silicon wafer qualification level; and outputting a standardized inspection report, which includes a defect location plan view, cross-sectional slices at various depths, a three-dimensional defect model, and quantitative data, directly connecting to the factory's MES quality control system.

[0020] A three-dimensional quantitative XRT system for detecting the depth of slip line defects on epitaxial silicon wafers is characterized by comprising: an X-ray source using a Mo target; a beam shaping system including a high-precision slit for compressing the beam into an ultra-thin parallel sheet-like beam with a thickness of 1–5 μm; a high-precision stage system including an θ / 2θ angle stage and an XYZ three-dimensional moving stage with a repeatability accuracy ≤ ±0.1 μm; a high-sensitivity X-ray surface detector with a pixel size ≤ 15 μm; and an analysis software module for performing global defect localization, three-dimensional reconstruction, depth calculation, and report generation.

[0021] The present invention can achieve the following effects: This invention provides a three-dimensional quantitative XRT method for detecting the depth of slip line defects in epitaxial silicon wafers. Compared with existing technologies, it has the following significant advantages: I. Breakthrough in Detection Bottlenecks, Achieving Precise 3D Quantification of Defects. A pioneering ultra-thin sheet-like X-ray layered slicing imaging technology upgrades the traditional full-thickness superimposed 2D projection to 3D layer-by-layer scanning. By exciting only a single fixed-depth thin-layer lattice to generate diffraction, the starting and ending depths of slip lines are precisely extracted, and the total depth is quantitatively calculated. This fills the technological gap in the industry where the Z-axis depth of slip lines cannot be measured, achieving a depth measurement accuracy of ±1μm.

[0022] II. Entirely Non-Destructive Process, Significantly Reducing Material Loss Costs. Employing a completely non-destructive testing process, samples only require standard cleaning to remove surface interference; no cutting, thinning, etching, or coating is necessary. After testing, the silicon wafer lattice and surface remain undamaged, allowing for direct reflow into subsequent epitaxial and chip manufacturing processes. Compared to TEM and etching methods, epitaxial silicon wafer material loss is reduced by 100%, and the material cost per batch of testing is reduced by over 90%.

[0023] Third, the combination of full-area initial screening and targeted slicing balances efficiency and inspection completeness. A combined process of "rapid localization using transmission-based full-area two-dimensional imaging + Z-axis targeted layer-by-layer scanning of the defect coordinate region" avoids the lengthy and time-consuming process of slicing the entire wafer layer by layer. The complete inspection time for a single 8-inch epitaxial silicon wafer is reduced from several hours with TEM to 60-90 minutes, and batch inspection capacity is increased by more than 2 times, effectively avoiding the risk of missed detections caused by partial sampling.

[0024] IV. Eliminating human error and achieving standardized and digitally graded defect data. A micron-level high-precision stage and beam-coordinated scanning system (repeatability ≤ ±0.1μm) are employed, combined with a 3D reconstruction algorithm to automatically calculate the 3D spatial coordinates and various morphological parameters of defects. This eliminates errors caused by human visual fatigue and subjective judgment; the depth data deviation for repeated detection of the same defect is ≤ 0.5μm. Standardized digital reports can be directly integrated with the factory's MES system, enabling automated grading and judgment of silicon wafer defects, significantly improving the consistency of production line quality control. Detailed Implementation

[0025] The technical solution of the invention will be further described in detail below through examples.

[0026] Example 1: An 8-inch N-type heavily doped silicon substrate epitaxial wafer with an epitaxial layer thickness of 5 μm was used. After undergoing a rapid thermal processing (RTP) process, slip line defects appeared in the edge region. The method described in this invention was used for detection, and the specific steps are as follows: Step 1: Sample Pretreatment. The aforementioned 8-inch epitaxial silicon wafer was cleaned using standard RCA cleaning solution, followed by low-frequency ultrasonic cleaning to remove trace amounts of oil, particles, and oxide layer interference adhering to the surface. No cutting, thinning, chemical etching, or coating operations were performed throughout the process to ensure that the silicon wafer lattice and surface remained completely undamaged, achieving non-destructive pretreatment.

[0027] Step 2: Wafer Loading and System Calibration. Place the cleaned silicon wafer horizontally on the high-precision stage and adjust the stage level to ≤±0.01°. Adjust the X-ray source (Mo target, characteristic energy 50keV), high-precision slit, sample, and high-sensitivity X-ray surface detector (pixel size ≤15μm) to be coplanar. Perform optical path calibration, angle calibration, and intensity normalization using a standard defect-free silicon wafer to ensure parallel X-ray beams, stable intensity, and consistent diffraction conditions.

[0028] Step 3: Full-surface transmission imaging (global positioning). Activate XRT transmission mode, allowing Mo target X-rays to penetrate perpendicularly through the thickness of the silicon wafer, acquiring a 2D diffraction contrast image of the entire wafer. Complete lattice regions satisfy the Bragg diffraction conditions and exhibit high brightness contrast, while edge slip line defect regions exhibit dark fringes due to lattice distortion and diffraction condition failure. The system software automatically analyzes and marks the dark fringe regions, locking the planar coordinate range of the edge annular slip line defects.

[0029] Step 4: Switch to layered slicing scanning mode. Control the XYZ three-dimensional moving stage (repeatability ≤ ±0.1μm) to move the marked defect area to the center of the optical path. Adjust the high-precision slit to compress the incident X-ray beam into an ultra-thin parallel sheet-like beam with a thickness of 2μm. Adjust the incident angle to the Bragg angle of the Si(400) crystal plane so that the beam is strictly parallel to the silicon wafer surface. At this time, the beam only excites the lattice of a certain fixed depth layer of the silicon wafer to diffract, and there is no signal in the other depth layers.

[0030] Step 5: Layer-by-layer slicing and scanning acquisition. Start the stage and perform a step scan along the depth direction (Z-axis) of the silicon wafer in 1μm increments. Acquire one 2D cross-sectional diffraction image at each depth position after every 1μm movement. In this embodiment, 120 slice images were continuously acquired, completely covering the entire depth range of the slip line defect extending from the surface into the bulk.

[0031] Step 6: 3D Reconstruction and Depth Calculation. Import 120 slice images into 3D reconstruction software (e.g., Amira) in a Z-axis stepping sequence. Through image registration, noise filtering, thresholding, and volume rendering, reconstruct the X / Y / Z 3D model of the slip line defect. The system identifies the defect's initial depth layer as 80.3 μm and its final depth layer as 91.6 μm. Based on the formula "Total Depth of Defect = Final Depth − Initial Depth," the total penetration depth of the slip line is calculated to be 11.3 μm. Simultaneously, quantitative parameters such as the defect's length, width, areal density, and orientation are automatically output.

[0032] Step 7: Result Determination and Report Output. Based on the depth data and edge distribution area described above, the system automatically matches the production line quality control standards to determine the silicon wafer grade and generates a standardized inspection report. The report includes a planar view of the defect location, a partial depth cross-sectional slice, a 3D model, and complete quantitative data.

[0033] Test results and evaluation: The single-wafer test in this embodiment took 78 minutes; the silicon wafer was undamaged and was directly returned to the production line for subsequent chip manufacturing processes after the test; the same defect was tested three times, and the depth data deviation was only 0.4μm, with no subjective human error, and the defect depth measurement accuracy reached ±1μm.

[0034] Example 2: A 12-inch P-type silicon epitaxial wafer was selected. During the high-temperature epitaxial process, local slip line defects were generated due to the temperature difference within the wafer. This was to verify the adaptability of the present invention under different sizes and process parameters.

[0035] The operation steps are the same as in Example 1, except that the process parameters used in this example are: beam thickness compressed to 5μm (wide parameter verification), and Z-axis scanning step size set to 2μm.

[0036] Detection results: The system successfully located the local slip line region, and the total depth of the slip line was calculated to be 7.8 μm. The complete detection time for a single wafer was 86 minutes, with no missed detections across the entire area. The system automatically generated standardized quality control reports, and the data was integrated with the factory's MES system, demonstrating that this method has the same efficient, comprehensive, and quantitative detection capability for larger silicon wafers and under different beam parameters.

[0037] Comparative Example 1: Preferred Etching Method for Copper Adornments. Comparative tests were conducted using 8-inch epitaxial silicon wafers from the same batch as those used in Example 1.

[0038] Technical process: Copper ion decoration → Chemical preferential etching to amplify defects → Manual observation under an optical microscope.

[0039] Results Comparison: After etching, only planar stripe morphology can be observed under a microscope, making it impossible to obtain three-dimensional data such as the starting depth, ending depth, and total depth of the slip line in the thickness direction of the silicon wafer, thus making defect classification impossible; moreover, the silicon wafer surface is damaged by chemical etching, rendering it completely unusable and unreturnable; the single-sample testing process takes approximately 140 minutes; different inspectors exhibit significant discrepancies in their assessment of the same defect level due to visual fatigue and subjective judgment differences. Compared to this method, the present invention achieves three-dimensional quantitative, non-destructive testing and data standardization.

[0040] Comparative Example 2: TEM (Transmission Electron Microscopy) detection method. 8-inch epitaxial silicon wafers from the same batch as in Example 1 were used for comparative testing.

[0041] Technical process: silicon wafer cutting and sampling → mechanical thinning and ion polishing sample preparation → transmission electron microscopy observation of defect cross-section.

[0042] Results Comparison: The previous method required wafer slicing for sample preparation, resulting in complete sample rejection after testing and severe loss of high-value epitaxial silicon wafers; TEM single-frame observation field of view was only at the micrometer level, allowing only a very small area at the wafer edge for sample preparation, failing to achieve full-area screening of the entire silicon wafer, and posing a serious risk of missed detection at edges and ring areas; single-area sample preparation and testing took up to 5 hours, unsuitable for routine quality control in mass production; only local two-dimensional cross-sectional images could be obtained, unable to reconstruct the complete three-dimensional spatial distribution of defects. Compared to this method, the present invention reduces the detection time from several hours to 60-90 minutes, achieving full-area screening and three-dimensional reconstruction, and reducing material loss by 100%.

[0043] In summary, this XRT three-dimensional quantitative detection method for slip line defect depth in epitaxial silicon wafers utilizes the principle of Bragg diffraction by exciting a single, fixed-depth thin-layer lattice of the silicon wafer with an ultrathin sheet-like parallel X-ray beam. Through Z-axis step scanning combined with three-dimensional reconstruction, it achieves precise quantitative measurement of slip line defect depth. This method simultaneously solves the problems of existing technologies, such as high destructiveness, inability to perform three-dimensional quantification, large human error, and low detection efficiency. It meets four core requirements: non-destructive testing, comprehensive screening, three-dimensional quantification, and high efficiency for mass production, demonstrating significant application value in the large-scale industrial quality control of semiconductor silicon wafers.

[0044] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. A three-dimensional quantitative XRT method for detecting the depth of slip line defects in epitaxial silicon wafers, characterized in that... The following steps are included: Step 1: Perform non-destructive surface cleaning on the silicon wafer to be inspected to remove surface interference; Step 2: Place the silicon wafer horizontally on a high-precision stage and perform optical path, angle, and intensity calibration; Step 3: Use X-ray transmission mode to perform two-dimensional global imaging of the entire silicon wafer. Based on the high brightness contrast of the complete lattice and the dark pattern characteristics of the slip line defect region, identify and automatically mark the planar coordinates of the slip line defect region. Step 4: Move the marked defect area on the silicon wafer to the center of the optical path, adjust the incident beam to an ultra-thin sheet-like X-ray beam parallel to the surface of the silicon wafer, and switch to the layered slicing scanning mode. Step 5: Control the stage to perform step scanning along the thickness direction of the silicon wafer, i.e., the Z direction. For each preset step, acquire a two-dimensional cross-sectional diffraction image of the thin layer at that fixed depth. Continuously acquire multiple images until the slip line defect covers the entire depth range from the surface to the bulk. Step 6: Perform three-dimensional reconstruction on the acquired multi-layer cross-sectional images, extract the starting depth layer and ending depth layer of the slip line defect, and calculate the total depth of the slip line defect.

2. The XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers according to claim 1, characterized in that: Standard RCA cleaning or low-frequency ultrasonic cleaning is used, and the entire process involves no cutting, thinning, chemical corrosion, or coating operations, achieving non-destructive pretreatment of silicon wafers.

3. The XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers according to claim 1, characterized in that: The X-ray beam is compressed into an ultrathin parallel sheet beam with a thickness of 1~5μm through a high-precision slit. The incident angle is adjusted to the Bragg angle of the Si crystal plane so that the ultrathin sheet beam excites only a single fixed-depth thin-layer lattice of the silicon wafer to produce Bragg diffraction, while other depth layers have no diffraction signal.

4. The XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers according to claim 1 or 3, characterized in that: The Mo target X-ray source is used with a characteristic energy of 50keV. The pixel size of the detector is ≤15μm. When placing the silicon wafer, the horizontal calibration accuracy of the sample stage is ≤±0.01°.

5. The XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers according to claim 1, characterized in that: The repeatability of the XYZ three-dimensional moving stage is ≤ ±0.1μm, and the Z-axis scanning step size is set to 1~2μm.

6. The XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers according to claim 1, characterized in that: The 3D reconstruction includes image registration, noise filtering, threshold segmentation, and volume rendering. It reconstructs the X / Y / Z 3D model of the slip line defect and simultaneously outputs quantitative parameters such as the length, width, surface density, and spatial distribution of the defect.

7. The XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers according to claim 1, characterized in that: The formula for calculating the total depth of slip line defects is: Total Defect Depth = Termination Depth − Starting Depth, and the defect depth measurement accuracy reaches ±1μm.

8. The XRT three-dimensional quantitative detection method for the depth of slip line defects in epitaxial silicon wafers according to claim 1, characterized in that: It also includes automatically determining the silicon wafer qualification level by matching the calculated total defect depth, areal density and distribution area with the production line quality control standards; It also outputs standardized inspection reports, which include a plan view of the defect location, cross-sectional slices at various depths, a three-dimensional model of the defect, and quantitative data, directly connecting to the factory's MES quality control system.

9. A three-dimensional quantitative XRT detection system for the depth of slip line defects in epitaxial silicon wafers, implementing the method of any one of claims 1 to 8, characterized in that, include: The X-ray source uses a Mo target. A beam shaping system, including a high-precision slit, is used to compress a beam into an ultra-thin parallel sheet beam with a thickness of 1~5μm; The high-precision stage system includes an θ / 2θ angle stage and an XYZ three-dimensional moving stage, with a repeatability accuracy of ≤±0.1μm; High-sensitivity X-ray surface detector with pixel size ≤15μm; The analysis software module is used to perform global defect localization, 3D reconstruction, depth calculation, and report generation.