A kind of metrology chip peripheral circuit based on self-calibration mechanism and electric energy metering box

Abstract

The application provides a metering chip peripheral circuit based on a self-calibration mechanism and an electric energy metering box, a mixed signal injection detection loop composed of a programmable gain amplifier, an analog-to-digital converter, a digital-to-analog converter and a digital processing unit is constructed, an out-of-band frequency analog excitation signal output by the DAC is injected into an amplifier input stage summing node. The digital processing unit generates an excitation signal by using a digital modulator, and extracts a response component transmitted after an internal acquisition channel by using a band-pass digital filter matched with a center frequency. A gain deduction and a non-linear discrimination module reverses an actual gain of the amplifier by using a known excitation amplitude, a measured response amplitude and a fixed link transfer coefficient, generates a gain correction code to realize self-calibration, and judges the linearity of the amplifier and the state of the internal acquisition channel of the metering chip by using gain changes under multiple amplitude excitations, so that the long-term stability and reliability of electric energy metering are improved.

Description

Technical Field

[0001] This application belongs to the field of circuits, and in particular relates to a peripheral circuit for a metering chip based on a self-calibration mechanism and an energy metering box. Background Technology

[0002] Electricity metering boxes are crucial terminal devices in smart grids, primarily used for the collection, measurement, and settlement of electricity parameters. The metering chip, as the core component of the metering box, directly impacts overall metering accuracy due to the stability of its analog front-end circuitry. During long-term grid operation, electricity metering boxes are typically exposed to environmental factors such as temperature fluctuations, humidity variations, and complex electromagnetic interference. The analog components within the metering chip are prone to parameter drift over time. The programmable gain amplifier, responsible for amplifying weak metering signals, can experience gain variations that propagate along the signal path, causing metering data deviations and consequently affecting the accuracy and fairness of electricity trading. Therefore, maintaining the gain stability and conversion reliability of the metering chip's analog front-end under complex operating environments is a critical issue that needs to be addressed in the field of smart meters and electricity metering boxes.

[0003] Existing error correction methods mostly rely on offline calibration before shipment or periodic manual on-site verification, resulting in high maintenance costs and difficulty in responding promptly to gain drift that occurs during equipment operation. Some online calibration methods require pausing normal metering tasks during execution, easily creating data acquisition blind spots; some self-calibration methods can only perform static deviation compensation, making it difficult to achieve online correction of the amplifier's actual gain without significantly interfering with normal metering. Furthermore, existing technologies lack the ability to identify linearity changes in programmable gain amplifiers under different signal amplitudes and also lack effective diagnostic methods for the status of the internal acquisition path of the metering chip. When hidden gain degradation, nonlinear distortion, or acquisition link anomalies occur within the chip, the system struggles to perform timely self-checks and warnings, easily leading to a decrease in metering accuracy. Therefore, it is necessary to provide a circuit architecture that can achieve online amplifier gain calibration during normal power acquisition and also possess internal acquisition path health diagnostic capabilities. Summary of the Invention

[0004] To address the problems in existing technologies, such as difficulty in timely correction of gain drift during metering chip operation, easy interference with normal metering during online calibration, and lack of effective diagnosis of amplifier linearity and internal acquisition path status, this invention provides a metering chip peripheral circuit and energy metering box based on a self-calibration mechanism.

[0005] In a first aspect, the present invention provides a peripheral circuit for a metering chip based on a self-calibration mechanism, comprising: A programmable gain amplifier (PLA) receives a signal from a metering sensor at its input stage, and the input stage is equipped with a summing node. An analog-to-digital converter (ADC) is used to digitize the output signal of the PLA. A digital-to-analog converter (DAC) has its output connected to the summing node. A digital processing unit connects the output of the ADC to the input of the DAC, and together with the PLA, ADC, and DAC, forms a mixed signal injection and detection loop. The digital processing unit includes a digital modulator, a bandpass digital filter, and a gain extrapolation and nonlinear discrimination module. The digital modulator generates a digital excitation code stream with a preset out-of-band frequency to drive the digital-to-analog converter to convert it into an analog injection signal injected into the summing node, so that the mixed signal injection and detection loop produces a stable response at the preset out-of-band frequency. The center frequency of the bandpass digital filter is matched with the preset out-of-band frequency, and is used to separate the response component of the programmable gain amplifier and the analog-to-digital converter from the output of the analog-to-digital converter. The gain derivation and nonlinearity discrimination module uses the known amplitude of the digital excitation code stream and the measured amplitude of the response component to back-calculate the actual gain of the programmable gain amplifier and generate a gain correction code based on the transfer function. It also controls the digital modulator to output digital excitation code streams with different target amplitudes, monitors whether the back-calculated actual gain is constant, and completes the online diagnosis of the gain linearity of the programmable gain amplifier and the integrity of the internal acquisition path of the metering chip.

[0006] Optionally, the analog-to-digital converter, used to digitize the output signal of the programmable gain amplifier, includes: It receives an external sampling clock signal and uses the rising edge of the external sampling clock signal to trigger the sample-and-hold circuit to perform a sampling operation on the voltage amplitude output by the programmable gain amplifier for 1μs. After the sampling operation is completed, it enters the voltage holding state and uses an external 10MHz clock signal to start the internal successive approximation register. With 1.2V as the reference voltage, it performs serial voltage comparison and bit value locking in 12 clock cycles according to the binary approximation logic, generating an original Boolean sequence composed of 12 comparison judgment results. A merge instruction is sent to the internal shift register to convert the original Boolean sequence into an independent 12-bit binary data word, and the status flag is set to 1 to notify the direct memory access controller to retrieve the corresponding 12-bit binary data word.

[0007] Optionally, the digital modulator generates a digital excitation code stream with a preset out-of-band frequency to drive a digital-to-analog converter to convert it into an analog injection signal for injection into the summing node, including: Read the preset constant from memory, trigger the sine wave table based on the preset phase resolution through the instruction scheduling system, and perform lookup and multiplication operations in combination with the time step increment parameter to generate a digital sine sequence with a data update rate of not less than 50kHz and a center frequency set at 8500Hz as a digital excitation code stream, which is then sent to the next level of the switching array. The switching array uses digital excitation code stream to sequentially control the switching elements of the internal capacitor network of the digital-to-analog converter to periodically release charge, so that the output analog injection signal is injected into the summing node according to the set target amplitude, so as to implement the test signal injection response start process outside the fundamental frequency band of the metering sensor signal.

[0008] Optionally, the center frequency of the bandpass digital filter is matched with a preset out-of-band frequency, used to separate the response component from the analog-to-digital converter output after passing through a programmable gain amplifier and the analog-to-digital converter, including: The passband frequency range of the filter is limited to between 7500Hz and 9500Hz by using the processor, and the stopband attenuation at the fundamental frequency of the power grid is set to be no less than 90dB in order to filter out power frequency interference signals from external power lines. For each segment of the digital signal sample periodic stream after filtering, an absolute value accumulation and averaging operation based on signal polarity is performed to extract the measured amplitude of the response component after transmission through the programmable gain amplifier and analog-to-digital converter, and the extracted measured amplitude is stored in the buffer register data queue for later retrieval.

[0009] Optionally, the gain derivation and nonlinear discrimination module, based on the known amplitude of the digital excitation code stream and the measured amplitude of the response component, combines the transfer function to inversely deduce the actual gain of the programmable gain amplifier and generate a gain correction code, including: Retrieve the known amplitude of the pre-saved digital excitation bitstream and the measured amplitude of the response component output by the bandpass digital filter; The measured amplitude is converted by waveform scaling and then divided by the known amplitude to obtain the overall transfer coefficient of the loop. Based on the overall transfer coefficient and the joint transfer coefficient of the pre-calibrated and built-in digital-to-analog converter, impedance matching circuit, coupling link, summing node network and analog-to-digital converter, the actual gain value of the programmable gain amplifier is obtained by combining the transfer function. The difference ratio between the target ideal gain value and the actual gain value is calculated. Based on the code value of the underlying gain control register and the physical control polarity direction of the actual gain of the programmable gain amplifier, the difference ratio is converted into a binary gain correction code of the corresponding polarity and stored in the underlying gain control register through a write instruction to update and correct the actual operating multiple of the programmable gain amplifier.

[0010] Optionally, the control digital modulator outputs digital excitation code streams with different target amplitudes, monitors whether the actual gain obtained by reverse engineering is constant, and completes online diagnosis of the gain linearity of the programmable gain amplifier and the integrity of the internal acquisition path of the metering chip, including: The first target amplitude excitation code stream, whose output amplitude is controlled to be 1% of the preset upper limit of the injected amplitude, is sustained for 1 second. The actual gain of the programmable gain amplifier in the current state is calculated and recorded as the first experimental quantity. After stopping the excitation action for 0.5s, the digital modulator is controlled to output the second target amplitude excitation code stream for 1s. The second target amplitude is 3% of the preset upper limit of the injected amplitude. The actual gain of the programmable gain amplifier in the current state is calculated and recorded as the second experimental quantity. Calculate the absolute value of the difference between the first experimental quantity and the second experimental quantity, and determine whether the absolute value is greater than a preset linearity threshold constant; If the absolute value is greater than the linearity threshold constant, the gain linearity of the programmable gain amplifier is determined to be out of tolerance, triggering the alarm pin level to flip, clearing the data bits of the SPI digital communication interface to zero, disabling SPI transmit and receive enable and putting the data output terminal into a high impedance state to cut off the underlying information transmission and reception channel and perform lockout protection isolation.

[0011] On the other hand, the present invention also provides an electricity metering box, comprising: The enclosure and the metering module installed inside the enclosure, the metering module including a metering sensor and peripheral circuitry of a metering chip based on a self-calibration mechanism as described in any of the above, the metering sensor being electrically connected to the signal input terminal of the programmable gain amplifier.

[0012] Furthermore, the exterior of the enclosure is equipped with a status indicator light or an audible and visual alarm, and the interior of the enclosure is equipped with a main control microprocessor; The alarm pin of the peripheral circuit is electrically connected to the status indicator or the audible and visual alarm, and is used to issue a physical alarm outside the enclosure when the gain linearity is determined to be out of tolerance and the alarm pin level is flipped. The SPI digital communication interface of the peripheral circuit is connected to the main control microprocessor.

[0013] Furthermore, the enclosure is also equipped with a load control circuit breaker, which is connected in series in the user's power supply circuit; The tripping control terminal of the load control circuit breaker is linked with the alarm pin of the peripheral circuit or the main control microprocessor to drive the load control circuit breaker to trip and cut off the power supply circuit when the peripheral circuit performs lockout protection isolation.

[0014] Furthermore, the metering sensor includes a current transformer and a voltage sampling terminal; The enclosure is equipped with an electromagnetic shielding cover made of conductive magnetic metal material. The peripheral circuit of the metering chip is installed inside the electromagnetic shielding cover to shield the enclosure from electromagnetic interference from the outside.

[0015] This invention achieves internal closed-loop calibration during normal metrology by constructing a hybrid signal injection and detection loop consisting of a programmable gain amplifier, an analog-to-digital converter, a digital-to-analog converter, and a digital processing unit. A digital modulator generates a preset out-of-band frequency excitation signal and injects it into the summing node. A bandpass digital filter separates the response components, reducing crosstalk between the calibration and measurement signals. The gain derivation and nonlinearity discrimination module infers the actual gain from known and measured amplitudes and generates a gain correction code. Simultaneously, it judges the amplifier linearity and the internal acquisition path status of the metrology chip by analyzing gain changes under different target amplitudes, reducing the impact of gain drift and nonlinearity errors on metrological accuracy and improving long-term operational reliability. Attached Figure Description

[0016] Figure 1 A schematic diagram of the capacitor array DAC injection link; Figure 2 This is a schematic diagram of ADC sample-and-hold and SAR conversion. Detailed Implementation

[0017] To make the purpose, features, and advantages of this application more apparent and understandable, specific embodiments and accompanying drawings will be used to clearly and completely describe the technical solution protected by this application. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] This specification provides one or more embodiments of a metering chip peripheral circuit based on a self-calibration mechanism, comprising: The programmable gain amplifier receives the signal from the metering sensor at its signal input terminal and has a summing node at its input stage; the analog-to-digital converter (ADC) is used to digitize the output signal of the programmable gain amplifier; the digital-to-analog converter (DAC) has its output terminal connected to the summing node; and the digital processing unit connects the output terminal of the ADC to the input terminal of the DAC, forming a mixed signal injection and detection loop with the programmable gain amplifier, the ADC, and the DAC.

[0019] The programmable gain amplifier adopts a differential operational amplifier architecture with a variable resistor network. The summing node achieves summation through a high-precision, low-noise resistor feedback network. The analog signal from the metering sensor of the voltage transformer or current transformer and the analog injection signal output by the digital-to-analog converter are passively superimposed using Kirchhoff's current law.

[0020] The analog-to-digital converter (ADC) adopts a successive approximation register (SAPPRN) architecture, which includes a sample-and-hold circuit, a comparator, a successive approximation register, and a reference digital-to-analog network to output digital codewords of a predetermined width.

[0021] The digital-to-analog converter (DAC) employs a current-steering array or capacitor array architecture, with resolution accuracy required to cover the range of the injected signal. The digital processing unit is deployed within a field-programmable gate array (FPGA) or digital signal processor (DSP) core. It utilizes a high-speed direct memory access controller module to read the DAC's output buffer register on an internal high-speed bus and writes digital waveform data to the DAC's input data register in real-time via a serial communication bus. The mixed-signal injection and detection loop is closed-looped via underlying copper wiring, enabling synchronous operation of chip-level analog signal superposition and digital domain demodulation, such as... Figure 1 As shown, a binary weighted capacitor branch is used in conjunction with a switch driver unit, and the back end is connected to a buffer operational amplifier and a coupling resistor link. It can receive digitally encoded outputs of continuous analog voltages and adapt to the requirements of high-frequency excitation signal generation.

[0022] As an optional implementation, the analog-to-digital converter, used to digitize the output signal of the programmable gain amplifier, includes: It receives an external sampling clock signal and uses the rising edge of the external sampling clock signal to trigger the sample-and-hold circuit to perform a sampling operation on the voltage amplitude output by the programmable gain amplifier for 1μs. After the sampling operation is completed, it enters the voltage holding state and uses an external 10MHz clock signal to start the internal successive approximation register. With 1.2V as the reference voltage, it performs serial voltage comparison and bit value locking in 12 clock cycles according to the binary approximation logic, generating an original Boolean sequence composed of 12 comparison judgment results. A merge instruction is sent to the internal shift register to convert the original Boolean sequence into an independent 12-bit binary data word, and the status flag is set to 1 to notify the direct memory access controller to retrieve the corresponding 12-bit binary data word.

[0023] At the initial stage of the sampling period, when the rising edge of an external high-precision sampling clock signal, for example, with a sampling rate of 200kHz and a period of 5μs, arrives, the complementary metal-oxide-semiconductor (CMOS) analog transmission gate switch is activated via the logic control circuit. This allows the output voltage of the programmable gain amplifier to be connected to the internal pF-level sampling capacitor network through the sampling switch. During the 1μs on-time, the input current charges the sampling capacitor until the potential across the capacitor is established and approaches the current analog output voltage value. The switch is then deactivated, allowing the capacitor charge to be maintained.

[0024] Upon entering the hold state, the controller activates a 1.2V reference source generated based on a bandgap reference source as a comparison reference, and uses an external 10MHz system clock to start the internal successive approximation register SAR conversion engine. In the first 100-nanosecond clock cycle, this engine compares the sampled and held voltage with half of the reference, i.e., 0.6V. If the sampled value is larger, the internal most significant bit (MSB) register is set to 1, and the 0.6V bias is retained using the internal reference analog-to-digital network to be superimposed on the next reference; if it is smaller, it is set to 0. This binary search logic is used to perform 12 consecutive analog comparisons, each comparison determining one bit of the logical result, generating a 12-bit original Boolean sequence, for example, "101100101101".

[0025] The control state machine of the analog-to-digital converter (ADC) uses an internal bus to trigger a word merging instruction, loading the aforementioned 12 independent Boolean values ​​into a 12-bit wide data buffer register and concatenating them into a binary data word. After the merging process is complete, the trigger pulls the flag bit in the conversion completion status register (EOC) high to logic level "1". Upon detecting this flag bit transition, the configured Direct Memory Access (DMA) controller, without CPU intervention, automatically moves and stores the 12-bit data word into the circular cache queue area within the SRAM via the bus according to the internally preset memory pointer, and simultaneously resets the status flag bit to 0, preparing the converter for sampling in the next sampling cycle. Figure 2 As shown, the on-chip successive approximation analog-to-digital conversion link hardware path includes sample and hold, comparator, SAR logic, 12-bit register and DMA transfer unit, and is equipped with a 1.2V reference base and reference digital-to-analog network to generate comparison reference level during SAR successive approximation, which can cover the main hardware nodes from single sampling to data transfer.

[0026] The digital processing unit includes a digital modulator, a bandpass digital filter, and a gain extrapolation and nonlinear discrimination module. The digital modulator generates a digital excitation code stream with a preset out-of-band frequency to drive the digital-to-analog converter to convert it into an analog injection signal injected into the summing node, so that the mixed signal injection and detection loop produces a stable response at the preset out-of-band frequency. The center frequency of the bandpass digital filter is matched with the preset out-of-band frequency, and is used to separate the response component of the programmable gain amplifier and the analog-to-digital converter from the output of the analog-to-digital converter.

[0027] The digital modulator is implemented using a direct digital frequency synthesizer algorithm, internally containing a phase accumulator and a sine wave amplitude lookup table, with a high-frequency sampling reference provided by the master clock. The digital modulator calculates the phase step for each accumulation based on the set frequency control word, mapping the phase step to an address in the sine wave amplitude lookup table to generate a continuous periodic sine wave digital excitation code stream. The set frequency control word corresponds to a preset out-of-band frequency, which is set to a frequency range higher than the fundamental frequency and major low-order harmonic frequencies to reduce crosstalk. The generated digital excitation code stream drives a digital-to-analog converter (DAC) via a data buffer. The DAC's conversion network converts discrete digital voltage points into continuous analog injection signal waveforms and injects them into the summing node through an impedance matching circuit. The bandpass digital filter is constructed using the finite impulse response filter function from the digital signal processing library, employing the Remitz exchange algorithm or multiple exchange algorithm to generate filter coefficients, ensuring the center frequency aligns with the preset out-of-band frequency of the digital modulator, and setting a high stopband attenuation rate for the power frequency signal band. The bandpass digital filter continuously performs convolution operations on the digital output of the analog-to-digital converter and the calculated filter coefficients through a hardware multiply-accumulate unit, filtering out high-amplitude power frequency signals and broadband quantization noise within the metering frequency band, and outputting response component waveform data containing preset out-of-band frequency characteristics.

[0028] As an optional implementation, the digital modulator generates a digital excitation code stream with a preset out-of-band frequency to drive a digital-to-analog converter to convert it into an analog injection signal for injection into the summing node, including: Read the preset constant from memory, trigger the sine wave table based on the preset phase resolution through the instruction scheduling system, and perform lookup and multiplication operations in combination with the time step increment parameter to generate a digital sine sequence with a data update rate of not less than 50kHz and a center frequency set at 8500Hz as a digital excitation code stream, which is then sent to the next level of the switching array. The switching array uses digital excitation code stream to sequentially control the switching elements of the internal capacitor network of the digital-to-analog converter to periodically release charge, so that the output analog injection signal is injected into the summing node according to the set target amplitude, so as to implement the test signal injection response start process outside the fundamental frequency band of the metering sensor signal.

[0029] The digital processing unit preloads a sine wave constant lookup table containing 512 phase quantization nodes in the chip's read-only memory area or flash memory. The sine wave constant lookup table is preset during the factory configuration or system initialization stage. The 0 to 2π phase range is evenly divided into 512 phase quantization nodes according to a complete sine cycle. The unit amplitude sine normalized code value corresponding to each node is calculated and stored in the read-only memory area or flash memory.

[0030] The system's internal timers, operating at 50kHz or higher (e.g., a 64kHz refresh clock timer), continuously trigger interrupt mechanisms to execute interrupt service routines. During each scheduling, a 32-bit data step accumulation parameter is calculated based on the 8500Hz center frequency and the current refresh frequency. This parameter is accumulated into the phase register, and the high 9 bits of the accumulator are extracted as the memory address index to read the lookup table value. This value is then used in the multiplication accumulator for unsigned multiplication calibration with a range percentage digital gain coefficient representing the expected injection intensity. This range percentage digital gain coefficient is a dimensionless scaling factor obtained by dividing the target injection amplitude by a preset injection amplitude upper limit. It is used to multiply and scale the unit amplitude code value read from the sine wave constant lookup table. The preset injection amplitude upper limit is the allowable injection amplitude upper limit of the digital-to-analog converter output signal after impedance matching circuitry and coupling link reduction to the summing node, and this allowable injection amplitude upper limit is less than the linear operating amplitude upper limit of the programmable gain amplifier input stage. The operation outputs a set of discrete digital sine wave with a center frequency of 8500Hz, an update period of tens of microseconds, and a data update rate of no less than 50kHz as a digital excitation code stream, which is pushed to the switch array bus port of the digital-to-analog converter stage.

[0031] At the front end of the digital-to-analog converter, the binary code stream is converted into physical level pulses to operate the underlying control and drive logic unit. Based on the high and low potential configuration of 1s and 0s in each latest input code, the drive logic outputs nanosecond-level gate control drive signals with complementary delays to the gates of the corresponding field-effect transistors. Through high-precision on / off logic, multiple branch connections on the internal ladder-type impedance matching charge redistribution capacitor nodes are controlled, allowing the fixed regulated reference voltage to release the corresponding charge flow at specific time periods according to the current input code during intermittent operation. After buffering, this forms the output bias waveform with the target amplitude.

[0032] These output biases, after being filtered by the amplifier network within the digital-analog chip, form a sinusoidal AC analog test signal with the set expected strength. This signal is then introduced through a coupling link composed of a set of matching resistor networks to the pre-summation node of the programmable gain amplifier core at the end of the acquisition channel. This allows the circuit to establish a closed-loop response startup state at 8500Hz, outside the main frequency domain of the 50 / 60Hz metering energy information, where the impact on the power frequency signal sampling is minimal.

[0033] As an optional implementation, the center frequency of the bandpass digital filter is matched with a preset out-of-band frequency, used to separate the response component from the analog-to-digital converter output after passing through a programmable gain amplifier and the analog-to-digital converter, including: The passband frequency range of the filter is limited to between 7500Hz and 9500Hz by using the processor, and the stopband attenuation at the fundamental frequency of the power grid is set to be no less than 90dB in order to filter out power frequency interference signals from external power lines. For each segment of the digital signal sample periodic stream after filtering, an absolute value accumulation and averaging operation based on signal polarity is performed to extract the measured amplitude of the response component after transmission through the programmable gain amplifier and analog-to-digital converter, and the extracted measured amplitude is stored in the buffer register data queue for later retrieval.

[0034] The embedded digital signal processor (DSP) executes a set of finite-length unit impulse response (FIR) filter tap operation code, employing a Kaiser window to truncate the filter coefficient sequence based on the sampling rate, transition bandwidth, and target stopband attenuation. In an embodiment with a sampling rate of 200kHz, a passband frequency range of 7500Hz to 9500Hz, and a stopband attenuation of not less than 90dB within 3kHz, the filter order is set to not less than 256. The processor limits the filter's passband frequency range to the lower limit of 7500Hz and the upper limit of 9500Hz through configuration registers, ensuring the 8500Hz test frequency passes. Simultaneously, the digital filter parameters set the stopband for the 50Hz or 60Hz fundamental frequency and the low-order harmonic region within 3kHz. The processor relies on its internal multiplication-accumulation arithmetic logic (MAC) to configure a 40-bit accumulation process to process the input components, setting the signal attenuation in the power frequency region to not less than 90dB. This configuration effectively suppresses ambient AC broadband interference after digital filtering while preserving the high-frequency feedback parameter component sequence stream at the specific test frequency.

[0035] For the filtered digital signal sample sequence mainly containing 8500Hz periodic components, an equivalent mathematical logic mechanism based on full-wave rectification is executed to extract the amplitude characteristics of the actual signal. The processor monitors the polarity bit characteristics of the point-by-point digital scalar data, and uses the underlying bit-complementing and absolute value taking method to realize the positive operation processing of the sampled data for input digital containing negative polarity. With a sliding window frame length that can accommodate 10 cycles of the test signal, the data within the entire window length are accumulated, and right shift and mean division operations are performed in combination with the total number of time points to calculate the average absolute value amplitude characteristic representing the feedback response amplitude. Based on the proportional coefficient between the average absolute value and the peak value of the sine wave, it is converted into the peak amplitude as the measured amplitude.

[0036] As the window width sampling and calculation operation is completed, the chip processing kernel initiates a low-level command to push the measured amplitude, which represents the system's true scaling capability, along with the measured amplitude system time synchronization flag, into the internal dedicated queue address space of the on-chip FIFO isolated circular cache static random access memory with a depth of 16 address levels. This is for use by the status diagnostic verification management scheduler to initiate an interrupt call.

[0037] The gain derivation and nonlinearity discrimination module uses the known amplitude of the digital excitation code stream and the measured amplitude of the response component to back-calculate the actual gain of the programmable gain amplifier and generate a gain correction code based on the transfer function. It also controls the digital modulator to output digital excitation code streams with different target amplitudes, monitors whether the back-calculated actual gain is constant, and completes the online diagnosis of the gain linearity of the programmable gain amplifier and the integrity of the internal acquisition path of the metering chip.

[0038] The gain derivation and nonlinear discrimination module uses a discrete Fourier transform algorithm or the Goertzel algorithm to perform digital spectrum calculations on the separated response components, solving for the measured amplitude and the corresponding phase at a preset out-of-band frequency. Internally, the module calls a hardware divider function to divide the measured amplitude by the known amplitude set by the digital modulator to obtain the total closed-loop gain of the system. It then calls a transfer function compensation algorithm to remove the fixed link transfer coefficients, including those of the digital-to-analog converter, impedance matching circuit, coupling links, summing node network, and analog-to-digital converter, extracting the current actual gain of the programmable gain amplifier. A proportional-integral microcontroller algorithm is used to calculate the difference between the target reference gain and the current actual gain to obtain the error value. After coefficient adjustment, this error value is converted into a gain correction code and written to the internal register of the programmable gain amplifier to adjust the variable resistor network built into the amplifier, completing the calibration.

[0039] The gain estimation and nonlinearity discrimination module internally runs a finite state machine scheduler, periodically changing the amplitude control word input to the digital frequency synthesizer algorithm. This controls the digital modulator to output multiple digital excitation code streams with different target amplitudes increasing in an arithmetic progression. At each amplitude stage, the module collects and calculates the corresponding actual gain, and calls a least-squares linear regression function to perform linear fitting calculations on the collected amplitude and gain data points to obtain the gain dispersion variance. If the calculated gain dispersion variance is less than a set tolerance threshold, the actual gain is considered constant and the gain linearity is normal. If the dispersion variance is greater than the set threshold, or the measured amplitude calculated by the discrete Fourier transform algorithm is zero, the module calls an interrupt generation function to trigger a hardware alarm signal to the external central processing unit and updates the internal status register flag to indicate that the amplifier may be in a nonlinear saturation state or that the signal path may have an open-circuit fault.

[0040] As an optional implementation, the gain derivation and nonlinear discrimination module, based on the known amplitude of the digital excitation code stream and the measured amplitude of the response component, combines the transfer function to inversely deduce the actual gain of the programmable gain amplifier and generate a gain correction code, including: Retrieve the known amplitude of the pre-saved digital excitation bitstream and the measured amplitude of the response component output by the bandpass digital filter; The measured amplitude is converted by waveform scaling and then divided by the known amplitude to obtain the overall transfer coefficient of the loop. Based on the overall transfer coefficient and the joint transfer coefficient of the pre-calibrated and built-in digital-to-analog converter, impedance matching circuit, coupling link, summing node network and analog-to-digital converter, the actual gain value of the programmable gain amplifier is obtained by combining the transfer function. The difference ratio between the target ideal gain value and the actual gain value is calculated. Based on the code value of the underlying gain control register and the physical control polarity direction of the actual gain of the programmable gain amplifier, the difference ratio is converted into a binary gain correction code of the corresponding polarity and stored in the underlying gain control register through a write instruction to update and correct the actual operating multiple of the programmable gain amplifier.

[0041] The on-chip algorithm logic engine within the system initiates an internal High-Level Microcontroller Bus (AHB) read interaction to access the static variable setting area in the system's non-volatile flash memory to obtain the "known amplitude" representing the injection parameter constant of the fixed source excitation signal. For example, it reads the quantized data constant 0x07D0LSB. It then uses the address pointer to retrieve the "measured amplitude" representing the response data from the previous-level filtering operation's cyclic update queue memory array, for example, 0x18F3LSB. The measured amplitude is then sent to the built-in divider as the dividend, and a division operation is performed with the known amplitude as the divisor to obtain the comprehensive transmission coefficient representing the transmission link. For example, the calculated ratio is approximately 3.1935. Subsequently, the controller reads the pre-calibrated fixed link transfer coefficients stored in the one-time programmable OTP memory area. The fixed link transfer coefficients are used to characterize the total gain or total attenuation of the test signal by the digital-to-analog converter, impedance matching circuit, coupling link, summing node network, and analog-to-digital converter. For example, the reading error calibration value is 0.9995. The combined transfer coefficient is divided by this constant factor to compensate for the influence of the fixed link and extract the actual gain of the programmable gain amplifier, such as 3.1950 times.

[0042] After calculating the actual gain, the deviation correction logic uses a fixed target reference gain, such as 3.2000, and calculates the error value by subtracting it from the actual gain. This error is then divided by the target reference gain to obtain the difference ratio expressed as a percentage, for example, a relative reduction of approximately 0.156%. Based on the control step size set by the internal low-level digital control bits, such as each minimum increment representing a 0.05% increase, and the hardware-level control polarity direction, this difference ratio is converted into a gain correction code in two's complement form, indicating the correction direction. For example, the corresponding instruction format 0x00000011 correction code value, which requires an increase of 3 microsteps, is calculated. In the next system instruction cycle, the microcontroller core initiates the execution command, overwriting the control base address data bits of the underlying operational amplifier through a write instruction; this completes the switching adjustment of transistors in the hardware analog feedback array, compensates for deviation drift, improves the actual amplification gain performance of the programmable gain amplifier, and completes the state calibration process.

[0043] As an optional implementation, the control digital modulator outputs digital excitation code streams with different target amplitudes, monitors whether the actual gain obtained by reverse engineering is constant, and completes online diagnosis of the gain linearity of the programmable gain amplifier and the integrity of the internal acquisition path of the metering chip, including: The first target amplitude excitation code stream, whose output amplitude is controlled to be 1% of the preset upper limit of the injected amplitude, is sustained for 1 second. The actual gain of the programmable gain amplifier in the current state is calculated and recorded as the first experimental quantity. After stopping the excitation action for 0.5s, the digital modulator is controlled to output the second target amplitude excitation code stream for 1s. The second target amplitude is 3% of the preset upper limit of the injected amplitude. The actual gain of the programmable gain amplifier in the current state is calculated and recorded as the second experimental quantity. Calculate the absolute value of the difference between the first experimental quantity and the second experimental quantity, and determine whether the absolute value is greater than a preset linearity threshold constant; If the absolute value is greater than the linearity threshold constant, the gain linearity of the programmable gain amplifier is determined to be out of tolerance, triggering the alarm pin level to flip, clearing the data bits of the SPI digital communication interface to zero, disabling SPI transmit and receive enable and putting the data output terminal into a high impedance state to cut off the underlying information transmission and reception channel and perform lockout protection isolation.

[0044] The internal chip scheduling center relies on a timer to initiate a dual-point diagnostic timing operation to evaluate nonlinearity and on / off conditions. The control sequence first overwrites the constant controlling the transmission intensity in the address of the sine test wave synthesis parameter control array, so that the digital modulator is directly driven at 1% of the preset upper limit of the injection amplitude, and outputs the first target amplitude excitation code stream. At the same time, the timing circuit constrains the transmission process to a measurement window of 1000ms, or 1s. After the time expires, the actual gain of the programmable gain amplifier calculated by reverse calculation is captured and stored in the reserved block of the independent observation calibration SRAM for archiving, as the first test quantity for reference verification. After completing the above test sampling operation, the controller stops the transmission behavior and waits for a 0.5s shutdown period to release the integrated energy to prevent the two measurements from overlapping and causing coupling interference.

[0045] After the 0.5s isolation protection period, the controller initiates and reconfigures the modulator, outputting a second target amplitude excitation stream with an amplitude of 3% of the preset upper limit of the injected amplitude, and maintaining the excitation for 1 second. Under this environment, the detection loop is invoked to invert and obtain the actual gain of the programmable gain amplifier, and this gain is also recorded as the second test quantity. The logic operation unit retrieves the two saved first test quantities and second test quantities, performs internal algebraic subtraction, and takes the absolute value to retain the difference characteristic number. This is compared with the linearity threshold constant of 0.02 pre-installed in the internal factory EEPROM, where the linearity threshold constant of 0.02 is the dimensionless gain difference threshold.

[0046] If the comparison determines that the absolute value is greater than the linearity threshold constant of 0.02, it indicates that the programmable gain amplifier may have nonlinear degradation, saturation distortion, or abnormal signal path. The hardware protection control line immediately activates, driving the external general-purpose pins. The GPIO fault error indicator pin control point reverses the ground potential, which was originally held at 0V, and pulls it high to 3.3V to continuously supply a warning level to activate the device alarm. Simultaneously, to ensure that metering data under fault conditions is no longer used as valid data transmission, the main control hardware switches to the external digital SPI physical layer data exchange mainline, clears the SPI data register, disables SPI transmit / receive enable, and controls the MISO data output to enter a high-impedance state, preventing the external main control from continuing to read valid metering data. The damaged chip enters a locked isolation state to prevent erroneous metering data from continuing to participate in billing or management decisions.

[0047] One or more embodiments of this specification also provide an energy metering box, comprising: The enclosure and the metering module installed inside the enclosure, the metering module including a metering sensor and peripheral circuitry of a metering chip based on a self-calibration mechanism as described in any of the above, the metering sensor being electrically connected to the signal input terminal of the programmable gain amplifier.

[0048] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A peripheral circuit for a metering chip based on a self-calibration mechanism, characterized in that, include: A programmable gain amplifier, with a signal input terminal receiving a metering sensor signal and an input stage equipped with a summing node; An analog-to-digital converter is used to digitize the output signal of a programmable gain amplifier. The digital-to-analog converter (DAC) has its output connected to the summing node; the digital processing unit connects the output of the DAC to the input of the DAC, and together with the programmable gain amplifier, the DAC, and the DAC, forms a mixed signal injection and detection loop. The digital processing unit includes a digital modulator, a bandpass digital filter, and a gain extrapolation and nonlinear discrimination module. The digital modulator generates a digital excitation code stream with a preset out-of-band frequency to drive the digital-to-analog converter to convert it into an analog injection signal injected into the summing node, so that the mixed signal injection and detection loop produces a stable response at the preset out-of-band frequency. The center frequency of the bandpass digital filter is matched with the preset out-of-band frequency, and is used to separate the response component of the programmable gain amplifier and the analog-to-digital converter from the output of the analog-to-digital converter. The gain derivation and nonlinearity discrimination module uses the known amplitude of the digital excitation code stream and the measured amplitude of the response component to back-calculate the actual gain of the programmable gain amplifier and generate a gain correction code based on the transfer function. It also controls the digital modulator to output digital excitation code streams with different target amplitudes, monitors whether the back-calculated actual gain is constant, and completes the online diagnosis of the gain linearity of the programmable gain amplifier and the integrity of the internal acquisition path of the metering chip.

2. The peripheral circuit of the metering chip according to claim 1, characterized in that, The analog-to-digital converter is used to digitize the output signal of the programmable gain amplifier, including: It receives an external sampling clock signal and uses the rising edge of the external sampling clock signal to trigger the sample-and-hold circuit to perform a sampling operation on the voltage amplitude output by the programmable gain amplifier for 1μs. After the sampling operation is completed, it enters the voltage holding state and uses an external 10MHz clock signal to start the internal successive approximation register. With 1.2V as the reference voltage, it performs serial voltage comparison and bit value locking in 12 clock cycles according to the binary approximation logic, generating an original Boolean sequence composed of 12 comparison judgment results. A merge instruction is sent to the internal shift register to convert the original Boolean sequence into an independent 12-bit binary data word, and the status flag is set to 1 to notify the direct memory access controller to retrieve the corresponding 12-bit binary data word.

3. The peripheral circuit for the metering chip according to claim 1, characterized in that, The digital modulator generates a digital excitation code stream with a preset out-of-band frequency to drive a digital-to-analog converter to convert it into an analog injection signal for injection into the summing node, including: Read the preset constant from memory, trigger the sine wave table based on the preset phase resolution through the instruction scheduling system, and perform lookup and multiplication operations in combination with the time step increment parameter to generate a digital sine sequence with a data update rate of not less than 50kHz and a center frequency set at 8500Hz as a digital excitation code stream, which is then sent to the next level of the switching array. The switching array uses digital excitation code stream to sequentially control the switching elements of the internal capacitor network of the digital-to-analog converter to periodically release charge, so that the output analog injection signal is injected into the summing node according to the set target amplitude, so as to implement the test signal injection response start process outside the fundamental frequency band of the metering sensor signal.

4. The peripheral circuit of the metering chip according to claim 3, characterized in that, The center frequency of the bandpass digital filter is matched with a preset out-of-band frequency, used to separate the response component from the analog-to-digital converter output after passing through a programmable gain amplifier and the analog-to-digital converter, including: The passband frequency range of the filter is limited to between 7500Hz and 9500Hz by using the processor, and the stopband attenuation at the fundamental frequency of the power grid is set to be no less than 90dB in order to filter out power frequency interference signals from external power lines. For each segment of the digital signal sample periodic stream after filtering, an absolute value accumulation and averaging operation based on signal polarity is performed to extract the measured amplitude of the response component after transmission through the programmable gain amplifier and analog-to-digital converter, and the extracted measured amplitude is stored in the buffer register data queue for later retrieval.

5. The peripheral circuit of the metering chip according to claim 1, characterized in that, The gain derivation and nonlinear discrimination module, based on the known amplitude of the digital excitation code stream and the measured amplitude of the response components, combined with the transfer function, inversely derives the actual gain of the programmable gain amplifier and generates a gain correction code, including: Retrieve the known amplitude of the pre-saved digital excitation bitstream and the measured amplitude of the response component output by the bandpass digital filter; The measured amplitude is converted by waveform scaling and then divided by the known amplitude to obtain the overall transfer coefficient of the loop. Based on the overall transfer coefficient and the joint transfer coefficient of the pre-calibrated and built-in digital-to-analog converter, impedance matching circuit, coupling link, summing node network and analog-to-digital converter, the actual gain value of the programmable gain amplifier is obtained by combining the transfer function. The difference ratio between the target ideal gain value and the actual gain value is calculated. Based on the code value of the underlying gain control register and the physical control polarity direction of the actual gain of the programmable gain amplifier, the difference ratio is converted into a binary gain correction code of the corresponding polarity and stored in the underlying gain control register through a write instruction to update and correct the actual operating multiple of the programmable gain amplifier.

6. The peripheral circuit of the metering chip according to claim 1, characterized in that, The control digital modulator outputs digital excitation code streams with different target amplitudes, monitors whether the actual gain obtained by reverse engineering is constant, and completes online diagnosis of the gain linearity of the programmable gain amplifier and the integrity of the internal acquisition path of the metering chip, including: The first target amplitude excitation code stream, whose output amplitude is controlled to be 1% of the preset upper limit of the injected amplitude, is sustained for 1 second. The actual gain of the programmable gain amplifier in the current state is calculated and recorded as the first experimental quantity. After stopping the excitation action for 0.5s, the digital modulator is controlled to output the second target amplitude excitation code stream for 1s. The second target amplitude is 3% of the preset upper limit of the injected amplitude. The actual gain of the programmable gain amplifier in the current state is calculated and recorded as the second experimental quantity. Calculate the absolute value of the difference between the first experimental quantity and the second experimental quantity, and determine whether the absolute value is greater than a preset linearity threshold constant; If the absolute value is greater than the linearity threshold constant, the gain linearity of the programmable gain amplifier is determined to be out of tolerance, triggering the alarm pin level to flip, clearing the data bits of the SPI digital communication interface to zero, disabling SPI transmit and receive enable and putting the data output terminal into a high impedance state to cut off the underlying information transmission and reception channel and perform lockout protection isolation.

7. An electricity metering box, characterized in that, include: The enclosure and the metering module installed inside the enclosure, the metering module including a metering sensor and a metering chip peripheral circuit based on a self-calibration mechanism as described in any one of claims 1 to 6, the metering sensor being electrically connected to the signal input terminal of the programmable gain amplifier.

8. The electricity metering box according to claim 7, characterized in that, The exterior of the enclosure is equipped with a status indicator light or an audible and visual alarm, and the interior of the enclosure is equipped with a main control microprocessor; The alarm pin of the peripheral circuit is electrically connected to the status indicator or the audible and visual alarm, and is used to issue a physical alarm outside the enclosure when the gain linearity is determined to be out of tolerance and the alarm pin level is flipped. The SPI digital communication interface of the peripheral circuit is connected to the main control microprocessor.

9. The electricity metering box according to claim 8, characterized in that, The enclosure is also equipped with a load control circuit breaker, which is connected in series with the user's power supply circuit. The tripping control terminal of the load control circuit breaker is linked with the alarm pin of the peripheral circuit or the main control microprocessor to drive the load control circuit breaker to trip and cut off the power supply circuit when the peripheral circuit performs lockout protection isolation.

10. The electricity metering box according to claim 7, characterized in that, The metering sensor includes a current transformer and a voltage sampling terminal; The enclosure is equipped with an electromagnetic shielding cover made of conductive magnetic metal material. The peripheral circuit of the metering chip is installed inside the electromagnetic shielding cover to shield the enclosure from electromagnetic interference from the outside.

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