A small-sized fault recording device for a converter valve cooling system
Patent Information
- Application Number
- CN202610993653.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-06
- Publication Date
- 2026-10-23
AI Technical Summary
[0004]常规监控采样率仅为1-10Hz，无法捕捉泵启停冲击、水锤效应等毫秒级扰动的高频特征；电量采集方面仅采集主泵单相电流有效值，缺乏三相电压电流原始波形，难以识别转子偏心、绕组匝间短路等机械故障引发的电流畸变；历史数据存储周期不足30天且多为私有格式，无法跨平台标准化调阅与分析；各子系统独立计时，多源数据缺乏精确时标对齐，难以同步比对；同时传统录波装置多为机柜式，体积庞大，难以嵌入阀冷本地控制柜，制约分布式部署，上述缺陷导致现有系统仅能记录开关量变位或模拟量越限事件，无法完整还原故障前后毫秒级动态过程，难以支撑深度根因分析；
[0031]1、专用架构与双模录波：集成通信、电气、模拟三类接口，首创面向阀冷系统的专用录波架构；稳态与暂态双模式兼顾长期趋势分析与瞬态事件捕获，突破传统监控"只记结果、不录过程"的局限；
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Figure CN122962310A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronic equipment monitoring and fault diagnosis technology, and more specifically, to a miniaturized fault recording device for a converter valve cooling system. Background Technology
[0002] In high-voltage direct current transmission systems, converter valves are the core equipment for realizing AC-DC energy conversion. Their safe and stable operation is highly dependent on the supporting valve cooling system. The valve cooling system is usually composed of a main circulation pump, deionization device, temperature and pressure sensors, flow meter, conductivity meter, etc., and has a highly redundant design (such as dual main pumps and dual control system A / B). Once the cooling system malfunctions (such as pump stoppage, sudden drop in flow, or temperature exceeding the limit), it may cause the converter valve to overheat or even shut down, resulting in significant economic losses.
[0003] Existing traditional valve cooling monitoring systems mostly use PLCs or DCSs for data acquisition and alarms. Although they have basic status monitoring capabilities, they generally have the following shortcomings:
[0004] Conventional monitoring sampling rates are only 1-10Hz, which cannot capture the high-frequency characteristics of millisecond-level disturbances such as pump start-up and shutdown impacts and water hammer effects; in terms of power acquisition, only the effective value of single-phase current of the main pump is collected, lacking the original waveforms of three-phase voltage and current, making it difficult to identify current distortions caused by mechanical faults such as rotor eccentricity and winding inter-turn short circuits; historical data storage period is less than 30 days and is mostly in proprietary formats, making it impossible to standardize cross-platform access and analysis; each subsystem is timed independently, and multi-source data lacks precise time stamp alignment, making synchronous comparison difficult; at the same time, traditional waveform recording devices are mostly cabinet-type, bulky, and difficult to embed into valve cooling local control cabinets, restricting distributed deployment. The above defects result in the existing system only being able to record switch quantity changes or analog quantity limit exceeding events, unable to fully restore the millisecond-level dynamic process before and after the fault, and unable to support in-depth root cause analysis;
[0005] Therefore, there is an urgent need for a miniaturized, high-precision, long-cycle, and standardized dedicated fault recording device to fill the gap in fault tracing and transient analysis of valve cooling monitoring systems. Summary of the Invention
[0006] In order to overcome the above-mentioned defects of the prior art, the present invention provides a miniaturized fault recording device for a converter valve cooling system to solve the problems mentioned in the background art.
[0007] To achieve the above objectives, the present invention provides the following technical solution:
[0008] A miniaturized fault recording device for a converter valve cooling system, with dual Ethernet interfaces for accessing the redundant control network of the valve cooling system;
[0009] Voltage and current acquisition interface, used to acquire the three-phase voltage and current signals of the main pump;
[0010] A 4-20mA analog signal acquisition interface is provided for connecting industrial sensor signals.
[0011] Dual fiber optic interfaces for uploading waveform recording data;
[0012] NTP time synchronization module, used for network time synchronization;
[0013] Wide-range AC / DC adaptive power supply module;
[0014] And an embedded waveform recording control unit, used for unified scheduling of data acquisition, waveform recording mode switching, file generation and communication management;
[0015] The embedded waveform recording control unit adopts a heterogeneous architecture of PowerPC and FPGA. The FPGA is used for high-speed analog-to-digital conversion sampling and has built-in hardware logic circuits to calculate the effective value, mutation amount, and execution threshold comparison and logic combination judgment of each channel in real time. When the trigger condition is met, it locks the data address corresponding to the trigger time in the circular buffer and generates an interrupt signal. The PowerPC is used to run the embedded operating system. After responding to the interrupt signal, it reads the locked pre-recorded waveform data from the FPGA and performs protocol parsing, waveform file generation, file management and network communication.
[0016] The device supports both steady-state and transient recording modes, and the recorded data is stored and uploaded in COMTRADE standard format.
[0017] As a further description of the above technical solution: the dual Ethernet interface collects the control system operation data of the valve cooling system A side and B side respectively through the Modbus TCP protocol to achieve redundant communication.
[0018] As a further description of the above technical solution: the voltage and current acquisition interface is used to acquire the three-phase voltage and current signals of the two redundant main pumps in real time, and supports waveform restoration and RMS value calculation.
[0019] As a further description of the above technical solution: the 4-20mA analog signal acquisition interface supports the access of no less than 4 industrial sensor signals.
[0020] As a further description of the above technical solution: In the steady-state recording mode: the sampling rate of digital signals is ≥10Hz and the continuous storage time is ≥12 months; the sampling rate of analog signals is ≥1000Hz and the continuous storage time is ≥7 days; the data adopts a cyclic overwrite mechanism to automatically retain the latest data.
[0021] As a further description of the above technical solution: the transient recording mode adopts an AB segment structure:
[0022] The transient sampling rate of the switch quantity is ≥100Hz, the pre-recording time of segment A is ≥120s and can be adjusted, and the post-recording time of segment B is ≥120s and can be adjusted.
[0023] The analog transient sampling rate is ≥5000Hz, the pre-recording time of segment A is ≥30s and can be adjusted, and the post-recording time of segment B is ≥60s and can be adjusted.
[0024] The waveform recording trigger conditions include threshold exceeding, mutation amount, or logic combination events, and support multi-channel synchronous triggering; the threshold exceeding, mutation amount calculation, and logic combination decision are executed in parallel by the hardware logic circuit inside the FPGA, and the decision delay does not exceed one sampling period;
[0025] When the triggering condition is met, the waveform recording control unit locks the data in the ring buffer before the triggering time as segment A, and continuously collects the data after the triggering time as segment B.
[0026] As a further description of the above technical solution: all waveform recording files are generated as .cfg configuration files and .dat data files according to the COMTRADE standard, and are simultaneously stored in the built-in local industrial-grade solid-state storage. They are also redundantly uploaded to a remote fault waveform recording server via dual-channel fiber optic interfaces. The device adopts a miniaturized chassis structure, supports magnetic installation and DIN35mm rail clip installation, and can be embedded in a valve-cooled local control cabinet for deployment. It also includes status indicator lights and a debugging interface. The status indicator lights are used to indicate power supply, operation, waveform recording, and fault status, while the debugging interface is used for on-site maintenance and parameter adjustment.
[0027] As a further description of the above technical solution: the NTP time synchronization module has a built-in NTP client to realize network time synchronization. In the event of the loss of an external clock source, the device's own timekeeping error is no more than 100ms / 24h.
[0028] As a further description of the above technical solution: the power module supports a wide input range of DC 100V~370V or AC 88V~264V, and has built-in EMI filtering and reverse connection protection circuits, making it suitable for the complex electromagnetic environment of converter stations.
[0029] As a further description of the above technical solution: the embedded waveform recording control unit supports the IEC 61850 MMS communication protocol service, which is used for maintenance personnel to remotely adjust the waveform recording sampling rate, A / B segment duration and trigger condition threshold.
[0030] The technical effects and advantages of this invention are as follows:
[0031] 1. Dedicated architecture and dual-mode waveform recording: Integrating communication, electrical and analog interfaces, it pioneers a dedicated waveform recording architecture for valve cooling systems; the steady-state and transient dual-mode architecture takes into account both long-term trend analysis and transient event capture, breaking through the limitation of traditional monitoring that "only records the result and not the process";
[0032] 2. High precision and long cycle: The analog transient sampling rate is up to 5000Hz, and with the ring buffer locking mechanism, the pre-recorded waveform can be pre-recorded for up to 30 seconds to ensure complete capture of fault precursors; steady-state data can be stored for up to 12 months to meet the needs of long-term trend analysis.
[0033] 3. Deep fault diagnosis capability: Complete acquisition of the original three-phase voltage and current waveforms of two redundant main pumps, which can be used to identify current distortion characteristics caused by mechanical faults such as rotor eccentricity and winding inter-turn short circuit, making up for the blind spots of traditional single-phase effective value monitoring.
[0034] 4. Standardization and high reliability: COMTRADE standard format output, compatible with mainstream analysis software; dual-channel fiber optic redundant upload, dual-channel Ethernet redundant acquisition, NTP time synchronization error ≤100ms / 24h, ensuring data integrity and reliability;
[0035] 5. Miniaturization and Intelligence: The miniaturized chassis supports magnetic / rail mounting and can be embedded in existing control cabinets; the wide-range AC / DC adaptive power supply adapts to complex electromagnetic environments; it supports IEC 61850 MMS remote parameter tuning, reducing the complexity of operation and maintenance.
[0036] In summary, this invention provides a high-precision, long-cycle, standardized, and easy-to-deploy dedicated waveform recording solution for converter valve cooling systems, which can improve fault diagnosis efficiency and system operational reliability. Attached Figure Description
[0037] Figure 1 This is a system architecture diagram.
[0038] Figure 2 This is a schematic diagram of the dual-mode waveform recording workflow.
[0039] Figure 3 This is a schematic diagram of the AB segment structure of the analog transient waveform recording.
[0040] Figure 4 This is a schematic diagram of the device's hardware interface layout.
[0041] The attached diagram is labeled as follows: 1. Wide-range AC / DC adaptive power supply module; 2. Voltage and current acquisition interface; 3. 4-20mA analog signal acquisition interface; 4. Dual Ethernet interface; 5. Dual fiber optic interface; 6. Status indicator light; 7. Debugging interface. Detailed Implementation
[0042] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0043] Example 1: Device Hardware Composition and Deployment
[0044] like Figure 1 and Figure 4 As shown, this device adopts a miniaturized industrial chassis design and can be installed in the local control cabinet of the valve cooling system via magnetic attachment or DIN 35mm rail clips. The chassis panel is equipped with status indicator lights, interfaces for power, operation, waveform recording, fault, and debugging, dual Ethernet interfaces, dual fiber optic interfaces, a power input interface, and various data acquisition interfaces. The drive pins of status indicator lights 6 are connected to the general purpose input / output (GPIO) ports of the FPGA, and the waveform recording control unit controls the lighting by outputting high / low levels according to the operating status. Specific information for each interface is as follows:
[0045] Dual Ethernet interfaces: labeled ETH1 and ETH2 respectively, used to connect to the valve cooling PLC redundant network;
[0046] Dual fiber optic interfaces: labeled P5 and P6, used to transmit COMTRADE files to the station-level waveform recording server;
[0047] Voltage and current acquisition interface: marked as P3, supports 3-phase × 2-channel main pump A / B acquisition, rated voltage 220V 50Hz, rated current 5A 50Hz;
[0048] 4-20mA analog signal acquisition interface: marked as P4, supports no less than 4 inputs;
[0049] Power input interface: marked P1, supports wide AC / DC voltage input DC100V~370V or AC88V~264V, with built-in EMI filtering and reverse connection protection circuit.
[0050] The device employs a PowerPC+FPGA heterogeneous architecture: the FPGA handles high-speed ADC sampling, while the PowerPC runs an embedded operating system to handle protocol parsing, waveform recording control, file management, and network communication. This heterogeneous architecture fully leverages the real-time advantages of the FPGA in high-speed data acquisition and the flexibility of the PowerPC in complex protocol processing and network communication.
[0051] As a further explanation of the hardware architecture in Embodiment 1, the division of responsibilities and data interaction mechanism between the FPGA and PowerPC in this device are as follows:
[0052] The FPGA performs the real-time triggering and judgment function.
[0053] The FPGA internally employs a parallel pipelined processing architecture, which immediately performs the following real-time calculations after the high-speed ADC sampled data enters the FPGA:
[0054] RMS value calculation: The root mean square of the voltage and current sampling sequence of each phase is calculated by sliding window. The window length is one power frequency cycle (20ms). The RMS value is updated once for each sampling point.
[0055] Mutation detection: Calculate the difference between the current sampled value and the corresponding sampled value of the previous power frequency cycle. When the absolute value of the mutation exceeds the preset threshold, a trigger flag is generated.
[0056] Threshold exceeding comparison: The real-time sampled value and the calculated valid value are compared with the preset upper and lower thresholds. A trigger flag is generated when the threshold is exceeded.
[0057] Logical combination judgment: Receive logical combination conditions (such as "current drop > 30% and temperature exceeds limit") from PowerPC, and implement the AND / OR / NOT combination judgment of multi-channel trigger flags in hardware logic inside the FPGA to ensure that the trigger judgment delay does not exceed one sampling period (i.e., 0.2ms when the sampling rate is 5000Hz).
[0058] When the trigger condition is met, the FPGA notifies the PowerPC via a hard-wired interrupt signal, and simultaneously latches the position of the circular buffer write pointer and the sampling sequence number corresponding to the trigger time into an internal register for subsequent reading by the PowerPC.
[0059] Data interaction mechanism between PowerPC and FPGA
[0060] The FPGA internally uses a dual-port RAM as a data exchange buffer, which is divided into the following areas:
[0061] Real-time sampling data area: The FPGA continuously writes the sampling data (analog + digital) of the current period, and the PowerPC reads it in batches periodically through PCIe or LocalBus for steady-state recording storage and network uploading;
[0062] Trigger Status Register Area: The FPGA updates the effective value, mutation rate and trigger flag status of each channel in real time. The PowerPC polls and reads the data at a lower frequency (e.g., 100Hz) for status display and remote communication response.
[0063] Circular Buffer Management Area: The FPGA internally maintains the write pointer and frame sequence number of a large-capacity circular buffer. During steady-state operation, the FPGA continuously writes sampled data to the circular buffer. When a trigger occurs, the FPGA locks the frame sequence number corresponding to the trigger point and notifies the PowerPC. Based on this, the PowerPC calculates the start and end addresses of segment A data in the circular buffer. After triggering, it reads the pre-recorded waveform data of segment A from the FPGA buffer and simultaneously receives the post-recorded waveform data of segment B continuously written by the FPGA.
[0064] System-level guarantee of real-time performance under high sampling rate
[0065] The internal ring buffer and trigger decision logic of the FPGA are entirely implemented by hard logic circuits in hardware description language (Verilog / VHDL), without relying on any software program. All operations are completed within a single clock cycle or pipeline stage. Even at a sampling rate of 5000Hz, the FPGA still has ample processing margin (typical operating frequency ≥100MHz, tens of thousands of clock cycle operations can be completed within a single sampling period of 200μs).
[0066] PowerPC runs a real-time operating system (RTOS) and sets the FPGA interrupt service thread to the highest priority to ensure that the time delay from interrupt triggering to completion of A-segment buffer locking and reading operations is less than 1ms, so as not to cause data loss.
[0067] The ring buffer capacity is configured according to the highest sampling rate (5000Hz for analog signals and 100Hz for digital signals), and its depth can accommodate at least twice the maximum A-segment duration (120s) of data, ensuring that the pre-recorded waveform data will not be overwritten by subsequent data before it is locked and read.
[0068] Through the above division of labor, this device fully leverages the hardware parallel advantages of FPGA in high-speed, low-latency real-time computing, and the software flexibility advantages of PowerPC in complex protocol stack processing, file system management, and network communication. The two work together to ensure the real-time performance and reliability of transient trigger judgment at a high sampling rate of 5000Hz.
[0069] Example 2: Dual-modal waveform recording workflow
[0070] To accommodate the differentiated requirements of different sampling rates and storage periods in both steady-state and transient modes, this device constructs a logically independent but physically uniformly addressed dual-ring buffer within the storage space of the embedded waveform recording control unit:
[0071] Analog ring buffer: Dedicated to storing voltage, current, and 4-20mA analog sampled data. The buffer capacity is configured for a maximum transient sampling rate of 5000Hz and a maximum A-segment duration of 30 seconds, with a depth of 5000×30×2=300,000 sampling points (i.e., twice the capacity of the maximum A-segment data). This ensures that after a transient trigger locks the A-segment, subsequent B-segment data writes will not immediately overwrite the locked A-segment data.
[0072] Digital signal ring buffer: Dedicated to storing digital signals. Capacity is configured for a transient sampling rate of 100Hz and a maximum A-segment duration of 120 seconds, with a depth of 100 × 120 × 2 = 24,000 sampling points;
[0073] Each buffer uses a "frame structure" as its basic storage unit. Each frame of data contains: [absolute timestamp (microsecond level), channel identifier mask, data payload]. The introduction of the frame structure allows PowerPC to perform subsequent timing alignment and fusion analysis based on the timestamp, even if analog and digital signals arrive at different sampling times.
[0074] Internally, the FPGA maintains separate write pointers for analog and digital signals. Because the analog signal sampling rate (5000Hz) is much higher than the digital signal sampling rate (maximum 100Hz), the FPGA employs an "asynchronous independent write" strategy.
[0075] When each analog sampling period (200μs) arrives, the FPGA immediately encapsulates the data into a frame and writes it to the address currently pointed to by the write pointer in the analog circular buffer, and then the write pointer increments by 1;
[0076] When the switch quantity changes or the timing acquisition cycle arrives (such as once every 10ms in transient state), the FPGA independently performs the write operation of the switch quantity frame, and its write pointer increments independently.
[0077] The two data streams do not block each other. The arbitration logic inside the FPGA occupies the storage bus in a time-sharing manner, ensuring that the real-time performance of high-speed analog data writing is not affected by low-speed switching quantity writing.
[0078] When the FPGA's internal hardware logic detects that the trigger condition is met, the device does not stop writing, but instead performs the following atomic operation (completed within one sampling period):
[0079] Freeze the write pointer value at the trigger moment: The FPGA immediately latches the instantaneous value of the current analog write pointer into the Trigger_Ptr_AI register and latches the current digital write pointer into the Trigger_Ptr_DI register;
[0080] Calculate the starting address of segment A data: After PowerPC responds to the interrupt, based on the preset segment A duration (e.g., 30 seconds for analog signals), calculate the number of frames N_A that needs to be rolled back = sampling rate × segment A duration. Then calculate the starting address of segment A: Start_Addr = (Trigger_Ptr_AI - N_A) % buffer depth;
[0081] Continuous reading of A-segment data: PowerPC reads N_A frame data continuously from Start_Addr in DMA mode until it reads the last frame pointed to by Trigger_Ptr_AI, thus forming a complete A-segment pre-recorded waveform dataset;
[0082] Continuous writing of segment B data: While the PowerPC is reading segment A data, the FPGA's write pointer continues to advance, continuously receiving segment B data after triggering. Since the buffer capacity is preset to twice the maximum duration of segment A, and the speed at which the PowerPC reads segment A (accessed via the high-speed bus) is much greater than the speed at which the FPGA writes, the locking operation only marks an index address and never blocks or pauses the physical writing process, ensuring zero loss of segment B data.
[0083] In steady-state mode, the analog sampling rate drops to 1000Hz, and the digital sampling rate drops to 10Hz. At this time, the embedded waveform recording control unit no longer relies on the FPGA's trigger lock, but instead, the PowerPC periodically (e.g., every minute) dumps the newly written data in the circular buffer into the external industrial-grade solid-state non-volatile memory in the form of file blocks.
[0084] Steady-state analog quantity files: A data block is generated every 10 minutes. After 7 days, space is released according to the principle of "deleting the earliest generated file first".
[0085] Steady-state switch quantity file: A data block is generated every 24 hours, and it is automatically overwritten after 12 months.
[0086] This mechanism ensures that steady-state trend data and transient high-fidelity data are physically isolated on the storage medium and managed separately, which guarantees both rapid response when transient events occur (operation is performed directly in the RAM ring area) and meets the capacity requirements for long-term data archiving.
[0087] After the device is powered on, the FPGA continuously sends real-time sampled values to the waveform recording control unit, which saves these data as steady-state continuous recording data.
[0088] The switch inputs are recorded cyclically at a sampling rate of 10Hz, covering the most recent 12 months;
[0089] Analog signals are recorded cyclically at a sampling rate of 1000Hz, covering the most recent 7 days; all data is cached in a circular buffer, and older data is automatically overwritten.
[0090] The cyclic overwrite storage used in steady-state waveform recording mode is implemented through a ring buffer inside the embedded waveform recording control unit, where newly written data automatically overwrites the earliest data.
[0091] When any preset trigger condition is met, such as a sudden drop in main pump current greater than 30%, or a combined alarm of over-temperature and low flow rate, the device immediately switches to transient waveform recording mode.
[0092] Start high sampling rate waveform recording. The switching frequency is greater than or equal to 100Hz, and the analog frequency is greater than or equal to 5000Hz.
[0093] The waveform recording control unit locks the data "before the trigger point" in the current circular buffer as the pre-recorded waveform of segment A. The length is retained according to the set value, with a default value of 120s for switch quantities and 30s for analog quantities.
[0094] Continue to collect data after the trigger point as the B-segment post-recording. The length can also be adjusted by default: 120s for switch quantity and 60s for analog quantity.
[0095] After recording is complete, a file conforming to the COMTRADE standard is automatically generated, including a .cfg configuration file and a .dat data file, and a precise UTC timestamp is added.
[0096] Figure 3 The AB segment structure of analog transient waveform recording is further demonstrated: segment A is the pre-recording window before triggering, and segment B is the recording window after triggering. Together, they constitute a complete fault event record.
[0097] Example 3: Communication and Time Synchronization
[0098] After the device is started, it connects to the station control layer NTP server, such as the Beidou / GPS timing device or the valve cooling system NTP server, via the ETH1 or ETH2 interface, and synchronizes every 60 seconds. If synchronization fails three times in a row, the internal temperature-compensated crystal oscillator is activated to ensure that the cumulative error does not exceed 100ms within 24 hours.
[0099] The Modbus TCP acquisition thread periodically polls the valve cooling A / B system registers for information such as pump operating status, water temperature setpoint, and conductivity alarms. After parsing, the data is uniformly labeled and stored in the database along with locally acquired electrical and analog quantities, ensuring that all channel data has a unified time reference.
[0100] Example 4: Parameter Tuning and Remote Maintenance
[0101] Maintenance personnel can remotely access the device via the IEC 61850 MMS service to configure the following parameters:
[0102] Steady-state / transient waveform recording sampling rate;
[0103] Recording duration for segments A and B;
[0104] Trigger condition thresholds and logical combinations;
[0105] NTP server IP and synchronization interval;
[0106] Data retention period and upload strategy.
[0107] The remote tuning function allows maintenance personnel to flexibly adjust the waveform recording strategy according to different operating conditions without going to the site, significantly improving maintenance efficiency.
[0108] Example 5: COMTRADE File Generation and Upload
[0109] After each transient recording session, the device automatically generates a file pair conforming to the COMTRADE standard, including:
[0110] .cfg configuration file: contains descriptive information such as channel name, sampling rate, data type, and transformer ratio;
[0111] .dat data file: Contains the raw sampled data for each channel, arranged in chronological order.
[0112] After the file is generated, the device simultaneously sends it to the remote fault recording server via dual fiber optic interfaces P5 and P6. This dual-path redundant transmission ensures reliable data delivery. The file naming convention includes the device ID and trigger time, facilitating automatic archiving and retrieval by the server.
[0113] In addition to remote uploading via dual fiber optic interfaces, all transient waveform recording files and steady-state historical data are simultaneously stored in the device's built-in local industrial-grade solid-state storage, ensuring that waveform recording data is completely preserved when the network is interrupted or the remote server is unavailable, and the remote server will actively initiate retransmission after communication is restored.
[0114] The local solid-state storage uses industrial-grade eMMC or SLCNANDFlash chips, with a standard capacity of at least 64GB (expandable to 256GB). This capacity design is based on the following calculations: the size of a single transient waveform recording file (including .cfg and .dat) is approximately 7.2MB (sampling rate 5000Hz × number of analog channels (at least 8 channels) × 2 bytes per sample × recording duration 90 seconds). Assuming an estimated 100 transient waveform recordings per month, the average monthly storage requirement is approximately 720MB. Steady-state analog signals continuously recorded at 1000Hz for 7 days occupy approximately 1000 × 8 × 2 × 3600 × 24 × 7 ≈ 9.6GB. The amount of steady-state switch signal data is negligible. Therefore, the 64GB capacity can simultaneously meet the needs of at least 6 months of transient file archiving and the local retention of the latest 7-day steady-state waveform data. Even if the remote upload link is completely interrupted, the local data will not overflow or be lost in the short term.
[0115] To address the continuous data writing requirements of 5000Hz × multi-channel, the device employs a two-tier storage strategy of "DDR cache + batch disk write": Data acquired by the FPGA is first written at high speed to the PowerPC's DDR memory cache (cache capacity not less than 512MB) via DMA. After the PowerPC assembles the COMTRADE file in the cache, it is saved to the solid-state storage (SSD) via SATA or SDIO interfaces in batch block write mode (each write is not less than 4KB aligned). The continuous sequential write speed of this SSD is not less than 20MB / s (measured value), while the maximum instantaneous write rate of waveform data is approximately 5000Hz × 10 channels × 2 bytes = 100KB / s. The memory write bandwidth margin exceeds 200 times, which fully meets the performance requirements of continuous data writing at high sampling rates, and there is no risk of data loss due to insufficient storage write speed.
[0116] When local storage space is exhausted, the device automatically executes a cyclic overwrite strategy: it prioritizes deleting transient waveform files with the earliest timestamps (sorted by trigger time), and then deletes the earliest steady-state data blocks to ensure that new data always has available storage space. The solid-state memory driver layer integrates wear-leveling algorithms and bad block management mechanisms to avoid premature failure of specific storage cells due to frequent overwrites, ensuring the reliability of the storage medium throughout the device's entire lifespan (no less than 10 years).
[0117] The device's power module has a built-in power failure detection circuit. When it detects that the external input voltage has dropped to the undervoltage threshold, it immediately sends a power failure warning interrupt to the PowerPC. After the PowerPC responds to the interrupt, it uses the millisecond-level sustaining time provided by the energy storage capacitor (with a capacity of not less than 1000μF) in the power module to urgently complete the closing operation of the currently being written COMTRADE file (including updating the FAT directory entry and closing the file handle), ensuring that the waveform data collected during the abnormal power failure is not damaged or lost, and that the file system remains intact and consistent.
[0118] Example 6: Typical Application Scenarios
[0119] Taking a certain UHVDC converter station as an example, the valve cooling system of the station is equipped with an A / B dual redundant control system and two main circulation pumps, one for use and one for standby; this device is embedded in the valve cooling local control cabinet and fixed in the empty space inside the cabinet by magnetic attraction.
[0120] The power module is connected to the DC 220V power supply in the station; ETH1 is connected to the A system switch and ETH2 is connected to the B system switch; the voltage and current acquisition interface is connected to the secondary side of the three-phase voltage and current transformers of main pump A and main pump B; the 4-20mA interface is connected to the cooling water inlet and outlet temperature sensors, flow meters and conductivity meters.
[0121] After the unit was put into operation, it operated in steady-state waveform recording mode for a long period of time. One day, pump B suddenly started in standby mode. Due to a sudden drop in the outlet pressure of pump A, the standby pump was automatically started. The unit detected that the current of pump B suddenly increased by more than 50% exceeding the set threshold, and immediately triggered transient waveform recording.
[0122] The analog data for the first 30 seconds and the digital data for the first 120 seconds are locked as segment A.
[0123] Continue to collect analog data for 60 seconds and digital data for 120 seconds after triggering as segment B;
[0124] Generate a COMTRADE file and upload it.
[0125] The maintenance personnel opened the waveform file using COMTRADE compatible analysis software and clearly saw the three-phase current imbalance waveform at the moment of pump B's start-up. They determined that there was a slight mechanical jam in the pump body and promptly arranged for maintenance, thus avoiding unplanned shutdown.
[0126] Working principle of the invention: After the device is powered on, the wide-range AC / DC adaptive power supply module 1 supplies power to each functional unit, the embedded waveform recording control unit completes the system initialization, and the standard time is obtained from the station control layer clock source through the NTP time synchronization module to ensure that the device is synchronized with the station clock.
[0127] Subsequently, the embedded waveform recording control unit establishes Modbus TCP communication links with the control systems on both sides of the valve cooling system (A and B) via dual Ethernet interfaces 4, and periodically reads the status of switch quantities and analog parameters. At the same time, it samples the three-phase voltage and current signals of the two redundant main pumps in real time through the voltage and current acquisition interface 2, and acquires industrial sensor signals such as temperature, pressure, and flow through the 4-20mA analog acquisition interface 3. All the above signals are aggregated to the embedded waveform recording control unit, and after being accurately timestamped, they are stored in a circular buffer.
[0128] The device defaults to steady-state recording mode, continuously recording and cyclically overwriting the stored data at a low sampling rate to meet the needs of long-term trend analysis. The embedded recording control unit simultaneously monitors all channel data, calculates the effective value, mutation rate and other characteristic quantities in real time, and compares them with preset trigger condition thresholds.
[0129] When any trigger condition threshold is exceeded, or a sudden change or logical combination event is met, the device immediately switches from steady-state mode to transient recording mode. The embedded recording control unit locks the data in the ring buffer before the trigger time as segment A pre-recorded waveform, and continues to collect data after the trigger time at a higher sampling rate as segment B post-recorded waveform. After segment A and B recording is completed, the device automatically generates a .cfg configuration file and a .dat data file conforming to the COMTRADE standard, and uploads them redundantly to a remote fault recording server via dual-path fiber optic interfaces. At the same time, they are saved in the local industrial-grade solid-state storage. After the upload is completed, the device automatically switches back to steady-state recording mode and continues to record in a loop.
[0130] Maintenance personnel can remotely access the device through the IEC 61850 MMS service to adjust waveform recording parameters, trigger thresholds, and communication configurations online, flexibly adapting to different operating conditions without on-site operation.
[0131] All contents not described in detail in the specification are existing technologies known to those skilled in the art, and the model parameters of each electrical appliance are not specifically limited; conventional equipment can be used. Electrical control components not mentioned in this technical solution are not shown in the figures because they are existing technologies, and will not be described here.
[0132] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A miniaturized fault recording device for a converter valve cooling system, characterized in that, include: Dual Ethernet interfaces (4) are used to access the redundant control network of the valve cooling system; Voltage and current acquisition interface (2) is used to acquire the three-phase voltage and current signals of the main pump; 4-20mA analog signal acquisition interface (3) is used to connect to industrial sensor signals; Dual fiber optic interface (5) for uploading waveform recording data; NTP time synchronization module, used for network time synchronization; Wide-range AC / DC adaptive power supply module (1); And an embedded waveform recording control unit, used for unified scheduling of data acquisition, waveform recording mode switching, file generation and communication management; The embedded waveform recording control unit adopts a heterogeneous architecture of PowerPC and FPGA. The FPGA is used for high-speed analog-to-digital conversion sampling and has built-in hardware logic circuits to calculate the effective value, mutation amount, and execution threshold comparison and logic combination judgment of each channel in real time. When the trigger condition is met, it locks the data address corresponding to the trigger time in the circular buffer and generates an interrupt signal. The PowerPC is used to run the embedded operating system. After responding to the interrupt signal, it reads the locked pre-recorded waveform data from the FPGA and performs protocol parsing, waveform file generation, file management and network communication. The device supports both steady-state and transient recording modes, and the recorded data is stored and uploaded in COMTRADE standard format.
2. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, The dual Ethernet interface (4) collects the control system operation data of the valve cooling system A side and B side respectively through the Modbus TCP protocol to achieve redundant communication.
3. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, The voltage and current acquisition interface (2) is used to acquire the three-phase voltage and current signals of the two redundant main pumps in real time, and supports waveform restoration and effective value calculation.
4. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, The 4-20mA analog signal acquisition interface (3) supports the access of no less than 4 industrial sensor signals.
5. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, In the steady-state recording mode: the sampling rate of digital signals is ≥10Hz and the continuous storage time is ≥12 months; the sampling rate of analog signals is ≥1000Hz and the continuous storage time is ≥7 days; the data adopts a cyclic overwrite mechanism to automatically retain the latest data.
6. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, The transient recording mode adopts an AB segment structure: The transient sampling rate of the switch quantity is ≥100Hz, the pre-recording time of segment A is ≥120s and can be adjusted, and the post-recording time of segment B is ≥120s and can be adjusted. The analog transient sampling rate is ≥5000Hz, the pre-recording time of segment A is ≥30s and can be adjusted, and the post-recording time of segment B is ≥60s and can be adjusted. The waveform recording trigger conditions include threshold exceeding, mutation amount, or logic combination events, and support multi-channel synchronous triggering; the threshold exceeding, mutation amount calculation, and logic combination decision are executed in parallel by the hardware logic circuit inside the FPGA, and the decision delay does not exceed one sampling period; When the triggering condition is met, the waveform recording control unit locks the data in the ring buffer before the triggering time as segment A, and continuously collects the data after the triggering time as segment B.
7. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, All waveform recording files are generated as .cfg configuration files and .dat data files according to the COMTRADE standard, and are stored in the built-in local industrial-grade solid-state storage. They are also redundantly uploaded to the remote fault waveform recording server through dual-channel fiber optic interfaces (5). The device adopts a miniaturized chassis structure, supports magnetic installation and DIN35mm guide rail snap-fit installation, and can be embedded in the valve cooling local control cabinet for deployment. It also includes status indicator lights (6) and debugging interfaces (7). The status indicator lights are used to indicate the power supply, operation, waveform recording and fault status, and the debugging interface is used for on-site maintenance and parameter debugging.
8. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, The NTP time synchronization module has a built-in NTP client to realize network time synchronization. In the event of the loss of an external clock source, the device's own timekeeping error is no more than 100ms / 24h.
9. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, The power module (1) supports a wide input range of DC 100V~370V or AC 88V~264V, and has built-in EMI filtering and reverse connection protection circuits, making it suitable for the complex electromagnetic environment of converter stations.
10. The miniaturized fault recording device for the converter valve cooling system according to claim 1, characterized in that, The embedded waveform recording control unit supports the IEC 61850 MMS communication protocol service, which allows maintenance personnel to remotely adjust the waveform recording sampling rate, A / B segment duration, and trigger condition threshold.