An energy-saving inverter loading method

Abstract

The present application relates to the technical field of power electronic transmission test, and more particularly to an energy-saving frequency converter loading method applied to a test system comprising a measured frequency converter, a loading frequency converter, a common DC bus and a three-phase filter reactor, comprising: extracting pulse width modulation pulses output by the measured frequency converter to configure a unique global reference clock source; analyzing dynamic test working condition instructions to extract instantaneous virtual angular velocity, and mapping effective bit data to target memory address offset; triggering a hardware event cascade response mechanism based on the global reference clock source, synchronously executing count value forced overwrite and direct memory access channel activation, and transporting virtual load discrete characteristic data from a static storage matrix according to the offset; executing interpolation operation to generate target duty cycle data; synchronously writing the duty cycle data into an active shadow register using a heavy load enable signal; generating an inverter drive waveform based on the shadow register to control the loading frequency converter to apply simulated load current.

Description

Technical Field

[0001] This invention relates to the field of power electronic drive testing technology, and in particular to an energy-saving frequency converter loading method. Background Technology

[0002] In the aging and dynamic performance testing of heavy-duty frequency converters at the factory, industrial sites typically employ a purely electrical parallel platform where the frequency converter under test and the load frequency converter are directly connected to the same DC bus to achieve internal feedback circulation of the test power. After stripping away the physical mechanical motor, the load frequency converter must rely on internal algorithms to reconstruct the target current to simulate real mechanical operating resistance. Existing frequency converter loading test methods, when dealing with extreme nonlinear conditions such as transient impacts from high-speed punch presses or sudden drops from full loads on cranes, heavily rely on the microcontroller's central processing unit to execute software interrupt services to solve complex mechanical dynamic differential equations in real time. The absolute physical time consumed by the software code computation inevitably leads to a microsecond-level phase lag between the calculation instructions of the underlying inverter drive waveform and the hardware carrier refresh cycle. The inherent computational delay within the system causes the electrical execution actions to fail to keep up with the sudden mechanical changes, resulting in severe distortion of the control output of the millisecond-level transient physical load, making it impossible to accurately verify the ultimate shock resistance capability of the frequency converter under test. Summary of the Invention

[0003] To overcome the above shortcomings, this invention provides an energy-saving inverter loading method, which aims to improve the problem that traditional inverter dynamic loading tests mostly use software to solve equations in real time. Due to the inherent time consumption of code execution, the drive waveform is delayed.

[0004] This invention provides the following technical solution: an energy-saving inverter loading method applied to a testing system, wherein the testing system includes the inverter under test, the loading inverter, a common DC bus, and a three-phase filter reactor, comprising the following steps: S1. Extract the pulse width modulation pulse output by the frequency converter under test, and configure the pulse width modulation pulse as a unique global reference clock source; S2. Parse the dynamic test condition instructions to extract the instantaneous virtual angular velocity, and map the effective bit data of the instantaneous virtual angular velocity to the target memory address offset; S3. Based on the unique global reference clock source, trigger the hardware event cascading response mechanism, synchronously execute the hardware timer count value forced overwrite action and the direct memory access channel activation action, and transfer the virtual load discrete feature data from the static storage matrix through the activated direct memory access channel according to the target memory address offset. S4. Perform interpolation operations based on the virtual load discrete characteristic data to generate target duty cycle data; S5. Using the global reload enable signal triggered by the hardware event cascading response mechanism, the target duty cycle data is synchronously written into the active shadow register. S6. Based on the active shadow register, generate an inverter drive waveform and control the loaded inverter to apply a simulated load current to the inverter under test via the three-phase filter reactor.

[0005] By adopting the above technical solution, a hardware event cascading response mechanism is triggered and load characteristic data is transported in conjunction with the direct memory access channel, thereby eliminating the computational delay of software interruption. This improves the problem that traditional frequency converter dynamic loading tests mostly use software to solve equations in real time, which causes a delay in the transmission of drive waveforms due to the inherent time consumption of code execution.

[0006] The present invention has the following beneficial effects: 1. In this invention, the discrete characteristic data of the virtual load is moved from the static storage matrix by using the direct memory access channel according to the target memory address offset, thereby eliminating the consumption of software computing power. This improves the problem that traditional frequency converter loading mostly uses the processor to solve the physical equation in real time. Due to the inherent time consumption of code execution, the control waveform is delayed.

[0007] 2. In this invention, a unique global reference clock source is generated by injecting the pulse width modulation pulse transition level into the hardware phase-locked loop logic, thereby establishing the singleness of the time reference. This improves the problem that traditional drag-load tests mostly use dual controllers with local crystal oscillators to start oscillation separately, which causes clock slippage and misalignment in the underlying control due to asynchronous physical clocks.

[0008] 3. In this invention, half of the carrier count value is forcibly loaded into the main counter to force overwrite the count value, thereby inducing a half-cycle phase misalignment of the carriers of the two frequency converters. This improves the problem that traditional common DC bus loading mostly adopts dual-machine independent wave generation, which causes serious heat loss of the bus filter capacitor due to the superposition of high-frequency pulsating currents in phase.

[0009] 4. In this invention, by outputting a reload enable signal when the main counter reaches the zero limit to synchronously load the duty cycle data, the register refresh is ensured to be closely aligned with the carrier. This improves the problem of truncation distortion of the inverter drive waveform caused by the fact that traditional pulse width modulation updates mostly use software interrupt random writing and the writing time deviates from the physical boundary of the carrier. Attached Figure Description

[0010] Figure 1 This is a flowchart of an energy-saving frequency converter loading method proposed in this invention; Figure 2This is a flowchart illustrating the physical routing and phase-locked loop reconfiguration of the global reference clock source for an energy-saving inverter loading method proposed in this invention. Figure 3 This is a flowchart illustrating the offline feature storage and online physical memory address mapping of an energy-saving inverter loading method proposed in this invention. Figure 4 This is a flowchart of a pure hardware event cascading transfer method for an energy-saving frequency converter loading method proposed in this invention, without central processing unit intervention. Figure 5 The flowchart shows the inverter waveform generation mechanism and power feedback closed-loop control process of the energy-saving inverter loading method proposed in this invention. Detailed Implementation

[0011] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Example 1: In a first embodiment of the present invention, the present invention provides an energy-saving inverter loading method, such as... Figures 1-2 As shown, it includes the following steps: S1. Extract the pulse width modulation pulse output from the inverter under test and configure the pulse width modulation pulse as the unique global reference clock source. Furthermore, in S1, the pulse width modulation pulse output by the inverter under test is extracted, and the pulse width modulation pulse is configured as a unique global reference clock source, including: Configure a direct connection routing channel between the external physical pins of the frequency converter and the internally contained input cross switch matrix; The input crossbar switch matrix is ​​used to shield the local crystal clock signal input within the microcontroller hardware architecture; Extract the rising edge transition level of the pulse width modulation pulse output by the inverter under test; Inject the rising edge transition level into the internally configured hardware phase-locked loop logic; After the hardware phase-locked loop logic is locked, a forced phase alignment action is performed to generate a synchronous square wave sequence as the sole global reference clock source.

[0013] Specifically, to establish a tight physical clock synchronization closed loop, the embodiment performs a hard-wired-level reconstruction of the clock input topology at the underlying level of the frequency converter. The microcontroller hardware architecture of the frequency converter includes external physical pins and an internal input crossbar switch matrix. A direct connection routing channel is configured between the external physical pins and the input crossbar switch matrix. The frequency converter under test continuously outputs pulse-width modulated pulses. The pulse-width modulated pulses, as physical level signals, are input to the crossbar switch matrix via the direct connection routing channel.

[0014] The pulse width modulation (PWM) pulse transition level captured by the external pin is directly input to the microcontroller's synchronization signal input network. A timer synchronization source selection register is configured within the underlying silicon chip. The microcontroller hardwires the external input pin numbers to the input channel of the timer synchronization source selection register according to configuration instructions. The timer synchronization source selection register cuts off the reference clock drive source generated internally by the target hardware timer using a local crystal oscillator clock tree. The timer synchronization source selection register establishes the PWM pulse transition level as the unique external synchronization count reset signal for the target hardware timer.

[0015] The microcontroller hardware architecture incorporates a hardware edge detection circuit. This circuit continuously monitors the pulse width modulation (PWM) pulses transmitted through the input crossbar switch matrix and extracts the rising edge transition level generated by the PWM pulses. This rising edge transition level is then directly injected into the hardware phase-locked loop (PLL) logic configured within the frequency converter as an external reference variable.

[0016] The hardware phase-locked loop (PLL) logic internally includes a phase detector and a loop filter. The phase detector compares the phase of the rising edge transition level with the feedback phase of the internal voltage-controlled oscillator (VCO). Discrete phase error compensation calculations are performed according to the PLL control principle. A mathematical model for phase-locking error adjustment is constructed at this stage. ; Where parameters This indicates that the hardware phase-locked loop logic is in the first... The synchronous angular frequency output in each discrete adjustment cycle, with the physical dimension being radians per second. Parameters This represents the pre-set base operating angular frequency of the inverter microcontroller hardware architecture, expressed in radians per second. (Parameter) Indicates the first The physical phase difference between the rising edge transition level of the inverter output under test and the feedback signal of the voltage-controlled oscillator within a discrete adjustment cycle, with the physical dimension in radians. Parameter This represents the proportional gain constant of the loop filter and is dimensionless. Parameter This represents the integral gain constant of the loop filter and is dimensionless. Parameter It represents the discrete-time cumulative independent variable index from the initial energized state to the current cycle, and is a dimensionless positive integer.

[0017] After a closed-loop iterative process involving multiple discrete adjustment cycles, the parameters... The value decays to within the hardware-preset zero-limit dead zone. The hardware phase-locked loop (PLL) logic establishes a locked state. The locked state signifies that the hardware PLL logic has completed the forced phase alignment operation for the rising edge transition level. The voltage-controlled oscillator (VCO) operates according to the parameters... The indicated angular frequency value is sent out as a synchronous square wave sequence. This sequence, via a clock distribution network, covers all arithmetic logic units and execution peripherals within the frequency converter. The microcontroller hardware architecture extracts the synchronous square wave sequence and configures it as the sole global reference clock source. This configuration action establishes the uniqueness of the underlying time reference, avoiding the clock slippage caused by two independent microcontroller systems oscillating independently.

[0018] like Figure 3 As shown, S2, the dynamic test condition command is parsed to extract the instantaneous virtual angular velocity, and the effective bit data of the instantaneous virtual angular velocity is mapped to the target memory address offset; Furthermore, in S2, the instantaneous virtual angular velocity is extracted from the dynamic test condition instructions, and the effective bit data of the instantaneous virtual angular velocity is mapped to the target memory address offset, including: Receive a two-dimensional data table containing nonlinear mechanical friction characteristics; Convert a two-dimensional data table into a static storage matrix in a one-dimensional continuous address format; The static storage matrix is ​​burned into the contiguous physical address space of the non-volatile memory; The extracted instantaneous virtual angular velocity is input into the hardware shift register; The hardware shift register performs a right shift truncation operation to remove the low-order floating-point fractional data and extract the pure digital sequence in the highest bit as the valid bit data. The effective bits are combined with the data bit width constant using a low-level multiplication operation to generate the target memory address offset.

[0019] Specifically, the system receives dynamic test condition commands from the host computer. These commands contain a two-dimensional data table characterizing nonlinear mechanical friction. The microcontroller lacks the physical path for high-speed low-level hardware addressing of this two-dimensional data. The host computer uses the code compilation chain to perform a dimensionality reduction and expansion operation on the two-dimensional data table. The row and column mapping relationships of the two-dimensional data table are forcibly flattened, and it is reconstructed into a static storage matrix in a one-dimensional continuous address format.

[0020] The programming device injects the static storage matrix into the non-volatile memory configured inside the frequency converter. The static storage matrix occupies an absolutely contiguous physical address space within the non-volatile memory.

[0021] During online operation, the microcontroller parses dynamic test condition commands and extracts instantaneous virtual angular velocities. These instantaneous virtual angular velocities are initially stored internally in a single-precision floating-point format containing a decimal mantissa. To match the pure digital displacement rules of the underlying silicon chip, the microcontroller core calls the built-in hardware floating-point to fixed-point conversion logic unit to forcibly convert the single-precision floating-point instantaneous virtual angular velocity to a fixed-point integer format containing a proportional scale within a single clock cycle. The hardware data bus then sends the bit stream in fixed-point integer format to the hardware shift register.

[0022] The hardware shift register receives the shift clock pulse from the control logic and performs a right shift truncation operation. This right shift truncation operation directly affects the underlying binary encoding of the fixed-point integer format, forcibly pushing the low-order binary data representing fractional precision out of the physical boundary of the hardware shift register and discarding it. Internally, the hardware shift register retains the binary information representing the integer addressing index. The remaining pure digital sequence in the most significant bit is extracted and defined as the valid bit data.

[0023] The logic arithmetic unit calls the valid bit data. To accurately align with the physical addressing spacing rules of the non-volatile memory, the logic arithmetic unit feeds the valid bit data and the data bit width constant into the internal hardware multiplier to perform low-level multiplication and combination operations. Instantaneous virtual angular velocity is a continuous variable in physical space. The microcontroller core arithmetic unit performs fixed-point conversion and memory offset mapping on the instantaneous virtual angular velocity according to a preset discretization scaling factor. The following physical address mapping mathematical model is constructed for this fixed-point addressing conversion process: ; Where parameters Represents the target memory address offset of the calculated output. It has no physical dimensions and directly represents the physical address step size that the direct memory access controller needs to jump. Parameter This represents the received instantaneous virtual angular velocity in floating-point format, with the physical unit being radians per second. Parameter This represents the pre-defined angular velocity discretization step size during the construction of the static storage matrix, with the physical dimension being radians per second. Division operations result in the absolute cancellation of the radians per second dimension.

[0024] parameter This represents the fixed-point scaling bit width constant used for converting floating-point numbers to fixed-point numbers; it is a dimensionless integer. Parameter This represents the magnification factor generated based on the fixed-point scaling bit-width constant. Parameter This represents the floor operation, removing decimal places. Right shift operator. Matching parameters This forces the data in the register to shift right, erasing the amplified fixed-point fractional part and retaining only the pure numeric integer index sequence in the high-order bits. Parameters This represents a constant physical byte width occupied by a single discrete feature reference point within the static storage matrix; it has no physical dimensions. All the above conversion operations are centrally processed by the CPU core arithmetic unit before the direct memory access controller is activated, and the results are stored in the memory address register awaiting retrieval. In an engineering setting where the system uses a 32-bit single-precision floating-point storage system, the parameters... The constant value is forcibly assigned to four.

[0025] The hardware multiplier pushes the calculated target memory address offset to the microcontroller's bus control matrix. The microcontroller's silicon-level architecture has a peripheral direct-trigger routing matrix independent of the CPU's instruction fetch channel. The target memory address offset is directly mapped and injected into the source address offset register channel of the direct memory access controller via the peripheral direct-trigger routing matrix using a pure hardware connection, achieving dynamic refreshing of the addressing physical base point without ever waking the CPU.

[0026] like Figure 4 like Figure 1 As shown, S3, based on the unique global reference clock source, triggers a hardware event cascading response mechanism, synchronously executes the hardware timer count value forced overwrite action and the direct memory access channel activation action, and moves the virtual load discrete feature data from the static storage matrix through the activated direct memory access channel according to the target memory address offset. Furthermore, in S3, a hardware event cascading response mechanism is triggered based on a unique global reference clock source. This mechanism synchronously executes the forced overwriting of hardware timer counter values ​​and the activation of direct memory access channels. Based on the target memory address offset, it then uses the activated direct memory access channels to move discrete virtual load characteristic data from the static storage matrix, including: Connect the trigger level of the unique global reference clock source to the synchronization input port of the hardware timer; Within a single clock cycle of capturing the trigger level, the existing accumulated value of the main counter contained in the hardware timer is forcibly erased; Half of the maximum carrier cycle count value is forcibly loaded into the main counter as the initial phase value, thus completing the forced overwrite of the hardware timer count value.

[0027] In S3, a hardware event cascading response mechanism is triggered based on a unique global reference clock source. This mechanism synchronously executes the forced overwriting of hardware timer counter values ​​and the activation of direct memory access channels. Furthermore, it moves virtual load discrete characteristic data from the static storage matrix through the activated direct memory access channels based on the target memory address offset. Other features include: Extract the hardware synchronization event pulse automatically triggered at the bottom layer of the silicon wafer at the moment the hardware timer counter value is forcibly overwritten; Connect the hardware synchronization event pulse directly to the hardware trigger source interface of the direct memory access controller; While maintaining the CPU core in a sleep state, the direct memory access controller's operation gate is activated by using hardware synchronization event pulses to complete the direct memory access channel activation action.

[0028] In S3, a hardware event cascading response mechanism is triggered based on a unique global reference clock source. This mechanism synchronously executes the forced overwriting of hardware timer counter values ​​and the activation of direct memory access channels. Furthermore, based on the target memory address offset, it moves virtual load discrete characteristic data from the static storage matrix through the activated direct memory access channel. The target memory address offset is concatenated with the base starting address of the static storage matrix using hardware address concatenation; After activation, the direct memory access channel is located to the target addressing unit. The first discrete torque reference point and the adjacent second discrete torque reference point in the target addressing unit are transported in parallel to the operation cache area through the internal data bus as virtual load discrete feature data.

[0029] Specifically, a global reference clock source generates a physical clock signal. The physical bus connects the trigger level of the unique global reference clock source to the synchronization input port of the hardware timer. The edge-capturing circuit at the bottom layer of the hardware timer detects the trigger level. The hardware timer is configured in shadow register loading mode. The initial phase value is pre-written into the phase shadow register of the hardware timer. At the moment when the physical boundary of the trigger level transition is captured, the synchronization control logic of the hardware timer bypasses the normal accumulation cycle. The loading circuit, relying on the shadow register loading mechanism of the hardware sequencer, hard copies the initial phase value in the phase shadow register to the main counter, completing the forced overwrite of the count value. The shadow register loading mechanism avoids the main counter value comparison mismatch caused by asynchronous writing. The hardware control flow completes the forced overwrite of the hardware timer count value through the above erase and load actions. The mathematical definition model of the main counter reset process is expressed as: ; Where parameters This represents the initial phase value forcibly loaded into the main counter; it is a dimensionless, purely numerical integer. (Parameter) It represents the maximum carrier cycle count value configured by the microcontroller according to the set pulse width modulation switching frequency, and is a dimensionless pure digital integer.

[0030] The underlying event triggering subsystem is triggered when the main counter completes its initial phase value loading. The event triggering subsystem captures the counter reset state and generates a timer synchronization output signal. The microcontroller's silicon architecture includes a direct memory access request multiplexer. The timer synchronization output signal enters the input channel of the direct memory access request multiplexer. The underlying configuration register hardwires the corresponding channel output of the direct memory access request multiplexer to the activation enable terminal of the target direct memory access channel. The timer synchronization output signal travels through the direct memory access request multiplexer to form a pure hardware event pulse. This hardware event pulse activates the direct memory access controller's operation gating.

[0031] During a normal operating cycle, the CPU core is responsible for executing arithmetic instructions. The CPU core remains in a sleep state during the current cascading triggering phase. This sleep state disconnects the CPU core's instruction fetch bus activity. Hardware synchronization event pulses act as purely physical level switches, activating the execution gating of the direct memory access controller. The activation of the execution gating signifies the completion of the direct memory access channel activation action. This process constructs a purely hardware event cascading response mechanism independent of software code intervention.

[0032] The central processing unit (CPU) in sleep mode does not consume any computational power during the addressing process. The internal address arithmetic unit of the direct memory access controller reads the target memory address offset from the source address offset register channel. The address arithmetic unit performs hardware address concatenation by combining the target memory address offset with the base starting address of the static storage matrix in non-volatile memory. The hardware address concatenation operation performs low-level binary addition, and its addressing mathematical model is constructed as follows: ; Where parameters Represents the absolute physical address after hardware address concatenation, i.e., the memory location of the target addressing unit, and has no physical dimensions. Parameter This represents the base address of the static storage matrix stored in non-volatile memory; it has no physical dimensions. Parameter It represents the target memory address offset generated after the system parses the valid bit data, and has no physical dimension.

[0033] The concatenated absolute physical address guides the activated Direct Memory Access (DMI) channel to accurately locate the target addressing unit. The DMI controller gains control of the system data bus. The DMI controller sends a read request for the target addressing unit to the non-volatile memory via the address bus. The internal data bus establishes a direct data transfer channel. The read logic extracts the first discrete torque reference point locked within the target addressing unit. The read logic extracts the adjacent second discrete torque reference point according to the consecutive address increment rule. The internal data bus transfers the first discrete torque reference point and the adjacent second discrete torque reference point in parallel to the arithmetic buffer. The two data points stored in the arithmetic buffer are combined to form the virtual load discrete characteristic data required by the system. The flow of the input clock level to the output characteristic data achieves a closed loop.

[0034] S4. Perform interpolation operations based on the discrete characteristic data of the virtual load to generate target duty cycle data; Furthermore, in S4, interpolation is performed based on the discrete characteristic data of the virtual load to generate target duty cycle data, including: Wake up the central processing unit kernel to read the first discrete torque reference point and the second discrete torque reference point; The pure digital normalized weighting coefficients of the instantaneous virtual angular velocity in the discrete interval are calculated using subtraction and division hardware multiplier instructions. The difference between the second discrete torque reference point and the first discrete torque reference point is multiplied and scaled using pure digital normalized weighting coefficients to generate a compensation torque value. The compensation torque value is summed with the first discrete torque reference point to output the target virtual load torque. The target duty cycle data is obtained by multiplying the target virtual load torque by the preset modulation coefficient.

[0035] Specifically, after the hardware triggering action at the bottom layer of the control logic chain is completed, the wake-up interrupt instruction is sent to the CPU core. The CPU core terminates its sleep state. The instruction prefetch bus resumes normal instruction fetching. The CPU core accesses the arithmetic cache through the internal data bus and reads the pre-loaded first and second discrete torque reference points.

[0036] After the reading operation is completed, the system initiates the calculation mechanism. The arithmetic logic unit retrieves the instantaneous virtual angular velocity intercepted at the front end of the control loop, and extracts the corresponding first and second reference angular velocity values ​​based on the system mapping system. The central processing unit core calls subtraction and division hardware multiplier instructions to perform basic data trimming and fitting. The execution logic of the microcontroller core constructs the following first-order linear interpolation space mathematical model: ; ; ; The parameters covered by the mathematical model of the first-order linear interpolation space are subject to strict physical dimensional constraints. Among these parameters... This represents a pure numerical normalized weighting coefficient generated by the central processing unit's core operations. The microprocessor uses the instantaneous virtual angular velocity minus the first reference angular velocity value to generate the velocity deviation numerator. The microprocessor uses the second reference angular velocity value minus the first reference angular velocity value to generate the interval span denominator. The physical units covered by the numerator and denominator are both radians per second. After the division hardware multiplier instruction is completed, the radians per second physical unit dimension completely cancels out. The cancellation of physical units is assigned to parameters. Absolutely dimensionless, purely numerical physical properties.

[0037] parameter This represents the instantaneous virtual angular velocity acquired by the microcontroller through tracking, with the physical dimension set to radians per second. Parameter This represents the first reference angular velocity value corresponding to the first discrete torque reference point in the static discrete mapping, with the physical dimension set to radians per second. Parameter The value of the second reference angular velocity corresponding to the second discrete torque reference point in the static discrete mapping is represented by the physical dimension set to radians per second.

[0038] parameter The target virtual load torque represents the output of the addition operation, and its physical dimension is defined as Newton-meter. Parameter This represents the first discrete torque reference point read by the system, with its physical dimension defined as Newton-meter. Parameter The second discrete torque reference point, representing the system's reading, is defined by its physical dimension as Newton-meter. The arithmetic logic unit utilizes parameters... For parameters With parameters The difference is used to perform a multiplication scaling operation to generate a compensation torque value. The compensation torque value and parameters... Output parameters after performing the addition and summation operation. .

[0039] parameter This represents the target duty cycle data generated at the end of the computation data stream. The target duty cycle data is a dimensionless pure integer threshold for the duty cycle of the hardware timer pulse width output. (Parameter) This represents the preset modulation coefficient set in the electromagnetic conversion process. To ensure absolute uniformity and standardization of dimensions on both sides of the equation conversion, the parameter... The physical dimension of the quantity is forcibly set to the reciprocal of the Newton-meter.

[0040] After the central processing unit (CPU) core completes the multiplication-accumulation instruction stream, it extracts the target duty cycle data. This target duty cycle data is then pushed to an internal register and written to the waiting bus interface. Through this sequence of steps, the data link layer completes the essential conversion loop from nonlinear mechanical characteristics to underlying electrical control instructions.

[0041] S5. Using the global reload enable signal triggered by the hardware event cascading response mechanism, the target duty cycle data is synchronously written to the active shadow register. Furthermore, in S5, the global reload enable signal triggered by the hardware event cascading response mechanism synchronously writes the target duty cycle data into the active shadow register, including: Write the target duty cycle data buffer to the preload register, which is in isolated working state; The hardware comparison monitoring circuit is configured to continuously compare the real-time value of the main counter contained in the hardware timer with the boundary of the zero count value; At the absolute moment when the real-time value reaches the zero count boundary, the hardware comparison monitoring circuit outputs a global reload enable signal. By using the global reload enable signal to force the internal multiplexed bus to be turned on, the target duty cycle data in the preload register is loaded into all active shadow registers in parallel and synchronously within a single clock cycle.

[0042] Specifically, after the CPU core completes the arithmetic operations, the target duty cycle data is delivered to the peripheral register address mapping area via the internal data bus. The target duty cycle data is then buffered and written to the preload register. At this time, the preload register is in an isolated operating state. This isolated operating state physically severs the direct connection between the cached data and the underlying pulse width modulation comparison logic, avoiding waveform truncation and divergence faults caused by unaligned refresh.

[0043] The microcontroller's silicon netlist contains a hardware comparison monitoring circuit. The input probes of this circuit continuously intercept the real-time value of the main counter contained in the hardware timer. The underlying control logic defines a fixed zero-count value boundary. The hardware comparison monitoring circuit continuously performs a hard-wired comparison operation between the real-time value of the main counter and the zero-count value boundary. A digital Boolean comparison mathematical model is constructed for this hardware triggering mechanism: ; The parameters within the mathematical model of digital Boolean comparisons strictly map to the level states of the underlying registers. Among these parameters... This represents the global reload enable signal output by the hardware comparison monitoring circuit after the condition is met. It is a dimensionless Boolean logic level state. Parameter This represents the real-time value of the main counter read by the hardware comparison monitoring circuit at each system clock cycle; it is a dimensionless, purely digital integer. (Parameter) Zero represents the zero-count boundary defined by the underlying structure of the silicon wafer, and is a purely numerical constant with no physical quantity.

[0044] The master counter continuously jumps according to the clock pulse. At the absolute hardware moment when the real-time value of the master counter reaches the zero count boundary, the parameters... With parameters The values ​​are perfectly aligned. The pulse width modulation module within the microcontroller is configured with global load control logic. The underlying initialization program pre-sets the global load enable bit of the pulse width modulation module to the active state. The global load trigger event selection register is configured to bind to the zero count value boundary of the main counter. When the hardware comparison monitoring circuit detects that the main counter has reached the zero count value boundary, it outputs a global reload enable pulse that meets the configuration conditions.

[0045] The global reload enable pulse directly triggers the global load control logic. This logic forcibly overwrites the regular local register refresh timing. Within one hardware clock cycle of the global reload enable pulse's active state, the global load control logic opens the data transmission gate between the preload register and the active shadow registers. The target duty cycle data in the preload register is transferred in parallel to all active shadow registers. The single-cycle global load mechanism based on zero-count boundary events ensures absolute alignment between the control data refresh time and the physical pulse width modulation carrier start point. Within a single clock cycle, the internal multiplexed bus uses a parallel transmission mechanism to synchronously load the target duty cycle data in the preload register into all active shadow registers. All active shadow registers complete the erasure of old data and the overwriting of new data at the same nanosecond level. The target duty cycle data crosses from the data buffer layer into the hardware execution layer with actual comparison control authority, realizing a closed-loop timing flow for writing the underlying digital control quantity into the channel.

[0046] like Figure 5 As shown, S6 generates an inverter drive waveform based on the active shadow register and controls the load inverter to apply a simulated load current to the inverter under test through a three-phase filter reactor. Furthermore, in S6, an inverter drive waveform is generated based on the active shadow register, and the load inverter is controlled to apply a simulated load current to the inverter under test via a three-phase filter reactor, including: Extract the digital comparison threshold stored in the active shadow register after synchronous loading; The underlying hardware logic comparator is used to perform a level cross-comparison between the digital comparison threshold and the continuously generated triangular wave carrier sequence. The output level is flipped at the moment when the comparison level inverts. A preset dead-time level protection interval is injected into the output level sequence after the flip, generating a pulse width modulation voltage square wave sequence with complementary dead-time characteristics as the inverter drive waveform.

[0047] In S6, an inverter drive waveform is generated based on the active shadow register, and the load inverter is controlled to apply a simulated load current to the inverter under test via a three-phase filter reactor, including: The inverter drive waveform is delivered to the trigger electrode of the insulated gate bipolar transistor of the inverter power module configured inside the frequency converter using an isolated drive optocoupler. Controlling the insulated gate bipolar transistor to perform high-frequency switching action, and constructing a driving potential with fundamental and harmonic characteristics at the AC terminal of the inverter power module; By utilizing the transient potential difference between the driving potential and the output potential of the frequency converter under test, the driving electron flow passes through the three-phase filter reactor to form a simulated load current.

[0048] The simulated load current is rectified into DC feedback power and directly injected into the common DC bus.

[0049] Specifically, the underlying extraction network reads the active shadow register after synchronization is complete. The value stored in the active shadow register is defined as the digital comparison threshold. The hardware timer uses an internal high-frequency counter to continuously accumulate and decrement according to the clock beat, generating a continuously generated triangular wave carrier sequence. The underlying hardware logic comparator extracts the digital comparison threshold and the triangular wave carrier sequence and sends them to the hardware comparison array to perform level cross-comparison. The level cross-comparison operation is constructed in the state machine mathematical model at the silicon level as follows: ; The independent parameters covered by the state machine mathematical model have a clear circuit mapping relationship. Among these parameters... This represents the digital logic level state output by the underlying hardware logic comparator after comparison and determination; it is a dimensionless Boolean variable. (Parameter) The threshold value for comparing numbers extracted from the active shadow register is a dimensionless, pure integer. (Parameter) This represents the count value of the transient triangular wave carrier sequence generated by the hardware timer; it is a dimensionless, purely numerical integer. (Parameter) The physical independent variable representing the evolution of the microcontroller's runtime is measured in seconds.

[0050] At the absolute moment when the digital comparison threshold and the triangular wave carrier sequence intersect, causing the comparison level to reverse, the underlying hardware logic comparator executes the output level flipping action according to the state machine mathematical model. Single-transistor level flipping can easily cause shoot-through short-circuit faults in the upper and lower transistors of the bridge arm. The dead-time generation circuit takes over the output level sequence after the flip and forcibly injects a preset dead-time level protection interval into the output level sequence. The dead-time level protection interval forces the complementary drive level to have a physical delay blind zone that is absolutely off. After the delay blind zone is eliminated, a pulse-width modulated voltage square wave sequence with complementary dead-time characteristics is generated. The pulse-width modulated voltage square wave sequence serves as the final inverter drive waveform and is output externally from the microcontroller's internal bus.

[0051] The inverter drive waveform travels through the circuit board traces to the isolation drive optocoupler. The isolation drive optocoupler performs electrical isolation and current cascade amplification to deliver the inverter drive waveform to the trigger electrode of the insulated-gate bipolar transistor (IGBT) in the inverter power module configured inside the frequency converter. The gate of the IGBT absorbs the drive level, forcing the device to perform a high-frequency switching action. This high-frequency switching action cuts the DC bus voltage at the AC terminal of the inverter power module at a high frequency, constructing a drive potential with fundamental and harmonic characteristics.

[0052] A transient potential difference is formed between the driving potential and the output potential of the frequency converter under test in the three-phase AC electrical topology. This transient potential difference creates an electromagnetic field that forces an electron flow through the three-phase filter reactor. Constrained by inductive characteristics, the electron flow undergoes a smooth evolution, ultimately forming a simulated load current. The differential-integral mathematical model of the transient current corresponding to the electromagnetic transformation stage is as follows: ; The parameters in the current integral mathematical model are closely related to the physical topological elements. Among these parameters... This represents the instantaneous value of the simulated load current actually formed through the three-phase filter reactor, with the physical dimension being amperes. Parameter The physical constant representing the fixed inductance of a three-phase filter reactor is expressed in Henry. This represents the transient drive potential output from the AC terminal of the inverter power module, with the physical dimension in volts. Parameter This represents the opposition potential generated at the corresponding port of the frequency converter under test, with the physical dimension being volts. Parameter This represents the time-dependent infinitesimal variable within the framework of integral operations, with the physical dimension being seconds.

[0053] Simulated load current flows along the power cable into the inverter bridge network of the inverter under test. The inverter under test is controlled to operate in a rectified feedback mode. The freewheeling diode network and the insulated-gate bipolar transistor perform reverse rectification to convert the simulated load current into DC feedback energy. The DC feedback energy is directly injected into the common DC bus through the bus terminals, completing the energy rotation of the closed-loop physical test circuit.

[0054] Example 2: In the factory full-load aging and dynamic performance testing scenarios of large heavy-duty frequency converters used in high-speed CNC punching machines or port cranes, industrial sites typically use a pure electrical drag test platform that directly connects the frequency converter under test and the load frequency converter to the same DC bus to achieve internal feedback circulation of test electrical energy. However, the aforementioned application scenarios face extremely stringent technical challenges: On the one hand, realistic nonlinear mechanical friction and transient violent impacts demand extremely high dynamic response speeds from the control system. Existing virtual loading architectures heavily rely on the central processing unit to execute software interrupt services to solve complex mechanical dynamic differential equations in real time. The absolute physical time consumption of code computation inevitably leads to microsecond-level phase lag in the updating of the underlying inverter drive waveform, resulting in severe distortion of the simulation results of millisecond-level transient physical loads. On the other hand, two high-power frequency converters asynchronously perform switching operations at high frequencies across the DC bus. The pulse width modulation carriers of the two converters are prone to superposition of in-phase levels, generating extremely intense high-frequency pulsating ripple currents on the common DC bus capacitor. This directly causes localized thermal stress concentration and uncontrollable physical heat loss in the equivalent series resistance inside the capacitor, severely restricting the operational reliability and underlying hardware lifespan of the full-load test system. To solve these problems, this invention provides an energy-saving frequency converter loading method, such as... Figure 1 As shown. The specific implementation process of this method is as follows: The test system relies on a common DC bus and a three-phase filter reactor to electrically connect the loaded inverter and the inverter under test. The microcontroller extracts the pulse width modulation pulses output from the inverter under test to establish a unique global reference clock source. The host computer issues dynamic test condition commands. The system parses the dynamic test condition commands and intercepts the instantaneous virtual angular velocity. The effective bits of the instantaneous virtual angular velocity undergo numerical conversion to generate the target memory address offset. The unique global reference clock source triggers a hardware event cascading response mechanism within the underlying silicon routing. The forced overwrite of the hardware timer count value and the activation of the direct memory access channel are forcibly executed synchronously. After the activation is completed, the direct memory access channel retrieves the virtual load discrete characteristic data from the static storage matrix across the bus based on the target memory address offset. The arithmetic unit uses the virtual load discrete characteristic data to perform interpolation calculations and outputs the target duty cycle data. The hardware event cascading response mechanism continues to run, inducing a global reload enable signal. The global reload enable signal forces the target duty cycle data to be written in parallel to the active shadow register. The level threshold latched in the active shadow register is reconstructed into the inverter drive waveform. The load inverter, based on the inverter drive waveform, performs high-frequency chopping and physically injects simulated load current into the inverter under test through a three-phase filter reactor.

[0055] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An energy-saving inverter loading method, applied in a testing system, the testing system comprising the inverter under test, the loading inverter, a common DC bus, and a three-phase filter reactor, characterized in that, Includes the following steps: S1. Extract the pulse width modulation pulse output by the frequency converter under test, and configure the pulse width modulation pulse as a unique global reference clock source; S2. Parse the dynamic test condition instructions to extract the instantaneous virtual angular velocity, and map the effective bit data of the instantaneous virtual angular velocity to the target memory address offset; S3. Based on the unique global reference clock source, trigger the hardware event cascading response mechanism, synchronously execute the hardware timer count value forced overwrite action and the direct memory access channel activation action, and transfer the virtual load discrete feature data from the static storage matrix through the activated direct memory access channel according to the target memory address offset. S4. Perform interpolation operations based on the virtual load discrete characteristic data to generate target duty cycle data; S5. Using the global reload enable signal triggered by the hardware event cascading response mechanism, the target duty cycle data is synchronously written into the active shadow register. S6. Based on the active shadow register, generate an inverter drive waveform and control the loaded inverter to apply a simulated load current to the inverter under test via the three-phase filter reactor.

2. The energy-saving inverter loading method according to claim 1, characterized in that, In S1, the step of extracting the pulse width modulation pulse output by the inverter under test and configuring the pulse width modulation pulse as a unique global reference clock source includes: A direct connection routing channel is configured between the external physical pins of the loaded frequency converter and the internally contained input cross switch matrix; The input crossbar switch matrix is ​​used to shield the local crystal clock signal input within the microcontroller hardware architecture; Extract the rising edge transition level of the pulse width modulation pulse output by the frequency converter under test; The rising edge transition level is injected into the internally configured hardware phase-locked loop logic; After the hardware phase-locked loop logic is locked, a forced phase alignment action is performed to generate a synchronous square wave sequence as the unique global reference clock source.

3. The energy-saving inverter loading method according to claim 1, characterized in that, In S2, the process of parsing the dynamic test condition instructions to extract the instantaneous virtual angular velocity and mapping the effective bit data of the instantaneous virtual angular velocity to a target memory address offset includes: Receive a two-dimensional data table containing nonlinear mechanical friction characteristics; The two-dimensional data table is converted into the static storage matrix in a one-dimensional continuous address format; The static storage matrix is ​​burned into the contiguous physical address space of the non-volatile memory; The extracted instantaneous virtual angular velocity is input into a hardware shift register; The hardware shift register performs a right shift truncation operation to remove low-order floating-point fractional data and extract the pure digital sequence in the highest bit as the effective bit data. The target memory address offset is generated by performing a low-level multiplication and combination operation on the effective bit data and the data bit width constant.

4. The energy-saving inverter loading method according to claim 1, characterized in that, In S3, the hardware event cascading response mechanism triggered based on the unique global reference clock source synchronously executes the hardware timer count value forced overwrite action and the direct memory access channel activation action, and moves the virtual load discrete feature data from the static storage matrix through the activated direct memory access channel according to the target memory address offset, including: Connect the trigger level of the unique global reference clock source to the synchronization input port of the hardware timer; Within a single clock cycle of capturing the trigger level, the existing accumulated value of the main counter contained in the hardware timer is forcibly erased; Half of the maximum carrier cycle count value is forcibly loaded into the main counter as the initial phase value, thus completing the forced overwrite of the hardware timer count value.

5. The energy-saving inverter loading method according to claim 4, characterized in that, In S3, the hardware event cascading response mechanism triggered based on the unique global reference clock source, synchronously executing the hardware timer count value forced overwrite action and the direct memory access channel activation action, and transferring virtual load discrete feature data from the static storage matrix through the activated direct memory access channel according to the target memory address offset, further includes: Extract the hardware synchronization event pulse automatically induced at the bottom layer of the silicon wafer at the moment the hardware timer count value is forcibly overwritten; The hardware synchronization event pulse is directly connected to the hardware trigger source interface of the direct memory access controller; While maintaining the CPU core in a sleep state, the operation gating of the direct memory access controller is activated by the hardware synchronization event pulse, thereby completing the direct memory access channel activation action.

6. The energy-saving inverter loading method according to claim 5, characterized in that, In S3, the hardware event cascading response mechanism triggered based on the unique global reference clock source, which synchronously executes the forced overwrite action of the hardware timer count value and the activation action of the direct memory access channel, and moves the virtual load discrete feature data from the static storage matrix through the activated direct memory access channel according to the target memory address offset, further includes: The target memory address offset is concatenated with the base starting address of the static storage matrix using hardware address concatenation. Once activated, the direct memory access channel is located to the target addressing unit. The first discrete torque reference point and the adjacent second discrete torque reference point in the target addressing unit are transported in parallel to the operation cache area through the internal data bus as the virtual load discrete feature data.

7. The energy-saving inverter loading method according to claim 1, characterized in that, In S4, the step of performing interpolation based on the discrete characteristic data of the virtual load to generate target duty cycle data includes: Wake up the central processing unit kernel to read the first discrete torque reference point and the second discrete torque reference point; The pure digital normalized weighting coefficients of the instantaneous virtual angular velocity in the discrete interval are calculated using subtraction and division hardware multiplier instructions; The difference between the second discrete torque reference point and the first discrete torque reference point is multiplied and scaled using the pure digital normalized weighting coefficient to generate a compensation torque value. The compensation torque value is summed with the first discrete torque reference point to output the target virtual load torque. The target duty cycle data is obtained by multiplying the target virtual load torque by a preset modulation coefficient.

8. The energy-saving inverter loading method according to claim 1, characterized in that, In S5, the global reload enable signal triggered by the hardware event cascading response mechanism synchronously writes the target duty cycle data into the active shadow register, including: Write the target duty cycle data buffer into the preload register, which is in isolated working state; The hardware comparison monitoring circuit is configured to continuously compare the real-time value of the main counter contained in the hardware timer with the boundary of the zero count value; At the absolute moment when the real-time value reaches the zero count value boundary, the global reload enable signal is output using the hardware comparison monitoring circuit. The internal multiplexed bus is forcibly turned on using the global reload enable signal, and the target duty cycle data in the preload register is loaded into all the active shadow registers in parallel and synchronously within a single clock cycle.

9. The energy-saving inverter loading method according to claim 1, characterized in that, In S6, the step of generating an inverter drive waveform based on the active shadow register and controlling the loaded inverter to apply a simulated load current to the inverter under test via the three-phase filter reactor includes: Extract the digital comparison threshold stored in the active shadow register after synchronous loading; The digital comparison threshold is compared with the level of a continuously generated triangular wave carrier sequence using a low-level hardware logic comparator. The output level is flipped at the moment when the comparison level inverts. A preset dead-time level protection interval is injected into the output level sequence after the flip, generating a pulse width modulation voltage square wave sequence with complementary dead-time characteristics as the inverter drive waveform.

10. The energy-saving inverter loading method according to claim 9, characterized in that, In S6, the step of generating an inverter drive waveform based on the active shadow register and controlling the loaded inverter to apply a simulated load current to the inverter under test via the three-phase filter reactor includes: The inverter drive waveform is delivered to the trigger electrode of the insulated gate bipolar transistor of the inverter power module configured inside the load inverter using an isolation drive optocoupler; The insulated gate bipolar transistor is controlled to perform high-frequency switching action, and a driving potential with fundamental and harmonic characteristics is constructed at the AC terminal of the inverter power module. The transient potential difference between the driving potential and the output potential of the frequency converter under test is used to drive the electron flow through the three-phase filter reactor to form the simulated load current. The simulated load current is rectified into DC feedback power and directly injected into the common DC bus.

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