Chip testing method, electronic device, and storage medium
Patent Information
- Application Number
- CN202510488311.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-17
- Publication Date
- 2026-10-23
AI Technical Summary
[0004]随着芯片引脚数量的增加，测试机需要更多的通道来处理这些信号，增加了硬件资源的需求，也提高了测试的成本
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Figure CN122962377A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of wafer fabrication, and more particularly to a chip testing method, electronic device, and storage medium. Background Technology
[0002] With advancements in semiconductor technology, wafer node sizes are continuously shrinking, integration levels are increasing, and transistor density within chips is also rising. Increased transistor density means chips can support more functions and more complex calculations, which typically requires more input / output (I / O) interfaces to communicate with external devices or other chips, thus increasing the number of pins on the chip.
[0003] Each chip pin typically corresponds to a signal channel. The test machine needs to use these channels to send input signals to the chip or receive output signals from the chip.
[0004] As the number of chip pins increases, the test machine needs more channels to process these signals, which increases the demand for hardware resources and also increases the cost of testing. Summary of the Invention
[0005] In a first aspect, embodiments of this application provide a chip testing method, wherein the probe card includes a plurality of first probes and a plurality of second probes, and the method includes:
[0006] A target test vector is received through a first number of the first probes, the target test vector including a first number of signal bits;
[0007] The target test vector is converted into an initial test vector, the initial test vector including a second number of signal bits, the first number being greater than the second number;
[0008] The initial test vector is sent to the pins of the chip using the second number of second probes to test the chip.
[0009] In one possible implementation, the conversion of the target test vector into the initial test vector further includes:
[0010] Receive the encoding rules corresponding to the initial test vector;
[0011] The target test vector is converted back to the initial test vector according to the encoding rules.
[0012] In one possible implementation, the encoding rules include a Huffman tree and an encoding table.
[0013] In one possible implementation, the method further includes:
[0014] The chip's initial response signal is received by a second number of the second probes;
[0015] Convert the initial response signal into the target response signal;
[0016] The target response signal is sent to the test device through a first number of the first probes, so that the test device generates test results based on the target response signal.
[0017] Secondly, this application provides a chip testing method, the method comprising:
[0018] Obtain an initial test vector, the initial test vector comprising a second number of signal bits;
[0019] The initial test vector is converted into a target test vector, the target test vector comprising a first number of signal bits, the first number being less than the second number;
[0020] The target test vector is sent to a first number of probes on a probe card through a first number of transmission channels of the test device, so that when the probe card receives the target test vector, it converts the target test vector into the initial test vector and sends it to the chip to test the chip.
[0021] In one possible implementation, converting the initial test vector into a target test vector includes:
[0022] The second number of signal bits in the initial test vector are grouped;
[0023] Generate Huffman tables and Huffman trees based on the grouping results;
[0024] Based on the Huffman table and Huffman tree, the target test vector is generated.
[0025] In one possible implementation, the method further includes:
[0026] The probe card receives the target response signal of the chip, which is obtained by the probe card based on the initial response signal of the chip. The target response signal includes a first number of signal bits, and the initial response signal includes a second number of signal bits.
[0027] Convert the target response signal into the initial response signal;
[0028] The test results of the chip are generated based on the initial response signal.
[0029] In one possible implementation, generating the test results of the chip based on the second number of initial response signals includes:
[0030] Generate a corresponding logic state based on each initial response signal and reference voltage;
[0031] The test results for the chip are generated by comparing the generated logical state with the expected logical state.
[0032] In one possible implementation, sending the target test vector to a first number of probes on the probe card via a first number of transmission channels of the test equipment includes:
[0033] After receiving the target response signal from the chip for the current cycle within a preset time, the target test vector for the next cycle is sent to the first probe of the first number of probes on the probe card through the first number of transmission channels of the test equipment.
[0034] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;
[0035] The memory stores computer-executed instructions;
[0036] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above. Attached Figure Description
[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0038] Figure 1 A schematic diagram illustrating a scenario for the chip testing method provided in this application;
[0039] Figure 2 Flowchart of the chip testing method provided in this application Figure 1 ;
[0040] Figure 3 A schematic diagram of a Huffman tree provided in an embodiment of this application;
[0041] Figure 4 A schematic diagram of a Huffman tree provided for another embodiment of this application;
[0042] Figure 5 Flowchart of the chip testing method provided in this application Figure 2 ;
[0043] Figure 6 This is a schematic diagram of a vector and response signal provided in an embodiment of this application;
[0044] Figure 7A schematic diagram of vectors and response signals provided in another embodiment of this application;
[0045] Figure 8 A schematic diagram of the probe card structure is provided for this application;
[0046] Figure 9 A schematic diagram of the structure of the electronic device provided in this application.
[0047] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0049] With advancements in semiconductor technology, wafer node sizes are continuously shrinking, leading to a corresponding reduction in transistor size and a significant increase in transistor density on chips. As the number of transistors on a chip increases, more pins are needed to support more signal channels, data buses, control signals, and so on.
[0050] After wafer manufacturing is completed and before wafer packaging, a number of unpackaged chips (bare dies) are regularly distributed on the wafer, and all the chip pins are exposed. These pins are connected to the test machine through probes on the probe card so that the chip can be tested.
[0051] For example, a probe card includes multiple tiny probes that can contact the pads or contacts of a chip. The tester includes multiple transmission channels, each corresponding to a specific signal or electrical parameter. The tester transmits the test signal to the probe card via the transmission channels, and the probe card delivers the test signal to the chip to perform chip testing.
[0052] For example, each pin on the chip is connected to a probe on the probe card, and each transmission channel on the tester is connected to a probe on the probe card, thus enabling the allocation of a corresponding transmission channel to each pin.
[0053] Therefore, as the number of chip pins increases, more transmission channels of the test machine are required, leading to increased testing costs.
[0054] Therefore, this application proposes a chip testing method. After receiving the target test vector transmitted by the test equipment through the transmission channel, the target test vector is converted into an initial test vector, and then the initial test vector is sent to the chip, thereby enabling effective testing of the chip. Furthermore, since the signal bits of the target test vector are fewer than those of the initial test vector, the occupation of the transmission channel in the test equipment can be reduced, saving test resources and reducing test costs.
[0055] Figure 1 This is a schematic diagram of a scenario for the chip testing method provided in this application, such as... Figure 1 As shown, the target test vector includes M signal bits, H0, H1, ..., HM. The test device 101 sends the target test vector to the probe card 102. The decoding unit 1021 in the probe card 102 decodes the target test vector to obtain an initial test vector, which includes N signal bits, D0, D1, ..., DN. The decoding unit 1021 in the probe card 102 sends the initial test vector to the chip 1031 on the wafer 103. Each signal bit includes a logic state of 1 or 0.
[0056] Then, the encoding unit 1022 in the probe card 102 receives the initial response signal from the chip 1031. The initial response signal includes N signal bits, each corresponding to a high-level signal (H) or a low-level signal (L). The initial response signal is compressed to obtain the target response signal, which includes M signal bits. This target response signal is then transmitted to the M transmission channels of the test device 101 through the M first probes. The test device 101 can decompress the target response signal to obtain the initial response signal and generate the test results of the chip 1031 based on the initial response signal.
[0057] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0058] Figure 2 Flowchart of the chip testing method provided in this application Figure 1 ,like Figure 2 As shown, using a probe card as the execution subject, the method includes:
[0059] S101. Receive a target test vector through a first number of first probes, the target test vector including a first number of signal bits.
[0060] In this embodiment of the application, the probe card is the interface between the test equipment and the chip. The probe card is connected to the pins of the chip through its probes and to the transmission channel on the test equipment, so as to apply the test signal output by the test equipment to the chip for testing.
[0061] A probe card may include multiple first probes and multiple second probes. Each first probe is connected to a transmission channel in the test equipment, and each second probe is connected to a pin of the chip. The first probes can be understood as the probes in the probe card that connect to the test equipment, and the second probes can be understood as the probes in the probe card that connect to the chip.
[0062] For example, the probe card can be integrated into the test equipment, and the probe card and the test equipment are separate hardware.
[0063] In this embodiment, the probe card can receive a target test vector transmitted by the test device through a first number of transmission channels via a first number of first probes. Correspondingly, each signal bit in the target test vector can be transmitted to a first probe on the probe card via a transmission channel.
[0064] It is understandable that the more signal bits in the target test vector, the more transmission channels and the more first probes are required; conversely, the fewer signal bits in the target test vector, the fewer transmission channels and the fewer first probes are required.
[0065] S102. Convert the target test vector into an initial test vector, which includes a second number of signal bits.
[0066] It should be noted that the target test vector is obtained by compressing the initial test vector. The target test vector has fewer signal bits than the initial test vector, thereby reducing the number of transmission channels required and minimizing the use of transmission channel resources on the test equipment. Furthermore, the initial test vector is used to test the chip; after obtaining the target test vector, it needs to be converted into the initial test vector to enable effective chip testing. The initial test vector is a sequence of input signals used to verify the chip's functionality and performance.
[0067] Therefore, in this embodiment of the application, after receiving the target test vector, the target test vector is converted into an initial test vector. The initial test vector may include a second number of signal bits, the second number being greater than the first number.
[0068] For example, the probe card may include a PLC (Programmable Logic Controller) or an FPGA (Field-Programmable Gate Array), both of which can perform bit-to-bit conversion.
[0069] In some embodiments, the encoding rules corresponding to the initial test vector are received, and the target test vector is converted back to the initial test vector according to the encoding rules corresponding to the initial test vector, so as to ensure the consistency of the encoding and decoding processes and the integrity of the data, so as to effectively test the chip.
[0070] For example, after an electronic device encodes an initial test vector based on a certain encoding rule, it can send the encoding rule to a probe card. Correspondingly, the probe card can convert the target test vector back to its original format based on the encoding rule. The process of converting back to the original format is called the decoding process.
[0071] Encoding rules can include, for example, Huffman coding. Huffman coding achieves efficient data compression by assigning different length binary codes to different characters—using shorter codes for high-frequency characters and longer codes for low-frequency characters—significantly reducing storage space and bandwidth required for data transmission. Furthermore, Huffman coding is a lossless compression method, ensuring the integrity of the original data. Encoding rules can also include other encoding methods.
[0072] In one specific implementation, the encoding rules corresponding to the initial test vector include a Huffman tree and a Huffman table corresponding to the initial test vector. That is, the Huffman tree and Huffman table are generated based on the initial test vector, and the target test vector is also generated based on the Huffman tree and Huffman table. Therefore, after receiving the Huffman tree and Huffman table corresponding to the initial test vector, the probe card can convert the target test vector into the initial test vector based on the Huffman tree and Huffman table.
[0073] For example, Huffman trees Figure 3 As shown, the Huffman tree includes four Huffman codes: 1, 010, 00, and 011. Each Huffman code corresponds to a character: Huffman code 1 corresponds to character A, Huffman code 010 corresponds to character B, Huffman code 00 corresponds to character C, and Huffman code 011 corresponds to character D. According to the Huffman tree, character A appears three times, character B appears once, character C appears twice, and character D appears once.
[0074] Table 1
[0075]
[0076] As shown in Table 1, if the target test vector is 10110110001100, the character group ABAACDC corresponding to the target test vector can be determined according to the Huffman tree, and then the initial test vector can be determined according to the signal group corresponding to the character in the Huffman table.
[0077] Table 2
[0078] signal group character Number of times a character appears 00 A 3 01 B 1 10 C 2 11 D 1
[0079] For example, as shown in Table 2, character A corresponds to signal group 00, character B corresponds to signal group 01, character C corresponds to signal group 10, and character D corresponds to signal group 11. Therefore, it can be determined that the initial test vector corresponding to the character group ABAACDC is 00010000101110.
[0080] For example, the electronic device can generate a Huffman tree and a Huffman table based on an initial test vector, and generate a target test vector based on the Huffman tree and the Huffman table. After generating the Huffman tree and the Huffman table, the electronic device can send the Huffman tree and the Huffman table to the probe card. The electronic device here can be other electronic devices besides the test device.
[0081] In another specific implementation, the encoding rule corresponding to the initial test vector can also be other encoding rules that can achieve vector compression, such as Run-Length Encoding (RLE) rules, prefix encoding rules, etc.
[0082] In other embodiments, the initial test vector can be obtained based on the correspondence between the initial test vector and the target test vector. For example, after generating the target test vector based on the initial test vector, the electronic device sends the correspondence between the initial test vector and the target test vector to the probe card. Here, the electronic device can be another electronic device besides the test device.
[0083] S103. The initial test vector is sent to the pins of the chip using the second number of second probes to test the chip.
[0084] For example, the initial test vector may include a second number of signal bits, thus requiring the initial test vector to be sent to a second number of pins of the chip via a second number of second probes to test the chip.
[0085] In some embodiments, the probe card can also send the initial response signal to the test equipment after receiving the initial response signal from the chip, so that the test equipment can generate test results for the chip based on the initial response signal.
[0086] In some examples, the initial response signal includes a second number of signal bits. After receiving the initial response signal from the chip through a second number of second probes, the initial response signal is compressed to obtain the target response signal. The target response signal includes a first number of signal bits, where the first number is less than the second number. Accordingly, the first number of target response signals can be sent to the test equipment through a first number of first probes. The test equipment receives the target response signals based on a first number of transmission channels and generates test results based on the target response signals, thereby reducing the occupancy of the test equipment's transmission channels.
[0087] For example, the response signal exists in the form of a high level or a low level. The high or low level can be considered a signal sequence. The signal sequence is grouped, and a Huffman table and a Huffman tree are generated based on the grouping results. Based on the Huffman table and Huffman tree, a second number of initial response signals are compressed into a first number of target response signals. For instance, characters can be formed by grouping initial response signals in pairs, or in groups of three, four, etc. Specifically, grouping can be based on the principle of maximizing the frequency of occurrence, which means maximizing the number of times a certain character appears.
[0088] Table 3
[0089]
[0090]
[0091] For example, the signal sequence consisting of 14 initial response signals is LLLHLLLLHLHHHL. As shown in Table 3, the signal sequence LLLHLLLLHLHHHL can be grouped in pairs according to the initial response signals, resulting in characters A, B, C, and D. Character A corresponds to signal group LL, character B corresponds to signal group LH, character C corresponds to signal group HL, and character D corresponds to signal group HH.
[0092] Table 4
[0093] signal group character Number of times a character appears LL A 3 LH B 1 HL C 2 HH D 1
[0094] After grouping the signal sequence, the grouping results are generated, which include signal groups, characters, and the number of times the characters appear, as shown in Table 4.
[0095] Table 5
[0096] character A B A A C D C Huffman coding H LHL H H LL LHH LL
[0097] Then, a Huffman tree and a Huffman table can be generated based on the grouping results. For example, the occurrence count of a character can be used as the leaf nodes to construct a Huffman tree, such as... Figure 3As shown in Table 5, the encoding is then accumulated from the root node to the leaf node to obtain the Huffman code. Based on the Huffman code and the character, a Huffman table is generated.
[0098] Table 6
[0099] Probe / Transmission Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 Target response signal H L H L H H L L L H H L L
[0100] As shown in Table 6, a new signal sequence HLHLHHLLLHHLL is generated based on the Huffman table and grouping results. For example, a new signal sequence is generated according to Tables 4 and 5. The new signal sequence includes 13 target response signals.
[0101] Subsequently, the compressed target response signal is sent to the test equipment, which can reduce the occupation of the test equipment's transmission channel.
[0102] Accordingly, the testing equipment can convert the first number of target response signals into a second number of initial response signals based on the Huffman tree and Huffman table described above. For example, the second number of initial response signals of the chip can be obtained based on the method of converting the target test vector into the initial test vector, which will not be elaborated here.
[0103] The chip testing method provided in this application receives a target test vector transmitted by a test device through a first number of transmission channels using a first number of first probes. The target test vector is then converted into an initial test vector, which is subsequently sent to the chip via a second number of second probes. This enables effective chip testing. Furthermore, because the number of signal bits in the target test vector is less than the number of signal bits in the initial test vector, the occupancy of transmission channels in the test device is reduced, thus lowering testing costs. Moreover, even with limited test resources, it can test chips with more pins and increase the number of chips that can be tested simultaneously.
[0104] Figure 5 Flowchart of the chip testing method provided in this application Figure 2 ,like Figure 5 As shown, using an electronic device (e.g., a test device, or a device other than a test device) as the execution subject, the method includes:
[0105] S201. Obtain the initial test vector, which includes a second number of signal bits.
[0106] The initial test vector is used to verify whether the logic function of the chip meets the design specifications. It includes a series of input signals. After these input signals are input to the chip, the chip's function and performance can be determined based on the chip's response signals.
[0107] S202. Convert the initial test vector into a target test vector, the target test vector including a first number of signal bits.
[0108] In this embodiment of the application, the initial test vector is compressed to obtain the target test vector. The number of bits in the target test vector is less than that in the initial test vector, so as to reduce the occupation of the transmission channel of the test equipment.
[0109] In some embodiments, the signal bits in the initial test vector are grouped, with each signal bit corresponding to either logic state 1 or logic state 0. A Huffman table and a Huffman tree are then generated based on the grouping results. This allows for the generation of the target test vector, achieving lossless compression of the initial test vector and ensuring data integrity. For example, characters can be formed by grouping two signal bits together, or by grouping three or four signal bits, etc. Specifically, grouping can be based on the principle of maximizing the frequency of occurrence, which means maximizing the number of times a particular character appears.
[0110] Table 7
[0111]
[0112] As shown in Table 7, the initial test vector 00010000101110 can be grouped into two signal bits per group to obtain characters A, B, C and D. Character A corresponds to signal group 00, character B corresponds to signal group 01, character C corresponds to signal group 10 and character D corresponds to signal group 11.
[0113] Table 8
[0114] signal group character Number of times a character appears 00 A 3 01 B 1 10 C 2 11 D 1
[0115] As shown in Table 8, the initial test vectors are grouped. Then, based on the grouping results, a Huffman tree can be generated, such as... Figure 3 As shown.
[0116] Table 9
[0117] character A B A A C D C Huffman coding 1 010 1 1 00 011 00
[0118] Then, a Huffman table can be generated based on the Huffman tree, as shown in Table 9.
[0119] Table 10
[0120] Probe / Transmission Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 Target test signal 1 0 1 0 1 1 0 0 0 1 1 0 0
[0121] Subsequently, a target test vector is generated based on the Huffman tree, as shown in Table 10. The target test vector includes 13 signal bits.
[0122] For example, the initial test vector includes 160 signal bits, specifically:
[0123] 10000110010110001111001101100101100011110011011001011000111 100110110011100010010000101101110110110110000011010100011001011000111100110110000101100111000100100001.
[0124] Table 11
[0125]
[0126] The initial test vectors are grouped as shown in Table 11. Then, a Huffman tree is generated based on Table 11, as follows: Figure 4 As shown.
[0127] Table 12
[0128]
[0129]
[0130] Subsequently, based on Figure 4 The Huffman table for generating Huffman variables is shown in Table 12. Accordingly, the target test vector can be generated based on Table 10 as follows:
[0131] 1010100110111101111010011011110111101001101111011110100001100 00111001100111100001100110100010010010011011110111101110100001100001110. At this point, the target test vector has 133 signal bits, which significantly reduces the occupancy of the transmission channel, saves test channel resources, and lowers test costs.
[0132] S203. The target test vector is sent to the first probe of the first probe card through the first number of transmission channels of the test equipment, so that when the probe card receives the target test vector, it converts the target test vector into an initial test vector and sends it to the chip to test the chip.
[0133] In this embodiment, the target test vector includes a first number of signal bits. Therefore, the target test vector is sent to a first number of probes on the probe card through a first number of transmission channels of the test equipment. The initial test vector includes a second number of signal bits. If the initial test vector is sent to the probe card, it needs to be sent through a second number of transmission channels, where N is greater than M and all are integers greater than 1. Therefore, sending the target test vector to the probe card can reduce the occupation of transmission channels in the test equipment and reduce test costs.
[0134] For example, if the electronic device is a test device, it can send the target test vector to a first number of first probes on the probe card through a first number of transmission channels after generating the target test vector. If the electronic device is a device other than a test device, it can send the target test vector to the test device, and then send the target test vector to a first number of first probes on the probe card through the test device's transmission channels.
[0135] In some embodiments, a target response signal of the chip sent by a probe card is received. The target response signal is obtained by the probe card based on the chip's initial response signal to reduce the occupation of the transmission channel of the test equipment. The target response signal includes a first number of signal bits, and the initial response signal includes a second number of signal bits, where the first number is less than the second number. Then, the target response signal is converted back into the initial response signal, and the chip test result is generated based on the initial response signal, thereby realizing the chip test.
[0136] In some examples, logic states can be generated based on the chip's initial response signal and reference voltage. The generated logic states are then compared to the expected logic states to produce test results. For instance, the response signal includes a response voltage. A response voltage less than or equal to a low-level voltage (Output Low Voltage, VOL) generates logic "0," and a response voltage greater than or equal to a high-level voltage (Output High Voltage, VOH) generates logic "1." The response voltage corresponding to each signal bit in the initial response signal can be compared to the high-level or low-level voltage to generate the corresponding logic state. The generated logic state is then compared to the expected logic state. If they match, the chip's functionality meets the design requirements; otherwise, it does not.
[0137] In some embodiments, after receiving the target response signal from the chip in the current cycle for a preset time, the target test vector for the next cycle can be sent to a first number of probes on the probe card through a first number of transmission channels of the test equipment. By introducing a time misalignment between input and output, the electronic device can prepare the next set of data while processing the current data, improving test efficiency, and the preset time delay can complete the necessary decoding without affecting the data flow.
[0138] For example, such as Figure 6 and Figure 7 As shown, Figure 6 Corresponding to the initial test vector and the initial response signal, it can be understood that after testing the chip based on the initial test vector, the initial response signal of the chip can be received.
[0139] Figure 7 The target test vector and target response signal are corresponding to the target test vector, which is the compressed vector of the initial test vector, and the target response signal is the compressed signal of the initial response signal.
[0140] Since the target test vector and the target response signal need to be decompressed, the output of the target test vector and the input of the target response signal are staggered by a preset time to ensure sufficient time for processing.
[0141] The chip testing method provided in this application compresses the initial test vector to obtain the target test vector. The signal bits of the target test vector are smaller than those of the initial test vector. Therefore, when the test vector is sent to the chip, the occupation of the transmission channel in the test equipment can be reduced, thereby reducing the test cost.
[0142] Figure 8 This is a schematic diagram of the probe card provided in this application, as shown below. Figure 8 As shown, the probe card provided in this embodiment includes multiple first probes 11 and multiple second probes 12, and the probe card also includes a decoding module 13.
[0143] Decoding module 13 is used to receive a target test vector through a first number of first probes 10, the target test vector including a first number of signal bits;
[0144] Decoding module 13 is also used to convert the target test vector into an initial test vector, the initial test vector including a second number of signal bits, the second number being greater than the first number;
[0145] The decoding module 13 is also used to send an initial test vector to the pins of the chip via a second number of second probes 11 to test the chip.
[0146] In one possible implementation, the decoding module 13 is specifically used to receive the encoding rules corresponding to the initial test vector and convert the target test vector back to the initial test vector according to the encoding rules.
[0147] In one possible implementation, the decoding module 13 is specifically used to receive the Huffman tree and encoding table corresponding to the initial test vector; and to convert the target test vector back to the initial test vector based on the Huffman tree and encoding table corresponding to the initial test vector.
[0148] In one possible implementation, the probe card further includes an encoding unit 14, which is used to receive a second number of initial response signals from the chip through a second number of second probes; compress the initial response signals into a target response signal, the target response signal including a first number of signal bits; and send the target response signal to a test device through a first number of first probes, so that the test device generates a test result based on the target response signal.
[0149] In one possible implementation, the probe card further includes a vector register module and registers. The vector register module receives target test vectors transmitted by the test equipment through a first number of transmission channels via a first number of first probes 11, and stores the target test vectors in the registers. The vector register module can also receive a second number of initial response signals from the chip via a second number of second probes, and store the second number of initial response signals in the registers. Based on this, sufficient time can be provided for data encoding or decoding. Encoding refers to compressing the second number of initial response signals to obtain a first number of target response signals, where the second number is greater than the first number; decoding refers to decompressing the target test vectors to obtain initial test vectors, where the initial test vectors include a second number of signal bits, and the target test vectors include a first number of signal bits.
[0150] The probe card provided in this embodiment can execute the methods provided in the above method embodiments. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0151] Figure 9 A schematic diagram of the structure of the electronic device provided in this application. Figure 9 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.
[0152] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.
[0153] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0154] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0155] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0156] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0157] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.
[0158] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.
[0159] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0160] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0161] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0162] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0163] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0164] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0165] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0166] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A chip testing method, characterized in that, The probe card includes multiple first probes and multiple second probes, and the method includes: A target test vector is received through a first number of the first probes, the target test vector including a first number of signal bits; The target test vector is converted into an initial test vector, the initial test vector including a second number of signal bits, the second number being greater than the first number; The initial test vector is sent to the pins of the chip using the second number of second probes to test the chip.
2. The method according to claim 1, characterized in that, The step of converting the target test vector into the initial test vector further includes: Receive the encoding rule corresponding to the initial test vector; The target test vector is converted back to the initial test vector according to the encoding rules.
3. The method according to claim 2, characterized in that, The encoding rules include a Huffman tree and an encoding table.
4. The method according to any one of claims 1-3, characterized in that, The method further includes: The chip's initial response signal is received by a second number of the second probes; Convert the initial response signal into the target response signal; The target response signal is sent to the test device through a first number of the first probes, so that the test device generates test results based on the target response signal.
5. A chip testing method, characterized in that, The method includes: Obtain an initial test vector, the initial test vector comprising a second number of signal bits; The initial test vector is converted into a target test vector, the target test vector including a first number of signal bits, the first number being less than the second number; The target test vector is sent to a first number of probes on a probe card through a first number of transmission channels of the test device, so that when the probe card receives the target test vector, it converts the target test vector into the initial test vector and sends it to the chip to test the chip.
6. The method according to claim 5, characterized in that, The step of converting the initial test vector into the target test vector includes: The second number of signal bits in the initial test vector are grouped; Generate Huffman tables and Huffman trees based on the grouping results; Based on the Huffman table and Huffman tree, the target test vector is generated.
7. The method according to claim 5 or 6, characterized in that, The method further includes: The probe card receives the target response signal of the chip, which is obtained by the probe card based on the initial response signal of the chip. The target response signal includes a first number of signal bits, and the initial response signal includes a second number of signal bits. Convert the target response signal into the initial response signal; The test results of the chip are generated based on the initial response signal.
8. The method according to claim 7, characterized in that, The step of generating the test results for the chip based on the initial response signal includes: Generate the corresponding logic state based on the initial response signal and the reference voltage; The test results for the chip are generated by comparing the generated logical state with the expected logical state.
9. The method according to claim 7, characterized in that, The step of sending the target test vector to a first number of probes on the probe card through a first number of transmission channels of the test equipment includes: After receiving the target response signal from the chip for the current cycle within a preset time, the target test vector for the next cycle is sent to the first probe of the first number of probes on the probe card through the first number of transmission channels of the test equipment.
10. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-9.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-9.