Resistance measurement structure, method, electronic device and storage medium

Abstract

The embodiment of the present disclosure provides a resistance measurement structure, a method, an electronic device and a storage medium, and belongs to the technical field of chips. The resistance measurement structure comprises: a first metal plate, a second metal plate, a third metal plate and a fourth metal plate arranged on a first metal wiring layer, the third metal plate and the fourth metal plate being electrically connected through a first trace; a fifth metal plate and a sixth metal plate arranged on a second metal wiring layer, the fifth metal plate and the sixth metal plate being electrically connected through a second trace; the first metal plate and the fifth metal plate being electrically connected through an electrical connector, and the second metal plate and the sixth metal plate being electrically connected through an electrical connector; the first trace and the second trace being electrically connected through a to-be-measured interlayer interconnection structure; the second metal plate and the third metal plate are used for acting on an excitation electrical quantity, and the first metal plate and the fourth metal plate are used for measuring a response electrical quantity, and the response electrical quantity is used for determining the resistance of the to-be-measured interlayer interconnection structure. The scheme can improve the accuracy of the resistance measurement result.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more particularly to a resistance measurement structure, method, electronic device, and storage medium. Background Technology

[0002] Three-dimensional integrated circuits (3D ICs) are integrated circuits that vertically stack multiple chip layers and achieve interlayer interconnection through through-silicon vias (TSVs) and hybrid bonding (HBs). The advent of 3D ICs has increased chip integration density, meaning an increase in the number of transistors that can be integrated per unit area of ​​the chip. This increased integration density leads to a larger resistive voltage drop (IR-drop), which in turn causes power integrity (PI) issues. Interlayer interconnect structures such as TSVs and HBs have relatively large parasitic resistances, capacitances, and inductances, significantly impacting the impedance of three-dimensional power distribution networks (3D-PDNs). Therefore, it is necessary to measure the resistance of interlayer interconnect structures such as TSVs and HBs to design and evaluate 3D-PDNs.

[0003] Currently, the resistance of interlayer interconnect structures is measured using the voltammetry method.

[0004] However, when using the voltmeter-ammeter method to measure the resistance of interlayer interconnect structures, contact resistance is introduced. Since the resistance of interlayer interconnect structures such as TSV and HB is relatively small, the introduced contact resistance will have a significant impact on the accuracy of the resistance measurement results, resulting in a large error in the resistance measurement results. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a resistance measurement structure, method, electronic device, and storage medium to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a resistance measurement structure is provided, comprising: a first metal wiring layer, a second metal wiring layer, and a dielectric layer, wherein the dielectric layer is located between the first metal wiring layer and the second metal wiring layer; a first metal plate, a second metal plate, a third metal plate, and a fourth metal plate are disposed on the first metal wiring layer, the third metal plate and the fourth metal plate being electrically connected via a first trace located in the first metal wiring layer; a fifth metal plate and a sixth metal plate are disposed on the second metal wiring layer, the fifth metal plate and the sixth metal plate being electrically connected via a second trace located in the second metal wiring layer; the first metal plate and the fifth metal plate are electrically connected via at least one electrical connector, and the second metal plate and the sixth metal plate are electrically connected via at least one electrical connector; the first trace and the second trace are electrically connected via at least one inter-layer interconnect structure under test; the second metal plate and the third metal plate are used to apply an excitation electrical quantity, and the first metal plate and the fourth metal plate are used to measure a response electrical quantity, the response electrical quantity being used to determine the resistance of the inter-layer interconnect structure under test.

[0007] According to a second aspect of the present disclosure, a measurement method is provided for measuring the resistance of an interlayer interconnect structure under test in a resistance measurement structure as described in the first aspect above. The method includes: applying an excitation electrical quantity through a second metal plate and a third metal plate; measuring a response electrical quantity through a first metal plate and a fourth metal plate; and determining the resistance of the interlayer interconnect structure under test based on the response electrical quantity.

[0008] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is used to store at least one executable instruction, wherein the executable instruction causes the processor to perform an operation corresponding to the resistance measurement method described in the second aspect above.

[0009] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the method described in the second aspect above.

[0010] According to a fifth aspect of the present disclosure, a computer program product is provided, which is tangibly stored on a computer-readable medium and includes computer-executable instructions that, when executed, cause at least one processor to perform the method described in the second aspect above.

[0011] According to the solution provided in this embodiment, the third and fourth metal plates are electrically connected via a first trace, the fifth and sixth metal plates are electrically connected via a second trace, the first and fifth metal plates are electrically connected via an electrical connector, the second and sixth metal plates are electrically connected via an electrical connector, the first trace and the second trace are electrically connected via the interlayer interconnect structure under test, the second metal plate, the sixth metal plate, the second trace, the interlayer interconnect structure under test, the first trace, and the third metal plate constitute an excitation circuit, and the first metal plate, the fifth metal plate, the second trace, the interlayer interconnect structure under test, the first trace, and the fourth metal plate constitute a response circuit. Thus, the resistance of the interlayer interconnect structure under test can be measured using the excitation circuit and the response circuit based on the Kelvin four-wire measurement method, eliminating lead resistance and contact resistance, and ensuring the accuracy of the resistance measurement results. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a schematic diagram of a resistance measurement structure according to an embodiment of the present disclosure;

[0014] Figure 2 This is a schematic diagram of a resistance measurement structure according to another embodiment of the present disclosure;

[0015] Figure 3 This is a schematic diagram of a resistance measurement structure according to yet another embodiment of this disclosure;

[0016] Figure 4 This is a flowchart of a resistance measurement method according to an embodiment of the present disclosure;

[0017] Figure 5 This is a schematic diagram of a reference structure according to an embodiment of the present disclosure;

[0018] Figure 6 This is a schematic diagram of a reference structure according to another embodiment of this disclosure;

[0019] Figure 7 This is a schematic diagram of a reference structure according to yet another embodiment of this disclosure;

[0020] Figure 8 This is a flowchart illustrating the derivation method of the resistance calculation formula according to an embodiment of this disclosure;

[0021] Figure 9 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0022] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0023] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0024] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0025] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0026] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0027] First, some nouns or terms appearing in the description of the embodiments of this disclosure shall be interpreted as follows:

[0028] Chip: Also known as an integrated circuit (IC), a chip is a miniature electronic device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) onto a small semiconductor material. Chips can be classified into various types based on their function and application, such as Central Processing Units (CPUs), Application-Specific Integrated Circuits (ASICs), and Field-Programmable Gate Arrays (FPGAs).

[0029] Metal wiring layer: The metal wiring layer is a metal line layer used to connect various components and realize electrical connections during the chip packaging process. The metal wiring layer enables the signals inside the chip to be effectively transmitted to the outside, and also supports power distribution and signal processing.

[0030] Through-Silicon Via (TSV): A through-silicon via is a vertical interconnect technology used in three-dimensional integrated circuits and advanced packaging technologies. It enables electrical connections between chip layers by creating tiny holes in a silicon wafer and filling them with conductive materials (such as copper).

[0031] Hybrid Bonding (HB) is an advanced chip stacking and interconnect technology that combines the features of direct bonding and metal interconnects to achieve high-density, high-performance three-dimensional integrated circuits and advanced packaging. Hybrid bonding achieves direct electrical and mechanical connections between chips by simultaneously forming insulating layers and metal connection points on the chip surface.

[0032] Resistance measurement structure

[0033] Figure 1 and Figure 2 A schematic diagram of a resistance measurement structure according to an embodiment of this disclosure is shown. Figure 1 As shown, the resistance measurement structure 10 includes a first metal wiring layer 11, a second metal wiring layer 12 and a dielectric layer 13. The dielectric layer 13 is located between the first metal wiring layer 11 and the second metal wiring layer 12. The dielectric layer 13 is an insulating material, such as a silicon wafer.

[0034] Combination Figure 1 and Figure 2A first metal wiring layer 11 is provided with a first metal plate 111, a second metal plate 112, a third metal plate 113, and a fourth metal plate 114. The third metal plate 113 and the fourth metal plate 114 are electrically connected through a first trace 115 located on the first metal wiring layer 11. A second metal wiring layer 12 is provided with a fifth metal plate 121 and a sixth metal plate 122. The fifth metal plate 121 and the sixth metal plate 122 are electrically connected through a second trace 123 located on the second metal wiring layer 12. The first trace 115 and the second trace 123 can be straight lines or broken lines. The wiring form of the first trace 115 and the second trace 123 is not limited in this embodiment.

[0035] The first metal plate 111 and the fifth metal plate 121 are electrically connected by at least one electrical connector 14, and the second metal plate 112 and the sixth metal plate 122 are electrically connected by at least one electrical connector 14. The electrical connector 14 is a cylindrical conductor that passes through the dielectric layer 13 along a direction perpendicular to the dielectric layer 13. One end of the electrical connector 14 is electrically connected to the first metal plate 111 or the second metal plate 112, and the other end of the electrical connector 14 is electrically connected to the fifth metal plate 121 or the sixth metal plate 122.

[0036] When the first metal plate 111 and the fifth metal plate 121 are electrically connected by a plurality of electrical connectors 14, as an example Figure 2 The diagram illustrates that the first metal plate 111 and the fifth metal plate 121 are electrically connected via two electrical connectors 14. These connectors 14 are connected in parallel, meaning that both ends of each connector 14 are electrically connected to the first metal plate 111 and the fifth metal plate 121, respectively. The diagram also illustrates the second metal plate 112 and the sixth metal plate 122 being electrically connected via multiple electrical connectors 14, as an example. Figure 2 The second metal plate 112 and the sixth metal plate 122 are shown to be electrically connected by two electrical connectors 14, which are connected in parallel, that is, the two ends of each electrical connector 14 are electrically connected to the second metal plate 112 and the sixth metal plate 122 respectively.

[0037] It should be noted that the number of electrical connectors 14 connecting the first metal plate 111 and the fifth metal plate 121 may differ from the number of electrical connectors 14 connecting the second metal plate 112 and the sixth metal plate 122. The specifications of the electrical connectors 14 connecting the first metal plate 111 and the fifth metal plate 121 may differ from the specifications of the electrical connectors 14 connecting the second metal plate 112 and the sixth metal plate 122. When the first metal plate 111 and the fifth metal plate 121 are electrically connected by multiple electrical connectors 14, the specifications of these multiple electrical connectors 14 may be different. Similarly, when the second metal plate 112 and the sixth metal plate 122 are electrically connected by multiple electrical connectors 14, the specifications of these multiple electrical connectors 14 may be different.

[0038] The first trace 115 and the second trace 123 are electrically connected through at least one inter-layer interconnect structure 15 under test, as an example. Figure 2 An inter-layer interconnect structure 15 under test is shown. The inter-layer interconnect structure 15 is a columnar conductor that runs perpendicular to the dielectric layer 13. The inter-layer interconnect structure 15 passes through the dielectric layer 13. One end of the inter-layer interconnect structure 15 is electrically connected to the first trace 115, and the other end of the inter-layer interconnect structure 15 is electrically connected to the second trace 123.

[0039] In some cases, the interconnect structure 15 under test and the electrical connector 14 have the same type and specifications, while in other cases, the interconnect structure 15 under test and the electrical connector 14 have different types and / or specifications.

[0040] The second metal plate 112 and the third metal plate 113 are used to apply excitation electrical quantities, while the first metal plate 111 and the fourth metal plate 114 are used to measure response electrical quantities, which are used to determine the resistance of the interlayer interconnect structure 15 under test. The first metal plate 111 is electrically connected to the fifth metal plate 121 via an electrical connector 14. The fifth metal plate 121 is electrically connected to the first end of the interlayer interconnect structure 15 under test via a second trace 123. The second end of the interlayer interconnect structure 15 under test is electrically connected to the fourth metal plate 114 via a first trace 115. The second metal plate 112 is electrically connected to the sixth metal plate 122 via an electrical connector 14. The sixth metal plate 122 is electrically connected to the first end of the interlayer interconnect structure 15 under test via a second trace 123. The second end of the interlayer interconnect structure 15 under test is electrically connected to the third metal plate 113 via a first trace 115.

[0041] When measuring the resistance of the interlayer interconnect structure 15 under test, an excitation electrical quantity that can act on the interlayer interconnect structure 15 under test is applied through the second metal plate 112 and the third metal plate 113 as positive and negative electrodes, and the response electrical quantity acting on the interlayer interconnect structure 15 under test is measured through the first metal plate 111 and the fourth metal plate 114 as positive and negative electrodes. Then, the resistance of the interlayer interconnect structure 15 under test can be determined by the response electrical quantity.

[0042] In this embodiment, the third metal plate 113 and the fourth metal plate 114 are electrically connected via a first trace 115, the fifth metal plate 121 and the sixth metal plate 122 are electrically connected via a second trace 123, the first metal plate 111 and the fifth metal plate 121 are electrically connected via an electrical connector 14, the second metal plate 112 and the sixth metal plate 122 are electrically connected via an electrical connector 14, and the first trace 115 and the second trace 123 are electrically connected via a test layer interconnect structure 15. The second metal plate 112 and the sixth metal plate... 122, 123, the interlayer interconnect structure under test 15, the first trace 115, and the third metal plate 113 constitute an excitation circuit. The first metal plate 111, the fifth metal plate 121, the second trace 123, the interlayer interconnect structure under test 15, the first trace 115, and the fourth metal plate 114 constitute a response circuit. Thus, the resistance of the interlayer interconnect structure 15 under test can be measured based on the Kelvin four-wire measurement method through the excitation circuit and the response circuit, eliminating lead resistance and contact resistance, and ensuring the accuracy of the resistance measurement results.

[0043] In one possible implementation, such as Figure 3 The resistance measurement structure 10 shown has a seventh metal plate 124 and an eighth metal plate 125 disposed on the second metal wiring layer 12. The seventh metal plate 124 and the third metal plate 113 are electrically connected by at least one electrical connector 14, and the eighth metal plate 125 and the fourth metal plate 114 are electrically connected by at least one electrical connector 14.

[0044] The electrical connector 14 that connects the seventh metal plate 124 and the third metal plate 113 is a columnar conductor. The axis of the electrical connector 14 is perpendicular to the dielectric layer 13. The electrical connector 14 passes through the dielectric layer 13. One end of the electrical connector 14 is electrically connected to the seventh metal plate 124, and the other end of the electrical connector 14 is electrically connected to the third metal plate 113.

[0045] The electrical connector 14 that connects the eighth metal plate 125 and the fourth metal plate 114 is a columnar conductor. The axis of the electrical connector 14 is perpendicular to the dielectric layer 13. The electrical connector 14 passes through the dielectric layer 13. One end of the electrical connector 14 is electrically connected to the eighth metal plate 125, and the other end of the electrical connector 14 is electrically connected to the fourth metal plate 114.

[0046] When the seventh metal plate 124 and the third metal plate 113 are electrically connected by a plurality of electrical connectors 14, as an example Figure 3 The diagram shows the seventh metal plate 124 and the third metal plate 113 electrically connected by two electrical connectors 14. These connectors 14 are connected in parallel, meaning that each connector 14 has its two ends electrically connected to the seventh metal plate 124 and the third metal plate 113, respectively. An example is shown where the eighth metal plate 125 and the fourth metal plate 114 are electrically connected by multiple electrical connectors 14. Figure 3The eighth metal plate 125 and the fourth metal plate 114 are shown to be electrically connected by two electrical connectors 14, which are connected in parallel, i.e., the two ends of each electrical connector 14 are electrically connected to the eighth metal plate 125 and the fourth metal plate 114 respectively.

[0047] It should be noted that the number and / or specifications of the electrical connectors 14 that electrically connect the first metal plate 111 and the fifth metal plate 121, the second metal plate 112 and the sixth metal plate 122, the third metal plate 113 and the seventh metal plate 124, and the fourth metal plate 114 and the eighth metal plate 125 may be the same or different, and this disclosure does not limit the embodiments.

[0048] On the first metal wiring layer 11, the first metal plate 111 and the second metal plate 112 can be electrically connected to other traces besides the first trace 115. The third metal plate 113 and the fourth metal plate 114 can also be electrically connected to other traces besides the first trace 115. On the second metal wiring layer 12, the fifth metal plate 121 and the sixth metal plate 122 can also be electrically connected to other traces besides the second trace 123. The seventh metal plate 124 and the eighth metal plate 125 can also be electrically connected to other traces besides the second trace 123.

[0049] In this embodiment, the overall structure formed by the first metal plate 111, the second metal plate 112, the fifth metal plate 121, the sixth metal plate 122, and the second trace 123 is spatially symmetrical with the overall structure formed by the third metal plate 113, the fourth metal plate 114, the first trace 115, the seventh metal plate 124, and the eighth metal plate 125. Therefore, the sixth metal plate 122 and the seventh metal plate 124 can be used to excite electrical quantities, and the fifth metal plate 121 and the eighth metal plate 125 can be used to measure response electrical quantities. That is, the response electrical quantities can be obtained through the metal plates on the first metal wiring layer 11 or through the metal plates on the second metal wiring layer 12, which allows the user to choose flexibly and facilitates the flexibility when measuring the resistance of the interlayer interconnect structure 15 under test.

[0050] The overall structure consisting of the first metal plate 111, the second metal plate 112, the fifth metal plate 121, the sixth metal plate 122, and the second trace 123 is spatially symmetrical with the overall structure consisting of the third metal plate 113, the fourth metal plate 114, the first trace 115, the seventh metal plate 124, and the eighth metal plate 125, which reduces the manufacturing difficulty of the resistance measurement structure 10.

[0051] In one possible implementation, the electrical connector 14 and the inter-layer interconnect structure 15 under test have the same specifications, that is, the electrical connector 14 and the inter-layer interconnect structure 15 under test are electrical connection structures of the same specifications.

[0052] In one example, when the interconnect structure under test 15 is a TSV, the electrical connector 14 is a TSV with the same specifications as the interconnect structure under test 15; that is, the interconnect structure under test 15 and the electrical connector 14 are TSVs with the same size and material. When the interconnect structure under test 15 is a hybrid bond, the electrical connector 14 is a hybrid bond with the same specifications as the interconnect structure under test 15; that is, the interconnect structure under test 15 and the electrical connector 14 are a hybrid bond with the same size and material.

[0053] In this embodiment of the disclosure, the electrical connector 14 and the interlayer interconnect structure 15 under test have the same specifications, which reduces the design difficulty of the resistance measurement structure 10. When the resistance measurement structure 10 is prepared, the electrical connector 14 and the interlayer interconnect structure 15 under test can be made by the same process and equipment, which reduces the preparation difficulty of the resistance measurement structure 10.

[0054] In one possible implementation, when measuring the resistance of the interlayer interconnect structure 15 under test by the resistance measuring structure 10, an excitation current can be applied by the second metal plate 112 and the third metal plate 113, and the response voltage can be measured by the first metal plate 111 and the fourth metal plate 114. The resistance of the interlayer interconnect structure 15 under test can then be determined based on the response voltage.

[0055] When measuring the resistance of the interlayer interconnect structure 15 under test, the second metal plate 112 and the third metal plate 113 are electrically connected to the positive and negative terminals of the current source, respectively, and the first metal plate 111 and the fourth metal plate 114 are electrically connected to the positive and negative terminals of the voltmeter, respectively. The first metal plate 111, the fifth metal plate 121, the second trace 123, the interlayer interconnect structure 15 under test, the first trace 115, and the fourth metal plate 114 are connected in series to form a response circuit, and the second metal plate 112, the sixth metal plate 122, the second trace 123, the interlayer interconnect structure 15 under test, the first trace 115, and the third metal plate 113 are connected in series to form an excitation circuit.

[0056] In one example, the current source can be electrically connected to the second metal plate 112 and the third metal plate 113 respectively via pins on the corresponding metal plates, and the voltmeter can be electrically connected to the first metal plate 111 and the fourth metal plate 114 respectively via pins on the corresponding metal plates.

[0057] The current source outputs a constant current. Since the resistance of the built-in resistor in the voltmeter is much larger than the resistance of the interconnect structure 15 under test, the response circuit is in a high-impedance state relative to the excitation circuit. Therefore, the current in the response circuit is relatively small. However, because the resistance of the interconnect structure 15 under test is small, this small current in the response circuit still has a significant impact on the resistance measurement result. If there is no current in the response circuit, the current flowing through the interconnect structure 15 under test is equal to the current output by the current source. However, because there is a small current in the response circuit, the current flowing through the interconnect structure 15 under test is less than the output current of the current source. Therefore, if the resistance of the interconnect structure 15 under test is directly calculated using Ohm's law based on the output current of the current source and the voltage measured by the voltmeter, the measured resistance will have a large error. Therefore, a specific algorithm is needed to eliminate the influence of the small current in the response circuit on the resistance measurement result to ensure the accuracy of the resistance measurement result. The specific implementation of the algorithm to eliminate the influence of the small current in the response circuit on the resistance measurement result will be described in detail in subsequent embodiments.

[0058] In this embodiment, the first metal plate 111, the fifth metal plate 121, the second trace 123, the interlayer interconnect structure 15 under test, the first trace 115, and the fourth metal plate 114 are connected in series to form a response circuit. The second metal plate 112, the sixth metal plate 122, the second trace 123, the interlayer interconnect structure 15 under test, the first trace 115, and the third metal plate 113 are connected in series to form an excitation circuit. An excitation current is applied through the second metal plate 112 and the third metal plate 113, and the response voltage is measured through the first metal plate 111 and the fourth metal plate 114. The resistance of the interlayer interconnect structure 15 under test can then be determined based on the response voltage. Since the first metal plate 111, the second metal plate 112, the third metal plate 113, and the fourth metal plate 114 are all located on the first metal wiring layer 11, it is convenient to connect a current source and a voltmeter, which improves the convenience of operation during resistance measurement.

[0059] In one possible implementation, when measuring the resistance of the interlayer interconnect structure 15 under test by the resistance measuring structure 10, an excitation voltage can be applied by the second metal plate 112 and the third metal plate 113, and the response current can be measured by the first metal plate 111 and the fourth metal plate 114. Then, the resistance of the interlayer interconnect structure 15 under test can be determined based on the response current.

[0060] When measuring the resistance of the interlayer interconnect structure 15 under test, the second metal plate 112 and the third metal plate 113 are electrically connected to the positive and negative terminals of the voltage source, respectively, and the first metal plate 111 and the fourth metal plate 114 are electrically connected to the positive and negative terminals of the ammeter, respectively. The first metal plate 111, the fifth metal plate 121, the second trace 123, the interlayer interconnect structure 15 under test, the first trace 115, and the fourth metal plate 114 are connected in series to form a response circuit, and the second metal plate 112, the sixth metal plate 122, the second trace 123, the interlayer interconnect structure 15 under test, the first trace 115, and the third metal plate 113 are connected in series to form an excitation circuit.

[0061] In one example, a voltage source can be electrically connected to the second metal plate 112 and the third metal plate 113 respectively via pins on the corresponding metal plates, and an ammeter can be electrically connected to the first metal plate 111 and the fourth metal plate 114 respectively via pins on the corresponding metal plates.

[0062] The voltage source outputs a constant voltage. The resistances of the first metal plate 111, the second metal plate 112, the third metal plate 113, the fourth metal plate 114, the first trace 115, the second trace 123, and the electrical connector 14 are fixed. The current measured by the ammeter is affected by the resistance of the inter-layer interconnect structure 15 under test. For inter-layer interconnect structures 15 with different resistances, the current value measured by the ammeter is different. That is, there is a definite correspondence between the resistance of the inter-layer interconnect structure 15 under test and the current value measured by the ammeter. Therefore, the resistance of the inter-layer interconnect structure 15 under test can be determined based on this correspondence according to the response current. The specific implementation of determining the resistance of the inter-layer interconnect structure 15 under test based on the correspondence between the resistance of the inter-layer interconnect structure 15 under test and the current value measured by the ammeter will be described in detail in subsequent embodiments.

[0063] In this embodiment, an excitation voltage is applied through the second metal plate 112 and the third metal plate 113, and the response current is measured through the first metal plate 111 and the fourth metal plate 114. Then, the resistance of the interlayer interconnect structure 15 under test can be determined according to the correspondence between the response current and the resistance of the interlayer interconnect structure 15 under test and the current value measured by the ammeter. Since the first metal plate 111, the second metal plate 112, the third metal plate 113 and the fourth metal plate 114 are all located on the first metal wiring layer 11, it is convenient to connect the voltage source and the ammeter, which improves the convenience of operation in the process of measuring resistance.

[0064] In one possible implementation, when the first trace 115 and the second trace 123 are electrically connected through multiple interconnect structures 15 under test, these multiple interconnect structures 15 are connected in parallel. As an example, such as... Figure 2 and Figure 3As shown, the first trace 115 and the second trace 123 are electrically connected through two parallel inter-layer interconnect structures 15 under test.

[0065] When the first trace 115 and the second trace 123 are electrically connected through multiple interconnect structures under test 15, the total resistance of the multiple interconnect structures under test 15 connected in parallel can be determined based on the response electrical quantities. Since the resistance of each interconnect structure under test 15 is basically equal, the resistance of each interconnect structure under test 15 can be determined based on this total resistance. For example, if the first trace 115 and the second trace 123 are electrically connected through n interconnect structures under test 15 connected in parallel, where n is an integer greater than 1, and the total resistance of these n interconnect structures under test 15 connected in parallel is determined to be R based on the response electrical quantities, then the resistance of each interconnect structure under test 15 is nR.

[0066] In this embodiment of the present disclosure, the first trace 115 and the second trace 123 are electrically connected through a plurality of interconnect structures 15 under test connected in parallel. The total resistance of the plurality of interconnect structures 15 under test connected in parallel can be determined based on the response electrical quantity. Then, the average resistance of the plurality of interconnect structures 15 under test can be calculated based on the total resistance, thereby reducing the influence of the resistance deviation of different interconnect structures 15 under test on the resistance measurement results and ensuring the accuracy of the resistance measurement results of the corresponding interconnect structures 15 under test.

[0067] In one possible implementation, the electrical connector 14 can be a through-silicon via or a hybrid bond, and the interlayer interconnect structure 15 under test can be a through-silicon via or a hybrid bond.

[0068] In one example, the electrical connector 14 is of the same type as the inter-layer interconnect structure 15 under test. For example, both the electrical connector 14 and the inter-layer interconnect structure 15 under test in the resistance measurement structure 10 are through-silicon vias, or both the electrical connector 14 and the inter-layer interconnect structure 15 under test in the resistance measurement structure 10 are hybrid bonds.

[0069] In another example, the electrical connector 14 is of a different type than the inter-layer interconnect structure 15 under test. For example, the electrical connector 14 is a through-silicon via (TSV) and the inter-layer interconnect structure 15 under test is a hybrid bond, or the electrical connector 14 is a hybrid bond and the inter-layer interconnect structure 15 under test is a TSV.

[0070] It should be noted that since the type of electrical connector 14 does not affect the resistance measurement result of the interlayer interconnect structure 15 under test, the resistance measurement structure 10 can include various types of electrical connectors 14. For example, the first metal plate 111 and the fifth metal plate 121 are electrically connected through a through-silicon via (TSV), and the second metal plate 112 and the sixth metal plate 122 are electrically connected through a hybrid bonding. The two electrically connected metal plates can be electrically connected through electrical connectors 14 of different types. For example, the first metal plate 111 and the fifth metal plate 121 are electrically connected through at least one TSV and at least one hybrid bonding.

[0071] In this embodiment, the interlayer interconnect structure 15 under test can be a through-silicon via (TSV) or a hybrid bond, so the resistance of the TSV or hybrid bond can be measured by the resistance measurement structure 10, thus improving the applicability of the resistance measurement structure 10. The electrical connector 14 can be a TSV or a hybrid bond, and the type of electrical connector 14 in the resistance measurement structure 10 can be selected according to requirements to meet the personalized needs of different users.

[0072] Resistance measurement methods

[0073] Figure 4 A flowchart of a resistance measurement method according to an embodiment of the present disclosure is shown. The method is implemented based on the resistance measurement structure 10 in any of the above embodiments and is used to measure the resistance of the interlayer interconnect structure 15 under test in the resistance measurement structure 10.

[0074] like Figure 4 As shown, the resistance measurement method includes the following steps:

[0075] Step 401: Excite electrical quantities through the action of the second and third metal plates.

[0076] like Figure 2 and Figure 3 As shown, the second metal plate 112 and the third metal plate 113 act as excitation electrical quantities, which act on the excitation circuit composed of the second metal plate 112, the sixth metal plate 122, the second trace 123, the interlayer interconnection structure 15 under test, the first trace 115 and the third metal plate 113 connected in series.

[0077] In one possible implementation, the excitation electrical quantity can be either an excitation voltage or an excitation current. When the excitation electrical quantity is an excitation current, the second metal plate 112 and the third metal plate 113 are electrically connected to the positive and negative terminals of a current source, respectively, and the current source can output a constant current, such as a constant excitation current of 1A (Amperes). When the excitation electrical quantity is an excitation voltage, the second metal plate 112 and the third metal plate 113 are electrically connected to the positive and negative terminals of a voltage source, respectively, and the voltage source can output a constant voltage, such as a constant excitation voltage of 0.75V (Volts).

[0078] Step 402: Measure the response electrical quantities through the first metal plate and the fourth metal plate.

[0079] like Figure 2 and Figure 3 As shown, the response electrical quantity is measured through the first metal plate 111 and the fourth metal plate 114. The response electrical quantity is measured through a response circuit composed of the first metal plate 111, the fifth metal plate 121, the second trace 123, the interlayer interconnect structure 15 under test, the first trace 115 and the fourth metal plate 114 connected in series.

[0080] In one possible implementation, the response electrical quantity can be either a response current or a response voltage. When the excitation electrical quantity is an excitation current, the response electrical quantity is a response voltage. The first metal plate 111 and the fourth metal plate 114 are electrically connected to the positive and negative terminals of a voltmeter, respectively, and the response voltage is measured using the voltmeter. When the excitation electrical quantity is an excitation voltage, the response electrical quantity is a response voltage. The first metal plate 111 and the fourth metal plate 114 are electrically connected to the positive and negative terminals of an ammeter, respectively, and the response current is measured using the ammeter.

[0081] Step 403: Determine the resistance of the interlayer interconnect structure under test based on the response electrical quantities.

[0082] Based on Ohm's law, when the resistance of the interlayer interconnect structure 15 under test is different, the measured response electrical quantity will be different under the same excitation electrical quantity. Therefore, there is a specific correspondence between the resistance of the interlayer interconnect structure 15 under test and the response electrical quantity. This correspondence is determined by the part of the resistance measurement structure 10 other than the interlayer interconnect structure 15 under test. Therefore, after obtaining the response electrical quantity, the resistance of the interlayer interconnect structure 15 under test can be calculated based on the specific correspondence between the resistance of the interlayer interconnect structure 15 under test and the response electrical quantity.

[0083] It should be noted that the correspondence between the resistance of the interlayer interconnect structure 15 under test and the response electrical quantity is determined by the part of the resistance measurement structure 10 other than the interlayer interconnect structure 15 under test. Therefore, when the part of the resistance measurement structure 10 other than the interlayer interconnect structure 15 under test remains the same, this correspondence is applicable to resistance measurement of interlayer interconnect structures 15 with different resistances.

[0084] like Figure 2 and Figure 3As shown, the first trace 115 and the second trace 123 can be electrically connected through a single interconnect structure under test 15, or through multiple interconnect structures under test 15 connected in parallel. When the first trace 115 and the second trace 123 are electrically connected through a single interconnect structure under test 15, the resistance of the interconnect structure under test 15 can be directly determined based on the response electrical quantity. When the first trace 115 and the second trace 123 are electrically connected through multiple interconnect structures under test 15 connected in parallel, these multiple interconnect structures under test 15 have the same resistance. The total resistance of these multiple interconnect structures under test 15 connected in parallel can be calculated based on the response electrical quantity, and then the resistance of a single interconnect structure under test 15 can be determined based on this total resistance.

[0085] When determining the correspondence between the resistance of the interlayer interconnect structure 15 under test and the response electrical quantity, the influence of the resistance of the part of the resistance measurement structure 10 other than the interlayer interconnect structure 15 under test on the measurement result can be eliminated, thereby ensuring the accuracy of the resistance measurement result.

[0086] In this embodiment, after the excitation electrical quantity is applied by the second metal plate 112 and the third metal plate 113, the response electrical quantity is measured by the first metal plate 111 and the fourth metal plate 114. Then, based on the correspondence between the response electrical quantity and the resistance of the interlayer interconnect structure 15 under test, the resistance of the interlayer interconnect structure 15 under test is determined. Since the resistance of the portion of the resistance measurement structure 10 other than the interlayer interconnect structure 15 under test has been eliminated when determining the correspondence between the resistance of the interlayer interconnect structure 15 under test and the response electrical quantity, the influence of contact resistance and path resistance on the resistance measurement result is eliminated when measuring the resistance of the interlayer interconnect structure 15 under test through the resistance measurement structure 10, thus improving the accuracy of the resistance measurement result.

[0087] In one possible implementation, after obtaining the response electrical quantity, the target resistance x can be calculated using the resistance calculation formula y = kx + b, where y characterizes the response electrical quantity. When the first trace 115 and the second trace 123 are electrically connected through a single inter-layer interconnect structure 15 under test (UTT), i.e., when the number of UTT TIT structures 15 is one, the target resistance x is the resistance of the UTT TIT structure 15. When the first trace 115 and the second trace 123 are electrically connected through multiple UTT TIT structures 15 connected in parallel, i.e., when the number of UTT TIT structures 15 is multiple, the target resistance x is the parallel resistance of these multiple UTT TIT structures 15, where k and b are constants.

[0088] The resistance calculation formula is based on the portion of the resistance measurement structure 10 excluding the interlayer interconnection structure 15 under test. y is the measured response electrical quantity, x is the resistance of a single interlayer interconnection structure 15 under test or the parallel resistance of multiple interlayer interconnection structures 15 under test, coefficient k represents the proportion of change in the number of interlayer interconnection structures 15 under test, and coefficient b represents the inherent impedance of the portion of the resistance measurement structure 10 excluding the interlayer interconnection structure 15 under test.

[0089] It should be noted that the coefficient b in the resistance calculation formula can be negative, for example, the resistance calculation formula is y = 0.98x - 0.48.

[0090] In this embodiment, the resistance calculation formula is determined based on the portion of the resistance measurement structure 10 excluding the inter-layer interconnect structure 15 under test. After measuring the response electrical quantity, the corresponding electrical quantity is substituted into the resistance calculation formula to calculate the target resistance. Then, based on the target resistance and the number of inter-layer interconnect structures 15 under test in the resistance measurement structure 10, the resistance of the inter-layer interconnect structure 15 under test is obtained. When the portion of the resistance measurement structure 10 excluding the inter-layer interconnect structure 15 under test remains the same, the resistance calculation formula can be different from the resistance of the inter-layer interconnect structure 15 under test, eliminating the need to re-derive the resistance calculation formula, thereby improving the efficiency of resistance measurement.

[0091] In one possible implementation, to determine the resistance calculation formula, reference response electrical quantities can be measured using at least three reference structures. These at least three measured reference response electrical quantities are then used to calculate the resistance using the least squares method. The reference structure is identical to the resistance measurement structure 10 except for the inter-layer interconnect structure 15 under test; that is, the reference structure is obtained by replacing the inter-layer interconnect structure 15 under test in the resistance measurement structure 10 with the reference inter-layer interconnect structure. Figures 5 to 7 The schematic diagram of the reference structure 20 shown illustrates that in the reference structure 20, the first trace 115 and the second trace 123 are electrically connected through at least one reference layer interconnect structure 21, and the number of reference layer interconnect structures 21 varies in different reference structures 20. Figure 5 The reference structure 20 shown includes two parallel reference interlayer interconnect structures 21. Figure 6 The reference structure 20 shown includes three parallel reference interlayer interconnect structures 21. Figure 7 The reference structure 20 shown includes four parallel reference interlayer interconnect structures 21.

[0092] It should be noted that the reference interlayer interconnect structures 21 included in each reference structure 20 have the same specifications. The specifications of the reference interlayer interconnect structure 21 and the interlayer interconnect structure 15 under test can be the same or different. The reference interlayer interconnect structure 21 can be a through-silicon via or a hybrid bond. Figures 5 to 7The reference structure 20 shown is an example of a reference structure and does not limit the number of reference interlayer interconnect structures 21 in the reference structure 20. In other embodiments, the reference structure 20 may include more or fewer reference interlayer interconnect structures 21. For example, the reference structure 20 may include one, four, five or more reference interlayer interconnect structures 21.

[0093] The following is combined with Figures 5 to 7 The reference structure 20 shown illustrates the derivation process of the resistance calculation formula. Figure 8 This invention illustrates a method for deriving the resistance calculation formula according to an embodiment of the present disclosure, such as... Figure 8 As shown, the derivation method of the resistance calculation formula includes the following steps:

[0094] Step 801: Apply excitation electrical quantities to at least three reference structures through the corresponding second and third metal plates.

[0095] If the excitation electrical quantity acting on the reference structure 20 is the excitation current when deriving the resistance calculation formula, then when measuring the resistance of the interlayer interconnect structure 15 under test, the excitation electrical quantity acting on the resistance measurement structure 10 is the excitation current, and the excitation current acting on the reference structure 20 and the resistance measurement structure 10 are the same. If the excitation electrical quantity acting on the reference structure 20 is the excitation voltage when deriving the resistance calculation formula, then when measuring the resistance of the interlayer interconnect structure 15 under test, the excitation electrical quantity acting on the resistance measurement structure 10 is the excitation voltage, and the excitation voltage acting on the reference structure 20 and the resistance measurement structure 10 are the same.

[0096] Corresponding to the method of applying an excitation electrical quantity to the resistance measuring structure 10 in the aforementioned embodiment, when applying an excitation electrical quantity to the reference structure 20, if the excitation electrical quantity is an excitation current, the second metal plate 112 and the third metal plate 113 are electrically connected to the positive and negative terminals of the current source, respectively, and the current source outputs a constant excitation current. If the excitation electrical quantity is an excitation voltage, the second metal plate 112 and the third metal plate 113 are electrically connected to the positive and negative terminals of the voltage source, respectively, and the voltage source outputs a constant excitation voltage.

[0097] In one example, in Figures 5 to 7 In the three reference structures 20 shown, the second metal plate 112 and the third metal plate 113 are electrically connected to the positive and negative terminals of the current source, respectively, and a constant excitation current of 1A is output through the current source.

[0098] Step 802: Measure the reference response electrical quantities of each reference structure using the corresponding first and fourth metal plates.

[0099] If the reference response electrical quantity is the reference response current when deriving the resistance calculation formula, then the response electrical quantity is the response current when measuring the resistance of the interlayer interconnect structure 15 under test. If the reference response electrical quantity is the reference response voltage when deriving the resistance calculation formula, then the response electrical quantity is the response voltage when measuring the resistance of the interlayer interconnect structure 15 under test.

[0100] Corresponding to the method of measuring an electrical quantity in the resistance measuring structure 10 in the aforementioned embodiment, when measuring the reference response electrical quantity, if the reference response electrical quantity is a reference response voltage, the first metal plate 111 and the fourth metal plate 114 are electrically connected to the positive and negative terminals of the voltmeter, respectively, and the reference response voltage is measured by the voltmeter. If the reference response electrical quantity is a reference response current, the first metal plate 111 and the fourth metal plate 114 are electrically connected to the positive and negative terminals of the ammeter, respectively, and the reference response current is measured by the ammeter.

[0101] In one example, in Figures 5 to 7 In the three reference structures 20 shown, the first metal plate 111 and the fourth metal plate 114 are electrically connected to the positive and negative terminals of a voltmeter, respectively, and the reference response voltage is measured by the voltmeter. For example, for... Figure 5 The reference response voltage measured by the reference structure 20 shown is 36.46mV, for... Figure 6 The reference response voltage measured by the reference structure 20 shown is 23.74mV, for... Figure 7 The reference response voltage measured by the reference structure 20 shown is 17.64mV.

[0102] Step 803: Determine the resistance calculation formula based on the reference response electrical quantities corresponding to each reference structure, the number of reference interlayer interconnect structures included, and the resistance of the reference interlayer interconnect structures.

[0103] After measuring the corresponding reference response electrical quantities through each reference structure 20, the resistance calculation formula is derived based on the reference response electrical quantities of each reference structure 20, the number of reference interlayer interconnect structures 21 included, and the resistance of the reference interlayer interconnect structures 21, using a least squares recursive linear formula. Since there are at least three reference structures, the least squares recursive linear formula includes two unknowns, k and b. Therefore, the process of deriving the resistance calculation formula is essentially a process of solving an overdetermined equation.

[0104] It should be noted that the resistance of the reference layer interconnect structure 21 in the reference structure 20 is known when deriving the resistance calculation formula.

[0105] In one example, the resistance of the reference interlayer interconnect structure 21 is 0.07854 ohms. Figure 5The parallel resistance of the two reference layer interconnect structures 21 included in the reference structure 20 shown is 0.03927 ohms. Figure 6 The parallel resistance of the three reference layer interconnect structures 21 included in the reference structure 20 shown is 0.02618 ohms. Figure 7 The parallel resistance of the four reference interlayer interconnect structures 21 included in the reference structure 20 shown is 0.019635 ohms. Figure 5 The reference response voltage measured by the reference structure 20 shown is 36.46mV, for... Figure 6 The reference response voltage measured by the reference structure 20 shown is 23.74mV, for... Figure 7 The reference response voltage measured by the reference structure 20 shown is 17.64 mV. Based on the above information, the following system of equations can be constructed:

[0106]

[0107] By solving the above system of equations using the least squares method, we can determine that k = 0.098 and b = -0.48, thus determining the resistance calculation formula as y = 0.98x - 0.48.

[0108] In this embodiment, reference response electrical quantities are measured using at least three reference structures 20. Based on the measured reference response electrical quantities, the number of reference interlayer interconnect structures 21 included in each reference structure 20, and the resistance of the reference interlayer interconnect structures 21, a resistance calculation formula can be derived using the least squares method. Since the circuitry in the reference structure 20, excluding the reference interlayer interconnect structures 21, has been eliminated during the derivation of the resistance calculation formula, and the resistance measurement structure 10 and the reference structure 20 are identical except for the interlayer interconnect structure 15 under test, the derived resistance calculation formula eliminates path circuitry and contact resistance, ensuring the accuracy of the resistance measurement results.

[0109] It should be noted that the resistance measurement method in this embodiment is based on the resistance measurement structure in the foregoing embodiment and has the beneficial effects of the resistance measurement structure embodiment. The specific process of measuring the resistance of the interlayer interconnect structure under test can be found in the description in the foregoing resistance measurement structure embodiment, and will not be repeated here.

[0110] electronic devices

[0111] Figure 9 This is a schematic block diagram of an electronic device provided in an embodiment of this disclosure. Specific embodiments of this disclosure do not limit the specific implementation of the electronic device. Figure 9As shown, the electronic device may include: a processor 902, a communications interface 904, a memory 906, and a communications bus 908. Wherein:

[0112] The processor 902, communication interface 904, and memory 906 communicate with each other via communication bus 908.

[0113] Communication interface 904 is used to communicate with other electronic devices or servers.

[0114] The processor 902 is used to execute program 910, which can specifically execute the relevant steps in any of the aforementioned resistance measurement method embodiments.

[0115] Specifically, program 910 may include program code that includes computer operation instructions.

[0116] The processor 902 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of this disclosure. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.

[0117] RISC-V is an open-source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle. It can be applied to various aspects such as microcontrollers and FPGA chips, and can be specifically applied to fields such as IoT security, industrial control, mobile phones, and personal computers. Because it was designed with small size, speed, and low power consumption in mind, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems.

[0118] The computer operation instructions in this embodiment can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 902 can be designed based on the RISC-V instruction set. Specifically, the processor chip in the electronic device provided in this embodiment can be a chip designed using the RISC-V instruction set. This chip can execute executable code based on the configured instructions, thereby implementing the resistance measurement method in the above embodiment.

[0119] Memory 906 is used to store program 910. Memory 906 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0120] Specifically, program 910 can be used to cause processor 902 to execute the resistance measurement method in any of the foregoing embodiments.

[0121] The specific implementation of each step in program 910 can be found in the corresponding steps and units described in any of the foregoing resistance measurement method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0122] In the electronic device of this disclosure, after an excitation electrical quantity is applied through the second and third metal plates, a response electrical quantity is measured through the first and fourth metal plates. Then, based on the correspondence between the response electrical quantity and the resistance of the inter-layer interconnect structure under test, the resistance of the inter-layer interconnect structure under test is determined. Since the resistance of the portion of the resistance measurement structure other than the inter-layer interconnect structure under test has been eliminated when determining the correspondence between the resistance of the inter-layer interconnect structure under test and the response electrical quantity, the influence of contact resistance and path resistance on the resistance measurement results is eliminated when measuring the resistance of the inter-layer interconnect structure under test through the resistance measurement structure, thus improving the accuracy of the resistance measurement results.

[0123] Computer storage media

[0124] This disclosure also provides a computer-readable storage medium storing instructions for causing a machine to perform the resistance measurement method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0125] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute a part of this disclosure.

[0126] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0127] Computer program products

[0128] This disclosure also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0129] It should be understood that the various embodiments in this description are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0130] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0131] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0132] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A resistance measuring structure, comprising: A first metal wiring layer, a second metal wiring layer, and a dielectric layer, wherein the dielectric layer is located between the first metal wiring layer and the second metal wiring layer; The first metal wiring layer is provided with a first metal plate, a second metal plate, a third metal plate and a fourth metal plate, and the third metal plate and the fourth metal plate are electrically connected through a first trace located in the first metal wiring layer; A fifth metal plate and a sixth metal plate are disposed on the second metal wiring layer, and the fifth metal plate and the sixth metal plate are electrically connected through a second trace located in the second metal wiring layer; The first metal plate and the fifth metal plate are electrically connected by at least one electrical connector, and the second metal plate and the sixth metal plate are electrically connected by at least one electrical connector. The first trace and the second trace are electrically connected through at least one interlayer interconnect structure under test; The second and third metal plates are used to apply an excitation electrical quantity, and the first and fourth metal plates are used to measure a response electrical quantity, which is used to determine the resistance of the interlayer interconnect structure under test.

2. The resistance measuring structure according to claim 1, wherein, A seventh metal plate and an eighth metal plate are disposed on the second metal wiring layer; The seventh metal plate and the third metal plate are electrically connected by at least one electrical connector, and the eighth metal plate and the fourth metal plate are electrically connected by at least one electrical connector.

3. The resistance measuring structure according to claim 2, wherein, The electrical connector and the interlayer interconnect structure under test have the same specifications.

4. The resistance measuring structure according to claim 1, wherein, The second and third metal plates are used to apply an excitation current, and the first and fourth metal plates are used to measure the response voltage, which is used to determine the resistance of the interlayer interconnect structure under test.

5. The resistance measuring structure according to claim 1, wherein, The second and third metal plates are used to apply an excitation voltage, and the first and fourth metal plates are used to measure the response current, which is used to determine the resistance of the at least one interlayer interconnect structure under test.

6. The resistance measuring structure according to claim 1, wherein, When the first trace and the second trace are electrically connected through multiple inter-layer interconnect structures under test, the multiple inter-layer interconnect structures under test are connected in parallel.

7. The resistance measurement structure according to any one of claims 1-6, wherein the electrical connector comprises a through-silicon via or a hybrid bonding, and / or the interlayer interconnect structure under test comprises a through-silicon via or a hybrid bonding.

8. A resistance measurement method for measuring the resistance of an interlayer interconnect structure under test in any of the resistance measurement structures described in claims 1-7, the method comprising: The electrical quantity is excited by the action of the second metal plate and the third metal plate; The response electrical quantities are measured using the first metal plate and the fourth metal plate; The resistance of the interlayer interconnect structure under test is determined based on the response electrical quantity.

9. The method according to claim 8, wherein, Determining the resistance of the interlayer interconnect structure under test based on the response electrical quantity includes: The target resistance x is calculated using the resistance calculation formula y = kx + b, where y represents the response electrical quantity. When the number of the inter-layer interconnect structure under test is 1, the target resistance x is the resistance of the inter-layer interconnect structure under test. When the number of inter-layer interconnect structures under test is multiple, the target resistance x is the parallel resistance of the multiple inter-layer interconnect structures under test. k and b are constants.

10. The method according to claim 9, further comprising: The same excitation electrical quantity is applied to at least three reference structures by the corresponding second metal plate and the third metal plate, wherein the reference structure and the resistance measurement structure are the same except for the interlayer interconnect structure under test. The first trace and the second trace in the reference structure are electrically connected through at least one interlayer interconnect structure, and the number of interlayer interconnect structures is different in different reference structures. The reference response electrical quantities of the at least three reference structures are measured using the corresponding first metal plate and the fourth metal plate, respectively. The resistance calculation formula is determined based on the reference response electrical quantities corresponding to the at least three reference structures, the number of the included reference interlayer interconnect structures, and the resistance of the reference interlayer interconnect structures.

11. The method according to any one of claims 9-10, wherein, The excitation electrical quantity includes the excitation current, and the response electrical quantity includes the response voltage; or, The excitation electrical quantity includes the excitation voltage, and the response electrical quantity includes the response current.

12. An electronic device, comprising: The processor, the communication interface, the memory, and the communication bus communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform an operation corresponding to the resistance measurement method as described in any one of claims 8-11.

13. A computer-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the method of any one of claims 8-11.

14. A computer program product tangibly stored on a computer-readable medium and comprising computer-executable instructions that, when executed, cause at least one processor to perform the method according to any one of claims 8-11.

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