Method and apparatus for selective and adaptive margin testing

Abstract

Adaptive check and control logic and process for monitoring performance of an integrated circuit by directly determining at least one of a setup margin, a hold margin, and a voltage margin in one or more critical paths of the integrated circuit. Data states of start points and end points of the critical paths are maintained prior to adaptive testing, and a functional clock of the integrated circuit is gated. Adaptive testing is performed by loading test data into the start points of the critical paths and capturing the test data at the end points of the critical paths using an adaptive test clock. The captured data is compared to expected values to detect timing violations. When adaptive testing is complete, the data states of the start points and end points of the critical paths are reloaded, and the functional clock of the integrated circuit is enabled.

Description

Technical Field

[0001] This implementation generally relates to monitoring the performance of integrated circuits, and specifically to devices and techniques for monitoring speed and power consumption in integrated circuits. Background Technology

[0002] Power consumption is one of the key factors in the performance of integrated circuits (ICs). ICs are driven by supply voltage and clock frequency. Power consumption in ICs can be significantly reduced by lowering the supply voltage and / or clock frequency. In ICs used in mobile devices (such as smartphones, tablets, and laptops) where battery life is a critical factor, reducing power consumption can be particularly desirable. However, lowering the supply voltage and / or clock frequency may reduce the speed of IC operation. For proper functionality, critical operations in ICs need to be able to execute quickly enough.

[0003] With increasing performance demands, power consumption is becoming a bottleneck in many systems due to various factors such as peak power consumption, power density / hot spots / thermal issues, and battery life. This problem is even more pronounced in battery-operated systems, where there is a constant need to extend hold-up time.

[0004] Lowering the voltage offers significant savings in both leakage power and active power. However, the gains obtained by lowering the voltage are limited due to the need to account for manufacturing process variations and timing margins for maintaining yield. Because of these requirements, ASIC (Application-Specific Integrated Circuit) designs can sometimes include sophisticated power management mechanisms where the supply voltage and / or clock frequency can be tuned to, for example, the mainstream speed of the integrated circuit. Examples of power-saving mechanisms include Dynamic Voltage Frequency Scaling (DVFS) and Adaptive Voltage Scaling (AVS).

[0005] Performance monitors are sometimes used to adjust supply voltage and / or clock frequency. For example, a conventional performance monitor may include a replica of the delay line of the critical path in an integrated circuit and is used to provide a measurement of the integrated circuit's speed. However, conventional performance monitors do not analyze all relevant timing margins and generally operate only by predicting or estimating the performance of the integrated circuit or monitoring performance independently of the critical path, and therefore are reaching their limits in terms of power management utility. Therefore, improvements in performance monitoring mechanisms are expected. Summary of the Invention

[0006] The present invention is provided to introduce, in a simplified form, the selection of concepts further described in the following detailed description. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] One innovative aspect of the subject matter of this disclosure can be implemented in an apparatus for monitoring the performance of an integrated circuit. The apparatus includes a first adaptive check logic circuit including a first state-holding electrical component comprising one of a multiplexer or latch coupled to the start point of a critical path in the integrated circuit. The first adaptive check logic circuit including the first state-holding electrical component holds a first data state at the start point of the critical path before adaptive testing, provides an adaptive check data mode to the start point of the critical path during adaptive testing, and reloads the first data state to the start point of the critical path after adaptive testing. The apparatus also includes a second adaptive check logic circuit including a second state-holding electrical component comprising one of a multiplexer or latch coupled to the end point of the critical path in the integrated circuit. The second adaptive check logic circuit including the second state-holding electrical component holds a second data state at the end point of the critical path before adaptive testing, provides a timing violation signal indicating a set violation or hold violation in response to the adaptive check data mode during adaptive testing, and reloads the second data state to the end point of the critical path after adaptive testing. The device also includes an integrated clock gating unit coupled to the critical path. The integrated clock gating unit selectively enables the functional clock signal to the critical path and disables the adaptive test clock signal to the critical path before and after adaptive testing, and selectively disables the functional clock signal to the critical path and enables the adaptive test clock signal to the critical path during adaptive testing.

[0008] One innovative aspect of the subject matter of this disclosure can be implemented in a method for monitoring the performance of an integrated circuit. The method includes: maintaining a first data state at the start point of a critical path and a second data state at the end point of the critical path prior to adaptive testing; and disabling a functional clock signal to the critical path and enabling an adaptive test clock signal to the critical path during adaptive testing. The method also includes: providing an adaptive check data mode to the start point of the critical path during adaptive testing; and generating a timing violation signal indicating a setup violation or hold violation at the end point of the critical path during adaptive testing, in response to the adaptive check data mode. The method further includes: restoring the first data state to the start point of the critical path and the second data state to the end point of the critical path after adaptive testing; and disabling the adaptive test clock signal to the critical path and enabling a functional clock signal to the critical path after adaptive testing.

[0009] One innovative aspect of the subject matter of this disclosure can be implemented in a controller for monitoring the performance of an integrated circuit. The controller includes a processing system and adaptive checking and control logic, which includes a first adaptive checking logic circuit and a second adaptive checking logic circuit coupled to the processing system, wherein the processing system is configured to perform operations. The controller can be configured to send an adaptive test enable signal to the first adaptive checking logic circuit prior to adaptive testing to maintain a first data state at the start of the critical path, the first adaptive checking logic circuit including at least one multiplexer or latch coupled to the start of the critical path in the integrated circuit, and to send an adaptive test enable signal to the second adaptive checking logic circuit to maintain a second data state at the end of the critical path, the second adaptive checking logic circuit including at least one multiplexer or latch coupled to the end of the critical path in the integrated circuit. The controller can also be configured to send an adaptive checking clock signal during adaptive testing to disable the functional clock signal to the critical path and enable the adaptive test clock signal to the critical path. The controller can also send an adaptive check data signal during adaptive testing to provide an adaptive check mode to the start point of the critical path, and during adaptive testing, in response to the adaptive check mode, send a timing event capture signal to capture timing violation signals indicating setup violations or hold violations at the end point of the critical path. The controller can also send an adaptive check reload signal to a first adaptive check logic circuit after adaptive testing to reload a first data state to the start point of the critical path, and send an adaptive check reload signal to a second adaptive check logic circuit after adaptive testing to reload a second data signal state to the end point of the critical path, and send an adaptive check clock signal after adaptive testing to enable the function clock signal to the critical path. Attached Figure Description

[0010] This implementation is illustrated by way of example and is not intended to be limited by the figures in the accompanying drawings.

[0011] Figure 1 A simplified view of a pipeline architecture for digital circuits that may be included in an integrated circuit is shown.

[0012] Figure 2 It shows Figure 1 The example pipeline architecture for the critical path in the digital circuit shown is illustrated.

[0013] Figure 3 A pipelined architecture of digital circuitry including adaptive checking and control logic for performance monitoring of the critical path is shown.

[0014] Figure 4An example pipeline architecture with adaptive checking and control logic is shown.

[0015] Figure 5 An example pipeline architecture with adaptive checking and control logic is shown, where the critical path has a data delay chain and a clock delay chain.

[0016] Figure 6 and Figure 7 The use of each is shown separately. Figure 3-5 The adaptive checking and control logic mentioned in the text is used to illustrate the waveform of the set margin check, where there are no timing violations and there are detected timing violations.

[0017] Figure 8 and Figure 9 The use of each is shown separately. Figure 3-5 The adaptive checking and control logic mentioned in the text is used to illustrate the waveform of the margin check, where there are no timing violations and there are detected timing violations.

[0018] Figure 10 This is a flowchart illustrating an example of using the adaptive checking and control logic discussed in this paper to control an adaptive testing process.

[0019] Figure 11 A block diagram of an example controller that can be used with adaptive checking and control logic to perform margin tests as discussed herein is shown.

[0020] Figure 12 An illustrative flowchart depicting an example method for monitoring the performance of an integrated circuit, based on some implementations, is shown. Detailed Implementation

[0021] In the following description, numerous specific details, such as examples of specific components, circuits, and processes, are set forth to provide a thorough understanding of this disclosure. As used herein, the term “coupled” means directly connected to or connected via one or more intermediate components or circuits. The terms “electronic system” and “electronic device” may be used interchangeably to refer to any system capable of electronically processing information. Similarly, specific terminology is set forth in the following description and for illustrative purposes to provide a thorough understanding of aspects of this disclosure. However, it will be apparent to those skilled in the art that these specific details are not required to practice the exemplary embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring this disclosure. Subsequent portions of the detailed description are presented in accordance with other symbolic representations of procedures, logic blocks, processes, and operations on data bits within computer memory.

[0022] These descriptions and representations are means used by those skilled in the art of data processing to most effectively communicate the substance of their work to others skilled in the art. In this disclosure, procedures, logic blocks, processes, etc., are considered as self-consistent sequences of steps or instructions that lead to a desired result. These steps are those that require physical manipulation of physical quantities. Typically, although not always, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated in a computer system. However, it should be remembered that all these terms and similar terms are to be associated with appropriate physical quantities and are merely convenient notations applied to those quantities.

[0023] Unless otherwise specifically stated, as will be apparent from the following discussion, throughout this application, the use of terms such as “access,” “receive,” “send,” “use,” “select,” “determine,” “normalize,” “multiply,” “average,” “monitor,” “compare,” “apply,” “update,” “measure,” “derive,” etc., relates to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system’s memory or registers or other such information storage, transmission, or display devices.

[0024] In the accompanying drawings, a single block may be described as performing one or more functions; however, in practice, the one or more functions performed by that block may be performed in a single component or across multiple components, and / or may be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described below according to their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure. Similarly, example input devices may include components other than those shown, including well-known components such as processors, memory, etc.

[0025] Unless the techniques described herein are specifically described as being implemented in a particular manner, the techniques may be implemented in hardware, software, firmware, or any combination thereof. Any feature described as a module or component may also be implemented together in an integrated logic device or separately as a discrete but interoperable logic device. If implemented in software, the techniques may be implemented at least in part by a non-transitory processor-readable storage medium comprising instructions that, when executed, perform one or more of the methods described above. The non-transitory processor-readable data storage medium may form part of a computer program product, which may include encapsulation material.

[0026] Non-transitory processor-readable storage media may include random access memory (RAM) such as synchronous dynamic random access memory (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, and other known storage media. Additionally or alternatively, the technology may be implemented at least in part by a processor-readable communication medium that carries or transmits code in the form of instructions or data structures and is accessible, read, and / or executed by a computer or other processor.

[0027] The various illustrative logic blocks, modules, circuits, and instructions described in conjunction with the embodiments disclosed herein can be executed by one or more processors (or processing systems). As used herein, the term "processor" can refer to any general-purpose processor, special-purpose processor, conventional processor, controller, microcontroller, and / or state machine capable of executing scripts or instructions of one or more software programs stored in memory.

[0028] As discussed in this paper, performance monitoring mechanisms and techniques for integrated circuits enable measurements of set-side margins, hold-side margins, and voltage margins in designs for efficient power management, such as using adaptive voltage scaling (AVS) or similar mechanisms. The performance monitoring mechanisms and techniques discussed in this paper ensure that no errors are generated in the application data or propagated in the design circuit, thus avoiding complex architectural changes that would otherwise require error correction. Additionally, performance monitoring mechanisms and techniques improve area optimization and / or power optimization while limiting the necessary overhead. The performance monitoring mechanisms and techniques discussed in this paper are also used to optimize silicon implementation and testing costs.

[0029] This article discusses performance monitoring mechanisms and techniques that enable the measurement of set-up margin, hold-up margin, and voltage margin in the design of integrated circuits. Set-up margin and hold-up margin are critical timing parameters used to ensure reliable operation of circuits such as those in which data is transferred between flip-flops or registers based on clock signals. Set-up margin and hold-up margin are related to timing requirements relative to the clock edge.

[0030] For example, setup margin refers to the extra amount of time a data signal has to be stable and available at the input of a flip-flop or register before the clock edge triggers data capture, such as exceeding a minimum requirement. Setup margin ensures that the flip-flop captures the correct data by preventing transitions too close to the clock edge. Reducing setup margin can be desirable to decrease power requirements; however, setup violations must be avoided, as data will arrive too late to be captured.

[0031] Hold margin is another critical timing parameter, referring to the extra time a data signal remains stable at the input of a flip-flop or register after the clock edge, for example, beyond a minimum requirement. Hold margin ensures that the flip-flop captures the correct data by preventing the data from changing prematurely after the clock edge. Reducing hold margin can reduce power requirements; however, hold violations must be avoided, as the data may change prematurely, resulting in the capture of corrupted data.

[0032] Voltage margin is not a strictly timing parameter, but rather relates to the electrical operating conditions of an integrated circuit and focuses on the robustness of circuit operation across a range of supply voltages. For example, voltage margin refers to the difference between the actual supply voltage applied to a circuit and the minimum or maximum voltage required for the circuit to operate correctly under specified conditions, such as current speed, temperature, supply noise, aging, manufacturing variations, etc. Therefore, voltage margin is a measurement of how much voltage difference a circuit can tolerate before failing due to insufficient or excessive voltage. As discussed herein, voltage margin can be a timing margin determined based on voltage, such as a setting and / or holding. Similar to reducing timing parameters, reducing voltage margin can be expected to reduce power requirements; however, a negative voltage margin can lead to improper circuit operation.

[0033] As discussed in this article, various margins (e.g., set margins and / or hold margins) can be determined in units of time, voltage, buffer count, or clock steps.

[0034] The performance monitoring mechanisms and techniques discussed in this paper work advantageously with standard electronic design automation (EDA) tools and implementation processes to enable scalability and thus reduce implementation costs.

[0035] Additionally, performance monitoring mechanisms and techniques can be used for area-only optimization, i.e., not for power optimization, while maintaining performance. For example, area-only optimization can be performed during the implementation phase by allowing sign-off timing with a slow angle at higher voltages, and the implementation of the performance monitoring mechanisms and techniques discussed in this paper can be used to determine the post-manufacturing voltage required for a single chip.

[0036] Compared to the performance monitoring mechanisms and techniques discussed in this paper, conventional performance monitoring systems focus solely on reducing setup margin, as setup margin limits the operating frequency and thus the voltage at a given frequency of the design. For example, some conventional systems can perform setup violation detection and error correction to handle errors using modifications to the design architecture to support voltage scaling. For instance, such systems could use special triggers that can detect timing violations, or additional detectors. In such systems, the architectural changes required to implement runtime error correction are problematic. For example, the required architectural changes increase the risk in silicon-verified designs. Additionally, a significant amount of extra logic may need to be added due to the need to cover a large number of critical paths for robustness. Furthermore, these systems face additional timing challenges when implementing error correction in high-speed designs due to feedback loops used for error correction. Additionally, these systems fail to provide solutions for retain margin removal, and retain margin increases as the supply voltage decreases.

[0037] Another common technique is to try using predictive margin to prevent setup violations. For example, such a system could use a copy of the critical path or add additional detector triggers and other types of detectors. Warnings on the detectors can be created by adding delays to the data or by adding delays to the clock. However, this technique is problematic because margin detectors require significant area, for example, by adding buffers and triggers or latches. Therefore, these systems are costly in terms of ASIC area and cost. Furthermore, these systems do not provide a solution for retaining margin removal, and retaining margin increases as the supply voltage decreases.

[0038] Another conventional system can use self-calibrating techniques that do not require changes to the functional design. These systems are similar to those described above, but they also implement self-calibration to avoid major architectural changes. Similar to the above, these techniques also use additional detector buffers and flip-flops, which have an additional cost in terms of area. Additionally, these techniques require additional logic for self-calibration. Furthermore, these systems fail to provide a solution for holding margin removal, and the holding margin increases as the supply voltage decreases.

[0039] Another conventional technique uses passive margin reduction with the use of process, voltage, and temperature sensors. For example, such a system can use on-chip sensors to predict changes, independent of the actual design logic. However, this system cannot effectively remove localized in-die variations and therefore has limited gain. Furthermore, it requires a large number of sensors to effectively reduce the margin, leading to increased ASIC area, power consumption, and cost. Additionally, these systems do not provide a solution for maintaining margin removal, and the maintained margin increases with decreasing supply voltage.

[0040] Alternatively, the implementation of the design can be optimized, for example, by using advanced implementation and testing techniques to minimize the required margin. This can be achieved, for example, by utilizing standard cells, planar layouts, clock tree optimization, and careful selection of operating voltage and sign-in angle. However, such techniques have limited power savings. For example, using aggressive voltage scaling results in reduced gain due to increased variation near the threshold voltage.

[0041] As described herein, adaptive checking and control logic and processes are used to monitor the performance of an integrated circuit by directly determining at least one of setup margin, hold margin, and voltage margin in one or more critical paths of the integrated circuit. Adaptive checking logic circuitry, including at least one multiplexer, is connected to the start and end points of the critical path. The adaptive checking logic circuitry is used to maintain the data state of the start and end points of the critical path before performing adaptive testing, and to reload the maintained data state to the start and end points of the critical path after adaptive testing. The adaptive checking logic circuitry connected to the start point of the critical path additionally provides an adaptive checking data pattern to the start point of the critical path during adaptive testing, while the adaptive checking logic circuitry connected to the end point of the critical path provides a timing violation signal indicating a setup violation or hold violation in response to the adaptive checking data pattern during adaptive testing. Additionally, an integrated clock gating unit connected to the critical path is used to selectively enable the functional clock signal to the critical path and disable the adaptive test clock signal to the critical path before and after adaptive testing, and to selectively disable the functional clock signal to the critical path and enable the adaptive test clock signal to the critical path during adaptive testing.

[0042] As discussed in this paper, the adaptive checking and control logic detects margin parameters in situ and checks the actual critical path. Additionally, the adaptive checking and control logic enables not only set violation detection but also hold violation detection and voltage margin determination. The adaptive checking and control logic can be used to aggressively reduce margins for both set and hold, for example, by the selected delay or voltage step size used during testing, while limiting any additional logic required for adaptive scaling. Since holding fixed at a lower voltage is not pessimistic, the technique discussed in this paper offers better area and power consumption due to the fact that it is not limited by the cost of holding fixed while aggressively reducing voltage. The adaptive checking and control logic also enables more critical path coverage in the design than conventional systems without significantly increasing the area required by the logic. Covering more critical paths in the design allows for more aggressive reduction of voltage margins, thus allowing for more efficient adaptive scaling, such as using AVS and / or DVFS. Furthermore, the proposed adaptive checking and control logic and technique are scalable without limitation for high-speed designs because the clock can be controlled independently during the data hold and reload phases.

[0043] Therefore, the adaptive checking and control logic and techniques discussed in this paper are beneficial because they allow for performance monitoring while reducing on-chip area and are a cost-effective way to support aggressive voltage scaling without significantly impacting area; thus, power and energy optimization. Furthermore, they reduce thermal issues of on-chip power management components and improve energy efficiency and battery life.

[0044] Figure 1 A simplified view of the pipeline architecture of digital circuitry 100 that may be included in an integrated circuit is shown. It should be understood that digital circuitry 100 is merely one example of digital circuitry, and integrated circuitry may include other digital circuitry and various combinations thereof.

[0045] As shown in the figure, digital circuit 100 includes various paths that start and end on flip-flops, with combinational positions set between the flip-flops. For example, the start of the digital circuit is shown with flip-flop FF1, which receives data D1 at data pin D, receives clock signal CLK at clock pin CP, and outputs data Q1 at output data pin Q. Additional flip-flops FF2 and FF3 are also shown as the front end of the digital circuit. The output data Q1, Q2, and Q3 from flip-flops FF1, FF2, and FF3, respectively, are provided as fan-in inputs to combinational logic 110, which may include some functional logic and provides data D4 to flip-flop FF4 and data Dx to flip-flop FFx. The output data Q4 and Qx from flip-flops FF4 and FFx, respectively, are provided to combinational logic 120, which may include some functional logic and provides data as data Dy to flip-flop FFy and data Dz to flip-flop FFz. The control settings of the digital circuit can be provided by configuration register 130.

[0046] Integrated circuits can include many different paths through which data signals can propagate. For example, digital circuit 100 illustrates multiple paths for data to travel from the front end of a circuit including flip-flops FF1, FF2, and FF3 to the rear end of a circuit including flip-flops FFy and FFz. Digital circuit 100 can include a critical path, which generally refers to the path through the digital circuit that takes the longest time to propagate for a signal due to the cumulative delays of logic gates, flip-flops, or other components, and defines the maximum clock frequency of the circuit. The critical path can include various delay components, including gate delay (e.g., the time required for a logic gate to perform its function), interconnect delay (e.g., the time required for a signal to travel through wiring between wires or components), and set-and-hold times (e.g., constraints imposed by memory elements, such as flip-flops, requiring the input to be stable for a certain duration before and after the clock edge). As described above, integrated circuits can include multiple digital circuits, each of which can have a different critical path. For example, critical path 140 in digital circuit 100 is shown as the path from flip-flop FF1 through combinational logic 110 to flip-flop FF4.

[0047] Figure 2 It shows Figure 1 The diagram illustrates an example pipelined architecture for the critical path 140 in the digital circuit 100 shown. The critical path 140 is the path from the input of flip-flop FF1 through combinational logic 110 to the output of flip-flop FF4, which is shown as including an XOR gate 212 and an AND gate 214. Flip-flops FF2 and FF3 provide fan-in inputs from non-critical paths to combinational logic 110.

[0048] Adaptive checking and control logic can be used to monitor the performance of the critical path 140, as discussed in this paper. The adaptive checking and control logic monitors the critical path itself and enables measurements of set margin, hold margin, and voltage margin without violating actual data in the design.

[0049] Figure 3 The pipeline architecture of digital circuit 300 is shown, which includes adaptive checking and control logic for performance monitoring of the critical path. As shown, the pipeline architecture of digital circuit 300 is similar to... Figure 1 The digital circuit 100 shown has similar designated components, wherein the critical path 140 runs from the input of flip-flop FF1 through combinational logic 110 to the output of flip-flop FF4. It should be understood that the critical path shown is only illustrated to show the components and functions of the adaptive checking and control logic used for performance monitoring of the critical path, and the actual critical path may have more complex combinational logic along the path.

[0050] The adaptive checking and control logic for critical path 140 includes adaptive checking logic circuitry 310, which includes at least one multiplexer electrically connected to the start point of critical path 140. The start point of the critical path is, for example, the beginning of the critical path where data is initiated at a specific edge or level of a control signal (such as a clock in a synchronization circuit) received at the clock pin CP of flip-flop FF1 (e.g., at data pin D of flip-flop FF1) before the adaptive test is performed. Prior to the adaptive test, at least one multiplexer in the adaptive checking logic circuitry 310 is used to maintain the data state at the start point of the critical path (e.g., at data pin D of flip-flop FF1). Additionally, during the adaptive test, at least one multiplexer in the adaptive checking logic circuitry 310 is used to provide an adaptive check data pattern to the start point of the critical path (e.g., at data pin D of flip-flop FF1). Furthermore, after the adaptive test, at least one multiplexer in the adaptive checking logic circuitry 310 is used to reload the maintained data state to the start point of the critical path (e.g., at data pin D of flip-flop FF1).

[0051] The adaptive check logic circuit 310 is shown as including adaptive check logic components 312 and 314, respectively connected to the data pin D and output data pin Q of the flip-flop FF1, and the adaptive check logic components 312 and 314 are connected via a loopback channel (shown in dashed lines) for maintaining and reloading the data state of the critical path's starting point before and after the adaptive test. In some implementations, the adaptive check logic circuit 310 may include fewer components, for example, only adaptive check logic component 312, which may use, for example, a multiplexer-based latch to maintain and reload the data state of the critical path's starting point before and after the adaptive test.

[0052] Additionally, the adaptive checking and control logic for critical path 140 includes a second adaptive checking logic circuit 320, which includes at least one multiplexer electrically connected to the end point of critical path 140. The end point of critical path is, for example, the end of the critical path where data is captured at a specific edge or level of a control signal (such as a clock in a synchronization circuit) received at the clock pin CP of flip-flop FF4 (e.g., the output data pin Q of flip-flop FF4) before the adaptive test is performed. Prior to the adaptive test, at least one multiplexer in the adaptive checking logic circuit 320 is used to maintain the data state at the end point of critical path (e.g., the output data pin Q of flip-flop FF4). Additionally, during the adaptive test, at least one multiplexer in the adaptive checking logic circuit 320 is used to provide a timing violation signal indicating a setup violation, hold violation, or voltage violation in response to the adaptive checking signal pattern. As used herein, a voltage violation is an indication that the voltage exceeds the safe operating voltage range and may cause data corruption. In addition, after the adaptive test, at least one multiplexer in the adaptive check logic circuit 320 is used to reload the held data state to the end of the critical path, for example at the output data pin Q of the flip-flop FF4.

[0053] The adaptive check logic circuit 320 is shown as including adaptive test (AT) logic components 322 and 324, respectively connected to the data pin D and output data pin Q of the flip-flop FF4, and connected via a loopback channel (shown in dashed lines) for maintaining and reloading the data state of the end point of the critical path before and after the adaptive test. In some implementations, the adaptive check logic circuit 320 may include fewer components, such as only adaptive check logic component 314, which may use, for example, multiplexer-based or latch-based circuitry to maintain and reload the data state of the start point of the critical path before and after the adaptive test.

[0054] The adaptive check logic circuit 320 can generate an adaptive check output signal, which is received by the scaling controller 330. For example, the scaling controller 330 may be an adaptive voltage scaling (AVS) circuit or a dynamic voltage frequency scaling (DVFS) circuit, or a similar scaling controller, which adjusts the adaptive voltage scaling and control voltage of the digital circuit 300 at a given operating frequency in response to the received adaptive check output signal.

[0055] The adaptive checking and control logic for critical path 140 may further include clock gating to selectively enable and disable clock signals at the start and end points of the critical path (e.g., flip-flops FF2 and FF3) independently of the remaining flip-flops (e.g., flip-flops FF1 and FF4). For example, the adaptive checking and control logic may include an integrated clock gating unit 340 electrically connected to the clock pin CP of critical path 140 (e.g., the clock pins CP of flip-flops FF1 and FF4). The integrated clock gating unit 340 receives a clock signal CLK on the clock pin CP, receives an adaptive checking clock enable signal avclken1 on the enable pin EN, and generates a clock signal CKL1 on the clock output pin CO. The integrated clock gating unit 340 selectively enables the functional clock signal CLK to critical path 140 before and after adaptive testing, and disables the functional clock signal CLK to critical path 140 during adaptive testing. Additionally, the integrated clock gating unit 340 selectively disables the adaptive check clock signal to the critical path 140 before and after adaptive testing, and enables the adaptive check clock signal to the critical path 140 during adaptive testing, for example, by controlling the clock signal CLK to generate the desired adaptive check clock signal when the adaptive check clock enable signal avclken1 is enabled.

[0056] The second integrated clock gating unit 350 can be electrically connected to a non-critical path in the digital circuit 300, such as the clock pin CP of non-critical path flip-flops FF2 and FF3. The second integrated clock gating unit 350 receives the clock signal CLK on the clock pin CP, receives the second adaptive check clock enable signal avclken2 on the enable pin EN, and generates the clock signal CKL2 on the clock output pin CO. The integrated clock gating unit 350 selectively enables the functional clock signal CLK to the non-critical path before and after the adaptive test, and disables the functional clock signal CLK during the adaptive test, for example, via CLK2 to flip-flops FF2 and FF3. Other non-critical paths may or may not receive CLK2, but may receive another clock signal that will be gated using an additional clock gating unit.

[0057] Additionally, if the combinational logic in the critical path includes fan-in inputs from non-critical paths, the adaptive checking and control logic for critical path 140 may include additional adaptive checking logic circuitry to provide state data to the combinational logic during adaptive testing to ensure that the adaptive checking data pattern provided to the start point of the critical path is correctly propagated to the end point of the critical path. For example, as shown, flip-flops FF2 and FF3 are electrically connected to adaptive checking logic circuits 362 and 364, respectively, each of which includes at least one multiplexer that selectively provides state data to combinational logic 110 during adaptive testing, but provides data from flip-flops FF2 and FF3 before and after the adaptive test.

[0058] In addition to the configuration register 130, which provides control settings for the digital circuit 300 and adaptive checking and control logic, the configuration register can also provide an indication, received by the controller 370, of which critical path or critical path group (ATE group) is being configured for adaptive testing. The controller 370 also receives an indication of when to perform adaptive testing (ATA), for example, when the system is idle or a request for adaptive testing. The ATA signal is, for example, a general enable signal received from software or hardware as a master control. The controller 370 can operate in conjunction with software and / or hardware. For example, firmware can be used to determine when to enable adaptive checking based on functionality, or hardware can be used to determine, for example, to perform self-checks and provide status in the system based on detected idle time or counter thresholds. The controller 370 can enable and disable adaptive testing and control the adaptive testing process, for example, by controlling the retention and reloading of data states at the start and end points of the critical path before and after adaptive testing, controlling the configuration of test data during adaptive testing, and controlling the adaptive clock signals for components of both critical and non-critical paths during adaptive testing.

[0059] Figure 4 An example pipeline architecture 400 for the critical path 140 is shown, which has the following characteristics: Figure 3 The adaptive checking and control logic shown uses similar specified components. Figure 2 As shown, critical path 140 is the path from the input of flip-flop FF1 through combinational logic 110 (shown as including XOR gate 212 and AND gate 214) to the output of flip-flop FF4.

[0060] like Figure 4As shown, the adaptive check logic circuit 310 may include a set of multiplexers electrically connected to the start point of the critical path 140 (e.g., the data pin D of the flip-flop FF1). This set of multiplexers is used to retain functional data before adaptive testing, insert adaptive check modes into the critical path during adaptive testing, and reload the retained functional data back into the critical path after adaptive testing.

[0061] For example, the adaptive check logic circuit 310 may include a first multiplexer 412 that receives adaptive test data (shown as Tf(T-final), Tf1(T-initial-1), and Tf2(T-initial-2)) selected by the ATD signal and generates an output Dav. For example, test data Tf1 and Tf2 are used to set the correct value of the adaptive test data Dav, which propagates to outputs Q1, D41, and Q14 on FF1, multiplexer 424, and FF4, respectively, during the initialization of the timing check. Test data Tf is used to trigger a timing path as a data start during the check to change the adaptive test data Dav, and thus change the adaptive test data Dav at output Q1 on the clock pulse on CLK1, thereby returning to change output Q14 on the next clock edge (if set). The second multiplexer 414 receives the output from the first multiplexer 412 at its first input pin 0, receives the hold data state for flip-flop FF1 at its second input pin 1, and receives the adaptive test reload (ATR) signal at its selector pin. The third multiplexer 416 receives data D1 at its first input pin 0, receives the output of multiplexer 414 (i.e., the hold data state for flip-flop FF1 or the adaptive test data Dav) at its second input pin 1, and receives the adaptive test enable signal ATE at its selector pin. The output of the third multiplexer 416 is received by the data pin D of flip-flop FF1. Additionally, the fourth multiplexer 418 operates as a latch, receiving a signal from the output data pin Q of flip-flop FF1 at its first input pin 0, and connecting its output to its second input pin 1, where the adaptive test enable signal ATE is on the selector pin. The output of the fourth multiplexer 418 provides the hold data state for flip-flop FF1 to the second input pin 1 of multiplexer 414 in the loopback path.

[0062] It should be understood that the adaptive checking logic circuit 310 can have other designs. For example, in some implementations, instead of using a multiplexer 418 to hold the state of the output Q1 from flip-flop FF1, other components such as latches can be used to hold the state of the output Q1 from flip-flop FF1 in a loopback path from the output data pin Q to the data pin D of flip-flop FF1. In some implementations, multiplexers 414 and 416 can be included in the latch-based loopback path.

[0063] Additionally, such as Figure 4 As shown, the adaptive check logic circuit 320 may include a set of multiplexers electrically connected to the end of the critical path 140 (e.g., the output data pin Q of flip-flop FF4) and configured to retain functional data in the critical path before adaptive testing, provide timing violation signals during adaptive testing, and reload the retained functional data back into the critical path after adaptive testing. For example, the adaptive check logic circuit 320 may include a first multiplexer 422 that can operate as a latch of the output of flip-flop FF4 by receiving an output signal Q4i from the output data pin Q of flip-flop FF4 at a first input pin 0 and connecting the output Q4 of multiplexer 422 to a second input pin 1 (where the adaptive test enable signal ATE is on the selector pin). A second multiplexer 424 receives an output signal from combinational logic 110 at the first pin 0. The second multiplexer 424 is connected to the first multiplexer 422 in the loopback path and receives the hold data state for flip-flop FF4 from the output of multiplexer 422 on a second input pin 1, and receives the adaptive test reload ATR signal on the selector pin. Additionally, the adaptive check logic circuit 320 may include logic circuitry (e.g., AND gate I1) to generate a timing violation signal Tv4 indicating a set violation or hold violation in critical path 140 in response to an adaptive check signal pattern during adaptive testing. For example, AND gate I1 may receive the output signal Q41 from flip-flop FF4 at the inverting input pin, and the adaptive test enable signal ATE on other input pins, and in response, generate the timing violation signal Tv4 on the output pin. For example, multiplexers 424 and 422 and AND gate I1 may be used as... Figure 3 The AT logic 322 and 324 are shown.

[0064] It should be understood that the adaptive checking logic circuit 320 can have other designs. For example, in some implementations, instead of using multiplexer 422 to hold the state of the output Q4i from flip-flop FF4, other components such as latches can be used to hold the state of the output Q4i of flip-flop FF4 in the loopback path from the output data pin Q of flip-flop FF4 to the data pin D of flip-flop FF4. In some implementations, multiplexer 424 can be included in the latch-based loopback path. In some implementations, a set of multiplexers similar to the sets of multiplexers 414 and 416 used at the data pin D of flip-flop FF1 can be included in the multiplexer- or latch-based loopback path to select the Ti# data that can be provided to the data pin D of flip-flop FF4.

[0065] Furthermore, the adaptive checking and control logic may include combinational logic 430, which receives timing violation signals from multiple critical paths in the integrated circuit and provides a common timing violation signal Tv, which indicates whether any set-up or hold-up violations exist in any critical path in the integrated circuit during adaptive testing. For example, as shown, combinational logic 430 may include an OR gate I2, which receives timing violation signals Tv4 from adaptive checking logic circuit 320 and other adaptive checking logic circuits from other critical paths as inputs, and outputs the common timing violation signal Tv at input pin D of flip-flop FF5. Flip-flop FF5 latches the common timing violation signal and generates the common timing violation signal on output pin Q in response to a timing event capture signal TCAP on a clock pin. For example, the common timing violation signal Tv may be provided to a scaling controller, such as... Figure 3 The scaling controller 330 shown.

[0066] As shown in the figure, the adaptive check logic circuits 362 and 364, connected to the non-critical path flip-flops FF2 and FF3 respectively, can be multiplexers. These multiplexers receive the flip-flop outputs on pin 0 of the first line, receive status data Tav_D2 and Tav_D3 on pin 1 of the second line, and receive the adaptive test enable signal ATE on the selector pin. In some implementations, the adaptive check logic circuits 362 and 364 can be AND and OR gates instead of multiplexers. The status data Tav_D# signal places the corresponding non-critical path flip-flop in the necessary state during adaptive testing and can be provided by configuration register 130. Additionally, as shown in the figure, configuration register 130 can provide Tf and Ti inputs and can provide an indication of which critical path or critical path group (ATE group) is being tested, which is received by controller 370. Controller 370 also receives an indication of when to perform adaptive testing (ATA), such as when the system is idle or a request for adaptive testing. The controller 370 can provide the adaptive test enable signal ATE, the adaptive test reload signal ATR, the adaptive test drive signal ATD, the test capture signal TCAP, and the adaptive check clock enable signals avclken1 and avclken2.

[0067] Figure 5 An example pipeline architecture 500 for a critical path 140 with adaptive checking and control logic is shown, such as Figure 4 As shown, similar designated elements are the same, but additionally include a data delay chain 510 and a clock delay chain 520, i.e., trigger FF4, preceding the end of the critical path (i.e., trigger FF4).

[0068] As shown in the figure, the data delay chain 510 is connected to the data pin D of the destination trigger FF4, for example, via a multiplexer 424, and is controlled by the adaptive test data configuration Tav_dcfg signal. The data delay chain 510 enables the selection of different delays at the data pin D of the destination trigger FF4 to perform setup margin detection controlled by the adaptive test data configuration Tav_dcfg signal.

[0069] Similarly, clock delay chain 520 is connected to the clock pin CP of the destination flip-flop FF4 and is controlled by the adaptive test clock configuration signal Tav_clkcfg. Clock delay chain 520 similarly enables the selection of different delays at the clock pin CP of the destination flip-flop FF4 to perform hold margin detection controlled by the adaptive test clock configuration signal Tav_clkcfg.

[0070] The implementation of clock delay chain 520 is shown in block 521. As shown, clock delay chain 520 may include a multiplexer 522 that can selectively enable the clock signal for the daisy-chain circuit. The daisy-chain circuit may include multiple buffers 524 and another multiplexer 526 configured to select a different number of buffers 524, for example, based on an adaptive test clock configuration signal. Data delay chain 510 may have a similar implementation to clock delay chain 520, but may use additional or fewer buffers and is controlled by the adaptive test data configuration Tav_dcfg signal.

[0071] Configuration register 130 can provide the adaptive test data configuration signal Tav_dcfg and the adaptive test clock configuration signal Tav_clkcfg to control the setting margin detection and holding margin detection tests.

[0072] like Figure 3-5 As shown, the adaptive checking and control logic used to monitor the performance of the critical path selectively maintains the state of the timing path (e.g., the critical path) under test at the beginning of the adaptive test, and reloads the maintained state back to the timing path under test after the adaptive test, while maintaining the state of the remaining logic during the adaptive test. The adaptive checking and control logic can be applied to determine the setup margin, hold margin, and voltage margin of the critical path in any given functional mode of the system-on-chip (SoC).

[0073] For example Figure 3-5 The adaptive checking and control logic shown can be used to set margin tests. For example, Figure 6 and Figure 7 The use of, as shown Figure 3-5 The waveforms shown are from the adaptive check and control logic setting margin check. Figure 6 and Figure 7 This illustrates a single iteration of adaptive testing. However, as indicated by the ellipsis, in practice, multiple iterations of adaptive testing can be performed using variations of one or more parameters as independent variables(s). For example, in some implementations, it is possible to use, for instance,... Figure 5 The data delay chain 510 preceding the flip-flop FF4 shown is used to vary the delay in the data path to reduce the delay and define a setup margin from functional to faulty based on the delay (e.g., the number of buffer elements). In some implementations, the delay in the data path may remain in its functional mode; for example, the daisy-chain circuitry may be bypassed by a multiplexer, or the data delay chain 510 may not exist in the critical path, such as... Figure 4As shown, the supply voltage can be varied in specific step sizes to decrease the supply voltage to define the setup margin from functional to fault based on the voltage (e.g., the number of voltage steps). Therefore, the setup margin can be determined based on buffer delay or voltage margin. In some implementations, the delay in the data path can be maintained in its functional mode, for example, and the voltage can be kept constant, and the frequency of the capture clock can be increased in specific step sizes to define the setup margin from functional to fault based on the clock frequency (e.g., the number of steps of the phase-locked loop (PLL) or clock controller). For example, determining the setup margin based on frequency can be particularly useful where overspeeding the clock would benefit the circuit's performance. In some implementations, one or more combinations of independent parameters can be used to determine the setup margin based on some combination of delay, voltage, and frequency.

[0074] Additionally, in some implementations, a set-margin check can be performed when the operating voltage approaches or falls below a threshold, regardless of whether the voltage step is positively increasing or decreasing the supply voltage. Therefore, the set-margin check can be cross-checked for pass / fail by monitoring without changing anything else. For example, monitoring can be performed at periodic intervals to verify pass conditions.

[0075] like Figure 6 and Figure 7 As shown, and with reference Figure 3-5 The circuit diagram shown enables adaptive testing during the initialization of the adaptive check by switching the adaptive test enable value high (ATE = 1), while the adaptive test reload ATR and adaptive test drive ATD values ​​remain low (0), which maintains the state of flip-flops FF1 and FF4 in the critical path. Other non-critical path signals affecting the critical path (e.g., signals from flip-flops FF2 and FF3) are configured with static values, such as Tav_D2 and Tav_D3 respectively, which enables testing of the critical path. The start and end points of the critical path (e.g., flip-flops FF1 and FF4) are initialized with data using the Ti# input at multiplexer 412, and as... Figure 6 and Figure 7 As shown, and by providing two clock pulses, which can be low-frequency, to ensure correct data capture on critical path triggers FF1 and FF2. Due to the adaptive check clock enable signal avclken1 at the integrated clock gating unit 340, the two clock pulses are only provided to components in the critical path, thereby initializing the data at Q1 and Q4. Non-critical path components (e.g., triggers FF3 and FF4) have their clock signals gated due to the adaptive check clock enable signal avclken2 at the integrated clock gating unit 350. The adaptive test drive ATD is incremented to initialize the path and select the start data for the desired timing arc.

[0076] Adaptive testing can then be performed by generating two clock cycles at a functional frequency (i.e., the normal frequency). The first clock cycle is used to transmit data at the start of the critical path (e.g., flip-flop FF1), and the second clock cycle is used to capture data at the end of the critical path (e.g., flip-flop FF4). The output generated at the end of the critical path (e.g., output Q4i generated by flip-flop FF4) can be coupled with logic circuitry (e.g., using...) Figure 4 and Figure 5 The expected output of the AND gate I1 shown is compared, and if a mismatch exists, a timing violation (e.g., signal Tv4) can be generated. Similarly, all critical paths are tested, and the output of each critical path is compared with the expected value to generate a timing violation signal for each critical path. These timing violation signals are provided to the logic circuit (e.g., OR gate I2) to generate a common timing violation signal Tv that can be captured using the timing event capture signal TCAP.

[0077] During adaptive testing, clock gating units 340 and 350, for example, are used to control the clock signals in the circuit based on enable signals avclken1 and avclken2. The clock signals in the circuit are then controlled so that clock signal CLK1 is used to time only the selected components of the critical path, while clock signal CLK2 is used to stop the clocking of the remaining components in the circuit clock to preserve data at those remaining components.

[0078] As by Figure 6 and Figure 7 As indicated by the ellipsis, adaptive testing can be repeated multiple times, where one or more parameters are gradually varied to determine the setup margin based on one or more independent variables. For example, the setup margin can be determined based on the delay element (e.g., buffer count) using the data delay chain 510 preceding the data pin D of flip-flop FF4, as... Figure 5As shown in the diagram. The adaptive test data configuration signal Tav_dcfg can be used to change the number of delay elements in the path, for example, changing the buffer count, for each iteration of the set-margin test. This process can be performed by decreasing the number of delay elements until a timing violation (function to failure) is detected, or by increasing the number of delay elements until no more timing violations (failure to function) are detected, at which point the minimum set-margin can be determined. In another implementation, the supply voltage can be varied to perform a voltage margin test for maximum speed (i.e., set-up), for example, by decreasing the supply voltage by a specific step size for each adaptive test iteration until a timing violation is detected, at which point the minimum supply voltage necessary for the set-margin can be determined. For example, if the voltage step size of the DC-DC converter is 10mV, and three steps from the operating voltage are required to cause a design failure, the set-margin can be defined as two steps from the voltage source (e.g., 20mV). In another implementation, the clock frequency can be varied until a timing violation is detected, at which point the maximum frequency for the set-margin can be determined.

[0079] Once the adaptive test is complete, the hold-over states from the start and end points of the critical path are reloaded. For example, adaptive test reloading is enabled by incrementing the adaptive test reload value (ATR = 1), and a single clock pulse is used to reload the data back onto the critical path triggers FF1 and FF4. After this, the adaptive test completes and is disabled; for example, the adaptive test enable ATE, the adaptive test drive ATD, and the adaptive test reload ATR value are pulsed down to "0"; then normal functional operation resumes.

[0080] It should be understood that, as described above, the adaptive checking and control logic can be modified or varied, which can correspondingly change the waveform. For example, in some implementations, the circuit can be designed to initialize the startup and capture of data at flip-flops FF1 and FF4 within a single clock cycle, i.e., requiring only a single-cycle initialization. For example, a set of multiplexers at the data pin D of flip-flop FF4 can be used to perform single-cycle initialization to select the Ti# data, and this set of multiplexers is similar to the set of multiplexers used at the data pin D of flip-flop FF1. Other optimizations and flexible variations can be performed similarly if desired.

[0081] Figure 6 The example illustrates the setup margin test waveform when no timing violation was detected, while Figure 7The setup margin test waveform is shown when a timing violation is detected. The critical path under the test is from Q1 to Q4, with a rising transition on Q4, i.e., from '0' to '1', which requires a transition from '0' to '1' for a given logic example Q1. During the initialization phase, two slow, low-frequency clock cycles ensure that Q1 and Q4 are '0' before the start of the adaptive test capture phase clock cycle; this is accomplished using the expected values ​​on Ti1 and Ti2 (as in this example, both Ti1 and Ti2 are '0', and the circuit implementation can be optimized to a single bit Ti and a single bit ATD). During the capture phase, based on the value on Tf, a first clock pulse (on clk1 during the adaptive test) initiates data ('1') on Q1, followed by a second clock pulse (on clk1 during the adaptive test) to capture data on Q4. Figure 6 As shown, D4 transitions high ('1') before the second clock pulse, and Q4 transitions high on the second clock pulse. However, as Figure 7 As shown, D4 transitions high ('1') after the second clock pulse, and therefore Q4 fails to transition high on the second clock pulse, resulting in a timing violation. After the second clock pulse, the timing event capture signal TCAP is used to latch the common timing violation signal Tv. As described above, and as indicated by the ellipsis, this can be repeated multiple times with different numbers of delay buffers, different voltages, or different clock frequencies to determine at which step the circuit transitions from functional to faulty, or vice versa. Once the adaptive test is complete, a reload cycle is performed, which puts Q1 and Q4 back to their functional state, allowing D4 to recover to its valid value when the test is complete (i.e., when ATE is pulsed down to '0').

[0082] For example Figure 3-5 The adaptive checking and control logic shown can be used for margin testing. For example, Figure 8 and 9 The waveforms for maintaining margin checks using adaptive checks and control logic diagrams are shown in the reference diagram. Figure 3-5 As shown in the image. Figure 8 and 9 This illustrates a single iteration of adaptive testing. However, as indicated by the ellipsis, in practice, multiple iterations of adaptive testing can be performed using variations in one or more parameters as independent variables(s). For example, in some implementations, it is possible to use, for instance,... Figure 5The clock delay chain 520 preceding the flip-flop FF4 shown varies the delay in the clock signal to increase the delay in the clock path, thereby defining a hold margin from functional to fault based on the delay (e.g., the number of buffer elements). In some implementations, the delay in the clock path can be maintained in its functional mode; for example, the daisy-chain circuit can be bypassed by a multiplexer, or the clock delay chain 520 may not exist in the critical path, such as... Figure 4 As shown, the supply voltage can be varied in specific step sizes to increase the supply voltage to define the hold-up margin from function to fault based on the voltage (e.g., the number of voltage steps). In some implementations, one or more combinations of independent variable parameters can be used to determine the hold-up margin based on some combination of delay and voltage.

[0083] Additionally, in some implementations, a hold-up margin check can be performed when the operating voltage approaches or falls below a threshold, regardless of whether the voltage step is positively increasing or decreasing the supply voltage. Therefore, the hold-up margin check can be cross-checked for pass / fail by monitoring without changing anything else. For example, monitoring can be performed at periodic intervals to verify pass conditions.

[0084] Depend on Figure 8 and Figure 9 The retention margin check shown in the waveform is similar to that by Figure 6 and Figure 7 The waveform shown illustrates the setup margin check. However, the hold margin check determines whether data initiated on the clock (adaptive test) arrives at its destination too quickly, for example, whether the data on Q4i is incorrectly changed (due to hold timing failure) on the clock cycle in which Q1 changes. Therefore, the hold margin check can use a single clock cycle for adaptive testing, instead of the two clock cycles used for the setup margin check. Additionally, to determine the hold margin based on the number of delay components, this process can be repeated multiple times, for example, in... Figure 5 Instead of using different delay configurations in the data path used for setting the hold margin check, a different delay configuration is utilized in clock delay chain 520 preceding the clock pin CP of the flip-flop FF4 shown. The adaptive test data configuration signal Tav_clkcfg can be used to change the number of delay elements in the clock path, for example, changing the buffer count, for each iteration of the hold margin test. This process can be repeated until a timing violation is detected; at this point, the minimum hold margin can be determined. In implementations where the supply voltage is varied to determine the hold margin based on voltage steps, clock delay chain 520 may be absent or unused.

[0085] Figure 8For example, a hold margin test waveform where no timing violation was detected might be generated if the number of delay elements selected by the adaptive test clock configuration Tav_clkcfg value is sufficient to meet the hold margin requirements. On the other hand, Figure 9 This describes the hold margin test waveform when a timing violation is detected. For example, the number of delay elements selected by the adaptive test clock configuration av_clkcfg is large enough to cause a hold violation, thus generating a timing violation (Tv).

[0086] Figure 10 This is a flowchart illustrating an example of using adaptive checking and control logic to control an adaptive test process 1000, including those discussed herein and... Figure 3-5 The controller 370 is shown in the figure.

[0087] As shown in the figure, after the System-on-Chip (SoC) is powered on (1002), the controller determines whether adaptive testing is enabled (1004), for example, by the scaling controller (such as...). Figure 3 Whether the scaling controller shown is operable in response to the voltage and / or frequency of the SoC's operation adaptively controlled by the adaptive test results. Once the adaptive test is enabled, the controller waits for an appropriate time to perform the adaptive test, such as after receiving a specific request for a check (1006), for example, the specific request may be issued based on the functionality of the circuit, or when a counter threshold for self-checking is reached, or when the system is detected to be idle (1008).

[0088] When the controller determines to perform adaptive testing, such as after receiving a check request (1006) or when the system is in idle mode (1008), it gates the design clock, for example, using enable signals avclken1 and avclken2 from clock gating units 340 and 350, and the adaptive test enable ATE signal increments (1010), for example, to hold data from the start and end points of the critical path. Then, for example, via the adaptive test drive ATD signal, the adaptive test configuration is provided to the circuit (1012), including the start and end points of the critical path and components of the non-critical path. For example, the adaptive test configuration can be used to select set margin detection, hold margin detection, or voltage margin for set or hold detection, as described above. Additionally, the adaptive test configuration can select one or a set of critical paths to be tested. The adaptive test can then be performed, including initialization of one or more critical paths and capture of test data from the end points of one or more critical paths (1014). Then, for example, the result of the adaptive test is captured based on the timing event capture signal TCAP (1016). The controller determines whether the test is complete (1018), for example, whether all expected iterations have been executed or a test failure result has been received. If not, it changes the adaptive test configuration (1020) and the process returns to execute the adaptive test, including initialization and capture (1014). For example, the type of adaptive test can be changed for the selected critical path or group of critical paths. Additionally, adaptive test configurations can be executed for multiple groups of critical paths. Each group can be selected by the adaptive test configuration, and once a group is completed, the adaptive test configuration (1020) is changed so that the next group of critical paths can be tested.

[0089] Once the test is complete (1018), the controller determines whether there are other critical paths to test (1022). For example, in some implementations, multiple critical paths can be tested individually, while in others, multiple critical paths can be tested simultaneously during the adaptive test process shown in boxes 1012-1016, where test results are logically combined to generate a common test result. However, the SoC may have one or more additional critical paths that can be tested individually. If additional critical paths are to be tested (1022), the process returns to perform an adaptive test configuration for those additional critical paths (1012).

[0090] If no other critical path needs to be tested (1022), the controller reloads the held data to the start and end points of the critical path, for example via the Adaptive Test Reload ATR signal, disables the Adaptive Test Enable ATE signal, and enables the design clock, for example via enable signals avclken1 and avclken2 from clock gating units 340 and 350 (1024). The controller can then determine whether the adaptive test is disabled (1026); if not, the process returns to blocks 1006 and 1008, and if so, the process ends (1028).

[0091] Figure 11 A block diagram of an example controller 1100, based on some implementations, that can be used with the adaptive checking and control logic discussed herein. In some implementations, controller 1100 may be... Figure 3-5 An example of a controller 370, and it can be used to control... Figure 10 The adaptive test process 1000 is shown in the figure. The controller 1100 includes a device interface 1110, a processing system 1120, and a memory 1130.

[0092] Device interface 1110 is configured to communicate with one or more components of the adaptive checking and control logic discussed herein. For example, device interface 1110 may be configured to receive various inputs, including indications of which critical path or critical path group (ATE group) is being tested, indications of when adaptive testing is enabled (e.g., enabled by a scaling controller), indications of when the system is idle, and requests for adaptive checking. Device interface 1110 may also be configured to provide various adaptive test enable / disable signals, such as the adaptive test enable signal ATE, the adaptive test reload signal ATR, the adaptive test drive signal ATD, the test capture signal TCAP, and the adaptive check clock enable signals avclken1 and avclken2.

[0093] Memory 1130 may include critical path storage 1131 configured to store critical paths or groups of critical paths. Memory 1130 may also include non-transitory computer-readable media (including one or more non-volatile memory elements, such as EPROM, EEPROM, flash memory, or hard disk drives, and other examples), which may store at least the following software (SW) modules: • Enable and disable SW module 1132 to control the enabling and disabling of adaptive testing for one or more critical paths, including maintaining and reloading state data at the start and end points of the critical path before and after adaptive testing, and providing adaptive test data configuration to the start and end points of the critical path and components of non-critical paths. • Adaptive Test SW Module 1134 is used to control adaptive testing, including controlling initialization and data capture during adaptive testing and changing configurations such as the number of delay elements, voltage levels, clock frequencies, etc. in different iterations of adaptive testing; • Results SW module 1136, used to control the reception and processing of timing violation results during adaptive testing, including providing instructions to the adaptive testing SW module 1134 to continue iteration or stop adaptive testing, and to the scaling controller (e.g., Figure 3 The scaling controller 330 in the middle provides an indication of the results to adjust the power supply voltage and / or clock frequency accordingly.

[0094] Each software module includes instructions that, when executed by the processing system 1120, cause the controller 1100 to perform a corresponding function.

[0095] Processing system 1120 can be configured to implement the functionality discussed herein using hardware, software, or a combination of hardware and software. For example, the functionality discussed herein can be hard-coded into logic within processing system 1120, or can be executed by any suitable processor or processor capable of executing scripts or instructions of one or more software programs (such as enabling and disabling SW module 1132, adaptive test SW module 1134, and results SW module 1136) stored in controller 1100 (such as in memory 1130), or by a combination of hard-coded logic and the execution of software instructions stored in memory. For example, processing system 1120 can be configured to control the enabling and disabling of adaptive tests on one or more critical paths, including maintaining and reloading state data at the start and end points of the critical paths before and after adaptive testing, and configuring adaptive test data to be provided to the start and end points of the critical paths as well as components of non-critical paths. The processing system 1120 can also be configured to control adaptive testing performed by adaptive checking and control logic, including controlling initialization and data acquisition during adaptive testing and varying configurations such as the number of delay elements, voltage levels, clock frequencies, etc., in different iterations of the adaptive test. The processing system 1120 can also be configured to control the reception and processing of timing violation results during adaptive testing, including providing indications of the results to continue iterations or stop the adaptive test, and instructing the scaling controller (e.g., ...) Figure 3 The scaling controller 330 in the middle provides an indication of the results to adjust the power supply voltage and / or clock frequency accordingly.

[0096] Figure 12 An illustrative flowchart depicting an example method 1200 for monitoring the performance of an integrated circuit, based on some implementations, is shown. In some implementations, example method 1200 may be... Figure 3-5 The adaptive checking and control logic shown herein, and Figure 6-9 The waveform shown is used for execution, and it can be controlled by a controller, as referenced. Figure 10 and Figure 11 The subject of discussion.

[0097] like Figure 12 As shown, a first data state at the start point of the critical path and a second data state at the end point of the critical path are maintained before adaptive testing (1210). For example, maintaining the first data state at the start point of the critical path can be performed by a first adaptive voltage check logic circuit, which includes a first state-holding electrical component, which includes one of a multiplexer or latch coupled to the start point of the critical path in the integrated circuit, such as connected to... Figure 3-5 The adaptive check logic circuit 310 of the flip-flop FF1 shown is responsive to the adaptive test enable signal ATE from the controller 370. For example, in response to the adaptive test enable signal ATE from the controller 370, a second adaptive check logic circuit can perform the holding of a second data state at the end of the critical path. This second adaptive check logic circuit includes a second state holding electrical component, which includes one of a multiplexer or latch coupled to the end of the critical path in the integrated circuit, such as one connected to... Figure 3-5 The adaptive checking logic circuit 320 for the flip-flop FF4 shown is illustrated.

[0098] The method includes disabling the functional clock signal to the critical path and enabling the adaptive test clock signal to the critical path (1220) during adaptive testing, for example, through an integrated clock gating unit coupled to the critical path, such as an integrated clock gating unit 340 connected to the clock pin CP of flip-flops FF1 and FF4, in response to an adaptive check clock enable signal avclken1 from the controller 370.

[0099] During adaptive testing, adaptive check data patterns are provided to the starting point (1230) of the critical path, for example, through a first adaptive voltage check logic circuit that includes at least one multiplexer coupled to the starting point of the critical path in the integrated circuit, such as connected to... Figure 3-5 The adaptive check logic circuit 310 of the flip-flop FF1 shown is responsive to the adaptive test drive signal ATD from the controller 370.

[0100] During adaptive testing, a timing violation signal (1240) indicating at least one of a setup violation, hold violation, or voltage violation is generated at the end of the critical path in response to the adaptive check data pattern. This is achieved, for example, by a second adaptive voltage check logic circuit including at least one second multiplexer coupled to the end of the critical path in the integrated circuit, such as one connected to... Figure 3-5 The adaptive check logic circuit 320 of the flip-flop FF4 shown is in response to the timing event capture signal TCAP from the controller 370.

[0101] The method includes restoring a first data state to the start of the critical path and a second data state to the end of the critical path (1250) after an adaptive test. For example, in response to an adaptive test reload signal ATR from controller 370, a first adaptive voltage check logic circuit (such as one connected to at least one multiplexer coupled to the start point) can be used. Figure 3-5 The adaptive check logic circuit 310 of the flip-flop FF1 shown can be used to restore the first data state to the start point of the critical path. For example, in response to the adaptive test reload signal ATR from the controller 370, a second adaptive check logic circuit (such as one connected to the end point) can be used to restore the first data state to the start point of the critical path. Figure 3-5 The adaptive check logic circuit 320 of the flip-flop FF4 shown in the figure is used to perform the restoration of the second data state to the end of the critical path.

[0102] The method further includes: after adaptive testing, disabling the adaptive test clock signal to the critical path and enabling the functional clock signal to the critical path (1260), for example, through an integrated clock gating unit coupled to the critical path, such as an integrated clock gating unit 340 connected to the clock pin CP of flip-flops FF1 and FF4, in response to an adaptive check clock enable signal avclken1 from the controller 370.

[0103] In some implementations, maintaining and restoring the first data state can be achieved using a first loopback path coupled to one of the first multiplexer or latch circuits (which is coupled to the start of the critical path), for example, as provided by... Figure 3-5 The adaptive check logic circuit 310 connected to flip-flop FF1 is shown, and maintaining and restoring the second data state uses a second loopback path coupled to one of the second multiplexer or latch circuits (which is coupled to the end of the critical path), for example, as shown by... Figure 3-5 The adaptive check logic circuit 320 connected to the flip-flop FF4 is shown in the figure.

[0104] In some implementations, during adaptive testing, the method may further include, for example, using a third adaptive check logic circuit that provides state data from a non-critical path coupled to the critical path via combinational logic. This third adaptive check logic circuit includes at least one third multiplexer or logic AND and OR gates coupled to the non-critical path, such as adaptive check logic circuit 362 connected to flip-flop FF2 in response to an adaptive test enable signal ATE from controller 370.

[0105] In some implementations, adaptive check data modes can be provided to the data pins at the end of the critical path during adaptive testing via a delay chain circuit for setting margin detection, for example, as shown by a data delay chain 510 connected to flip-flop FF4. For example, various buffers in the delay chain circuit can be selectively connected to the data pins at the end of the critical path during adaptive testing for at least one of the following detections: setting margin detection based on buffer counts, voltage margin detection towards the lower side based on buffer counts, or clock speed margin detection based on buffer counts, for example, as shown by... Figure 5 The multiple buffers 524 shown are illustrated and referenced Figure 6 and Figure 7 The waveforms shown are the subject of discussion.

[0106] In some implementations, the adaptive test clock signal may be provided via a delay chain circuit to a clock pin at the end of the critical path during adaptive testing for hold margin detection, as illustrated by, for example, the clock delay chain 520 connected to flip-flop FF4. For example, multiple different buffers in the delay chain circuit may be selectively connected to a clock pin at the end of the critical path during adaptive testing for at least one of the following detections: hold margin detection based on buffer count or voltage margin detection towards the higher side based on buffer count, as illustrated by, for example, the clock delay chain 520 connected to flip-flop FF4. Figure 5 The multiple buffers 524 shown are illustrated and referenced Figure 8 and 9 The waveforms shown are discussed.

[0107] In some implementations, the method includes providing an indication of a timing violation signal to an adaptive voltage scaling circuit, for example, as provided by... Figure 3 The scaling controller 330 is described in the text.

[0108] In some implementations, the method includes performing at least one of a set margin detection and a hold margin detection based on a voltage step count, for example, as referenced. Figure 6-9 The waveforms shown are discussed.

[0109] In some implementations, the method includes performing a set margin detection based on a clock signal step count, for example, as referenced. Figure 6 and Figure 7 The waveforms shown are discussed.

[0110] In some implementations, the method may also include disabling the functional clock signal to the non-critical path during adaptive testing and enabling the functional clock signal to the non-critical path before and after adaptive testing, for example, as illustrated by the integrated clock gating unit 350, which is connected to the clock pin CP of flip-flops FF2 and FF3 in response to the adaptive check clock enable signal avclken2 from the controller 370.

[0111] In some implementations, combinational logic is used to combine timing violation signals associated with the critical path with one or more additional timing violation signals associated with one or more other critical paths in the integrated circuit to generate a common timing violation signal, for example, as provided by... Figure 4 and Figure 5 The combinational logic 430 shown in the figure illustrates this.

[0112] In some implementations, timing violation signals are used to monitor at least one of the voltage or frequency scaling of the integrated circuit. Monitoring can be initiated in response to an indication that the integrated circuit is in an idle state or within a regular time interval, for example, as referenced. Figure 10 and Figure 11 As discussed above, for example, monitoring can be initiated by a controller using hardware or software.

[0113] Those skilled in the art will recognize that information and signals can be represented using any of a wide variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the description above can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0114] Furthermore, those skilled in the art will recognize that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above according to their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0115] The methods, sequences, or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor.

[0116] In the foregoing description, embodiments have been described with reference to specific examples thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader scope of this disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be viewed in an illustrative rather than a limiting sense.

Claims

1. An apparatus for monitoring the performance of an integrated circuit, the apparatus comprising: A first adaptive check logic circuit includes a first state holding electrical component, the first state holding electrical component including one of a multiplexer or latch coupled to the start point of a critical path in the integrated circuit, including the first adaptive check logic circuit of the first state holding electrical component holding a first data state of the start point of the critical path before adaptive testing, providing an adaptive check data mode to the start point of the critical path during the adaptive test, and reloading the first data state to the start point of the critical path after the adaptive test; A second adaptive check logic circuit includes a second state holding electrical component, the second state holding electrical component including one of a multiplexer or latch coupled to the end point of the critical path in the integrated circuit, wherein the second adaptive check logic circuit of the second state holding electrical component holds a second data state of the end point of the critical path from before the adaptive test, provides a timing violation signal indicating at least one of a setting violation, a holding violation, or a voltage violation in response to the adaptive check data mode during the adaptive test, and reloads the second data state to the end point of the critical path after the adaptive test; as well as An integrated clock gating unit coupled to the critical path selectively enables the functional clock signal to the critical path and disables the adaptive test clock signal to the critical path before and after the adaptive test, and selectively disables the functional clock signal to the critical path and enables the adaptive test clock signal to the critical path during the adaptive test.

2. The apparatus of claim 1, wherein the first state holding electrical component further includes a first loopback channel coupled to the multiplexer or latch, the first loopback channel holding the first data state at the start point of the critical path prior to the adaptive test and reloading the first data state to the start point of the critical path after the adaptive test, and wherein the second state holding electrical component further includes a second loopback channel coupled to the multiplexer or latch, the second loopback channel holding the second data state at the end point of the critical path prior to the adaptive test and reloading the second data state to the end point of the critical path after the adaptive test.

3. The apparatus of claim 1 further includes a third adaptive checking logic circuit, the third adaptive checking logic circuit including a third at least one multiplexer coupled to a non-critical path, the non-critical path being coupled to the critical path via combinational logic, wherein the third adaptive checking logic circuit including the third at least one multiplexer provides state data to the combinational logic during the adaptive test.

4. The apparatus of claim 1, further comprising a delay chain circuit including at least one multiplexer coupled to a data pin at the end of the critical path, wherein the delay chain circuit including the at least one multiplexer is selectively enabled during the adaptive test for setting margin detection, wherein the delay chain circuit further includes a plurality of buffers selectively coupled to the data pin at the end of the critical path during the adaptive test for at least one of: setting margin detection based on buffer count, voltage margin detection based on buffer count, or clock speed margin detection based on buffer count.

5. The apparatus of claim 1, further comprising a delay chain circuit including at least one multiplexer coupled to a clock pin at the end of the critical path, wherein the delay chain circuit including the at least one multiplexer is selectively enabled during the adaptive test for hold margin detection, wherein the delay chain circuit further includes a plurality of buffers selectively coupled to the clock pin at the end of the critical path during the adaptive test for at least one of: hold margin detection based on buffer count or voltage margin detection based on buffer count.

6. The apparatus of claim 1 further includes an adaptive voltage scaling circuit coupled to the second adaptive checking logic circuit.

7. The apparatus of claim 1, wherein the timing violation signal is used for at least one of setting margin detection and holding margin detection based on voltage step count.

8. The apparatus of claim 1, wherein the timing violation signal is used for setting margin detection based on clock signal step count.

9. The apparatus of claim 1, further comprising a second integrated clock gating unit coupled to a non-critical path, the non-critical path being coupled to the critical path via combinational logic, the second integrated clock gating unit selectively enabling the functional clock signal to the non-critical path before and after the adaptive test, and selectively disabling the functional clock signal to the non-critical path during the adaptive test.

10. The apparatus of claim 1, further comprising combinational logic coupled to receive the timing violation signal associated with the critical path and one or more additional timing violation signals associated with one or more other critical paths in the integrated circuit, and to provide an indication of the setup violation or the hold violation in any critical path in the critical path of the integrated circuit during the adaptive test.

11. A method for monitoring the performance of an integrated circuit, the method comprising: Maintain the first data state of the starting point of the critical path and the second data state of the ending point of the critical path before adaptive testing; During the adaptive test, the functional clock signal to the critical path is disabled and the adaptive test clock signal to the critical path is enabled. An adaptive inspection data pattern is provided to the starting point of the critical path during the adaptive test; During the adaptive test, in response to the adaptive check data pattern, a timing violation signal is generated indicating at least one of a setup violation, a hold violation, or a voltage violation at the end point of the critical path; After the adaptive test, the first data state is restored to the starting point of the critical path and the second data state is restored to the ending point of the critical path; as well as After the adaptive test, the adaptive test clock signal to the critical path is disabled and the functional clock signal to the critical path is enabled.

12. The method of claim 11, wherein maintaining the first data state and restoring the first data state uses a first loopback path coupled to one of a first multiplexer or latch circuit, the first multiplexer or latch circuit being coupled to the start point of the critical path, and wherein maintaining the second data state and restoring the second data state uses a second loopback path coupled to one of a second multiplexer or latch circuit, the second multiplexer or latch circuit being coupled to the end point of the critical path.

13. The method of claim 11, wherein during the adaptive test, the method further comprises: Provide status data from non-critical paths, which are coupled to the critical paths through combinational logic.

14. The method of claim 11, further comprising: During the adaptive test, the adaptive check data pattern is provided to the data pin at the end point of the critical path via a delay chain circuit to set the margin detection. as well as During the adaptive test, various buffers in the delay chain circuit are selectively coupled to the data pin at the end of the critical path for at least one of the following detections: setup margin detection based on buffer count, voltage margin detection based on buffer count, or clock speed margin detection based on buffer count.

15. The method of claim 11, further comprising: During the adaptive test, the adaptive test clock signal is provided to the clock pin at the end point of the critical path via a delay chain circuit to maintain margin detection; as well as During the adaptive test, various buffers in the delay chain circuit are selectively coupled to the clock pin at the end of the critical path for at least one of the following detections: hold margin detection based on buffer count or voltage margin detection based on buffer count.

16. The method of claim 11, further comprising providing an indication of the timing violation signal to an adaptive voltage scaling circuit.

17. The method of claim 11, further comprising performing at least one of a set margin detection and a hold margin detection based on the timing violation signal according to a voltage step count.

18. The method of claim 11, further comprising performing a setting margin detection based on clock signal step counts based on the timing violation signal.

19. The method of claim 11, further comprising: The function clock signal to the non-critical path is disabled during the adaptive test; as well as The functional clock signal to the non-critical path is enabled before and after the adaptive test.

20. A controller configured for monitoring the performance of an integrated circuit, the controller comprising: Processing system; as well as Adaptive checking and control logic, comprising a first adaptive checking logic circuit and a second adaptive checking logic circuit coupled to the processing system, wherein the processing system is configured to: Before adaptive testing, an adaptive test enable signal is sent to the first adaptive check logic circuit to maintain a first data state at the start point of the critical path, the first adaptive check logic circuit including at least one of a multiplexer or latch coupled to the start point of the critical path in the integrated circuit, and an adaptive test enable signal is sent to the second adaptive check logic circuit to maintain a second data state at the end point of the critical path, the second adaptive check logic circuit including at least one of a multiplexer or latch coupled to the end point of the critical path in the integrated circuit; During the adaptive test, an adaptive check clock signal is sent to disable the functional clock signal to the critical path and enable the adaptive test clock signal to the critical path. During the adaptive test, an adaptive check data signal is sent to provide an adaptive check mode to the starting point of the critical path; During the adaptive test, in response to the adaptive check mode, a timing event capture signal is sent to capture a timing violation signal indicating at least one of a setup violation, a hold violation, or a voltage violation at the end point of the critical path; After the adaptive test, an adaptive check reload signal is sent to the first adaptive check logic circuit to reload the first data state to the start point of the critical path, and after the adaptive test, an adaptive check reload signal is sent to the second adaptive check logic circuit to reload the second data state to the end point of the critical path. as well as After the adaptive test, the adaptive check clock signal is sent to enable the functional clock signal to the critical path.

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