An integrated circuit aging test apparatus and a test method thereof

Abstract

The application relates to the technical field of integrated circuit aging test, in particular to an integrated circuit aging test equipment and a test method thereof, which solves the problems of insufficient test power of general test equipment, deviation of test results caused by external electromagnetic interference, and large crosstalk between test channels. The test method of the integrated circuit aging comprises the following steps: S1, installing a measured integrated circuit on a test station and eliminating the interference of electromagnetic signals on the test; S2, sending test parameters to a test module through a master control module; S3, generating an optimal parallel test scheduling scheme according to the test parameters and the system state; and S4, applying synchronous electric stress, thermal stress and mechanical stress to the measured integrated circuit according to the test scheduling scheme. The application offsets the electromagnetic interference generated by the three-dimensional stacked power drive array of the external environment and the equipment interior, thereby reducing the electromagnetic interference of the test area and eliminating the influence of the electromagnetic signals on the test accuracy.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit aging test technology, specifically to an integrated circuit aging test device and its test method. Background Technology

[0002] An integrated circuit is a miniature electronic device or component. Using certain processes, transistors, resistors, capacitors, inductors, and other components required for a circuit, along with interconnected wiring, are fabricated on one or several small pieces of semiconductor wafers or dielectric substrates. These are then packaged in a housing to form a miniature structure with the required circuit function. All components are structurally integrated into a whole, enabling electronic components to be miniaturized, low-power, intelligent, and highly reliable.

[0003] Integrated circuit aging test is an accelerated life reliability test after integrated circuit packaging. It simulates extreme operating conditions to induce potential defects, screen products that fail early, and verify long-term reliability. It is a key link in ensuring quality in semiconductor mass production.

[0004] Conventional testing equipment has insufficient testing power, and external electromagnetic interference can lead to deviations in test results. In addition, there is significant crosstalk between test channels. Therefore, it does not meet the existing requirements. To address this, we propose a new integrated circuit aging test equipment and its testing method. Summary of the Invention

[0005] The purpose of this invention is to provide an integrated circuit aging test device and a test method thereof to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a testing method for integrated circuits, the testing method comprising the following steps:

[0007] S1: Install the integrated circuit under test on the test station and eliminate electromagnetic interference to the test;

[0008] S2: Send test parameters to the test module through the main control module;

[0009] S3: Generate the optimal parallel test scheduling scheme based on test parameters and system status;

[0010] S4: Apply synchronous electrical, thermal, and mechanical stresses to the integrated circuit under test according to the test scheduling scheme;

[0011] S5: During the test, the electrical parameters of the integrated circuit under test are collected at a specific sampling frequency, and the collected data is preprocessed.

[0012] S6: Perform real-time error correction on the preprocessed test data and monitor the aging status of the integrated circuit under test in real time through the early warning unit;

[0013] S7: Establish a mathematical model of aging characteristic parameters and failure time based on the corrected test data, and generate a test report.

[0014] Preferably, in S1, the interference of electromagnetic signals on the test is eliminated using an active global electromagnetic interference cancellation method. The real-time electromagnetic interference cancellation algorithm includes:

[0015] Establish an electromagnetic interference signal model:

[0016]

[0017] in, for Electromagnetic interference signals at any time For the first The amplitude of each interference component, For the first The frequency of each interference component For the first The phase of each interference component, It is Gaussian white noise. The number of interference components;

[0018] The parameters of the interference signal are estimated using an adaptive spectral estimation algorithm:

[0019]

[0020] in, For the first The estimated value of the disturbance parameter in the next iteration For parameter-based The estimated value of the interference signal, To estimate the window size, we use values ​​between 256 and 1024;

[0021] Generate cancellation signal:

[0022]

[0023] in, for The cancellation signal at that moment;

[0024] Closed-loop feedback adjustment:

[0025] The convergence condition is met when the root mean square value of the residual electromagnetic interference is less than 0.5 μV and remains stable for 100 consecutive sampling periods.

[0026] Preferably, the parallel test scheduling scheme in S3 is generated by a parallel test intelligent scheduling algorithm, which includes:

[0027] Define the objective function:

[0028]

[0029] in, The objective function value, This represents the total number of test channels. For the first The time it takes for each channel to complete all test tasks.

[0030] Preferably, in step S5, when acquiring electrical parameters, an inter-channel crosstalk cancellation algorithm is used to eliminate the influence of inter-channel crosstalk on the sampled data. The inter-channel crosstalk cancellation algorithm includes:

[0031] Establish an inter-channel crosstalk model:

[0032]

[0033] in, For the first The sampling signals of each channel, For the first The original signal of each channel, For the first The first channel to the first Crosstalk impulse response of each channel This represents the convolution operation. Additive noise, Total number of channels;

[0034] The crosstalk impulse response is estimated using the normalized least mean square algorithm:

[0035]

[0036] in, For the first Estimate of crosstalk impulse response in the next iteration Step size factor For the first The input signal vector of each channel, This is an error signal;

[0037] Step size factor dynamically adjusted:

[0038] The initial step size is 0.01. When the root mean square value of the error signal is greater than 1mV, the step size is increased to 0.1; when the root mean square value of the error signal is less than 10μV, the step size is decreased to 0.001.

[0039] Cancel crosstalk:

[0040]

[0041] in, The first after crosstalk cancellation One channel signal.

[0042] Preferably, in step S4, the synchronous application of electrical, thermal, and mechanical stresses to the integrated circuit under test is performed using a multiphysics coupling stress application algorithm. The mathematical expression of the multiphysics coupling stress application algorithm is as follows:

[0043]

[0044] in, for The total coupled stress vector at time t, The electric stress vector. For thermal stress vector, For mechanical stress vector, These are the coupling coefficients for electrical stress, thermal stress, and mechanical stress, respectively, and they satisfy... .

[0045] Preferably, the preprocessing in S5 is performed using a synchronous differential sampling data processing algorithm, which includes:

[0046] Perform a difference operation on the raw data of each sampling channel:

[0047]

[0048] in, For the first The differential voltage at each sampling point The sampling voltage is the positive input terminal. The negative input terminal samples the voltage.

[0049] Perform moving average filtering on the differential voltage:

[0050]

[0051] in, This is the filtered voltage. This is the size of the sliding window; when the sampling frequency is 1 MSPS, Take 16; when the sampling frequency is 2MSPS, Take 32.

[0052] Preferably, the real-time error correction in S6 is performed using an adaptive error correction algorithm, which includes:

[0053] Establish a systematic error model:

[0054]

[0055] in, For the first Systematic error of the measurement Zero-point error, This is the temperature error coefficient. For current error coefficient, This is the temperature-current crossover error coefficient. The current temperature. This is the current.

[0056] The error coefficients are updated in real time using the Kalman filter algorithm.

[0057]

[0058] in, For the first The estimated error coefficients of the next iteration For Kalman gain, These are actual measured values. For observation vectors;

[0059] Kalman gain calculation formula:

[0060]

[0061] in, For the first The error covariance matrix of the next iteration. To measure the noise covariance matrix.

[0062] Preferably, the aging warning method for the early warning unit in S6 to monitor the aging status of the integrated circuit under test includes:

[0063] A continuous sequence of aging characteristic parameters was collected, including threshold voltage drift, leakage current change, and on-resistance change.

[0064] Input the aging characteristic parameter sequence into a long short-term memory neural network model to output the failure probability;

[0065] When the failure probability exceeds 0.9, an early warning signal is issued and the test of that channel is automatically stopped;

[0066] The warning threshold was determined using the ROC curve, at which point the warning accuracy rate was 95% and the false alarm rate was 3%.

[0067] For different types of integrated circuits, the output layer of the model is fine-tuned using aging test data from approximately 100 target type integrated circuits.

[0068] An integrated circuit aging test apparatus for performing an integrated circuit aging test method, comprising:

[0069] The main control module is used to control the operation of the entire device and to receive and process test data;

[0070] A three-dimensional stacked adaptive multiphysics coupling test module, at least one of which is connected to the main control module, integrates an inter-channel crosstalk adaptive cancellation unit, a parallel test intelligent scheduling unit, and an aging parameter real-time early warning unit, which is used to apply multiphysics coupling stress to the integrated circuit under test and collect test data.

[0071] The active global electromagnetic interference cancellation module communicates with the main control module and includes a distributed electromagnetic sensor array, an interference signal processing unit, an adaptive cancellation signal generation unit, a multi-point cancellation signal radiation array, and a closed-loop feedback unit. It is used to detect and cancel the interference of electromagnetic signals from the external environment and the equipment inside the test in real time.

[0072] The environmental control module communicates with the main control module and is used to control the environmental parameters inside the test chamber;

[0073] The data storage module communicates with the main control module and is used to store test data and test results;

[0074] The power module is used to provide power to the entire test equipment.

[0075] Preferably, the three-dimensional stacked adaptive multiphysics coupling test module includes:

[0076] The module substrate is made of high thermal conductivity silicon carbide ceramic material and has multiple testing stations.

[0077] The three-dimensional stacked power drive array is vertically stacked on the module substrate and adopts a combination of liquid cooling and heat dissipation through thermal holes. Each power drive unit corresponds to a test station.

[0078] A synchronous differential sampling array, corresponding one-to-one with a three-dimensional stacked power drive array, is used to acquire the electrical parameters of the integrated circuit under test.

[0079] A local thermal control unit is integrated below each test station to precisely control the temperature of the integrated circuit under test;

[0080] A mechanical stress application unit is installed above each test station to apply controllable mechanical stress to the integrated circuit under test.

[0081] The inter-channel crosstalk adaptive cancellation unit is communicatively connected to the synchronous differential sampling array and uses the normalized minimum mean square algorithm to cancel the mutual crosstalk between test channels;

[0082] The parallel test intelligent scheduling unit communicates with the module controller and uses a dynamic task scheduling strategy based on genetic algorithms to optimize task scheduling for multiple test channels.

[0083] The aging parameter real-time early warning unit is connected to the synchronous differential sampling array and uses a long short-term memory neural network model to monitor the aging status of the integrated circuit under test in real time and provide early warning.

[0084] The unit controller is connected to each of the above units for communication.

[0085] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0086] 1. This invention employs an active global electromagnetic interference cancellation module, which combines distributed electromagnetic sensing and adaptive active cancellation technology to simultaneously cancel electromagnetic interference generated by the external environment and the three-dimensional stacked power drive array inside the equipment, thereby reducing electromagnetic interference in the test area and eliminating the influence of electromagnetic signals on test accuracy.

[0087] 2. This invention improves voltage and current testing accuracy by adding an inter-channel crosstalk adaptive cancellation unit, combined with the original synchronous differential sampling technology and adaptive error correction algorithm, and can accurately capture nanometer-level parameter changes during the aging process of integrated circuits.

[0088] 3. This invention employs a dynamic task scheduling strategy based on genetic algorithms through a parallel test intelligent scheduling unit, which can automatically optimize test resource allocation and improve test efficiency. Furthermore, the aging parameter real-time early warning unit can issue early warnings before failure occurs, reducing invalid test time.

[0089] 4. This invention improves the single-channel power output intensity by adopting a three-dimensional stacked power drive array, and at the same time improves the junction temperature control of the power drive array by combining liquid cooling and heat dissipation through hot holes, thereby ensuring the long-term stable operation of the three-dimensional stacked structure.

[0090] 5. This invention integrates electrical stress, thermal stress, and mechanical stress into one unit to simulate the multi-physical field coupling effect that integrated circuits are subjected to during actual use, making the aging test results closer to the actual situation.

[0091] 6. This invention improves the prediction accuracy of the remaining service life of integrated circuits by establishing a mathematical model that integrates aging characteristic parameters and failure time with multiple parameters. At the same time, it adopts the transfer learning method to adapt the aging early warning model to different types of integrated circuits, thereby improving the early warning accuracy. Attached Figure Description

[0092] Figure 1 Complete block diagram for running test logic

[0093] Figure 2 This is a block diagram of the overall architecture of the integrated circuit aging test equipment.

[0094] Figure 3 This is a block diagram of the internal structure of an active global electromagnetic interference cancellation module.

[0095] Figure 4 This is a diagram of the internal structure of a three-dimensional stacked adaptive multiphysics coupling test module.

[0096] Figure 5 Block diagram of the adaptive crosstalk cancellation unit structure;

[0097] Figure 6 Block diagram of the intelligent scheduling unit for parallel testing;

[0098] Figure 7 Block diagram of the unit for real-time early warning of aging parameters. Detailed Implementation

[0099] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0100] An integrated circuit aging test apparatus for performing integrated circuit aging tests, comprising:

[0101] The main control module is used to control the operation of the entire device and to receive and process test data.

[0102] A three-dimensional stacked adaptive multiphysics coupling test module, of which there is at least one, is connected to the main control module. It integrates an inter-channel crosstalk adaptive cancellation unit, a parallel test intelligent scheduling unit, and an aging parameter real-time early warning unit. It is used to apply multiphysics coupling stress to the integrated circuit under test and collect test data.

[0103] The three-dimensional stacked adaptive multiphysics coupling test module includes:

[0104] Module baseboard:

[0105] It is made of high thermal conductivity silicon carbide ceramic material and has multiple testing stations.

[0106] Three-dimensional stacked power drive array:

[0107] Vertically stacked on the module substrate, using a combination of liquid cooling and heat dissipation through thermal holes, each power drive unit corresponds to a test station;

[0108] The three-dimensional stacked power drive array uses through-silicon via interconnect technology to achieve vertical stacking. Each layer contains 16 power drive units, with a stacking of 4 layers and a total of 64 test channels per module. Each layer of power drive units is equipped with a liquid cooling heat sink, and the coolant is deionized water with a flow rate of 5L / min.

[0109] Synchronous differential sampling array:

[0110] It corresponds one-to-one with the three-dimensional stacked power drive array and is used to acquire the electrical parameters of the integrated circuit under test;

[0111] The synchronous differential sampling array uses an 18-bit high-precision ADC with a sampling rate of up to 2MSPS. All channels are synchronized through the same clock source, and the synchronous sampling error is less than 5ns.

[0112] Local thermal control unit:

[0113] Integrated beneath each test station, it is used for precise temperature control of the integrated circuit under test.

[0114] Mechanical stress application unit:

[0115] It is positioned above each test station to apply controllable mechanical stress to the integrated circuit under test.

[0116] Inter-channel crosstalk adaptive cancellation unit:

[0117] It communicates with the synchronous differential sampling array and uses the normalized least mean square algorithm to cancel the crosstalk between test channels;

[0118] The crosstalk suppression ratio of the inter-channel crosstalk adaptive cancellation unit can reach over 80dB. The order of the crosstalk impulse response is determined according to the channel spacing: 16th order for adjacent channels, 8th order for every other channel, and 4th order for every two or more channels.

[0119] Parallel Test Intelligent Scheduling Unit:

[0120] It communicates with the module controller and uses a dynamic task scheduling strategy based on genetic algorithms to optimize task scheduling for multiple test channels.

[0121] Real-time aging parameter early warning unit:

[0122] It communicates with the synchronous differential sampling array and uses a long short-term memory neural network model to monitor the aging status of the integrated circuit under test in real time and provide early warnings.

[0123] The long short-term memory neural network model structure used in the real-time early warning unit for aging parameters is as follows:

[0124] The input layer has one neuron, the hidden layers have two layers with 64 neurons each, the activation function is ReLU, and the output layer has one neuron. For different types of integrated circuits, transfer learning is used to fine-tune the model.

[0125] Unit controller:

[0126] It communicates with each of the above units respectively.

[0127] The active global electromagnetic interference cancellation module communicates with the main control module and includes a distributed electromagnetic sensor array, an interference signal processing unit, an adaptive cancellation signal generation unit, a multi-point cancellation signal radiation array, and a closed-loop feedback unit. It is used to detect and cancel the interference of electromagnetic signals from the external environment and the equipment inside the test in real time.

[0128] The distributed electromagnetic sensing array includes 24 external three-dimensional electromagnetic sensors arranged on the outer surface of the test chamber and 8 internal three-dimensional electromagnetic sensors arranged inside the test chamber. The detection frequency range is 10Hz to 10GHz, and the detection sensitivity is 1nV / m and 1pT.

[0129] The multi-point cancellation signal radiation array consists of 16 radiation elements, which are evenly arranged on the inner wall of the test cavity. Each radiation element adopts a three-dimensional orthogonal antenna structure and can independently control the radiation amplitude and phase in the X, Y and Z directions.

[0130] The environmental control module communicates with the main control module and is used to control the environmental parameters inside the test chamber.

[0131] The data storage module communicates with the main control module and is used to store test data and test results.

[0132] The power module is used to provide power to the entire test equipment.

[0133] A method for testing integrated circuits includes the following steps:

[0134] The integrated circuit under test is installed on the test station of the three-dimensional stacked adaptive multiphysics coupling test module.

[0135] The active global electromagnetic interference cancellation module is activated to eliminate electromagnetic interference to the test.

[0136] Spatial electromagnetic interference signals are detected by a distributed electromagnetic sensor array. The interference signal processing unit separates external and internal interference and generates and radiates corresponding cancellation signals through a real-time electromagnetic interference cancellation algorithm, thereby eliminating electromagnetic signal interference.

[0137] The real-time electromagnetic interference cancellation algorithm executed by the active global electromagnetic interference cancellation module includes:

[0138] Establish an electromagnetic interference signal model:

[0139]

[0140] in, for Electromagnetic interference signals at any time For the first The amplitude of each interference component, For the first The frequency of each interference component For the first The phase of each interference component, It is Gaussian white noise. The number of interference components;

[0141] The parameters of the interference signal are estimated using an adaptive spectral estimation algorithm:

[0142]

[0143] in, For the first The estimated value of the disturbance parameter in the next iteration For parameter-based The estimated value of the interference signal, To estimate the window size, we use values ​​between 256 and 1024;

[0144] Generate cancellation signal:

[0145]

[0146] in, for The cancellation signal at that moment;

[0147] Closed-loop feedback adjustment:

[0148] The convergence condition is met when the root mean square value of the residual electromagnetic interference is less than 0.5 μV and remains stable for 100 consecutive sampling periods.

[0149] The main control module sends test parameters to the test module, including electrical stress parameters, thermal stress parameters, and mechanical stress parameters.

[0150] The intelligent parallel test scheduling unit generates the optimal parallel test scheduling scheme based on test parameters and system status.

[0151] The parallel test intelligent scheduling algorithms executed by the parallel test intelligent scheduling unit include:

[0152] Define the objective function:

[0153]

[0154] in, The objective function value, This represents the total number of test channels. For the first The time it takes for each channel to complete all test tasks.

[0155] The parallel test intelligent scheduling algorithm also includes:

[0156] Constraints:

[0157] The load rate of a single power supply module shall not exceed 80%, the temperature gradient inside the test chamber shall not exceed 2℃ / m, and the temperature difference between adjacent test stations shall not exceed 1℃.

[0158] The optimal scheduling scheme is solved using a genetic algorithm:

[0159] Encoding: Integer encoding is used, the chromosome length is the total number of test tasks, and each gene represents the channel number assigned to the corresponding test task;

[0160] Initialize the population: Randomly generate 50 to 200 individuals as the initial population;

[0161] Fitness calculation: Calculate the fitness value for each individual. ;

[0162] Selection: The roulette wheel selection method is used to select superior individuals, and the selection probability is directly proportional to the fitness value;

[0163] Crossover: Perform a single-point crossover operation on the selected individuals, with a crossover probability of 0.7 to 0.9;

[0164] Mutation: Perform random mutation operations on individuals, with a mutation probability ranging from 0.01 to 0.1;

[0165] Termination condition: When the number of iterations reaches 100-500 or the fitness value converges, the algorithm terminates and outputs the optimal scheduling scheme.

[0166] Scheduling scheme updates: Updated every 10 minutes, or immediately when a test task is completed or a new task is added.

[0167] According to the test scheduling scheme, the test module applies synchronous electrical stress, thermal stress and mechanical stress to the integrated circuit under test through a multi-physics field coupled stress application algorithm.

[0168] The mathematical expression for the multiphysics coupled stress application algorithm is:

[0169]

[0170] in, for The total coupled stress vector at time t, The electric stress vector. For thermal stress vector, For mechanical stress vector, These are the coupling coefficients for electrical stress, thermal stress, and mechanical stress, respectively, and they satisfy... ;

[0171] Method for determining coupling coefficient:

[0172] The determination is made through orthogonal experiments based on the actual operating environment of the integrated circuit under test; for integrated circuits used in automotive electronics, Take 0.5, Take 0.3, Take 0.2; for aerospace integrated circuits, Take 0.4, Take 0.4, Take 0.2.

[0173] The synchronous differential sampling array acquires the electrical parameters of the integrated circuit under test according to the preset sampling frequency.

[0174] The inter-channel crosstalk adaptive cancellation unit eliminates the impact of inter-channel crosstalk on the sampled data through an inter-channel crosstalk cancellation algorithm.

[0175] The inter-channel crosstalk cancellation algorithm executed by the adaptive inter-channel crosstalk cancellation unit includes:

[0176] Establish an inter-channel crosstalk model:

[0177]

[0178] in, For the first The sampling signals of each channel, For the first The original signal of each channel, For the first The first channel to the first Crosstalk impulse response of each channel This represents the convolution operation. Additive noise, Total number of channels;

[0179] The crosstalk impulse response is estimated using the normalized least mean square algorithm:

[0180]

[0181] in, For the first Estimate of crosstalk impulse response in the next iteration Step size factor For the first The input signal vector of each channel, This is an error signal;

[0182] Step size factor dynamically adjusted:

[0183] The initial step size is 0.01. When the root mean square value of the error signal is greater than 1mV, the step size is increased to 0.1; when the root mean square value of the error signal is less than 10μV, the step size is decreased to 0.001.

[0184] Cancel crosstalk:

[0185]

[0186] in, The first after crosstalk cancellation One channel signal.

[0187] The sampled data is preprocessed using a synchronous differential sampling data processing algorithm.

[0188] Synchronous differential sampling data processing algorithms include:

[0189] Perform a difference operation on the raw data of each sampling channel:

[0190]

[0191] in, For the first The differential voltage at each sampling point The sampling voltage is the positive input terminal. The negative input terminal samples the voltage.

[0192] Perform moving average filtering on the differential voltage:

[0193]

[0194] in, This is the filtered voltage. This is the size of the sliding window; when the sampling frequency is 1 MSPS, Take 16; when the sampling frequency is 2MSPS, Take 32.

[0195] An adaptive error correction algorithm is used to perform real-time error correction on the preprocessed test data.

[0196] Adaptive error correction algorithms include:

[0197] Establish a systematic error model:

[0198]

[0199] in, For the first Systematic error of the measurement Zero-point error, This is the temperature error coefficient. For current error coefficient, This is the temperature-current crossover error coefficient. The current temperature. This is the current.

[0200] The error coefficients are updated in real time using the Kalman filter algorithm.

[0201]

[0202] in, For the first The estimated error coefficients of the next iteration For Kalman gain, These are actual measured values. For observation vectors;

[0203] Kalman gain calculation formula:

[0204]

[0205] in, For the first The error covariance matrix of the next iteration. To measure the noise covariance matrix.

[0206] The aging parameter real-time early warning unit monitors the aging status of the integrated circuit under test in real time, and issues an early warning and automatically stops the test of that channel when an abnormality is detected.

[0207] The aging warning methods executed by the real-time aging parameter warning unit include:

[0208] A continuous sequence of aging characteristic parameters was collected, including threshold voltage drift, leakage current change, and on-resistance change.

[0209] Input the aging characteristic parameter sequence into a long short-term memory neural network model to output the failure probability;

[0210] When the failure probability exceeds 0.9, an early warning signal is issued and the test of that channel is automatically stopped;

[0211] The warning threshold was determined using an ROC curve, at which point the warning accuracy rate was 95% and the false alarm rate was 3%.

[0212] For different types of integrated circuits, the output layer of the model is fine-tuned using aging test data from approximately 100 target type integrated circuits.

[0213] The corrected test data is sent to the main control module to establish a mathematical model of aging characteristic parameters and failure time.

[0214] The remaining lifespan of the integrated circuit under test is predicted based on a mathematical model, and a test report is generated.

[0215] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A test method for aging integrated circuits, characterized in that: The testing method includes the following steps: S1: Install the integrated circuit under test on the test station and eliminate electromagnetic interference to the test; S2: Send test parameters to the test module through the main control module; S3: Generate the optimal parallel test scheduling scheme based on test parameters and system status; S4: Apply synchronous electrical, thermal, and mechanical stresses to the integrated circuit under test according to the test scheduling scheme; S5: During the test, the electrical parameters of the integrated circuit under test are collected at a specific sampling frequency, and the collected data is preprocessed. S6: Perform real-time error correction on the preprocessed test data and monitor the aging status of the integrated circuit under test in real time through the early warning unit; S7: Establish a mathematical model of aging characteristic parameters and failure time based on the corrected test data, and generate a test report.

2. The integrated circuit aging test method according to claim 1, characterized in that: In step S1, the interference of electromagnetic signals on the test is eliminated using an active global electromagnetic interference cancellation method. The real-time electromagnetic interference cancellation algorithm includes: Establish an electromagnetic interference signal model: in, for Electromagnetic interference signals at any time For the first The amplitude of each interference component, For the first The frequency of each interference component For the first The phase of each interference component, It is Gaussian white noise. The number of interference components; The parameters of the interference signal are estimated using an adaptive spectral estimation algorithm: in, For the first The estimated value of the disturbance parameter in the next iteration For parameter-based The estimated value of the interference signal, To estimate the window size, we use values ​​between 256 and 1024; Generate cancellation signal: in, for The cancellation signal at that moment; Closed-loop feedback adjustment: The convergence condition is met when the root mean square value of the residual electromagnetic interference is less than 0.5 μV and remains stable for 100 consecutive sampling periods.

3. The integrated circuit aging test method according to claim 2, characterized in that: The parallel test scheduling scheme in S3 is generated through a parallel test intelligent scheduling algorithm, which includes: Define the objective function: in, The objective function value, This represents the total number of test channels. For the first The time it takes for each channel to complete all test tasks.

4. The integrated circuit aging test method according to claim 3, characterized in that: When collecting electrical parameters in S5, an inter-channel crosstalk cancellation algorithm is used to eliminate the influence of inter-channel crosstalk on the sampled data. The inter-channel crosstalk cancellation algorithm includes: Establish an inter-channel crosstalk model: in, For the first The sampling signal of each channel, For the first The original signal of each channel, For the first The first channel to the first Crosstalk impulse response of each channel This represents the convolution operation. Additive noise, Total number of channels; The crosstalk impulse response is estimated using the normalized least mean square algorithm: in, For the first Estimate of crosstalk impulse response in the next iteration Step size factor For the first The input signal vector of each channel, This is an error signal; Step size factor dynamically adjusted: The initial step size is 0.

01. When the root mean square value of the error signal is greater than 1mV, the step size is increased to 0.1; when the root mean square value of the error signal is less than 10μV, the step size is decreased to 0.

001. Cancel crosstalk: in, The first after crosstalk cancellation One channel signal.

5. The integrated circuit aging test method according to claim 4, characterized in that: In step S4, the synchronous application of electrical, thermal, and mechanical stresses to the integrated circuit under test is performed using a multi-physics field coupling stress application algorithm. The mathematical expression of the multi-physics field coupling stress application algorithm is as follows: in, for The total coupled stress vector at time t, The electric stress vector. The thermal stress vector For mechanical stress vector, These are the coupling coefficients for electrical stress, thermal stress, and mechanical stress, respectively, and they satisfy... .

6. The integrated circuit aging test method according to claim 5, characterized in that: The preprocessing in S5 is performed using a synchronous differential sampling data processing algorithm, which includes: Perform a difference operation on the raw data of each sampling channel: in, For the first The differential voltage at each sampling point The sampling voltage is the positive input terminal. The negative input terminal samples the voltage. Perform moving average filtering on the differential voltage: in, This is the filtered voltage. This is the size of the sliding window; when the sampling frequency is 1 MSPS, Take 16; when the sampling frequency is 2MSPS, Take 32.

7. The integrated circuit aging test method according to claim 6, characterized in that: The real-time error correction in S6 is performed using an adaptive error correction algorithm, which includes: Establish a systematic error model: in, For the first Systematic error of the measurement Zero-point error, This is the temperature error coefficient. For current error coefficient, This is the temperature-current crossover error coefficient. The current temperature. This is the current. The error coefficients are updated in real time using the Kalman filter algorithm. in, For the first The estimated error coefficients of the next iteration For Kalman gain, These are actual measured values. For observation vectors; Kalman gain calculation formula: in, For the first The error covariance matrix of the next iteration. To measure the noise covariance matrix.

8. The integrated circuit aging test method according to claim 7, characterized in that: The aging warning method for monitoring the aging status of the integrated circuit under test by the early warning unit in S6 includes: A continuous sequence of aging characteristic parameters was collected, including threshold voltage drift, leakage current change, and on-resistance change. Input the aging characteristic parameter sequence into a long short-term memory neural network model to output the failure probability; When the failure probability exceeds 0.9, an early warning signal is issued and the test of that channel is automatically stopped; The warning threshold was determined using the ROC curve, at which point the warning accuracy rate was 95% and the false alarm rate was 3%. For different types of integrated circuits, the output layer of the model is fine-tuned using aging test data from approximately 100 target type integrated circuits.

9. An integrated circuit aging test apparatus, used to perform the integrated circuit aging test method according to any one of claims 1-8, characterized in that: include: The main control module is used to control the operation of the entire device and to receive and process test data; A three-dimensional stacked adaptive multiphysics coupling test module, at least one of which is connected to the main control module, integrates an inter-channel crosstalk adaptive cancellation unit, a parallel test intelligent scheduling unit, and an aging parameter real-time early warning unit, which is used to apply multiphysics coupling stress to the integrated circuit under test and collect test data. The active global electromagnetic interference cancellation module communicates with the main control module and includes a distributed electromagnetic sensor array, an interference signal processing unit, an adaptive cancellation signal generation unit, a multi-point cancellation signal radiation array, and a closed-loop feedback unit. It is used to detect and cancel the interference of electromagnetic signals from the external environment and the equipment inside the test in real time. The environmental control module communicates with the main control module and is used to control the environmental parameters inside the test chamber; The data storage module communicates with the main control module and is used to store test data and test results; The power module is used to provide power to the entire test equipment.

10. An integrated circuit aging test apparatus according to claim 9, characterized in that: The three-dimensional stacked adaptive multiphysics coupling test module includes: The module substrate is made of high thermal conductivity silicon carbide ceramic material and has multiple testing stations. The three-dimensional stacked power drive array is vertically stacked on the module substrate and adopts a combination of liquid cooling and heat dissipation through thermal holes. Each power drive unit corresponds to a test station. A synchronous differential sampling array, corresponding one-to-one with a three-dimensional stacked power drive array, is used to acquire the electrical parameters of the integrated circuit under test. A local thermal control unit is integrated below each test station to precisely control the temperature of the integrated circuit under test; A mechanical stress application unit is installed above each test station to apply controllable mechanical stress to the integrated circuit under test. The inter-channel crosstalk adaptive cancellation unit is communicatively connected to the synchronous differential sampling array and uses the normalized minimum mean square algorithm to cancel the mutual crosstalk between test channels; The parallel test intelligent scheduling unit communicates with the module controller and uses a dynamic task scheduling strategy based on genetic algorithms to optimize the task scheduling of multiple test channels. The aging parameter real-time early warning unit is connected to the synchronous differential sampling array and uses a long short-term memory neural network model to monitor the aging status of the integrated circuit under test in real time and provide early warning. The unit controller is connected to each of the above units for communication.

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