Chip automated integrated test system and method

Abstract

The application discloses a kind of chip automation integrated test system and method, including host computer software module, instrument control layer, test instrument cluster, probe station-clamp component, the measured chip component and data acquisition storage module;The host computer software module is used to control and manage the order process of whole test, receives the detection data of return transmission, completes data comparison, result analysis and test report export;The beneficial effects of the application are: whole system can automatically complete chip all detection process, save a lot of manual debugging operation, substantially compress the test length of chip, the overall detection efficiency is improved;Automated control can reduce the error caused by manual operation, the operation condition of each test is uniform, and the test data stability, repeatability is better;System can automatically collect, save all original test data, automatically complete parameter comparison, qualified determination, facilitate staff to do data review, yield control and optimize chip processing technology.

Description

Technical Field

[0001] This invention belongs to the field of chip testing technology, specifically relating to an automated chip integration testing system and method. Background Technology

[0002] The optical communication industry is constantly being updated and iterated. Electrically modulated laser chips are a key light-emitting component in high-speed optical modules. The chips themselves are becoming more and more integrated and their internal structures are becoming more complex.

[0003] Currently, many factories still rely on operators to manually complete various chip performance tests. The touch position and adjustment parameters of each manual operation are prone to deviation, resulting in poor repeatability of the test data. The entire testing process is time-consuming, and a single complete test often takes a long time. Moreover, manually recorded data is prone to omissions, making it inconvenient to subsequently calculate chip yield and trace defects in the production process. Manual positions also require the long-term employment of skilled testers, resulting in significant long-term human resource costs.

[0004] Most of the simple testing devices currently available on the market can only test one chip parameter at a time. They cannot integrate DC parameters, high-speed optical signals, and high and low temperature environment tests into a single device. The scheduling between instruments is cumbersome, and the optical path coupling debugging also requires repeated manual adjustments, resulting in poor overall compatibility. Summary of the Invention

[0005] The purpose of this invention is to provide an automated chip integration testing system and method to solve the problems of low overall testing efficiency, high labor costs, and poor overall adaptability mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: an automated chip integration testing system, comprising a host computer software module, an instrument control layer, a cluster of test instruments, a probe station-fixture assembly, a chip under test assembly, and a data acquisition and storage module; The host computer software module is used to manage the entire testing process, receive the returned test data, and complete data comparison, result analysis, and test report export. The instrument control layer is connected to the detection instrument and has built-in drive instructions corresponding to the instrument. After receiving the operation instructions sent by the host computer, it is converted into control signals that the instrument can recognize. The test instrument cluster includes a power supply unit, an optical power detection device, a spectral analysis device, a bit error rate tester, and a digital communication analyzer. The power supply unit outputs bias current and modulation voltage to the chip under test, and the other devices sequentially complete optical power reading, spectral analysis, high-speed eye diagram, and bit error rate performance testing. The probe station-fixture assembly has a temperature control structure. The chip in wafer state completes electrode docking by relying on the probe station, and the packaged chip is placed inside the test fixture. The fixture is equipped with an optical fiber coupling structure to transmit the optical signal output by the chip into the testing instrument. The temperature control structure is used to adjust the working environment temperature of the chip. The data acquisition and storage module captures the raw parameters generated during the entire testing process in real time and compares them with the chip's factory specifications to determine whether it is qualified or unqualified.

[0007] As a preferred technical solution of the present invention, the host computer software module is used to manage the entire test process, receive the returned test data, complete data comparison, result analysis and test report export; the staff can change the test parameters and view the chip test status in real time on the host computer interface.

[0008] As a preferred technical solution of the present invention, the instrument control layer is connected to the detection instrument via GPIB, USB or local area network line.

[0009] As a preferred technical solution of the present invention, the chip component under test is an EML chip to be tested. The chip receives the electrical signal output by the instrument cluster, outputs the corresponding optical signal, and simultaneously feeds back its own operating parameters in real time.

[0010] As a preferred technical solution of the present invention, the data acquisition and storage module captures the raw parameters generated in the entire test process in real time, compares them with the chip's factory specifications to determine whether they are qualified or unqualified, and stores the test data in a local database or document for the host computer to retrieve and analyze.

[0011] As a preferred technical solution of the present invention, the chip component under test is an EML chip to be tested, which receives the electrical signal output by the instrument cluster and outputs the corresponding optical signal.

[0012] This invention also discloses an automated chip integration testing method, comprising the following steps: Step 1: Connect the entire set of hardware equipment, and perform equipment self-test, optical path coupling debugging, and testing instrument calibration; Step 2: Start DC parameter detection, scan voltage and current data, and then detect the corresponding parameters of chip optical power, current, and voltage; Step 3: Connect to high-speed testing equipment, output high-speed code pattern signal to drive the chip, collect optical signals to generate eye diagrams, and then perform long-term bit error rate detection under multiple working conditions; Step 4: Extract chips for stability testing through high-temperature aging and temperature cycling. Step 5: Summarize all test parameters, compare them with standard thresholds to determine the quality of the chip, store the data, and generate the corresponding test document.

[0013] Compared with the prior art, the beneficial effects of the present invention are: The entire system can automatically complete the entire chip testing process, saving a lot of manual debugging operations, significantly reducing the chip testing time, and improving the overall testing efficiency. Automated operation can reduce errors caused by manual operation. The operating conditions are consistent for each test, resulting in better stability and repeatability of test data. The system can automatically collect and save all raw test data, automatically complete parameter comparison and qualification judgment, which makes it convenient for staff to review data, control yield and optimize chip processing technology. By integrating electrical power supply, optical detection, high-speed signal testing, chip temperature control, and optical path coupling structure into one device, a single unit can complete multiple tests including DC parameters, high-speed performance, and environmental reliability. The device has a high degree of integration, eliminating the need to repeatedly disassemble and reassemble multiple testing instruments. Attached Figure Description

[0014] Figure 1 This is a flowchart of an automated chip integration testing method according to the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention provides an automated chip integration testing system, including a host computer software module, an instrument control layer, a cluster of test instruments, a probe station-fixture assembly, a chip under test assembly, and a data acquisition and storage module; The host computer software module is connected to the instrument control layer, and the instrument control layer is connected to the test instrument cluster. The test instrument cluster is connected to the probe station-fixture assembly and the chip under test assembly respectively. The probe station-fixture assembly and the chip under test assembly are interconnected. The chip under test assembly is connected to the data acquisition and storage module, and the data acquisition and storage module sends back data to the host computer software module.

[0017] In this embodiment, the host computer software module is used to manage the entire test process, receive the returned test data, and complete data comparison, result analysis, and test report export. Operators can change test parameters and view the chip test status in real time on the host computer interface. The specific implementation method is as follows: The host computer has a separate visual operation window. After logging in, the operator fills in the EML chip specifications to be tested and the order of each test. To skip a test or modify the current and voltage scan range, the operator simply enters the value or selects the corresponding option on the page, without modifying the underlying control program. After the entire test is started, the software will proceed according to the previously set steps, recording the progress of each step, whether the instrument is responding normally, and which group of chips is currently being tested. The parameters are displayed on the page in real time. The raw data transmitted from each instrument is continuously sent to the software. The background automatically compares the real-time measured values ​​with the chip specification thresholds entered at the beginning. Parameters that exceed the standard range will be marked directly. After all the test items are completed, the software will collect all the raw data measured and the marks of pass or fail. There is no need for manual copying and pasting to organize the tables. The system can automatically export a document that can be directly archived. It will list all the results of DC parameters, eye diagrams, bit errors, and high and low temperature tests separately. For subsequent yield checks and process problem reviews, the corresponding files can be retrieved directly. If an instrument loses connection or the optical path signal is abnormal during the test, the interface will also pop up a prompt box to pause the process and clearly mark the fault point for the operator, so that there is no need to check the problem of each instrument one by one.

[0018] In this embodiment, the instrument control layer connects to the detection instrument via GPIB, USB, or local area network. It has built-in drive instructions corresponding to the instrument and converts the operation instructions sent by the host computer into control signals that the instrument can recognize.

[0019] In this embodiment, the test instrument cluster includes a power supply unit, an optical power detection device, a spectral analysis device, a bit error rate tester, and a digital communication analyzer. The power supply unit outputs bias current and modulation voltage to the chip under test, and the other devices sequentially complete optical power reading, spectral analysis, high-speed eye diagram, and bit error rate performance testing.

[0020] In this embodiment, the probe station-fixture assembly is equipped with a temperature control structure. The chip in wafer state completes electrode docking by relying on the probe station, and the packaged chip is placed inside the test fixture. The fixture is equipped with an optical fiber coupling structure to transmit the optical signal output by the chip into the testing instrument. The temperature control structure is used to adjust the working environment temperature of the chip.

[0021] In this embodiment, the data acquisition and storage module captures the raw parameters generated during the entire testing process in real time, compares them with the chip's factory specifications to determine whether they are qualified or unqualified, and stores the test data in a local database or document for the host computer to retrieve and analyze.

[0022] In this embodiment, the chip component under test is the EML chip to be tested. The chip receives the electrical signal output by the instrument cluster, outputs the corresponding optical signal, and simultaneously feeds back its own operating parameters in real time.

[0023] Please see Figure 1 This invention provides an automated chip integration testing method, comprising the following steps: Step 1: Connect the entire set of hardware equipment, and perform equipment self-test, optical path coupling debugging, and testing instrument calibration; Step 2: Start DC parameter detection, scan voltage and current data, and then detect the corresponding parameters of chip optical power, current, and voltage; Step 3: Connect to high-speed testing equipment, output high-speed code pattern signal to drive the chip, collect optical signals to generate eye diagrams, and then perform long-term bit error rate detection under multiple working conditions; Step 4: Extract chips for stability testing through high-temperature aging and temperature cycling. Step 5: Summarize all test parameters, compare them with standard thresholds to determine the quality of the chip, store the data, and generate the corresponding test document.

[0024] Although embodiments of the invention have been shown and described (see the detailed description above), it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An automated chip integration testing system, characterized in that: It includes a host computer software module, an instrument control layer, a cluster of test instruments, a probe station-fixture assembly, a chip under test assembly, and a data acquisition and storage module; The host computer software module is used to manage the entire testing process, receive the returned test data, and complete data comparison, result analysis, and test report export. The instrument control layer is connected to the detection instrument and has built-in drive instructions corresponding to the instrument. After receiving the operation instructions sent by the host computer, it is converted into control signals that the instrument can recognize. The test instrument cluster includes a power supply unit, an optical power detection device, a spectral analysis device, a bit error rate tester, and a digital communication analyzer. The power supply unit outputs bias current and modulation voltage to the chip under test, and the other devices sequentially complete optical power reading, spectral analysis, high-speed eye diagram, and bit error rate performance testing. The probe station-fixture assembly has a temperature control structure. The chip in wafer state completes electrode docking by relying on the probe station, and the packaged chip is placed inside the test fixture. The fixture is equipped with an optical fiber coupling structure to transmit the optical signal output by the chip into the testing instrument, and the temperature control structure is used to adjust the working environment temperature of the chip. The data acquisition and storage module captures the raw parameters generated during the entire testing process in real time and compares them with the chip's factory specifications to determine whether it is qualified or unqualified.

2. The automated chip integration testing system according to claim 1, characterized in that: The host computer software module is used to manage the entire testing process, receive the returned test data, complete data comparison, result analysis, and export test reports; staff can change test parameters and view the chip testing status in real time on the host computer interface.

3. The automated chip integration testing system according to claim 1, characterized in that: The instrument control layer is connected to the testing instrument via GPIB, USB, or a local area network.

4. The automated chip integration testing system according to claim 1, characterized in that: The chip component under test is an EML chip that receives electrical signals from the instrument cluster, outputs corresponding optical signals, and simultaneously provides real-time feedback of its own operating parameters.

5. The automated chip integration testing system according to claim 1, characterized in that: The data acquisition and storage module captures the raw parameters generated during the entire testing process in real time, compares them with the chip's factory specifications to determine whether it is qualified or unqualified, and stores the test data in a local database or document for the host computer to retrieve and analyze.

6. The automated chip integration testing system according to claim 1, characterized in that: The chip component under test is an EML chip that receives electrical signals from the instrument cluster and outputs corresponding optical signals.

7. A method for automated chip integration testing, applied to the automated chip integration testing system as described in any one of claims 1-6, characterized in that, Includes the following steps: Step 1: Connect the entire set of hardware equipment, and perform equipment self-test, optical path coupling debugging, and testing instrument calibration; Step 2: Start DC parameter detection, scan voltage and current data, and then detect the corresponding parameters of chip optical power, current, and voltage; Step 3: Connect to high-speed testing equipment, output high-speed code pattern signal to drive the chip, collect optical signals to generate eye diagrams, and then perform long-term bit error rate detection under multiple working conditions; Step 4: Extract chips for stability testing through high-temperature aging and temperature cycling. Step 5: Summarize all test parameters, compare them with standard thresholds to determine the quality of the chip, store the data, and generate the corresponding test document.

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