High-precision slope testing machine

Abstract

The application discloses a high-precision slope testing machine, which comprises a testing platform installed on a machine body and extending downwardly and obliquely, and a scanning box arranged in the machine body and below the testing platform. The application can effectively improve the testing precision and stability of a chip testing system, ensure the testing accuracy of a single parameter, greatly improve the whole machine testing reliability and batch testing consistency, and promote the application capability of the equipment in a high-end precise chip testing scene. The application is suitable for the technical field of chip testing equipment.

Description

Technical Field

[0001] This invention belongs to the technical field of testing machines, specifically, it relates to a high-precision slope testing machine. Background Technology

[0002] In the existing chip testing equipment architecture, long cabling is commonly used to interconnect signals and power supply between the tester and the scanning box. Although this conventional cabling structure can meet the basic requirements of equipment layout and wiring adaptation, in high-precision chip electrical testing scenarios, excessively long transmission cabling will produce a series of unavoidable electrical defects. Its inherent parasitic parameters and resistance loss problems will seriously interfere with the electrical characteristics of the test circuit, destroy the balance and stability of the test system, and ultimately lead to the distortion of many core test indicators, making it impossible to accurately reflect the true electrical performance of the chip. The specific defects and impact mechanisms are as follows.

[0003] Parasitic interference from long cabling is one of the core issues affecting test accuracy. In electrical testing theory, ideal conductors have no inductance or capacitance characteristics. However, long cabling in practical applications is a non-ideal transmission line. The longer the cabling, the more significant the residual parasitic inductance and inter-line distributed capacitance become. Moreover, these parasitic parameters are random and uncontrollable, and cannot be eliminated through conventional calibration. During chip dynamic and high-frequency parameter testing, the parasitic inductance of the cabling generates induced impedance as the test signal frequency changes, hindering the instantaneous current response of the test circuit and causing signal phase shift and amplitude attenuation. Furthermore, the distributed capacitance between adjacent cores of the cabling can cause inter-line signal coupling and charge accumulation, easily generating signal crosstalk and noise interference. This type of parasitic interference introduced by the cabling is superimposed on the original chip test signal, completely polluting the valid test data. This leads to a significant deviation between the dynamic and high-frequency parameters acquired by the equipment and the chip's true performance. Especially in precise small-signal testing scenarios, the errors caused by parasitic parameters are further amplified.

[0004] Long cabling structures significantly increase the contact and loop resistance of the testing system, leading to inaccurate DC resistance testing and zero-point drift. Excessively long cabling directly extends the transmission path of the entire electrical circuit, significantly increasing not only the inherent resistance of the cabling itself but also the number of connection nodes such as test connectors, plug-in interfaces, and scan box terminals, greatly increasing the probability of cumulative contact resistance at these nodes. Influenced by assembly tolerances, metal oxidation, contact pressure, and ambient temperature and humidity, various contact resistances and total loop resistance are not fixed values ​​but fluctuate dynamically. In precise DC parameter testing such as chip DC resistance and static power consumption, the fluctuating additional loop resistance will be superimposed in series with the chip's resistance under test, forming both fixed test deviations and random errors, directly reducing the accuracy of DC testing. Simultaneously, unstable loop resistance continuously alters the reference electrical zero point of the testing system, causing severe zero-point drift. This results in a lack of consistency in the reference zero point for each power-on and each test cycle, significantly reducing test repeatability and consistency, making it difficult to accurately identify minute resistance defects and static electrical anomalies in chips, and easily leading to misjudgments of good products and missed detections of defective products.

[0005] Long cabling can disrupt the common-mode symmetry of the test circuit, causing mode conversion errors and leading to the failure of longitudinal balance test results. Longitudinal balance metrics such as LCL (Longitudinal Conversion Loss) and BL (Balance Loss) are core indicators for measuring the signal transmission balance and anti-interference capabilities of a chip. Their test accuracy depends entirely on the high symmetry and impedance consistency of the positive and negative signal paths and differential transmission channels in the test circuit. However, during the wiring process, ultra-long cabling is prone to issues such as trace misalignment, bending differences, and uneven core spacing, directly causing mismatches in parasitic inductance, distributed capacitance, and circuit resistance parameters of the positive and negative transmission paths, completely disrupting the common-mode symmetry characteristics of the test system. Under these conditions, severe mode conversion errors occur during testing, and the common-mode signal, which is supposed to suppress interference, is abnormally converted into an interfering differential-mode signal, introducing additional invalid interference components. These errors cannot be eliminated through conventional calibration and parameter compensation, resulting in the LCL and BL metrics acquired by the test system failing to absorb the interference errors caused by the cabling structure. This completely fails to reflect the true longitudinal electrical balance characteristics of the chip itself, ultimately causing distortion in the core balance test results and failing to meet the test acceptance standards for high-end chips, high-precision analog chips, and high-speed signal chips.

[0006] In summary, the long cabling structure between the tester and the scanning box comprehensively reduces the testing accuracy and stability of the chip testing system from three dimensions: parasitic parameter interference, DC resistance inaccuracy, and disruption of loop symmetry. It not only affects the testing accuracy of individual parameters, but also leads to a significant reduction in the overall testing reliability and batch testing consistency, thus restricting the equipment's application capability in high-end precision chip testing scenarios. Summary of the Invention

[0007] This invention provides a high-precision ramp tester to improve the testing accuracy and stability of chip testing systems, ensure the testing accuracy of single parameters, significantly improve the overall testing reliability and batch testing consistency, and promote the application capability of the equipment in high-end precision chip testing scenarios.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A high-precision ramp testing machine includes a testing platform mounted on the machine body and extending downward at an angle, and a scanning box disposed inside the machine body and below the testing platform.

[0009] A further technical solution involves providing an assembly slot on one side of the machine body, into which the scanning box is placed.

[0010] A further technical solution is that the testing platform includes a tube feeding area, a pressure resistance testing area, a comprehensive testing area, and a tube receiving area arranged sequentially at an inclined downward direction. A defective product receiving area is provided on one side of the junction between the comprehensive testing area and the tube receiving area. A linear slide is installed on the machine body at the position of the pressure resistance testing area and the comprehensive testing area, which can reciprocate between the tube feeding area, the pressure resistance testing area, the comprehensive testing area, and the tube receiving area. Two pneumatic grippers are installed at intervals on the linear slide along the inclined direction of the testing platform.

[0011] A further technical solution is that a first tube placement area is provided on one side of the tube feeding area, and multiple first empty tubes are placed side by side in the first tube placement area; a second tube placement area is provided on one side of the tube receiving area, and multiple second empty tubes are placed side by side in the second tube placement area.

[0012] A further technical solution is that a feed pipe is placed in the tubular feeding area, the feed pipe extends along the inclined direction of the test platform, and multiple products to be tested are placed sequentially in the feed pipe along its inclined direction.

[0013] A further technical solution is that a receiving tube is placed in the tube receiving area, the receiving tube extends along the inclined direction of the test platform, and multiple tested products are placed sequentially in the receiving tube along its inclined direction.

[0014] A further technical solution is that the scanning box is located below the pressure resistance test area and the comprehensive test area.

[0015] A further technical solution involves assembling a control console and an operation screen on the machine body.

[0016] The technological advancements achieved by this invention compared to existing technologies, due to the adoption of the aforementioned structure, are as follows: This invention employs a built-in scanning box, resulting in an extremely short ribbon cable connected to the scanning box. Compared to existing external scanning boxes that use long ribbon cables, this significantly reduces the parasitic inductance of the ribbon cable. During dynamic and high-frequency parameter testing of chips, no additional induced impedance is generated, and the instantaneous current response of the chip test circuit is not hindered, eliminating undesirable phenomena such as signal phase shift and amplitude attenuation. Furthermore, the distributed capacitance between the ribbon cable lines is greatly reduced, eliminating signal coupling and charge accumulation between the cable cores and avoiding signal crosstalk and noise interference. Especially for precision small-signal testing scenarios, interference errors introduced by the ribbon cable itself can be greatly suppressed. The dynamic and high-frequency parameters acquired by the device can accurately reproduce the chip's original electrical performance, and the test data is not subject to additional contamination from the wiring structure.

[0017] Significantly reducing the cable length shortens the overall electrical transmission loop, completely eliminating DC test deviation and zero-point drift issues. Firstly, the reduced cable length shortens the overall transmission path of the test electrical circuit, significantly lowering the inherent resistance of the cable itself. It also reduces various connection nodes such as terminals and plugs, lowering the total cumulative contact resistance and mitigating loop resistance fluctuations caused by factors such as assembly tolerances, metal oxidation, contact pressure, and changes in ambient temperature and humidity. Secondly, when testing DC parameters such as chip DC resistance and static power consumption, there are no fixed deviations or random errors caused by additional series resistance, greatly improving the accuracy of DC parameter testing. Thirdly, the test loop resistance remains stable over a long period, ensuring a unified electrical reference zero point for the test system. Zero-point drift does not occur during each power-on and batch test, significantly improving test repeatability. This allows for accurate identification of minute resistance defects and static electrical anomalies in chips, effectively avoiding production inspection problems such as misjudging good products and missing defective products.

[0018] The extremely short cabling layout ensures the common-mode symmetry of the differential transmission loop, enabling accurate detection of longitudinal balance indicators such as LCL longitudinal conversion loss and BL balance loss. LCL longitudinal conversion loss and BL balance loss are core indicators for evaluating the signal transmission balance and anti-interference capabilities of high-end chips. The accuracy of these tests depends entirely on the matching degree of impedance and parasitic parameters between the positive and negative differential signal channels. With the extremely short cabling structure of this invention, problems such as trace offset, bending differences, and uneven core spacing that disrupt loop symmetry are essentially eliminated. The parasitic inductance, distributed capacitance, and loop resistance of the positive and negative signal transmission paths can achieve a high degree of matching, completely preserving the common-mode symmetry characteristics of the test loop itself. During testing, there will be no mode conversion error from abnormal conversion of the common-mode signal to the interfering differential-mode signal, and no additional invalid interference components will be superimposed on the test signal. Interference errors caused by the wiring structure can be eliminated without complex calibration and parameter compensation operations, accurately measuring the chip's true longitudinal electrical balance characteristics. This meets the stringent factory testing and acceptance standards for high-speed signal chips, high-precision analog chips, and various high-end precision chips.

[0019] Building upon this foundation, the present invention simultaneously addresses three types of systematic test errors: parasitic parameter interference, DC test errors, and transmission loop asymmetry. This effectively improves the overall testing reliability and batch testing consistency, broadening the equipment's adaptability in the field of high-end precision chip testing. On one hand, the accuracy of testing various electrical parameters of a single chip is significantly improved, and various test errors derived from wiring are uniformly eliminated. On the other hand, the dispersion of test data between chips from the same batch and different production batches is greatly reduced, significantly optimizing batch testing consistency. The overall testing stability and reliability are comprehensively enhanced, breaking through the performance bottleneck of traditional chip testing equipment limited by long cabling structures. It can be widely adapted to various high-end precision chip testing scenarios, effectively expanding the application scope of this equipment. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0021] In the attached diagram: Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention; Figure 2 This is a structural schematic diagram from another angle of an embodiment of the present invention.

[0022] Components marked: 1-Main body, 2-Control console, 3-Operation screen, 4-Assembly slot, 5-Power socket, 6-Tube feeding area, 7-First tube placement area, 8-Pressure resistance test area, 9-Comprehensive test area, 10-Defective product receiving area, 11-Tube receiving area, 12-Second tube placement area. Detailed Implementation

[0023] The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0024] This invention discloses a high-precision slope testing machine, such as... Figures 1-2 As shown, it includes a test platform mounted on the body 1 and extending downward at an angle. A scanning box is set inside the body 1 and below the test platform, and the ribbon cable connecting the scanning box is shortened to 5-10cm.

[0025] This invention employs two models: an older long-ribbon cable design and a newer short-ribbon cable design. Hereinafter, the long-ribbon cable design refers to Model A, and the short-ribbon cable design refers to Model B. (All probes must be replaced with new ones before testing.) 10,000 pieces of HST-24030SXR product model to be tested for electrical properties were taken and the following comparative tests were conducted: (1) First, try using model A for 100% testing, record the yield rate, manually retest defective products, and record the equipment's misjudgment rate.

[0026] (2). After (1) is confirmed, all products are tested on the B model (good products and defective products together), and then the operation is carried out according to the requirements of (1), and the comparison data is recorded.

[0027] Experimental conclusion: Based on the data above, the following conclusions can be drawn: 1. The yield rate of model B is 7.64% higher than that of model A. 2. The false positive rate of model B is 64.99% lower than that of model A. 3. Continue to increase the quantity to verify the stability of the yield rate of Model B, accumulating up to 200K data.

[0028] Conclusion of the second experiment: Final conclusion: 1. Based on the data from 200K, the machine yield rate is around 96% on average.

[0029] 2. The false positive rate of the test can be controlled at around 19.5%.

[0030] 3. All subsequent new models will adopt the B mechanism design scheme.

[0031] 4. The overall yield rate is declining, while the misjudgment rate is rising. This is normal. The probe has a lifespan of 200,000 uses and needs to be replaced.

[0032] Based on the above, the advantages of this invention are: This invention employs a built-in scanning box, resulting in an extremely short ribbon cable connected to the scanning box. Compared to existing external scanning boxes that use long ribbon cables, this significantly reduces the parasitic inductance of the ribbon cable. During dynamic and high-frequency parameter testing of chips, no additional induced impedance is generated, and the instantaneous current response of the chip test circuit is not hindered, eliminating undesirable phenomena such as signal phase shift and amplitude attenuation. Furthermore, the distributed capacitance between the ribbon cable lines is greatly reduced, eliminating signal coupling and charge accumulation between the cable cores and avoiding signal crosstalk and noise interference. Especially for precision small-signal testing scenarios, interference errors introduced by the ribbon cable itself can be greatly suppressed. The dynamic and high-frequency parameters acquired by the device can accurately reproduce the chip's original electrical performance, and the test data is not subject to additional contamination from the wiring structure.

[0033] Significantly reducing the cable length shortens the overall electrical transmission loop, completely eliminating DC test deviation and zero-point drift issues. Firstly, the reduced cable length shortens the overall transmission path of the test electrical circuit, significantly lowering the inherent resistance of the cable itself. It also reduces various connection nodes such as terminals and plugs, lowering the total cumulative contact resistance and mitigating loop resistance fluctuations caused by factors such as assembly tolerances, metal oxidation, contact pressure, and changes in ambient temperature and humidity. Secondly, when testing DC parameters such as chip DC resistance and static power consumption, there are no fixed deviations or random errors caused by additional series resistance, greatly improving the accuracy of DC parameter testing. Thirdly, the test loop resistance remains stable over a long period, ensuring a unified electrical reference zero point for the test system. Zero-point drift does not occur during each power-on and batch test, significantly improving test repeatability. This allows for accurate identification of minute resistance defects and static electrical anomalies in chips, effectively avoiding production inspection problems such as misjudging good products and missing defective products.

[0034] The extremely short cabling layout ensures the common-mode symmetry of the differential transmission loop, enabling accurate detection of longitudinal balance indicators such as LCL longitudinal conversion loss and BL balance loss. LCL longitudinal conversion loss and BL balance loss are core indicators for evaluating the signal transmission balance and anti-interference capabilities of high-end chips. The accuracy of these tests depends entirely on the matching degree of impedance and parasitic parameters between the positive and negative differential signal channels. With the extremely short cabling structure of this invention, problems such as trace offset, bending differences, and uneven core spacing that disrupt loop symmetry are essentially eliminated. The parasitic inductance, distributed capacitance, and loop resistance of the positive and negative signal transmission paths can achieve a high degree of matching, completely preserving the common-mode symmetry characteristics of the test loop itself. During testing, there will be no mode conversion error from abnormal conversion of the common-mode signal to the interfering differential-mode signal, and no additional invalid interference components will be superimposed on the test signal. Interference errors caused by the wiring structure can be eliminated without complex calibration and parameter compensation operations, accurately measuring the chip's true longitudinal electrical balance characteristics. This meets the stringent factory testing and acceptance standards for high-speed signal chips, high-precision analog chips, and various high-end precision chips.

[0035] Building upon this foundation, the present invention simultaneously addresses three types of systematic test errors: parasitic parameter interference, DC test errors, and transmission loop asymmetry. This effectively improves the overall testing reliability and batch testing consistency, broadening the equipment's adaptability in the field of high-end precision chip testing. On one hand, the accuracy of testing various electrical parameters of a single chip is significantly improved, and various test errors derived from wiring are uniformly eliminated. On the other hand, the dispersion of test data between chips from the same batch and different production batches is greatly reduced, significantly optimizing batch testing consistency. The overall testing stability and reliability are comprehensively enhanced, breaking through the performance bottleneck of traditional chip testing equipment limited by long cabling structures. It can be widely adapted to various high-end precision chip testing scenarios, effectively expanding the application scope of this equipment.

[0036] As a preferred embodiment of the present invention, such as Figure 2As shown, an assembly slot 4 is provided on one side of the main body 1, and the scanning box is placed in the assembly slot 4. After the scanning box is embedded in the assembly slot 4, the horizontal and vertical distance between it and the chip testing station above is minimized, which can precisely define the installation position of the scanning box and further reduce the length of the connecting cable between the scanning box and the test host and the test station, so that the structural advantage of the extremely short cable can be fully realized. Compared with the traditional solution of externally suspending the scanning box and placing it at a long distance, the limiting structure of this assembly slot 4 completely avoids the situation where the cable is forced to be lengthened due to the offset of the scanning box installation position or its distance from the test station. It minimizes the parasitic inductance, distributed capacitance and additional loop resistance introduced by the cable, continuously weakens test interference such as high-frequency signal crosstalk, DC resistance test deviation and differential circuit asymmetry, and consolidates the equipment's high-precision detection capability of chip dynamic parameters, DC static parameters and longitudinal balance indicators, ensuring the accuracy of batch test data from the installation structure level.

[0037] Assembly slot 4 is an independent, open-type storage station reserved for the main body 1. Without the large-area obstruction of the upper testing mechanism, it allows direct access to and removal of the scanning box within the slot without the need for complete disassembly of the main body 1 frame or removal of precision transmission testing components such as the testing platform. This greatly simplifies the disassembly, repair, and replacement process of the scanning box. When the scanning box experiences signal abnormalities or aging / damaged internal components, maintenance personnel can independently disassemble and replace the scanning box, significantly reducing equipment downtime. Simultaneously, the repair process avoids touching or disturbing the precision positioning components of the upper testing platform, effectively mitigating the risk of test mechanism displacement and equipment accuracy deviation caused by disassembly operations, thus lowering the operational threshold and accuracy calibration costs for subsequent equipment maintenance.

[0038] The assembly slot 4, formed by the sheet metal of the main body 1, can form an integrated limiting and protective structure for the scanning box. On the one hand, it plays a simple electromagnetic shielding role, preventing external stray electromagnetic waves generated by workshop servo motors, frequency converters, and other surrounding test equipment from entering the signal circuit of the scanning box, reducing the superposition of external electromagnetic noise on the original test signal of the chip, and avoiding additional test errors. On the other hand, the assembly slot 4 can prevent workshop dust and condensation from directly adhering to the circuit board and terminals of the scanning box, delaying failure problems such as metal oxidation of the terminals and short circuits due to dust accumulation on the circuit board, extending the service life of the core components of the scanning box, and ensuring stable performance of the equipment under long-term continuous batch testing conditions.

[0039] As a preferred embodiment of the present invention, such as Figure 1As shown, the testing platform includes a tube feeding area 6, a pressure resistance testing area 8, a comprehensive testing area 9, and a tube receiving area 11 arranged sequentially at an inclined downward direction. A defective product receiving area 10 is provided on one side of the junction of the comprehensive testing area 9 and the tube receiving area 11. A linear slide is mounted on the machine body 1 at the position of the pressure resistance testing area 8 and the comprehensive testing area 9, which can reciprocate between the tube feeding area 6, the pressure resistance testing area 8, the comprehensive testing area 9, and the tube receiving area 11. Two pneumatic grippers are installed at intervals on the linear slide along the inclined direction of the testing platform.

[0040] This embodiment features a segmented test platform structure tilted downwards, relying on gravity for assisted material feeding. Simultaneously, the isolation of different testing zones eliminates electrical interference between different testing processes, providing dual protection for high-precision electrical testing of the chips. Firstly, the test platform's downward tilt allows the feed tube, placed within the tube-mounted feeding area 6, to extend naturally along the tilt angle. The chips under test within the tube adhere and automatically position themselves based on their own gravity, eliminating the need for additional independent pusher cylinders or top-loading mechanisms to continuously push materials, significantly simplifying the overall transmission structure. Reducing unnecessary power components effectively avoids problems such as chip positioning misalignment and probe contact issues caused by mechanical vibration, eliminating random fluctuations in test parameters due to vibration disturbances, and providing a stable physical basis for high-precision electrical testing. Secondly, the testing platform adopts an independent partition design, with the withstand voltage test area 8 and the comprehensive test area 9 separated. The high-voltage withstand voltage test and the weak small signal comprehensive test have their own independent workstations. The instantaneous pulses and electromagnetic noise generated by the high-voltage test will not directly interfere with the comprehensive test circuit. From a physical space perspective, the high-voltage noise is isolated from the pollution of chip dynamic parameters and high-frequency small signal test data. The two types of test processes do not interfere with each other, and can stably ensure the test accuracy of withstand voltage index and comprehensive electrical index respectively. Thirdly, the tube feeding, withstand voltage test, comprehensive test, and tube receiving are arranged serially and unidirectionally along the inclined direction. The chips strictly follow the standardized sequence of "material feeding - withstand voltage test - comprehensive performance test - good product storage". The material flow path is unique and the process logic is irreversible. There will be no material backflow or process skipping errors. This ensures that each chip under test completes the full set of electrical tests and completely avoids the risk of chip quality omission caused by missed test processes.

[0041] Setting the defective product receiving area 10 on the side connecting the comprehensive testing area 9 and the tube receiving area 11 ensures the integrity of the defective product sorting criteria while not interrupting the continuous receiving process of good products, thus balancing sorting accuracy and continuous equipment operation capability. On one hand, the sorting station is located after all electrical testing processes are completed. Defective products are only sorted after the chip has passed both the withstand voltage and comprehensive tests and is determined to be electrically abnormal. This prevents the situation where materials are sorted before all tests are completed, ensuring complete defective product judgment data. This reduces the probability of missorting good products and missing defective products from the source of the process, significantly improving sorting accuracy. On the other hand, the defective product receiving area 10 is arranged independently to the side next to the main conveyor channel, completely separated from the good product tube receiving channel. The pneumatic gripper's sorting of defective products will not occupy the main path for good products to be conveyed downwards and collected into the receiving tube. Good products can continuously enter the tube receiving area 11 along the inclined platform without interruption, without the need for equipment shutdown to switch material channels. This enables continuous batch chip testing and synchronous diversion of defective products, significantly reducing equipment downtime. At the same time, the side-arranged defective product receiving area 10 does not occupy the core inclined conveyor space of the testing platform, and there is no need to change the original overall layout of feeding, testing, and good product receiving, resulting in low structural modification costs. Operators can intuitively observe the status of defective product output, which facilitates real-time statistics of the number of defective products produced, and quickly provides feedback on the overall quality trend of the batch of chips, making it convenient for the production line to adjust upstream production processes in a timely manner.

[0042] The linear slide table, capable of covering reciprocating motion across all workstations, completes the entire material transfer process with a single motion module. This simplifies the overall machine transmission architecture, eliminates accumulated positioning errors from multiple modules, and improves alignment accuracy throughout the entire process. The motion stroke of a single linear slide table fully covers all core workstations: the tube feeding area (6), the pressure testing area (8), the comprehensive testing area (9), and the tube receiving area (11). This replaces the complex structure of traditional equipment with multiple independent handling modules, simplifying the overall mechanical transmission layout. The linear slide table uses linear transmission, ensuring high repeatability and positioning accuracy. It can precisely deliver chips to the standard testing points at each testing station, guaranteeing that the signal docking position of each chip with the test probe and the scanning box below is completely consistent during testing. This eliminates the problem of test data dispersion caused by positioning deviations and effectively improves the consistency of test data for chips in the same batch. The linear slide has reciprocating movement function. One set of motion mechanism can independently complete the entire process of chip handling, from picking up the chip from the feed tube, transferring it to the withstand voltage test station, transferring it to the comprehensive test station, transferring good products to the receiving tube, and transferring defective products to the defective product receiving area 10, which greatly reduces the hardware manufacturing cost of the equipment. At the same time, it eliminates the complex program logic of multi-module collaborative control, and significantly reduces the difficulty of debugging, troubleshooting and daily maintenance of the equipment control system.

[0043] In this embodiment, two pneumatic grippers are installed at intervals on a linear slide along the inclined direction of the testing platform. This enables parallel operation at two workstations, compressing the single-chip testing cycle and significantly increasing the overall batch testing capacity. Furthermore, the actions do not interfere with each other, resulting in enhanced stability during material handling. Firstly, the two sets of pneumatic grippers are spaced apart along the inclined direction of the platform. During a single movement of the linear slide, both sets of gripping operations can be performed simultaneously, achieving parallel operation at two workstations. For example, one set of pneumatic grippers grips a chip that has completed testing in the comprehensive testing area 9, preparing it for transfer and sorting. Simultaneously, the other set of pneumatic grippers grips a chip that has completed testing in the withstand voltage testing area 8, transferring it to the comprehensive workstation. The two sets of gripping actions do not interfere with each other. This parallel operation mode directly shortens the total cycle of complete testing of a single chip, effectively increasing the chip testing capacity per unit time. Secondly, the two pneumatic grippers are arranged separately along the inclined direction, and their respective gripping areas and movement paths are independent of each other. During the gripping and transfer of chips, there will be no material collision or material tube interference. At the same time, the two sets of pneumatic grippers can independently receive control signals and perform two differentiated actions: good product transfer and defective product sorting. The sorting and material transfer processes are carried out simultaneously, without waiting for a single pneumatic gripper to complete all its actions before starting the next process, further reducing the waiting time between processes.

[0044] As a preferred embodiment of the present invention, such as Figure 1 As shown, a first tube placement area 7 is provided on one side of the tube feeding area 6, where multiple first empty tubes are placed side by side. A second tube placement area 12 is provided on one side of the tube receiving area 11, where multiple second empty tubes are placed side by side. A feed tube is placed in the tube feeding area 6, extending along the inclined direction of the testing platform. Multiple products to be tested are sequentially placed inside the feed tube along its inclined direction. A receiving tube is placed in the tube receiving area 11, extending along the inclined direction of the testing platform. Multiple tested products are sequentially placed inside the receiving tube along its inclined direction.

[0045] In this embodiment, the feed tube extending along the inclined direction of the test platform carries the product under test. It can achieve autonomous and orderly chip arrangement based on the gravity of the inclined platform, simplifying the feeding mechanism and ensuring the accuracy of material handling and testing. The feed tube is arranged to fit the inclined angle of the test platform. The chips under test inside naturally adhere to the bottom of the tube body under their own gravity and are arranged in a single, orderly row along the inclined direction. There is no need to add additional active feeding mechanisms such as pusher cylinders, top sliders, or conveyor belts to push materials, significantly simplifying the transmission components at the feeding end of the machine and reducing continuous vibration interference from mechanical movement. This avoids the chip under test shifting at the workstation and poor contact with the test probe caused by vibration, eliminating random fluctuations in test parameters caused by vibration disturbance at the physical level, and providing a stable material positioning basis for withstand voltage and comprehensive high-precision electrical testing. A first tube placement area 7 is provided on the side of the tube-loaded feeding area 6, and the first tube placement area 7 can store multiple empty tubes side by side, enabling continuous material supply without equipment downtime and optimizing the manual tube preparation process. The first tube placement area 7 serves as a dedicated empty tube storage bin for the feeding station, capable of pre-storing multiple spare first empty tubes. Once all the chips to be tested inside the feeding tube have been removed by the pneumatic grippers, the operator can directly retrieve a spare empty tube from the nearest first tube placement area 7 to replace the empty feeding tube. Simultaneously, the tube fully loaded with the products to be tested is placed at the feeding station. The entire tube replacement and material replenishment operation does not require the entire machine to be stopped while waiting for material unpacking and empty tube sorting, effectively reducing equipment downtime and significantly increasing the continuous testing operation time, thereby reducing the production capacity loss of batch testing.

[0046] In this embodiment, a receiving tube extending along the inclined direction of the testing platform collects finished products after testing. Good products are stably collected by gravity, simultaneously achieving finished product protection and batch isolation control. The receiving tube extends downwards along the overall inclined direction of the testing platform. Good chips, after passing pressure resistance and a comprehensive set of tests, are placed into the receiving tube inlet by pneumatic grippers. They then slide smoothly down the tube under their own weight, stacking in an orderly single row. The entire process is free from violent impacts and collisions, effectively preventing physical damage such as chip pin bending, package scratches, and pin deformation, ensuring the integrity of the finished product's appearance after testing. A second tube placement area 12 is provided on the side of the tube receiving area 11. This second tube placement area 12 can store multiple empty tubes side-by-side, enabling rapid replacement of full tubes without downtime, ensuring uninterrupted continuous testing. The second tube placement area 12 serves as a dedicated storage area for spare empty tubes at the receiving station. It can pre-store multiple second empty tubes. When the receiving tube is filled with finished chips that have been tested, the operator can directly take out the spare empty tube from the second tube placement area 12 to replace the receiving tube that is full of finished products. The entire tube replacement operation will not interrupt the core processes of equipment feeding, withstand voltage testing, comprehensive testing, and defective product sorting. It completely eliminates the production capacity loss caused by the machine stopping to wait for tube replacement when the finished product tube is full, and supports the equipment to conduct batch chip testing for a long time, 24 hours a day.

[0047] As a preferred embodiment of the present invention, such as Figures 1-2As shown, the scanning box is located below the withstand voltage test area 8 and the comprehensive test area 9. A control console 2 and an operation screen 3 are mounted on the main body 1, and a power socket 5 is located on the lower back of the main body 1. In this embodiment, placing the scanning box directly below the withstand voltage test area 8 and the comprehensive test area 9 minimizes the signal transmission cabling between the scanning box and the two core test stations, eliminating various test interferences caused by traditional long cabling architectures at the source of electrical transmission, and stably ensuring the accuracy of the withstand voltage and comprehensive electrical performance tests. The withstand voltage test area 8 is used to complete the high-voltage withstand voltage test of the chip, while the comprehensive test area 9 is responsible for collecting weak signals such as high-frequency dynamic parameters, DC resistance, and longitudinal balance characteristics of the chip. The scanning box is directly positioned vertically below the two test stations, and the signal cable between them only needs to be extremely short to complete the connection, greatly reducing the parasitic inductance and inter-line distributed capacitance of the ribbon cable. On the one hand, under high-voltage withstand voltage test conditions, the short ribbon cable can reduce the transmission loss and waveform distortion of the high-voltage pulse signal, ensuring that the withstand voltage applied to the chip pin is accurate and controllable, and will not cause the actual test voltage to deviate from the set value due to impedance attenuation of long cables. On the other hand, during the testing of weak signals and high-frequency dynamic parameters of the chip, it effectively suppresses crosstalk noise caused by inter-line signal coupling and charge accumulation, eliminates signal phase shift and amplitude attenuation problems, and avoids the effective test signal being contaminated by wiring interference. The control console 2 and operation screen 3 are directly mounted on the main body 1 to realize the integrated human-machine interaction module, which greatly optimizes the operator's work experience in debugging, monitoring, and controlling the equipment, and simultaneously simplifies the overall control wiring and improves the synchronization of actions.

[0048] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A high-precision slope testing machine, characterized in that: It includes a test platform mounted on the machine body and extending downward at an angle, and a scanning box is installed inside the machine body and below the test platform.

2. The high-precision slope testing machine according to claim 1, characterized in that: An assembly slot is provided on one side of the machine body, and the scanning box is placed in the assembly slot.

3. The high-precision slope testing machine according to claim 1, characterized in that: The testing platform includes a tube feeding area, a pressure resistance testing area, a comprehensive testing area, and a tube receiving area arranged sequentially at an angle downwards. A defective product receiving area is provided on one side of the junction between the comprehensive testing area and the tube receiving area. A linear slide is mounted on the machine body at the position of the pressure resistance testing area and the comprehensive testing area, which can reciprocate between the tube feeding area, the pressure resistance testing area, the comprehensive testing area, and the tube receiving area. Two pneumatic grippers are installed at intervals on the linear slide along the tilt direction of the testing platform.

4. The high-precision slope testing machine according to claim 3, characterized in that: A first tube placement area is provided on one side of the tube feeding area, and multiple first empty tubes are placed side by side in the first tube placement area. A second tube placement area is provided on one side of the tube receiving area, and multiple second empty tubes are placed side by side in the second tube placement area.

5. A high-precision slope testing machine according to claim 3, characterized in that: A feed pipe is placed in the tubular feeding area. The feed pipe extends along the inclined direction of the test platform, and multiple products to be tested are placed sequentially inside the feed pipe along its inclined direction.

6. A high-precision slope testing machine according to claim 3, characterized in that: A receiving tube is placed in the tube receiving area. The receiving tube extends along the inclined direction of the test platform, and multiple tested products are placed sequentially inside the receiving tube along its inclined direction.

7. A high-precision slope testing machine according to claim 3, characterized in that: The scanning box is located below the pressure resistance test area and the comprehensive test area.

8. A high-precision slope testing machine according to claim 1, characterized in that: The machine body is equipped with a control console and an operation screen.

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