Wafer level quantum circuit element testing apparatus and testing method

Abstract

The application provides a wafer-level quantum circuit element testing device and testing method. The device can enable a superconducting quantum wafer to be loaded into a bearing substrate to realize testing of quantum circuit elements in an intact and uncut state, to realize wafer-level nondestructive evaluation, to facilitate reduction of consumption of low-temperature cooling resources and reduction of testing costs. The testing module is connected with the quantum circuit element through a connector and a resonant cavity, to ensure efficient coupling transmission of signals and to improve accuracy of testing parameters. The testing module obtains testing results through testing parameters of at least one quantum circuit element, to facilitate analysis and statistics of testing data of multiple quantum circuit elements of the entire wafer, and to further realize yield control of superconducting quantum chips.

Description

Technical Field

[0001] This application relates to the field of quantum chip testing technology, and in particular to wafer-level quantum circuit element testing devices and methods. Background Technology

[0002] Currently, the fabrication of superconducting quantum chips typically includes the following process flow: wafer processing, Josephson junction fabrication, chip dicing, chip packaging, and low-temperature testing.

[0003] The testing devices in related technologies can usually only be tested after the wafer is cut into superconducting quantum chips, and cannot obtain the relevant distribution information of quantum circuit elements on the entire wafer. At the same time, since multiple quantum circuit elements on the wafer need to be cooled frequently before testing, cooling resources are wasted and testing costs are high, which is not conducive to the statistical analysis of test data of multiple quantum circuit elements on the entire wafer. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a wafer-level quantum circuit element testing device and testing method.

[0005] In a first aspect, this application provides a wafer-level quantum circuit element testing device, including a carrier substrate, connectors, and a testing module. The carrier substrate has a front side and a back side disposed opposite to each other. A plurality of resonant cavities are formed on the front side of the carrier substrate. The front side of the carrier substrate is used to support a superconducting quantum wafer to be tested, and each quantum circuit element on the superconducting quantum wafer is disposed opposite to a corresponding resonant cavity. A plurality of connectors are installed through the carrier substrate in a one-to-one correspondence with the plurality of resonant cavities. Each connector passes through the carrier substrate from the front side and extends to the back side of the carrier substrate. The end of the connector located on the front side of the carrier substrate is at least partially located within the resonant cavity, so as to form microwave signal coupling with the corresponding quantum circuit element through the resonant cavity. The testing module is connected to the end of the plurality of connectors located on the back side of the carrier substrate, and is used to acquire test parameters of at least one quantum circuit element and output corresponding test results based on the test parameters.

[0006] In some embodiments, the plurality of resonant cavities are arranged in a first array on the front side of the carrier substrate, and the plurality of quantum circuit elements are arranged in a second array on the superconducting quantum wafer. The array size of the first array is greater than or equal to the array size of the second array, and the arrangement of the first array and the second array are matched.

[0007] In some embodiments, the resonant cavity includes a resonant cavity body and a coupling post, wherein the coupling post is disposed within the resonant cavity body and is used to couple with the corresponding quantum circuit element.

[0008] In some embodiments, the coupling post is located at the center of the resonant cavity body and extends along the thickness direction of the supporting substrate, and the coupling post and the sidewall of the resonant cavity body form a coaxial resonant structure.

[0009] In some embodiments, the quantum circuit element testing apparatus further includes an alignment module disposed on the front side of the carrier substrate and configured to surround the superconducting quantum wafer to limit the positional offset of the superconducting quantum wafer in the plane on the front side of the carrier substrate, thereby maintaining the relative arrangement of each quantum circuit element on the superconducting quantum wafer with its corresponding resonant cavity.

[0010] In some embodiments, the alignment module includes a plurality of alignment posts disposed in the peripheral region of a plurality of resonant cavities, and the limiting space formed by the plurality of alignment posts matches the size of the superconducting quantum wafer.

[0011] In some embodiments, the test module includes a plurality of signal processing units and a processor. Each signal processing unit is connected to one end of a corresponding connector located on the back side of the carrier substrate. The processor is connected to the plurality of signal processing units respectively. The processor is used to acquire the test parameters of at least one of the quantum circuit elements.

[0012] In some embodiments, the quantum circuit element includes at least one of a quantum bit, a coupler, a readout resonator, and a filter.

[0013] Secondly, this application provides a quantum circuit element testing method, applied to the quantum circuit element testing device described above. The method includes: acquiring a superconducting quantum wafer to be tested, on which a plurality of quantum circuit elements are formed; placing the superconducting quantum wafer on the front side of a carrier substrate, wherein a plurality of resonant cavities are formed on the front side of the carrier substrate, and a connector is installed through each of the resonant cavities, and each quantum circuit element on the superconducting quantum wafer is positioned opposite to the corresponding resonant cavity; sending a microwave detection signal to the corresponding quantum circuit element through the connector, and receiving a microwave response signal returned by the quantum circuit element in response to the microwave detection signal through the connector; acquiring test parameters of the corresponding quantum circuit element based on the microwave response signal, and outputting a corresponding test result based on the test parameters.

[0014] In some embodiments, the step of outputting the corresponding test result according to the test parameters includes: obtaining test parameters of at least one of the quantum circuit elements and judging the test parameters; when the test parameters meet a first preset condition, marking the corresponding quantum circuit element as a first-level element; when the test parameters meet a second preset condition, marking the corresponding quantum circuit element as a second-level element.

[0015] In some embodiments, the step of outputting the corresponding test results according to the test parameters includes: determining the grade information of each quantum circuit element according to the test parameters of each quantum circuit element; and generating a sorting map of the superconducting quantum wafer according to the grade information of each quantum circuit element, wherein the sorting map is used to indicate the grade distribution of each quantum circuit element on the superconducting quantum wafer.

[0016] In some embodiments, the method further includes: testing the superconducting quantum wafer at multiple predetermined process nodes to obtain test parameter sets corresponding to each predetermined process node, wherein each test parameter set includes multiple test parameters; establishing a correspondence between the performance parameters of the quantum circuit element and the predetermined process node based on the test parameter sets corresponding to each predetermined process node; and outputting process quality evaluation results for each predetermined process node based on the correspondence.

[0017] In some embodiments, testing the superconducting quantum wafer at multiple predetermined process nodes to obtain test parameter sets corresponding to each predetermined process node includes: testing the superconducting quantum wafer at a first predetermined process node to obtain a first test parameter set; testing the superconducting quantum wafer at a second predetermined process node to obtain a second test parameter set; and calculating the change in each test parameter based on the first test parameter set and the second test parameter set, wherein the change is used to characterize the impact of process steps between the first and second predetermined process nodes on the performance of the quantum circuit element.

[0018] In some embodiments, the predetermined process node includes at least one of the Josephson junction fabrication process node, deep silicon etching process node, TSV fabrication process node, and three-dimensional packaging process node.

[0019] In some embodiments, after outputting the process quality evaluation results of each predetermined process node according to the correspondence, the method further includes: comparing the change amount of each test parameter with the standard change amount of the predetermined process node; when the change amount exceeds the preset range of the standard change amount, outputting a prompt message indicating that the corresponding predetermined process node has a process abnormality.

[0020] In some embodiments, after outputting a prompt message indicating a process anomaly at the corresponding predetermined process node, the method further includes: obtaining process parameters of the predetermined process node corresponding to the process anomaly; adjusting the process parameters of the predetermined process node according to the prompt message and the process parameters; testing the superconducting quantum wafer at the adjusted predetermined process node to obtain verification test parameters; and confirming the effectiveness of the process adjustment of the predetermined process node when the verification test parameters meet preset verification conditions.

[0021] In some embodiments, the test parameters include at least one of spectrum test parameters, relaxation time parameters, decoherence time parameters, and readout test parameters.

[0022] In some embodiments, multiple quantum circuit elements are arranged in an array on the superconducting quantum wafer, and the test results include a two-dimensional distribution map. The step of outputting the corresponding test results based on the test parameters includes: establishing a wafer coordinate system based on the arrangement positions of the quantum circuit elements on the superconducting quantum wafer; determining the parameter values ​​of each quantum circuit element based on the test parameters of each quantum circuit element; and generating a two-dimensional distribution map of the superconducting quantum wafer based on the parameter values ​​of each quantum circuit element and the position coordinates of the quantum circuit elements in the wafer coordinate system. The two-dimensional distribution map is used to characterize the spatial distribution of each parameter value on the superconducting quantum wafer.

[0023] In some embodiments, the parameter values ​​include at least one of the following: quantum bit frequency value, energy relaxation time value, decoherence time value, or JJ resistance value; and the two-dimensional distribution map includes at least one of the following: frequency map, T1 map, decoherence time map, or JJ resistance map.

[0024] This application provides a wafer-level quantum circuit element testing device and method. The device includes a carrier substrate, connectors, and a testing module. The carrier substrate has a front and a back side arranged opposite to each other. The front side of the carrier substrate has multiple resonant cavities and is used to support the superconducting quantum wafer to be tested, with each quantum circuit element on the superconducting quantum wafer arranged opposite to a corresponding resonant cavity. Multiple connectors are installed through the carrier substrate, corresponding one-to-one with the multiple resonant cavities. Each connector passes through the carrier substrate from the front side and extends to the back side of the carrier substrate. The end of the connector on the front side of the carrier substrate is at least partially located within the resonant cavity to form microwave signal coupling with the corresponding quantum circuit element through the resonant cavity. The testing module is connected to the end of the multiple connectors on the back side of the carrier substrate and is used to acquire test parameters of at least one quantum circuit element and output corresponding test results based on the test parameters.

[0025] Based on the above structure, this application has at least the following beneficial effects: 1) Achieving wafer-level non-destructive evaluation and reducing testing costs: By directly mounting superconducting quantum wafers onto a substrate with resonant cavity arrays, performance testing of all quantum circuit elements on the wafer can be completed without dicing the wafer into individual chips. This avoids the potential impact of dicing processes on chip performance and achieves wafer-level non-destructive evaluation. Furthermore, batch testing of the entire wafer can be completed in a single mounting operation, effectively reducing the consumption of cryogenic cooling resources and significantly lowering testing costs.

[0026] 2) Ensuring efficient microwave signal transmission and improving test accuracy: Through a one-to-one through-mounting of connectors and resonant cavities, with the connector tips extending into the resonant cavity, a direct microwave signal coupling path is formed between the quantum circuit elements and the test module. This structure avoids the contact resistance and signal reflection loss introduced by multiple probe contacts in traditional testing methods involving bonding individual components after wafer dicing. It ensures efficient and low-loss microwave signal transmission, thereby significantly improving the accuracy of test parameters and the reliability of test results.

[0027] 3) Supports wafer-level data analysis for yield control: The testing module can acquire test parameters of multiple quantum circuit elements on the wafer and perform statistical analysis on the test data of the entire wafer. This allows for rapid identification of performance anomalies at the wafer level, precise location of process defects, and guidance for process optimization. Simultaneously, based on the test parameters of each element, a sorting map containing grade distribution information can be generated, directly guiding the subsequent slicing process route and preventing low-grade chips from entering the packaging stage. This forms a complete yield control closed loop from testing to packaging, providing reliable data support for the mass production of superconducting quantum chips.

[0028] In summary, this application solves the technical problems of low testing efficiency, high cost, poor signal quality, and inability to achieve wafer-level yield control caused by the need for individual testing after dicing in the prior art. It has significant application value and industrial promotion prospects in the field of quantum chip testing. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the quantum circuit element testing device provided in this application; Figure 2 This application is Figure 1 A schematic diagram of the structure of an embodiment of the carrier substrate; Figure 3This is a schematic diagram of the structure of an embodiment of the superconducting quantum wafer provided in this application; Figure 4 This is a schematic diagram of the structure of the second embodiment of the quantum circuit element testing device provided in this application; Figure 5 This application is Figure 2 A schematic diagram of the structure of an embodiment of the resonant cavity; Figure 6 This application is Figure 1 A schematic diagram of the side view of the quantum circuit element testing device; Figure 7 This application is Figure 1 A schematic diagram of the bottom structure of a quantum circuit element testing device; Figure 8 This is a schematic flowchart of an embodiment of the quantum circuit element testing method provided in this application; Figure 9 This application is Figure 8 A flowchart illustrating the first embodiment of outputting test results; Figure 10 This is a flowchart illustrating the second embodiment of the quantum circuit element testing method of this application; Figure 11 This application is Figure 10 A flowchart illustrating an embodiment of obtaining a test parameter set; Figure 12 This is a flowchart illustrating the third embodiment of the quantum circuit element testing method of this application; Figure 13 This application is Figure 12 A flowchart illustrating an embodiment of outputting prompt information; Figure 14 This application is Figure 8 A flowchart illustrating the second embodiment for outputting test results.

[0030] In the figure, 10 is the quantum circuit element testing device; 11 is the carrier substrate; 111 is the resonant cavity; 1111 is the resonant cavity body; 1112 is the coupling pillar; 12 is the superconducting quantum wafer; 121 is the quantum circuit element; 13 is the connector; 14 is the testing module; 141 is the signal processing unit; 142 is the processor; 15 is the alignment module; and 151 is the alignment pillar. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0032] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0033] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0034] This application first provides a wafer-level quantum circuit element testing device, which is used to perform wafer-level testing on multiple quantum circuit elements on an uncut superconducting quantum wafer. The testing items include at least one of spectrum testing, relaxation time testing, decoherence time testing, and readout testing.

[0035] In some embodiments, see Figures 1-3 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the quantum circuit element testing device provided in this application. Figure 2 This application is Figure 1 A schematic diagram of the structure of one embodiment of the carrier substrate. Figure 3 This is a schematic diagram of the structure of an embodiment of the superconducting quantum wafer provided in this application. Figure 4 This is a schematic diagram of the second embodiment of the quantum circuit element testing device provided in this application. Figures 1-4 As shown, the quantum circuit element testing device 10 of this embodiment includes a carrier substrate 11, a connector 13, and a testing module 14.

[0036] The carrier substrate 11 has a front and a back side arranged opposite to each other. Multiple resonant cavities 111 are formed on the front side of the carrier substrate 11. The front side of the carrier substrate 11 also supports the superconducting quantum wafer 12 to be tested, and each quantum circuit element 121 on the superconducting quantum wafer 12 is arranged opposite to a corresponding resonant cavity 111. Multiple connectors 13 are installed through the carrier substrate 11, corresponding one-to-one with the multiple resonant cavities 111. Each connector 13 extends from the front side of the carrier substrate 11 through the carrier substrate 11 to the back side of the carrier substrate 11. The end of the connector 13 located on the front side of the carrier substrate 11 is at least partially located within the resonant cavity 111, so as to form microwave signal coupling with the corresponding quantum circuit element 121 through the resonant cavity 111. The test module 14 is connected to the end of the multiple connectors 13 located on the back side of the carrier substrate 11, and is used to acquire the test parameters of at least one quantum circuit element 121, and output the corresponding test results based on the test parameters.

[0037] The superconducting quantum wafer 12 includes a wafer substrate and a superconducting material layer disposed on the wafer substrate. Quantum circuit elements 121, such as qubits, readout resonators, and couplers, are formed on the superconducting material layer. A carrier substrate 11 has a front and a back side disposed opposite to each other, with the front side used to support the superconducting quantum wafer 12. Multiple resonant cavities 111 are processed and formed on the front side of the carrier substrate 11. Each resonant cavity 111 is a three-dimensional resonator. The number and layout of the resonant cavities 111 match the number and position of the quantum circuit elements 121 on the superconducting quantum wafer 12, such that when the superconducting quantum wafer 12 is placed on a predetermined area of ​​the carrier substrate 11, each quantum circuit element 121 is positioned opposite to a corresponding resonant cavity 111.

[0038] Connector 13 is used to realize microwave signal transmission of quantum circuit element 121. Multiple connectors 13 correspond one-to-one with multiple resonant cavities 111. Connector 13 extends from the front of the carrier substrate 11 through the carrier substrate 11 to the back. One end of connector 13 is located within the resonant cavity 111 on the front of the carrier substrate 11 to form microwave signal coupling with the corresponding quantum circuit element 121 through the resonant cavity 111; the other end of connector 13 extends out from the back of the carrier substrate 11 to connect to test module 14. Connector 13 may be, but is not limited to, at least one of the following connectors: Sub-Miniature version A (SMA), Sub-Miniature Push-on (SMP), and Super Miniature Push-on (SSMP).

[0039] The test module 14 is connected to one end of a plurality of connectors 13 located on the back side of the carrier substrate 11. In one possible embodiment, the test module 14 is used to send a microwave detection signal to the quantum circuit element 121 through the connectors 13, and to acquire the microwave response signal output by the quantum circuit element 121 in response to the microwave detection signal through the connectors 13, so as to obtain test parameters of at least one quantum circuit element 121 based on the microwave response signal. In another possible embodiment, the test module 14 is used to directly acquire the microwave response signal output by the quantum circuit element 121 through the connectors 13, so as to obtain test parameters based on the microwave response signal. The test module 14 is also used to analyze the performance parameters of the quantum circuit element 121 based on the received test parameters, so as to output the corresponding test results. The test results include the test results of at least one quantum circuit element 121 or the test results of the entire superconducting quantum wafer 12.

[0040] It should be understood that the aforementioned "direct acquisition" refers to the test module 14 not sending microwave detection signals to the quantum circuit element 121, but only acquiring the microwave response signals spontaneously emitted or reflected by the quantum circuit element 121 after being excited to a predetermined state by an external manipulation signal. This direct acquisition mode is suitable for scenarios such as energy relaxation time T1 measurement and decoherence time T2 measurement; the active detection mode is suitable for scenarios such as spectrum testing and transmission characteristic testing.

[0041] Therefore, the quantum circuit element testing device 10 of this embodiment allows the superconducting quantum wafer 12 to be directly mounted on the carrier substrate 11 in a complete and uncut state for wafer-level testing of the quantum circuit element 121, thereby achieving non-destructive evaluation at the wafer level. Compared with the traditional chip-by-chip dicing testing scheme, there is no need to perform a dicing process before testing, reducing the wafer processing steps, and multiple quantum circuit elements 121 can be tested simultaneously, which helps to reduce the consumption of cryogenic cooling resources and lower testing costs; the testing module 14 forms a signal path with the quantum circuit element 121 through the connector 13 and the resonant cavity 111, with one end of the connector 13 extending directly into the resonant cavity 111, enabling micro- The microwave signal does not require additional conversion or contact links in the transmission path, avoiding contact resistance and signal reflection loss introduced by multiple probe contacts, ensuring efficient and low-loss transmission of microwave signals, and improving the accuracy of test parameters and the reliability of test results. The test module 14 acquires the test parameters of multiple quantum circuit elements 121 on the superconducting quantum wafer 12, and can perform statistical analysis and anomaly identification on the performance data of each quantum circuit element 121 at the wafer level. Based on the analysis results, it generates the grade information of each quantum circuit element 121 and the wafer-level sorting map, providing data support for subsequent slicing process and yield control, thereby realizing closed-loop yield management from the testing end to the packaging end.

[0042] In some embodiments, such as Figure 2and Figure 3 As shown, multiple resonant cavities 111 are arranged in a first array on the front side of the substrate 11, and multiple quantum circuit elements 121 are arranged in a second array on the superconducting quantum wafer 12. The array size of the first array is greater than or equal to the array size of the second array, and the arrangement of the first array and the second array are matched.

[0043] The first array arrangement refers to the regular arrangement of multiple resonant cavities 111 on the front side of the carrier substrate 11. The arrangement of the first array is defined by the relative position, spacing, and overall topology (arrangement rule) of each resonant cavity 111 on the carrier substrate 11. The second array arrangement refers to the regular arrangement of multiple quantum circuit elements 121 on the surface of the superconducting quantum wafer 12. The arrangement of the second array is defined by the relative position, spacing, and overall topology (arrangement rule) of each quantum circuit element 121 on the superconducting quantum wafer 12. The arrangement of the first array and the arrangement of the second array are matched, that is, the spacing of the first array and the second array in the row direction and column direction are the same or in an integer multiple relationship, and their topology (arrangement rule) is compatible, so that the arrangement of the second array can be compatible with the arrangement of the first array. Therefore, when the superconducting quantum wafer 12 is placed on the predetermined area on the front side of the carrier substrate 11, each resonant cavity 111 is precisely aligned with a specific quantum circuit element 121 in a direction perpendicular to the carrier substrate 11. That is, the projection of each quantum circuit element 121 on the plane on the front side of the carrier substrate 11 is located in the position area of ​​the corresponding resonant cavity 111, thereby realizing microwave signal coupling between the quantum circuit element 121 and the corresponding resonant cavity 111, which is beneficial to ensuring the coupling accuracy between the resonant cavity 111 and the quantum circuit element 121.

[0044] It is understood that when the spacing between the first array and the second array in the row and column directions is the same, the quantum circuit elements 121 on the superconducting quantum wafer 12 are arranged in a one-to-one correspondence with at least a portion of the resonant cavities 111 on the carrier substrate 11, and there are no idle resonant cavities 111 between two adjacent quantum circuit elements 121; when the spacing between the first array and the second array in the row and column directions is an integer multiple, the quantum circuit elements 121 on the superconducting quantum wafer 12 are arranged in a one-to-one correspondence with a portion of the resonant cavities 111 on the carrier substrate 11, and there is at least one resonant cavity 111 between two adjacent quantum circuit elements 121.

[0045] Furthermore, the array size of the first array is greater than or equal to the array size of the second array. That is, the number of resonant cavities 111 in the first array is greater than or equal to the number of quantum circuit elements 121 in the second array; and / or, the coverage area of ​​the first array on the front side of the carrier substrate 11 is greater than or equal to the coverage area of ​​the second array on the superconducting quantum wafer 12. This ensures that the multiple resonant cavities 111 on the carrier substrate 11 can cover all the quantum circuit elements 121 on the superconducting quantum wafer 12, thereby enabling full-wafer-scale quantum circuit element testing. In possible implementations, both the first and second array arrangements can be rectangular arrays, rhomboid arrays, or other polygonal arrays. In one example, the first and second array arrangements can be presented as an N×M matrix, where N and M are positive integers; for example, the first and second array arrangements can be in the form of 8×9, 4×5, 9×10, 10×12, etc. In another example, the first and second array arrangements can be presented as an N×N matrix, where N is a positive integer; for example, the first and second array arrangements can be presented as arrays of 8×8, 10×10, or 12×12, etc.

[0046] In some embodiments, the first array and the second array are completely identical. Specifically, from the perspective of array spacing, the row spacing of the first array is equal to the row spacing of the second array, and the column spacing of the first array is equal to the column spacing of the second array, so that the first array and the second array have the same arrangement period and arrangement rules. From the perspective of array quantity, the number of resonant cavities 111 in the first array is equal to the number of quantum circuit elements 121 in the second array. Thus, when the superconducting quantum wafer 12 is placed on the front side of the carrier substrate 11, the first array and the second array are completely overlapped and aligned in space, and each quantum circuit element 121 on the superconducting quantum wafer 12 is correspondingly arranged opposite to each resonant cavity 111 on the carrier substrate 11.

[0047] In some embodiments, the first array and the second array have equal spacing but different array sizes. Specifically: in terms of spacing, the row spacing of the first array is equal to the row spacing of the second array, and the column spacing of the first array is equal to the column spacing of the second array, so that the first array and the second array have the same arrangement period and arrangement rules; in terms of quantity, the number of resonant cavities 111 in the first array is greater than the number of quantum circuit elements 121 in the second array. For example, the first array is a 4×4 array, and the second array is a 2×2 array, both with the same row spacing and column spacing, and both are rectangular arrays, with the second array being a subset of the first array. At this time, each quantum circuit element 121 on the superconducting quantum wafer 12 is correspondingly arranged opposite to a portion of the resonant cavities 111 on the carrier substrate 11, while the remaining uncorresponding resonant cavities 111 on the carrier substrate 11 are in an idle state.

[0048] In some embodiments, the spacing and size of the first array and the second array are unequal. Specifically: in terms of spacing, the row spacing of the first array is proportional to the row spacing of the second array by 1 / N, where N is a positive integer greater than 1 (e.g., the row spacing ratio is 1:2, 1:3, or 1:5, etc.), and / or, the column spacing of the first array is proportional to the column spacing of the second array, making the first array and the second array geometrically similar; in terms of quantity, the number of resonant cavities 111 in the first array is greater than the number of quantum circuit elements 121 in the second array. At this time, each quantum circuit element 121 on the superconducting quantum wafer 12 is correspondingly arranged with a portion of the resonant cavities 111 on the carrier substrate 11, while the remaining uncorresponding resonant cavities 111 on the carrier substrate 11 are in an idle state.

[0049] In possible implementations, the arrangement of the resonant cavity 111 on the carrier substrate 11 can be achieved, but is not limited to, by micromachining, etching, or 3D printing on the front side of the carrier substrate 11. The arrangement of the quantum circuit elements 121 on the superconducting quantum wafer 12 can be formed, but is not limited to, by semiconductor processes such as photolithography, vapor deposition, or etching.

[0050] In some embodiments, see Figure 5 , Figure 5 This application is Figure 2 A schematic diagram of one embodiment of the resonant cavity 111 is shown. Figure 5 As shown, the resonant cavity 111 includes a resonant cavity body 1111 and a coupling post 1112. The coupling post 1112 is disposed inside the resonant cavity body 1111 and is used to couple with the corresponding quantum circuit element 121.

[0051] The resonant cavity body 1111 is used to form a microwave resonant space. The resonant cavity body 1111 can be fabricated from superconducting material to form a semi-enclosed cavity shape. A coupling post 1112 is disposed inside the resonant cavity body 1111, with one end of the coupling post 1112 located inside the resonant cavity body 1111 and the other end of the coupling post 1112 extending towards the superconducting quantum wafer 12 for coupling with the corresponding quantum circuit element 121.

[0052] In a possible implementation, the resonant cavity body 1111 and the coupling pillar 1112 are integrally formed. For example, the carrier substrate 11 is made of a superconducting material, and the integrally formed resonant cavity body 1111 and coupling pillar 1112 are formed by processing the front side of the carrier substrate 11. Alternatively, the resonant cavity body 1111 and the coupling pillar 1112 can also be assembled after separate processing to form the resonant cavity 111.

[0053] In other implementations, by adjusting the position and dimensions (including height and diameter) of the coupling post 1112, the coupling coefficient between the coupling post 1112 and the quantum circuit element 121 can be adjusted, optimizing the coupling efficiency at different frequencies, thereby ensuring accurate reading of the test signal and adapting to the testing requirements of different frequencies. Specifically, the electromagnetic field distribution within the resonant cavity 111 is non-uniform, with varying electric and magnetic field strengths at different locations. The electromagnetic field strength of the coupling post 1112 varies with its location. Changing the position of the coupling post 1112 alters the degree of electromagnetic field overlap between it and the quantum circuit element 121, thus changing the coupling coefficient. Changing the distance and coupling area between the coupling post 1112 and the quantum circuit element 121 directly changes the magnitude of capacitive coupling, thereby changing the coupling coefficient. For example, a higher height and a larger diameter result in a larger capacitive coupling area and a larger coupling coefficient.

[0054] For example, for a higher frequency quantum circuit element 121, the coupling post 1112 can be configured with a shorter height or placed at a position away from the center of the resonant cavity body 1111 to reduce the coupling capacitance and reduce the coupling strength; for a lower frequency quantum circuit element 121, the coupling post 1112 can be configured with a longer height or placed at a position close to the center of the resonant cavity body 1111 to enhance the coupling strength.

[0055] In some embodiments, the coupling post 1112 is located at the center of the resonant cavity body 1111 and extends along the thickness direction of the supporting substrate 11, and the coupling post 1112 and the sidewall of the resonant cavity body 1111 form a coaxial resonant structure.

[0056] The coupling post 1112 is located at the center of the resonant cavity body 1111 and extends along the thickness direction of the supporting substrate 11, such that the axis of the coupling post 1112 coincides with or substantially coincides with the central axis of the resonant cavity body 1111. This creates a coaxial resonant structure between the outer surface of the coupling post 1112 and the inner surface of the sidewall of the resonant cavity body 1111. In other words, a coaxial transmission line or coaxial resonator is formed between the coupling post 1112 and the sidewall of the resonant cavity body 1111. This coaxial resonant structure significantly reduces electromagnetic energy radiation loss and external interference. Simultaneously, this coaxial resonant structure has good symmetry, which is beneficial for achieving a uniform and stable electromagnetic field distribution. This makes the coupling between the quantum circuit element 121 and the resonant cavity 111 more linear and controllable, which is beneficial for improving the signal-to-noise ratio and measurement accuracy of the test signal, thereby achieving high-precision wafer-level testing.

[0057] In some embodiments, see Figure 6 , Figure 6 This application is Figure 1 A side view of the quantum circuit element testing device. (See diagram below.) Figure 1 and Figure 6 As shown, the quantum circuit element testing device 10 also includes an alignment module 15, which is disposed on the front side of the carrier substrate 11 and is used to surround the superconducting quantum wafer 12 to limit the positional offset of the superconducting quantum wafer 12 in the plane on the front side of the carrier substrate 11, thereby maintaining the relative arrangement of each quantum circuit element 121 on the superconducting quantum wafer 12 with the corresponding resonant cavity 111.

[0058] The alignment module 15 is used to align the superconducting quantum wafer 12 with the array of resonant cavities 111 on the carrier substrate 11. The alignment module 15 can be disposed on the front side of the carrier substrate 11 and located on the periphery of the superconducting quantum wafer 12, in a region directly in contact with or adjacent to the superconducting quantum wafer 12. The alignment module 15 is used to surround the superconducting quantum wafer 12 to limit the positional displacement of the superconducting quantum wafer 12 within the plane of the front side of the carrier substrate 11, thereby limiting the superconducting quantum wafer 12 and maintaining the relative arrangement of each quantum circuit element 121 on the superconducting quantum wafer 12 with its corresponding resonant cavity 111, ensuring positional stability between the quantum circuit element 121 and the resonant cavity 111 during testing.

[0059] In possible implementations, the alignment module 15 includes at least one of the following limiting structures: mechanical limiting block, positioning pin, groove edge limiting, magnetic adsorption limiting, etc., for restricting the movement of the superconducting quantum wafer 12. In a first example, the alignment module 15 includes a limiting frame disposed on the front side of the support substrate 11, the inner diameter of which is slightly larger than the diameter of the superconducting quantum wafer 12, thereby confining the superconducting quantum wafer 12 within the limiting frame. In a second example, the alignment module 15 includes a plurality of alignment posts 151 distributed on the front side of the support substrate 11, the alignment posts 151 being used to cooperate with edge markings of the superconducting quantum wafer 12 to achieve precise positioning and alignment. In a third example, the alignment module 15 includes an optical alignment structure, which can be an optical window or marking point disposed on the front side of the support substrate 11 by emitting light, to cooperate with the vision module to achieve positional alignment of the superconducting quantum wafer 12.

[0060] Therefore, by setting the alignment module 15 around the superconducting quantum wafer 12, the superconducting quantum wafer 12 is confined within the preset area defined by the alignment module 15 during the testing process. This helps improve the alignment accuracy between the quantum circuit elements 121 on the superconducting quantum wafer 12 and the resonant cavity 111, thereby ensuring the coupling efficiency of the test signal and the accuracy of the test results. In addition to its limiting function, the alignment module 15 also functions as an alignment marker. Through the alignment markers provided by the alignment module 15, the relative positioning of each quantum circuit element 121 on the superconducting quantum wafer 12 and its corresponding resonant cavity 111 can be achieved quickly and with high precision, maintaining high-precision alignment between them during the testing process. This helps reduce test failures caused by positional deviations, improves testing efficiency, and reduces testing costs.

[0061] In some embodiments, such as Figure 1 and Figure 6 As shown, the alignment module 15 includes multiple alignment posts 151, which are disposed in the peripheral region of multiple resonant cavities 111 and distributed around the preset position of the superconducting quantum wafer 12. The multiple alignment posts 151 together enclose a limiting space, the outline of which is adapted to the outer outline of the superconducting quantum wafer 12 to confine the superconducting quantum wafer 12 within the limiting space.

[0062] In this configuration, the alignment module 15 comprises multiple alignment posts 151 disposed in the peripheral region of the multiple resonant cavities 111. The size of the confinement space formed by the multiple alignment posts 151 matches the actual size of the superconducting quantum wafer 12, that is, the inner contour of the confinement space matches the outer contour of the superconducting quantum wafer 12. For example, the confinement space formed by the multiple alignment posts 151 is polygonal or circular, with its inscribed circle diameter slightly larger than or equal to the diameter of the superconducting quantum wafer 12, so that the superconducting quantum wafer 12 can be stably placed within the confinement space formed by the multiple alignment posts 151 and confined by the multiple alignment posts 151.

[0063] In some possible embodiments, alignment marks are provided on the superconducting quantum wafer 12, which is configured to be placed on the carrier substrate 11 when the alignment marks are aligned with at least one alignment post 151, so that each quantum circuit element 121 is positioned opposite a resonant cavity 111. In other possible embodiments, the alignment post 151 may be integrally formed with the carrier substrate 11 or the alignment post 151 may be detachably mounted on the carrier substrate 11; the cross-sectional shape of the alignment post 151 may be circular, square, or other polygonal.

[0064] In some embodiments, such as Figure 4As shown, the test module 14 includes multiple signal processing units 141 and a processor 142. Each signal processing unit 141 is connected to one end of a corresponding connector 13 located on the back side of the carrier substrate 11. The processor 142 is connected to the multiple signal processing units 141 respectively. The processor 142 is used to acquire test parameters of at least one quantum circuit element 121.

[0065] The signal processing unit 141 connects the processor 142 and the connector 13, enabling each quantum circuit element 121 to form an independent signal transmission channel with the processor 142 via the resonant cavity 111, the connector 13, and the signal processing unit 141. The processor 142 receives the microwave response signal of the corresponding quantum circuit element 121 through the signal processing unit 141, obtains the test parameters of the corresponding quantum circuit element 121 based on the microwave response signal, and outputs the test results based on the test parameters.

[0066] In possible implementations, processor 142 is a central processing unit, a field-programmable gate array, or a dedicated signal processing chip. In other implementations, processor 142 receives microwave response signals from multiple quantum circuit elements 121 via signal processing unit 141 to achieve parallel testing of multiple quantum circuit elements 121 and improve testing efficiency; or, processor 142 receives microwave response signals from quantum circuit elements 121 one by one to test a single quantum circuit element 121.

[0067] It should be noted that the signal processing unit 141 is connected between the connector 13 and the processor 142, and is used to perform front-end preprocessing on the microwave response signal transmitted by the connector 13, including signal amplification, filtering, mixing, and analog-to-digital conversion modules, converting the analog microwave signal into a digital signal before transmitting it to the processor 142. Each signal processing unit 141 is signal-connected to a corresponding connector 13, and the multiple signal processing units 141 are independent of each other and can work in parallel. The processor 142 is connected to the multiple signal processing units 141 respectively, and is used to receive the digital signals preprocessed by each signal processing unit 141, and obtain the test parameters of the corresponding quantum circuit element 121 (including quantum bit frequency f01, energy relaxation time T1, decoherence time T2, etc.) based on the digital signals. The processor 142 is also used to perform performance judgment and grade classification based on the test parameters, generate wafer-level sorting maps, and calculate the changes based on the test parameter sets measured at multiple process nodes of the same wafer to locate process abnormal steps.

[0068] Thus, the two form a complete link in the signal flow direction: "microwave response signal → signal processing unit 141 (preprocessing) → processor 142 (algorithm processing) → test result output". The signal processing unit 141 is responsible for front-end physical layer signal conditioning, and the processor 142 is responsible for back-end application layer data processing and decision-making. Their functions complement each other and together constitute the core signal processing capability of the test module 14.

[0069] Therefore, in this application, the processor 142 is connected to multiple signal processing units 141 respectively, and receives the microwave response signal of the corresponding quantum circuit element 121 based on the signal processing unit 141 and the connector 13 to obtain test parameters and output test results. Each signal processing unit 141 corresponds to each connector 13, so that the microwave response signal of each quantum circuit element 121 can be independently transmitted to the processor 142 for processing, thereby realizing the parallel testing of multiple quantum circuit elements 121, which is beneficial to improving the overall efficiency of wafer-level testing.

[0070] In some embodiments, the quantum circuit element 121 is a structural unit with independent quantum circuit function formed on a superconducting quantum wafer 12. The quantum circuit element 121 includes at least one of a qubit, a coupler, a readout resonator, and a filter.

[0071] In this context, a qubit is the basic unit for carrying and manipulating quantum information. A coupler is used to achieve mutual coupling between two or more qubits; the coupler can be a fixed coupler and / or a tunable coupler. A filter is a frequency-selective structure used to suppress noise and protect the coherence of qubits. A readout resonator is an electromagnetic resonant structure used to realize the readout of the quantum state of a qubit. All of the above quantum circuit elements 121 are formed through the same process using a superconducting material layer on a superconducting quantum wafer 12, and are distributed in a predetermined area of ​​the superconducting quantum wafer 12 according to a predetermined layout rule to constitute the complete functional circuit of the superconducting quantum chip.

[0072] In one embodiment, each of the aforementioned quantum circuit elements 121 is formed on a superconducting material layer on a superconducting quantum wafer 12 using the same fabrication process. In other embodiments, some of the quantum circuit elements 121 may be formed using different fabrication processes and then integrated onto the superconducting quantum wafer 12.

[0073] In a possible implementation, a plurality of qubits are arranged in an array on the superconducting quantum wafer 12; couplers are arranged between adjacent qubits to achieve mutual coupling between adjacent qubits; a readout resonator is coupled to the qubits to read the quantum state information of the qubits; a filter is arranged on the signal transmission path between the qubits and the readout resonator to filter out environmental noise and stray signals. A plurality of resonators 111 on the carrier substrate 11 are respectively arranged corresponding to at least one of the qubits, couplers, readout resonators, and filters to test at least one of the qubits, couplers, readout resonators, and filters and obtain test parameters.

[0074] In some embodiments, see Figure 7 , Figure 7 This application is Figure 1 A schematic diagram of the bottom structure of the quantum circuit element testing device 10. (See diagram below.) Figure 7 As shown, multiple connectors 13 are arranged in a third array on the back side of the carrier substrate 11. The arrangement of the third array is the same as that of the first array, so that each connector 13 on the back side of the carrier substrate 11 corresponds one-to-one with each resonant cavity 111 on the front side. That is, the arrangement of the third array matches the arrangement of the first array and the second array mentioned above.

[0075] This application also proposes a testing method for use in the quantum circuit element testing apparatus 10 of any of the above embodiments. Please refer to... Figure 8 , Figure 8 This is a flowchart illustrating the first embodiment of the testing method provided in this application. Figure 8 As shown, the testing method includes the following steps: Step S1: Obtain the superconducting quantum wafer 12 to be tested, on which multiple quantum circuit elements 121 are formed.

[0076] The superconducting quantum wafer 12 is the object to be tested, on which a plurality of quantum circuit elements 121 are formed, including at least one of a quantum bit, a readout resonator, a coupler, or a filter.

[0077] Step S2: Place the superconducting quantum wafer 12 on the front side of the carrier substrate 11. The front side of the carrier substrate 11 has multiple resonant cavities 111. A connector 13 is installed through each resonant cavity 111, and each quantum circuit element 121 on the superconducting quantum wafer 12 is positioned opposite to the corresponding resonant cavity 111.

[0078] The front side of the substrate 11 has multiple resonant cavities 111 corresponding to the quantum circuit elements 121 on the superconducting quantum wafer 12. These multiple resonant cavities 111 can form an array, which matches the array arrangement of the multiple quantum circuit elements 121 on the superconducting quantum wafer 12, so that each quantum circuit element 121 is positioned opposite to a corresponding resonant cavity 111. A connector 13 is located at the corresponding position of each resonant cavity 111, and the quantum circuit elements 121 form signal coupling with the connector 13 through the resonant cavity 111.

[0079] Step S3: Send a microwave detection signal to the corresponding quantum circuit element 121 through connector 13, and receive the microwave response signal returned by the quantum circuit element 121 in response to the microwave detection signal through connector 13.

[0080] First, a microwave detection signal is sent to the corresponding quantum circuit element 121 through connector 13. Under the action of the microwave detection signal, the quantum circuit element 121 outputs a corresponding microwave response signal. Then, the microwave response signal returned by the quantum circuit element 121 in response to the microwave detection signal is received through connector 13.

[0081] Step S4: Obtain the test parameters of the corresponding quantum circuit element 121 based on the microwave response signal, and output the corresponding test results based on the test parameters.

[0082] Test parameters of quantum circuit element 121 are obtained based on the microwave response signal. These test parameters include at least one of the following: quantum bit frequency, coupling strength, dispersion shift, energy relaxation time, decoherence time, or readout fidelity. Test results are output based on the test parameters of at least one quantum circuit element 121.

[0083] Therefore, in this embodiment, the superconducting quantum wafer 12 can be directly placed on the carrier substrate 11 without dicing or packaging. This allows the quantum circuit elements 121 to form microwave signal coupling with the connector 13 through the resonant cavity 111, thereby achieving wafer-level non-destructive testing. This avoids the cumbersome process of dicing and packaging required for testing in related technologies, significantly reducing the cost of wafer testing. Simultaneously, the quantum circuit elements 121 on the superconducting quantum wafer 12 correspond precisely one-to-one with the resonant cavity 111, enabling each quantum circuit element 121 to be independently read and tested. This facilitates statistical analysis of the test data of multiple quantum circuit elements 121 on the entire wafer, and further allows for the generation of grade information and wafer-level sorting maps for each quantum circuit element 121 based on the statistical analysis results. This provides data support for dicing process path planning and yield control, thereby achieving closed-loop yield management throughout the entire process from testing to packaging.

[0084] In some embodiments, see Figure 9, Figure 9 This application is Figure 8 A flowchart illustrating the first embodiment of outputting test results. (See attached diagram.) Figure 9 As shown, step S4 includes the following steps: Step S41: Obtain test parameters of at least one quantum circuit element 121 and judge the test parameters.

[0085] Based on the microwave response signal returned by the quantum circuit element 121 in response to the microwave detection signal, the corresponding test parameters are obtained. Understandably, these test parameters can be key performance indicators or relevant design parameters of the quantum circuit element 121, such as the quantum bit frequency, energy relaxation time, decoherence time, coupling strength, dispersion shift, or readout fidelity of the quantum circuit element 121.

[0086] Step S42: When the test parameters meet the first preset conditions, the corresponding quantum circuit element 121 is marked as a first-level element.

[0087] After obtaining the test parameters, it is determined whether the test parameters meet the preset conditions to determine the performance level of the quantum circuit element 121. The preset conditions can be pre-set according to parameter type, process characteristics, industrialization requirements, etc. When the test parameters meet the first preset conditions, the key performance indicators or related design parameters of the quantum circuit element 121 can be considered to meet the first-level production requirements, and the corresponding quantum circuit element 121 is marked as a first-level element.

[0088] In a possible implementation, when the test parameter includes energy relaxation time, the corresponding first preset condition is that the energy relaxation time is greater than or equal to a first threshold. If the tested energy relaxation time is greater than or equal to the first threshold, the first preset condition is considered met, and the corresponding quantum circuit element 121 is marked as a first-level element. For example, the first threshold can be 180μs, 190μs, 200μs, 210μs, or 220μs.

[0089] Step S43: When the test parameters meet the second preset conditions, mark the corresponding quantum circuit element 121 as a second-level element.

[0090] If the test parameters do not meet the first preset condition, the system further determines whether the second preset condition is met to determine the performance level of the quantum circuit element 121. If the test parameters meet the second preset condition, the system considers that the key performance indicators or related design parameters of the quantum circuit element 121 do not meet the first-level production requirements, but meet the second-level production requirements, and the corresponding quantum circuit element 121 is marked as a second-level element.

[0091] In a possible implementation, when the test parameter includes energy relaxation time, the corresponding second preset condition is that the energy relaxation time is less than a first threshold and greater than or equal to a second threshold. If the tested energy relaxation time is less than the first threshold and greater than or equal to the second threshold, the second preset condition is considered met, and the corresponding quantum circuit element 121 is marked as a second-level element. For example, the second threshold is less than the first threshold; the second threshold can be 80 μs, 90 μs, 100 μs, 110 μs, or 120 μs.

[0092] Furthermore, when the energy relaxation time obtained from the test is less than the second threshold (i.e., the third preset condition is met), the quantum circuit element 121 can be marked as a third-level element.

[0093] For example, first-level components are qualified components; second-level components are downgraded components, that is, components whose performance does not meet the first level but can be downgraded for use; third-level components are scrapped components, that is, components whose performance is seriously substandard and have no downgrade or repair value.

[0094] Understandably, the specific marking methods for the aforementioned first-level components, second-level components, and third-level components can be set according to actual testing requirements and chip classification standards, and this application does not limit them in this regard.

[0095] In other implementations, in addition to using energy relaxation time to classify and screen quantum circuit elements 121, at least one of the following parameters can be used to classify and screen quantum circuit elements 121: decoherence time, the ratio of decoherence time to energy relaxation time, and spectral test parameters (such as frequency offset or linewidth). No specific limitations are made here.

[0096] Therefore, by determining whether the test parameters meet the preset conditions and marking the components as components of the corresponding grade, the results of wafer-level testing can be directly converted into a screening process for production qualification. Automatic grading and screening of components can be achieved without manual intervention, thereby quickly identifying low-performance or failed quantum circuit components 121 before the wafer is diced. Furthermore, based on the marking results during the aforementioned testing, low-performance or failed components can be eliminated in advance, ensuring that subsequent packaging processes are only performed on qualified components. This reduces packaging costs, shortens processing time, and further improves the yield and production efficiency of the superconducting quantum wafer 12.

[0097] In some embodiments, in the testing method of this embodiment, step S4 further includes the following steps: determining the grade information of each quantum circuit element 121 according to the test parameters of each quantum circuit element 121; generating a sorting map of the superconducting quantum wafer 12 according to the grade information of each quantum circuit element 121, the sorting map being used to indicate the grade distribution of each quantum circuit element 121 on the superconducting quantum wafer 12.

[0098] The test parameters include relevant performance indicators of the quantum circuit element 121 extracted from the microwave response signal, including at least one of the following: qubit frequency, energy relaxation time, decoherence time, coupling strength, dispersion shift, or readout fidelity. The grading information is a classification and identification information for each quantum circuit element 121 based on preset performance threshold standards. Based on the test parameters of each quantum circuit element 121, the quantum circuit elements 121 on the superconducting quantum wafer 12 are classified into grades to obtain the grade information of each quantum circuit element 121.

[0099] In one possible approach, the quantum circuit elements 121 can be classified into three levels based on the test parameters of each element; for example, elements with excellent performance are labeled as level A, those with medium performance as level B, and those with poor performance as level C. The criteria for determining each level can be preset according to the type of test parameters and specific performance thresholds, and will not be elaborated here.

[0100] Based on the grade information of each quantum circuit element 121, a sorting map of the superconducting quantum wafer 12 is generated. The sorting map is a two-dimensional visualization chart used to display the grade information of the quantum circuit elements 121 corresponding to each location on the superconducting quantum wafer 12 in spatial coordinates. In a possible scheme, the values ​​of test parameters are mapped to discrete grade classification labels according to preset rules, and the grade information of each element is mapped to the corresponding position on a two-dimensional plane using the coordinate system of the superconducting quantum wafer 12 as a reference, to generate a sorting map that can indicate the grade distribution of each quantum circuit element 121 on the superconducting quantum wafer 12. For example, the sorting map presents a planar view of the superconducting quantum wafer 12, and displays relevant labels for the corresponding grade information on the grid areas corresponding to each quantum circuit element 121 in the planar view. The relevant labels for displaying grade information on the sorting map can be distinguished by icons, colors, text, or numbers corresponding to different grades.

[0101] Therefore, by determining the grade information of each quantum circuit element based on test parameters, the performance level of each quantum circuit element 121 on the superconducting quantum wafer 12 can be quantitatively analyzed, thereby enabling rapid classification of the quality grade of each quantum circuit element 121. This facilitates the selection of qualified elements that meet specific quality requirements. Simultaneously, a sorting map indicating the grade distribution is generated based on the grade information, allowing the quality status of each region on the superconducting quantum wafer 12 to be visually presented in a spatial distribution form. This makes it easy for users to quickly identify local process defects such as edge effects, uneven evaporation, or lithography deviations from the sorting map. Through the above-mentioned graded screening and spatial distribution identification, data support can be provided for the optimization of subsequent process schemes, avoiding the packaging of low-performance, low-yield components into the final product, thereby improving overall production efficiency and packaging resource utilization.

[0102] In some embodiments, see Figure 10 , Figure 10 This is a flowchart illustrating a second embodiment of the testing method of this application. Figure 10 As shown, the testing method in this embodiment further includes the following steps: Step S100: Test the superconducting quantum wafer 12 at multiple predetermined process nodes to obtain the test parameter set corresponding to each predetermined process node. Each test parameter set includes multiple test parameters.

[0103] The predetermined process node refers to the process steps in the manufacturing flow of the superconducting quantum wafer 12 that may affect quantum performance. The predetermined process node includes, but is not limited to, production nodes related to processes such as Josephson junction fabrication, deep silicon etching, through-silicon via (TSV) fabrication, and passivation layer deposition. The test parameter set is a collection of test parameters measured for each quantum circuit element 121 of at least one superconducting quantum wafer 12 at the same process node.

[0104] In one possible approach, for a superconducting quantum wafer 12, during its manufacturing process, the tests described above in steps S1-S4 are performed at multiple predetermined process nodes. The set of multiple test parameters obtained for each predetermined process node is the aforementioned test parameter set.

[0105] In another possible approach, for multiple superconducting quantum wafers 12 at the same process node, the tests described in steps S1-S4 are performed respectively to obtain the test parameters of the multiple superconducting quantum wafers 12. Statistical processing (such as calculating the average, median, or variance) is performed on the test parameters of multiple quantum circuit elements 121 at the same location on the multiple superconducting quantum wafers 12. The statistically processed test parameters form the test parameter group corresponding to the process node.

[0106] Step S200: Based on the test parameter group corresponding to each predetermined process node, establish the correspondence between the performance parameters of the quantum circuit element 121 and the predetermined process node.

[0107] After obtaining the test parameter sets corresponding to each predetermined process node, a correspondence between the performance parameters of the quantum circuit element 121 and the predetermined process nodes is established based on the test parameter sets corresponding to each predetermined process node. This correspondence is used to characterize the impact of each predetermined process node on the performance of the quantum circuit element 121. In some embodiments, this correspondence can be a data mapping relationship formed by the test parameter values ​​corresponding to the predetermined process node or the change of the test parameter values ​​relative to the previous process node. In some embodiments, this correspondence can be obtained by processing the test parameter sets through at least one of experimental design, regression analysis, simulation, or machine learning.

[0108] Step S300: Output the process quality evaluation results for each predetermined process node according to the corresponding relationship.

[0109] After obtaining the correspondence between the performance parameters of the quantum circuit element 121 and the predetermined process nodes, the process quality of each predetermined process node can be evaluated based on this correspondence, and the process quality evaluation results of each predetermined process node can be output. For example, the process quality evaluation results can be used to indicate relevant information such as yield prediction and process defect warning for the predetermined process node.

[0110] In one possible approach, a first test can be performed after the Josephson junction is fabricated to obtain the first set of test parameters for the superconducting quantum wafer 12. A second test can be performed after deep silicon etching to obtain the second set of test parameters for the superconducting quantum wafer 12. By comparing the first and second set of test parameters, the specific impact of the deep silicon etching process on the test parameters can be determined. A third test can be performed after through-silicon via (TSV) fabrication to obtain the third set of test parameters for the superconducting quantum wafer 12. By comparing the second and third set of test parameters, the specific impact of the TSV fabrication process on the test parameters can be determined. Therefore, when a predetermined process node causes the change in test parameters to exceed a preset threshold, that predetermined process node can be marked as a high-risk node, and the corresponding process quality evaluation result can be output.

[0111] The test parameter set includes at least two different test parameters, such as qubit frequency, energy relaxation time, and decoherence time. When comparing the second and third test parameter sets, one test parameter can be selected for individual comparative analysis, or the changes in multiple test parameters can be calculated separately and then comprehensively compared to evaluate the impact of each predetermined process node on different performance parameters. For example, by comparing the test parameter sets corresponding to different predetermined process nodes, key process steps leading to the degradation of specific test parameters can be identified.

[0112] Therefore, by testing the superconducting quantum wafer 12 at multiple predetermined process nodes, the impact of each key process step on the performance of the quantum circuit element 121 can be monitored in real time without compromising wafer integrity. This enables dynamic monitoring of the manufacturing process and avoids the lag of discovering problems only during final product testing. By obtaining the test parameter sets corresponding to each predetermined process node and establishing the correspondence between performance parameters and process nodes, the specific contribution or loss of different process steps to key performance parameters can be quantitatively analyzed. This facilitates tracing the source of process impact and improves the targeting and efficiency of process optimization. Outputting the process quality evaluation results for each predetermined process node based on the correspondence allows for the early identification of yield distribution patterns and potential defect areas. This helps guide subsequent slicing path planning and quality control, reducing the probability of defective components entering subsequent packaging stages, thereby reducing overall production costs and improving mass production yield.

[0113] In some embodiments, see Figure 11 , Figure 11 This application is Figure 10 A flowchart illustrating an embodiment of obtaining a test parameter set. For example... Figure 11 As shown, step S100 further includes the following steps: Step S110: Test the superconducting quantum wafer 12 at the first predetermined process node to obtain the first set of test parameters.

[0114] Step S120: Test the superconducting quantum wafer 12 at the second predetermined process node to obtain the second set of test parameters.

[0115] The first predetermined process node and the second predetermined process node are adjacent process nodes in the fabrication process of the superconducting quantum chip. For example, the first predetermined process node can be a node after the Josephson junction is fabricated; the second predetermined process node can be a node after deep silicon etching is completed.

[0116] The superconducting quantum wafer 12 is tested at a first predetermined process node to obtain test parameters for each quantum circuit element 121 on the superconducting quantum wafer 12, and these test parameters form a first test parameter set. Similarly, the same testing method is used to test the superconducting quantum wafer 12 at a second predetermined process node to obtain test parameters for each quantum circuit element 121 on the superconducting quantum wafer 12, and this forms a second test parameter set. By comparing the first test parameter set and the second test parameter set, the impact of process steps between the first and second predetermined process nodes on the performance of the quantum circuit element 121 can be quantitatively evaluated.

[0117] Step S130: Calculate the change in each test parameter according to the first test parameter group and the second test parameter group. The change is used to characterize the impact of the process steps between the first predetermined process node and the second predetermined process node on the performance of the quantum circuit element 121.

[0118] Based on the first set of test parameters for the first predetermined process node and the second set of test parameters for the second predetermined process node, the variation of the test parameters of the quantum circuit element 121 at the same location on the superconducting quantum wafer 12 at the two predetermined process nodes can be calculated. This variation is used to characterize the impact of the process steps between the first and second predetermined process nodes on the performance of the quantum circuit element 121.

[0119] Therefore, by conducting tests at the first and second predetermined process nodes and calculating the changes in each test parameter, the impact of adjacent process steps on the performance of the quantum circuit element 121 can be accurately quantified. This allows for the direct identification of specific process steps that affect performance during the manufacturing process, thereby improving the precision of process control and product yield, reducing the waste of subsequent packaging and testing resources, and improving overall production efficiency.

[0120] In some embodiments, the predetermined process node includes at least one of the following: Josephson junction fabrication process node, deep silicon etching process node, TSV (Through-Silicon Via) fabrication process node, and three-dimensional packaging process node.

[0121] The Josephson junction fabrication process node is a step in forming the core structure of the quantum circuit element 121. This process node is used to form a Josephson junction on the superconducting quantum wafer 12 that enables quantum tunneling. The deep silicon etching process node is a step in forming deep trenches or vias in the substrate or structural layer of the superconducting quantum wafer 12 using etching technology. The through-silicon via (TSV) process node refers to the through-silicon via process, used to form vertical conductive paths through the thickness of the superconducting quantum wafer 12 to achieve electrical connections between the front and back sides of the wafer. The three-dimensional packaging process node is the step in combining the diced chips from the superconducting quantum wafer 12 with the packaging structure. In possible schemes, the three-dimensional packaging process node includes flip-chip technology or wire bonding technology, among other related processes.

[0122] In possible solutions, the aforementioned predetermined process nodes include any combination of two of the following: Josephson junction fabrication process node, deep silicon etching process node, TSV fabrication process node, and 3D packaging process node. For example, testing can be performed after the Josephson junction fabrication process node is completed to obtain a first set of test parameters, and testing can be performed after the deep silicon etching process node is completed to obtain a second set of test parameters; or, for another example, testing can be performed after the TSV fabrication process node is completed to obtain a first set of test parameters, and testing can be performed after the 3D packaging process node is completed to obtain a second set of test parameters.

[0123] In other implementations, the first test can be performed after the Josephson junction is fabricated to obtain the first set of test parameters; the second test can be performed after deep silicon etching to obtain the second set of test parameters; the third test can be performed after TSV fabrication to obtain the third set of test parameters; and the fourth test can be performed after 3D packaging to obtain the fourth set of test parameters. Therefore, the process quality of each agreed-upon process node can be comprehensively evaluated based on the first, second, third, and fourth set of test parameters, and the corresponding process quality evaluation results can be obtained.

[0124] In some embodiments, see Figure 12 , Figure 12 This is a flowchart illustrating the third embodiment of the testing method of this application. Figure 12 As shown, the testing method in this embodiment further includes the following steps: Step S100: Test the superconducting quantum wafer 12 at multiple predetermined process nodes to obtain the test parameter set corresponding to each predetermined process node. Each test parameter set includes multiple test parameters.

[0125] Step S200: Based on the test parameter group corresponding to each predetermined process node, establish the correspondence between the performance parameters of the quantum circuit element and the predetermined process node.

[0126] Step S300: Output the process quality evaluation results for each predetermined process node according to the corresponding relationship.

[0127] Steps S100-S300 are similar to the steps described above, and will not be repeated here.

[0128] Step S400: Compare the changes in each test parameter with the standard changes at the predetermined process node.

[0129] The change in each test parameter is the difference between the test parameters of the quantum circuit element 121 at the current predetermined process node and the test parameters at the previous predetermined process node. This change can be used to characterize the impact of the current predetermined process node on the performance of the quantum circuit element 121.

[0130] Therefore, by comparing the changes in each test parameter with the standard changes at the predetermined process node, it can be determined whether the current predetermined process node meets the standard requirements based on the comparison results.

[0131] Step S500: When the change exceeds the preset range of the standard change, output a prompt message indicating that there is a process abnormality at the corresponding predetermined process node.

[0132] The standard variation refers to the pre-set allowable variation threshold for a specific process node. The preset range of the standard variation is a numerical interval extending outwards from the standard variation as the center or benchmark and the allowable deviation range as the radius. This preset range of the standard variation can be dynamically adjusted according to the process type, equipment status, or product grade, and is not specifically limited here.

[0133] After obtaining the changes in each test parameter, it is determined whether the changes exceed the preset range of the corresponding standard changes. When the changes exceed the preset range of the standard changes, it indicates that the impact of the current predetermined process node on the performance of the quantum circuit element 121 exceeds the normal fluctuation range. At this time, a prompt message indicating that there is a process anomaly at the corresponding predetermined process node can be output. When the changes are within the preset range of the standard changes, the process status of the current predetermined process node is determined to be normal.

[0134] In possible solutions, the prompt information includes abnormal process nodes, abnormal parameter types, deviation magnitudes, or causes of the abnormality. Other solutions may involve pre-setting different abnormal threshold ranges to determine the abnormal threshold range within which the change falls and outputting corresponding abnormal prompts; for example, the abnormality levels of predetermined process nodes can be divided into minor deviations and severe deviations, with different handling strategies corresponding to different abnormality levels.

[0135] Therefore, by comparing the changes in each test parameter with the standard changes at predetermined process nodes, quantitative data can be used to objectively reflect the impact of each process step on the performance of the quantum circuit element 121, thereby achieving refined control over the process. When the changes exceed the preset range, a process anomaly warning message is output, enabling timely detection of process deviations in the early stages of problems. This allows for rapid identification of the specific process steps leading to performance degradation, preventing defects from accumulating in subsequent stages and causing greater losses. This improves the real-time early warning capability of wafer-level testing and the accuracy of process control.

[0136] In some embodiments, see Figure 13 , Figure 13 This application is Figure 12 A flowchart illustrating one embodiment of outputting prompt information. For example... Figure 13 As shown, after step S500, the testing method of this embodiment further includes the following steps: Step S510: Obtain the process parameters of the predetermined process node corresponding to the process anomaly.

[0137] Specifically, after a predetermined process node is determined to be abnormal, the specific process parameters that caused the aforementioned test parameters to change beyond the preset range are obtained.

[0138] For example, when an output prompt indicates a process anomaly, the system automatically associates and extracts the key process parameters involved in the anomaly. For instance, if the prompt indicates a decrease in energy relaxation time T1 due to deep silicon etching, the system can extract relevant process parameters such as etching power, gas ratio, etching depth, and etching time involved in the deep silicon etching process.

[0139] Step S520: Adjust the process parameters of the predetermined process node according to the prompt information and process parameters.

[0140] Specifically, after locating the abnormal predetermined process node and the process parameters under that node, the process parameters of the predetermined process node are adjusted according to the prompt information and process parameters.

[0141] In possible solutions, process parameter adjustment can be based on anomaly type, historical data, or preset algorithm rules to automatically adjust or optimize process parameters at predetermined process nodes based on prompts and process parameters. Alternatively, process parameter adjustment can be achieved by acquiring manually input parameters. For example, when the prompt indicates a decrease in energy relaxation time T1 due to deep silicon etching, the specific anomaly can be identified, allowing adjustment of deep silicon etching process parameters. This could involve reducing etching power to minimize surface damage or adjusting gas ratios to improve selectivity.

[0142] Step S530: Test the superconducting quantum wafer 12 at the adjusted predetermined process node to obtain verification test parameters.

[0143] Specifically, after adjusting the process parameters for a predetermined process node, the processing steps of that predetermined process node are executed on subsequent batches of superconducting quantum wafers 12 using the adjusted process parameters. After the predetermined process node is completed, the subsequent batches of superconducting quantum wafers 12 are tested to obtain verification test parameters. The verification test parameters are used to verify whether the process parameter adjustment is effective, and the verification results are fed back into the processing of subsequent batches.

[0144] Step S540: When the verification test parameters meet the preset verification conditions, confirm that the process adjustment of the predetermined process node is effective.

[0145] If the verification test parameters meet the preset verification conditions, the process adjustment of the predetermined process node is confirmed to be effective. If the verification test parameters do not meet the preset verification conditions, the process adjustment of the predetermined process node is confirmed to be ineffective.

[0146] The preset verification conditions are the standards used to determine whether the process adjustment is successful. The preset verification conditions can correspond to the standard change amount mentioned above, or the preset verification conditions can be the parameter range corresponding to the standard change amount.

[0147] When the verification test parameters meet the preset verification conditions, it indicates that the current adjustment strategy can eliminate or significantly improve abnormal process conditions. At this point, the effectiveness of the process adjustment at the predetermined process node can be confirmed. Therefore, this adjustment parameter can be solidified or marked as a recommended parameter.

[0148] Therefore, by acquiring the process parameters corresponding to process anomalies and adjusting the process parameters at predetermined process nodes based on the prompts and process parameters, targeted corrective measures can be taken for specific detected process deviations, achieving proactive intervention and dynamic optimization of the process. After adjustment, subsequent batches of superconducting quantum wafers are tested at the predetermined process nodes to obtain verification test parameters. When the verification test parameters meet the preset verification conditions, the process adjustment is confirmed to be effective. This allows for rapid verification of the effectiveness of the adjustment strategy during process debugging, avoiding resource waste caused by ineffective adjustments, improving the accuracy of process control, and contributing to improved yield consistency in wafer-level manufacturing.

[0149] In some embodiments, a plurality of quantum circuit elements 121 are arranged in an array on a superconducting quantum wafer 12, and the test results include a two-dimensional distribution map. This two-dimensional distribution map is used to characterize the spatial distribution of the test parameters of each quantum circuit element 121 on the superconducting quantum wafer 12.

[0150] Please see Figure 14 , Figure 14 This application is Figure 8 A flowchart illustrating the second embodiment for outputting test results. (See attached diagram.) Figure 14 As shown, step S4 above further includes the following steps: Step S44: Establish a wafer coordinate system based on the arrangement of quantum circuit elements 121 on the superconducting quantum wafer 12.

[0151] Since multiple quantum circuit elements 121 are arranged in a second array on the superconducting quantum wafer 12, a wafer coordinate system can be established based on the arrangement of the quantum circuit elements 121 on the superconducting quantum wafer 12. Each quantum circuit element 121 has a corresponding position coordinate in this wafer coordinate system, which is used to represent the arrangement position of the quantum circuit element 121 in the second array.

[0152] In one example, the aforementioned wafer coordinate system can be a coordinate system established with the quantum circuit element 121 located at a corner of the array as the origin. For example, the second array is arranged in an N×M matrix form, where N and M are positive integers; in this case, with the quantum circuit element 121 located at a corner of the rectangular array as the origin, the position coordinates corresponding to a certain quantum circuit element 121 can be represented as (x, y), where x is a positive integer less than or equal to N, and y is a positive integer less than or equal to M.

[0153] In another example, the aforementioned wafer coordinate system can also be a coordinate system established with the quantum circuit element 121 located at the center point in the second array as the origin; in this case, the quantum circuit elements 121 distributed around the center point are located in the four quadrants of the wafer coordinate system, so as to accurately locate the positional relationship of each quantum circuit element 121 relative to the center point.

[0154] Step S45: Determine the parameter values ​​of each quantum circuit element 121 based on the test parameters of each quantum circuit element 121.

[0155] After acquiring the test parameters of all quantum circuit elements 121 on the entire superconducting quantum wafer 12, the parameter value of each quantum circuit element 121 is calculated. The aforementioned test parameters include at least one of the following: spectral test parameters, relaxation time parameters, decoherence time parameters, and readout test parameters. For example, the test parameters can be transition frequency parameters, relaxation time parameters, decoherence time parameters, or readout fidelity. The parameter value can be used to indicate the magnitude range of the corresponding type of test parameter, and the parameter value includes at least one of the following: quantum bit frequency value, energy relaxation time value, decoherence time value, or JJ resistance value.

[0156] In a possible implementation, the aforementioned parameter values ​​can be thermal values. For example, based on a preset color-gradient mapping rule, the test parameters of all quantum circuit elements 121 are mapped to corresponding color-gradient values ​​to determine the thermal value of each quantum circuit element 121. This can be achieved by mapping the test value of a single type of test parameter (such as any one of spectrum test parameters, relaxation time parameters, decoherence time parameters, or readout test parameters) to a color-gradient value. Alternatively, all types of test parameters of the quantum circuit element 121 can be comprehensively calculated to obtain a comprehensive performance parameter, which is then mapped to a color-gradient value to obtain the thermal value.

[0157] Step S46: Based on the parameter values ​​of each quantum circuit element 121 and the position coordinates of the quantum circuit element 121 in the wafer coordinate system, a two-dimensional distribution map of the superconducting quantum wafer 12 is generated. The two-dimensional distribution map is used to characterize the spatial distribution of each parameter value on the superconducting quantum wafer 12.

[0158] Therefore, by mapping the parameter values ​​of each quantum circuit element 121 to the corresponding position coordinates of the quantum circuit element 121 on the superconducting quantum wafer 12, a two-dimensional distribution map of the superconducting quantum wafer 12 is generated. This two-dimensional distribution map can characterize the spatial distribution of each parameter value on the superconducting quantum wafer 12. The wafer coordinate system is a two-dimensional rectangular coordinate system or polar coordinate system established on the plane of the superconducting quantum wafer 12. The wafer coordinate system is used to uniquely identify the physical location of any quantum circuit element 121 on the superconducting quantum wafer 12. The wafer coordinate system can have the wafer center or a specific marker point as its origin. For example, the two-dimensional distribution map includes at least one of a frequency map, a T1 map, a decoherence time map, or a JJ resistance map.

[0159] A two-dimensional distribution map is an image formed by mapping the parameter values ​​of discrete individual quantum circuit elements 121 to a continuous spatial coordinate system. The two-dimensional distribution map includes at least one of a heatmap, contour plot, or scatter plot. When the two-dimensional distribution map is a heatmap, a visualization of the superconducting quantum wafer 12 can be rendered based on the parameter values ​​of all quantum circuit elements 121 calculated above to generate a parameter distribution heatmap of the superconducting quantum wafer 12. This visualization can be drawn according to the actual morphology of the superconducting quantum wafer 12.

[0160] By establishing a wafer coordinate system and combining the parameter values ​​of each quantum circuit element 121 with its position coordinates to generate a two-dimensional distribution map, the performance state of the quantum circuit element 121 on the superconducting quantum wafer 12 can be presented in a visual manner, thereby realizing a global analysis and display of the overall performance distribution of the superconducting quantum wafer 12. Based on this two-dimensional distribution map, regions with abnormal performance caused by factors such as edge effects, uneven evaporation, or photolithography deviations can be intuitively identified, which is beneficial for quickly locating process defect sources and further improving the targeting of process optimization.

[0161] In some embodiments, the test parameters include at least one of the following: spectrum test parameters, relaxation time parameters, decoherence time parameters, and readout test parameters.

[0162] The spectrum test parameters are the relevant parameters obtained after performing spectrum testing on the quantum circuit element 121 using the aforementioned quantum circuit element testing device 10. These parameters include at least one of the following: the transition frequency parameter between the ground state and the first excited state of the qubit, and the resonance frequency parameter of the readout resonator. The relaxation time parameter (Energy Relaxation Time, T1) characterizes the rate of energy dissipation of the quantum state of the quantum circuit element 121, i.e., the time required for the qubit to spontaneously decay back to the ground state from the excited state. The decoherence time parameter (Spin Echo Coherence Time, T2) characterizes the ability to retain the phase information of the quantum state. For example, the decoherence time parameter can be measured by a spin echo (Hahn Echo) test and reflects the decay of the quantum superposition state during the decoherence process. The readout test parameters are the relevant parameters obtained after performing a quantum bit readout performance test (Readout test) on the quantum circuit element 121 using the quantum circuit element test device 10 described above. The readout test parameters are used to evaluate the performance of reading quantum state information, and the readout test parameters include at least one of readout fidelity, readout efficiency, or readout signal-to-noise ratio.

[0163] Therefore, when the test parameters include spectral parameters, this test method can accurately monitor the frequency drift or detuning of the quantum circuit element 121 caused by each process step, which is beneficial for identifying frequency distribution unevenness caused by evaporation uniformity or photolithography deviation, providing data support for frequency planning. When the test parameters include relaxation time parameters, this test method can quantitatively evaluate the impact of dielectric loss and two-level system defects on the lifetime of the qubit, which is beneficial for tracing high-loss process steps and guiding material selection or process parameter optimization. When the test parameters include decoherence time parameters, this test method can characterize the stability of the quantum superposition state, further improving the accuracy of process noise source analysis. When the test parameters include readout test parameters, this test method can evaluate the reliability and efficiency of quantum state readout, which is beneficial for optimizing the readout resonator design and interconnect structure. Based on the above-mentioned multiple types of test parameters, the performance indicators of the quantum circuit element 121 in different physical dimensions can be comprehensively obtained, thereby realizing multi-faceted evaluation of the quantum circuit element 121, which is beneficial for improving the test reliability of the quantum circuit element 121, and thus guiding the subsequent slicing route planning, further realizing the yield control of the superconducting quantum chip.

[0164] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A wafer-level quantum circuit element testing device, characterized in that, include: The carrier substrate has a front side and a back side that are arranged opposite to each other. The front side of the carrier substrate has multiple resonant cavities. The front side of the carrier substrate is used to support the superconducting quantum wafer to be tested, and each quantum circuit element on the superconducting quantum wafer is arranged opposite to a corresponding resonant cavity. Multiple connectors, corresponding one-to-one with the multiple resonant cavities, are installed through the carrier substrate. Each connector passes through the front of the carrier substrate and extends to the back of the carrier substrate. At least one end of the connector located on the front of the carrier substrate is located within the resonant cavity to form microwave signal coupling with the corresponding quantum circuit element through the resonant cavity. The test module is connected to one end of the multiple connectors located on the back of the carrier substrate, and is used to acquire test parameters of at least one of the quantum circuit elements and output corresponding test results based on the test parameters.

2. The quantum circuit element testing device according to claim 1, characterized in that, The resonant cavities are arranged in a first array on the front side of the substrate, and the quantum circuit elements are arranged in a second array on the superconducting quantum wafer. The array size of the first array is greater than or equal to the array size of the second array, and the arrangement of the first array and the second array are matched.

3. The quantum circuit element testing device according to claim 1, characterized in that, The resonant cavity includes a resonant cavity body and a coupling post. The coupling post is disposed within the resonant cavity body and is used to couple with the corresponding quantum circuit element.

4. The quantum circuit element testing device according to claim 3, characterized in that, The coupling post is located at the center of the resonant cavity body and extends along the thickness direction of the supporting substrate. The coupling post and the sidewall of the resonant cavity body form a coaxial resonant structure.

5. The quantum circuit element testing device according to claim 1, characterized in that, The quantum circuit element testing device further includes an alignment module disposed on the front side of the carrier substrate and used to surround the superconducting quantum wafer to limit the positional displacement of the superconducting quantum wafer in the plane on the front side of the carrier substrate, thereby maintaining the relative arrangement of each quantum circuit element on the superconducting quantum wafer with the corresponding resonant cavity.

6. The quantum circuit element testing device according to claim 5, characterized in that, The alignment module includes multiple alignment pillars, which are disposed in the peripheral region of the multiple resonant cavities. The limiting space formed by the multiple alignment pillars matches the size of the superconducting quantum wafer.

7. The quantum circuit element testing device according to claim 1, characterized in that, The test module includes multiple signal processing units and a processor. Each signal processing unit is connected to one end of the corresponding connector located on the back side of the carrier substrate. The processor is connected to the multiple signal processing units respectively. The processor is used to acquire the test parameters of at least one of the quantum circuit elements.

8. The quantum circuit element testing apparatus according to any one of claims 1-7, characterized in that, The quantum circuit elements include at least one of qubits, couplers, readout resonators, and filters.

9. A method for testing quantum circuit elements, characterized in that, The method, applied to the quantum circuit element testing apparatus as described in any one of claims 1-8, comprises: Obtain a superconducting quantum wafer to be tested, on which multiple quantum circuit elements are formed; The superconducting quantum wafer is placed on the front side of a carrier substrate. The front side of the carrier substrate has multiple resonant cavities. A connector is installed through each resonant cavity, and each quantum circuit element on the superconducting quantum wafer is arranged opposite to the corresponding resonant cavity. A microwave detection signal is sent to the corresponding quantum circuit element through the connector, and a microwave response signal returned by the quantum circuit element in response to the microwave detection signal is received through the connector; the test parameters of the corresponding quantum circuit element are obtained based on the microwave response signal, and the corresponding test results are output based on the test parameters.

10. The quantum circuit element testing method according to claim 9, characterized in that, The step of outputting the corresponding test results based on the test parameters includes: Obtain test parameters for at least one of the quantum circuit elements, and determine the test parameters; When the test parameters meet the first preset condition, the corresponding quantum circuit element is marked as a first-level element; When the test parameters meet the second preset conditions, the corresponding quantum circuit element is marked as a second-level element.

11. The quantum circuit element testing method according to claim 9, characterized in that, The step of outputting the corresponding test results based on the test parameters includes: Based on the test parameters of each quantum circuit element, determine the grade information of each quantum circuit element; A sorting map of the superconducting quantum wafer is generated based on the rank information of each quantum circuit element. The sorting map is used to indicate the rank distribution of each quantum circuit element on the superconducting quantum wafer.

12. The quantum circuit element testing method according to claim 9, characterized in that, The method further includes: The superconducting quantum wafer is tested at multiple predetermined process nodes to obtain test parameter sets corresponding to each predetermined process node. Each test parameter set includes multiple test parameters. Based on the test parameter group corresponding to each predetermined process node, establish the correspondence between the performance parameters of the quantum circuit element and the predetermined process node; Based on the correspondence, output the process quality evaluation results for each of the predetermined process nodes.

13. The quantum circuit element testing method according to claim 12, characterized in that, The step of testing the superconducting quantum wafer at multiple predetermined process nodes to obtain a set of test parameters corresponding to each predetermined process node includes: The superconducting quantum wafer is tested at a first predetermined process node to obtain a first set of test parameters; The superconducting quantum wafer is tested at a second predetermined process node to obtain a second set of test parameters; Based on the first set of test parameters and the second set of test parameters, the change in each of the test parameters is calculated. The change is used to characterize the impact of the process steps between the first predetermined process node and the second predetermined process node on the performance of the quantum circuit element.

14. The quantum circuit element testing method according to claim 12, characterized in that, The predetermined process nodes include at least one of the following: Josephson junction fabrication process node, deep silicon etching process node, TSV fabrication process node, and three-dimensional packaging process node.

15. The quantum circuit element testing method according to claim 12, characterized in that, After outputting the process quality evaluation results for each predetermined process node according to the correspondence, the method further includes: Compare the changes in each of the test parameters with the standard changes at the predetermined process nodes; When the change exceeds the preset range of the standard change, a prompt message indicating that there is a process abnormality at the corresponding predetermined process node is output.

16. The quantum circuit element testing method according to claim 15, characterized in that, After outputting the prompt message indicating a process anomaly at the predetermined process node, the method further includes: Obtain the process parameters of the predetermined process node corresponding to the process anomaly; Based on the prompt information and the process parameters, the process parameters of the predetermined process node are adjusted; The superconducting quantum wafer is tested at the adjusted predetermined process node to obtain verification test parameters; When the verification test parameters meet the preset verification conditions, the process adjustment of the predetermined process node is confirmed to be effective.

17. The quantum circuit element testing method according to claim 12, characterized in that, The test parameters include at least one of the following: spectrum test parameters, relaxation time parameters, decoherence time parameters, and readout test parameters.

18. The quantum circuit element testing method according to claim 9, characterized in that, Multiple quantum circuit elements are arranged in an array on the superconducting quantum wafer, and the test results include a two-dimensional distribution map; The step of outputting the corresponding test results based on the test parameters includes: A wafer coordinate system is established based on the arrangement of the quantum circuit elements on the superconducting quantum wafer. Based on the test parameters of each quantum circuit element, the parameter values ​​of each quantum circuit element are determined; Based on the parameter values ​​of each quantum circuit element and the position coordinates of the quantum circuit element in the wafer coordinate system, a two-dimensional distribution map of the superconducting quantum wafer is generated. The two-dimensional distribution map is used to characterize the spatial distribution of each parameter value on the superconducting quantum wafer.

19. The quantum circuit element testing method according to claim 18, characterized in that, The parameter values ​​include at least one of the following: quantum bit frequency value, energy relaxation time value, decoherence time value, or JJ resistance value; and the two-dimensional distribution map includes at least one of the following: frequency map, T1 map, decoherence time map, or JJ resistance map.

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