Wafer level HTOL reliability risk assessment and grading method and system

Abstract

The application relates to the technical field of silicon optical chip reliability testing, in particular to a wafer-level HTOL reliability risk evaluation and grading method and system, which prepositions the HTOL reliability evaluation from the post-packaging stage to the wafer CP stage, and the single-die evaluation only needs about 30 seconds, the long-term reliability risk can be predicted before the chip packaging, the whole-link cost waste caused by the failure after the packaging is avoided, the reliability verification is matched with the rapid mass production rhythm of the 800G / 1.6T silicon optical chip, the three-level grading multiplexing is realized based on the double mechanism of the reliability score and the critical value one-vote veto, the edge qualified chips directly discarded in the traditional scheme are shunted to the number of channels, the consumer level and other scenes according to the grades, the wafer value is maximized, and the packaging material loss and the terminal repair cost are significantly reduced. In addition, the rule determination logic based on the physical mechanism is adopted, a model does not need to be trained by relying on historical failure samples, and the problem that the existing data-driven prediction scheme cannot be landed in the new product stage is solved.

Description

Technical Field

[0001] This application relates to the field of silicon photonics chip reliability testing technology, specifically a wafer-level HTOL reliability risk assessment and classification method and system. Background Technology

[0002] With the upgrading of data center bandwidth requirements, 800G / 1.6T optical modules have become the mainstream in mass production, and silicon photonics chips have become the core solution due to their high integration, low power consumption, and multi-channel parallel advantages. The reliability of high-speed silicon photonics chips is the core threshold for commercial application. The industry generally follows Telcordia GR-468 "Generic Reliability Assurance Requirements for Optoelectronic Devices" standard for reliability verification, among which HTOL testing (typical conditions 85℃ / 2000h) is the core item for evaluating long-term operational reliability.

[0003] The current industry standard process is as follows: wafer manufacturing, wafer probe testing (CP, which only performs yield screening and determines whether the parameters meet the specifications), chip dicing, packaging, and post-packaging HTOL (High Temperature Operating Life) reliability verification.

[0004] This process presents significant industry pain points: HTOL testing cycles can last for thousands of hours, and by the time verification is complete, the product has already undergone iterations and upgrades; furthermore, discovering unreliable chips only after packaging leads to wasted costs across the entire packaging, assembly, and testing chain, with losses being particularly pronounced in high-value 800G / 1.6T multi-channel chip scenarios. As Herrick pointed out in his invited paper at IEEE IRPS2024, reliability testing of silicon photonics and optoelectronic devices needs to focus on key reliability issues in field deployments and differ from general methods for electronic reliability testing. The testing platform needs to make differentiated choices between sub-component and component levels. Meanwhile, Li Yu et al., in their 2024 review in the *Acta Optica Sinica*, pointed out that large-scale silicon-based optoelectronic integrated chips have entered the stage of annual production in the millions, but reliability, durability, and compatibility verification with the functional development ecosystem are relatively limited. Consistency control and reliability verification are the core challenges of large-scale manufacturing. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a wafer-level HTOL reliability risk assessment and classification method and system to solve the problems in the background art.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] This application discloses a wafer-level HTOL reliability risk assessment and classification method, including the following steps:

[0008] Reliability parameters are tested for all channels of each die in the wafer under test to obtain wafer-level optoelectronic parameter test data;

[0009] The channel features of each grain are extracted from the test data. When the number of channels in the grain is one, the channel features include multiple single-channel morphological features. When the number of channels in the grain is multiple, the channel features include multiple single-channel morphological features and multi-channel dispersion features. The single-channel morphological features include risk assessment benchmark features.

[0010] Combining the channel characteristics, preset channel characteristic warning values, and channel characteristic weights, the reliability score of each chip is calculated; and the critical value of the pre-calibrated risk assessment benchmark characteristic is obtained; the chip whose risk assessment benchmark characteristic value exceeds the critical value is determined as the lowest level; for the chip whose risk assessment benchmark characteristic value does not exceed the critical value, the chip is classified based on the reliability score.

[0011] In one embodiment of this application, the risk assessment benchmark features include the slope of the germanium-silicon photodetector and the leakage current of the Mach-Zehnder modulator; the critical values ​​of the risk assessment benchmark features include the critical value of the slope of the germanium-silicon photodetector and the critical value of the leakage current of the Mach-Zehnder modulator.

[0012] In one embodiment of this application, after classifying based on the reliability score, the method further includes: sorting the dies of different reliability levels to different storage locations to connect with the subsequent packaging production line.

[0013] In one embodiment of this application, reliability parameter tests are performed on all channels of each die in the wafer under test to obtain wafer-level optoelectronic parameter test data, including:

[0014] The wafer under test is fed into a probe testing platform, and under preset testing accuracy constraints, target test items are performed on each channel of each die of the wafer under test based on the probe testing platform. The target test items include:

[0015] Perform a reverse bias dark current-voltage scan based on a preset scan step size for each germanium-silicon photodetector and record the complete dark current-voltage curve.

[0016] Perform a reverse bias leakage current test on each Mach-Zehnder modulator under a preset half-wave voltage bias to obtain reverse bias leakage current test data.

[0017] The resistance value at room temperature and the temperature coefficient of resistance within a preset temperature range were tested for each thermo-optical heater.

[0018] By using on-chip test structure and end face coupling test, the on-chip insertion loss, optical port insertion loss and center wavelength of each channel were collected respectively.

[0019] The test accuracy constraints include: using a high-precision measurement unit with a current measurement accuracy less than or equal to the target current value to perform leakage current testing; repeating the test multiple times for each set of dark current-voltage curves and using median filtering to remove noise from a single test; and ensuring that the voltage stabilization delay is greater than or equal to a preset duration.

[0020] In one embodiment of this application, the single-channel morphological features include the slope of the germanium-silicon photodetector, the breakdown voltage value, the absolute value of the reverse bias leakage current and the linearity of the bias voltage, the leakage current of the Mach-Zehnder modulator, the deviation rate of the temperature coefficient of resistance from the preset process baseline, and the insertion loss difference.

[0021] The extraction of single-channel morphological features for each grain from the test data includes:

[0022] The leakage current slope of the low bias segment is extracted from the dark current-voltage curve to obtain the slope of the germanium-silicon photodetector, and the breakdown voltage value corresponding to the soft breakdown inflection point of the curve is extracted from the dark current-voltage curve.

[0023] Extract the absolute value of the reverse-bias leakage current and the linearity of the bias voltage, as well as the Mach-Zehnder modulator leakage current, from the reverse-bias leakage current test data.

[0024] Calculate the deviation rate between the temperature coefficient of resistance and the preset process baseline. , wherein the deviation rate The formula for calculation is:

[0025]

[0026] In the formula, The temperature coefficient of resistance. This serves as the process baseline;

[0027] Calculate the difference between the on-chip insertion loss and the optical port insertion loss for the same channel.

[0028] In one embodiment of this application, the process baseline is a design simulation value or a historical statistical value from multiple batches.

[0029] In one embodiment of this application, when the number of channels of the grain is multiple, the multi-channel dispersion feature includes the standard deviation and range of each single-channel morphological feature of multiple channels of each grain, and includes the maximum value of the feature difference between adjacent channels.

[0030] In one embodiment of this application, the reliability score of each grain is calculated by combining the channel characteristics, a preset channel characteristic warning value, and a channel characteristic weight, including:

[0031] The deviation between the value of a single channel feature and a preset channel feature warning value is calculated. Based on the deviation, a single reliability score for the single channel feature is assigned. The greater the deviation between the value of the channel feature and the preset channel feature warning value, the higher the reliability risk of the channel feature and the lower the single reliability score.

[0032] The reliability score of the grain is obtained by weighted summation of the individual reliability scores of multiple channel features based on the preset channel feature weights.

[0033] In one embodiment of this application, the critical value of the risk assessment benchmark characteristic is calibrated, including:

[0034] Based on the Shockley-Reid-Hall defect evolution theory and the physical model of germanium-silicon PN junctions, a quantitative relationship between the slope of the dark current in the low-bias segment and the interface state density is established:

[0035]

[0036] In the formula, It is the reverse dark current. The amount of electron charge. Intrinsic carrier concentration, The width of the exhaustion region, For defect capture section, The thermal velocity of charge carriers. The density of states at the interface;

[0037] In the quantitative formula, when the interface state density exceeds a preset density threshold, it is determined to be a defect state saturation critical point, and the depletion region width of the current process node is substituted into it. With defect capture section The theoretical critical value of the slope of the germanium-silicon photodetector was calculated.

[0038] Differentiated accelerated stresses are configured based on the degradation activation energies of different devices, and accelerated calibration tests are performed to obtain calibration test data. Based on the calibration test data and the theoretical critical value of the slope of the germanium-silicon photodetector, the critical value of the slope of the germanium-silicon photodetector and the critical value of the leakage current of the Mach-Zehnder modulator are determined.

[0039] In one embodiment of this application, differentiated accelerated stress is configured based on the degradation activation energy of different devices, and accelerated calibration tests are performed to obtain calibration test data; and based on the calibration test data and the theoretical critical value of the slope of the germanium-silicon photodetector, the critical value of the slope of the germanium-silicon photodetector and the critical value of the leakage current of the Mach-Zehnder modulator are determined, including:

[0040] To address the interface state degradation of germanium-silicon photodetectors, a first experiment was conducted using a first acceleration temperature and a first acceleration duration, resulting in the dark current-voltage curves of the germanium-silicon photodetectors and the reverse bias leakage current data of the Mach-Zehnder modulators for each experimental sample.

[0041] Based on the general reliability assurance requirements standard for optoelectronic devices, the samples that have completed the first test are divided into a failure group and a pass group;

[0042] Extract the dark current low-bias slope data of the germanium-silicon photodetector measured in accelerated testing of the samples of the failed group and the qualified group, and select the value that best distinguishes the failed group and the qualified group within a preset percentage range based on the theoretical critical value, as the critical value of the slope of the germanium-silicon photodetector.

[0043] The critical value of the leakage current of the Mach-Zehnder modulator is determined based on the jump value when the reverse bias leakage current of the Mach-Zehnder modulator undergoes dielectric breakdown during the accelerated calibration test.

[0044] In one embodiment of this application, it further includes:

[0045] To address thermal fatigue or electromigration degradation of metal leads, a second experiment was conducted using a second acceleration temperature and a second acceleration duration to obtain resistance drift data of the thermo-optical heater under high-temperature stress.

[0046] The average drift rate of the target duration prior to the first experiment is taken as the first mapping index;

[0047] The slope of the linear fit throughout the second experiment is taken as the second mapping index;

[0048] By statistically analyzing data from multiple batches of accelerated calibration tests, empirical lookup tables were established for the drift of the first mapping index, the second mapping index, and the corresponding parameters after the standard high-temperature working life test.

[0049] For each drift rate in the experience lookup table, the measured drift values ​​from multiple standard high-temperature working life tests are fitted with a normal distribution, and the upper limit of the 95% prediction interval on one side is taken as a conservative estimate.

[0050] In one embodiment of this application, the grading based on the reliability score includes:

[0051] The reliability score is compared with the score range of multiple preset grading levels;

[0052] When the reliability score falls within the range of any grade level, the corresponding grade level is output, wherein the number of grade levels is determined according to the specific scenario.

[0053] In one embodiment of this application, the channel features further include optical crosstalk features and thermal crosstalk features.

[0054] This application also provides a wafer-level HTOL reliability risk assessment and classification system, including:

[0055] The test module is used to perform reliability parameter tests on all channels of each die in the wafer under test, and obtain wafer-level optoelectronic parameter test data;

[0056] The feature extraction module is used to extract the channel features of each grain from the test data. When the number of channels in the grain is one, the channel features include multiple single-channel morphology features. When the number of channels in the grain is multiple, the channel features include multiple single-channel morphology features and multi-channel dispersion features. The single-channel morphology features include risk assessment benchmark features.

[0057] The risk grading assessment module is used to calculate the reliability score of each chip by combining preset channel feature warning values ​​and weights; and to obtain the critical value of the pre-calibrated risk assessment benchmark feature; to determine the grading of the chip whose risk assessment benchmark feature value exceeds the critical value as the lowest level; and to grade the chip whose risk assessment benchmark feature value does not exceed the critical value based on the reliability score.

[0058] The beneficial effects of this application are as follows: This application provides a wafer-level HTOL reliability risk assessment and classification method and system, which moves the HTOL reliability assessment from post-packaging (requiring 2000 hours) to the wafer CP stage. The assessment of a single die takes only about 30 seconds, allowing for the prediction of long-term reliability risks before chip packaging. This avoids the waste of end-to-end costs caused by post-packaging failures, ensuring that reliability verification matches the rapid mass production pace of 800G / 1.6T silicon photonics chips. It breaks through the existing binary judgment mode of "qualified / scrapped" in the CP process, achieving three-level classification and reuse based on a dual mechanism of reliability scoring and critical value veto. This diverts edge-qualified chips that would be directly scrapped in traditional solutions to data communication-level, consumer-level, and other scenarios according to their level, maximizing wafer value and significantly reducing packaging material loss and end-product repair costs. It adopts a rule-based judgment logic based on physical mechanisms, eliminating the need to rely on historical failure samples to train the model. New products can be imported and the system can be deployed immediately, solving the problem that existing data-driven prediction solutions cannot be implemented in the new product stage. In addition, the present invention has significant economic benefits in mass production scenarios: by pre-classifying and screening, the material loss caused by failure after packaging can be greatly reduced. At the same time, edge qualified chips that are directly scrapped in traditional solutions can be graded and reused in data communication, consumer and other scenarios, which significantly improves the overall wafer utilization rate and reduces the cost of terminal repair. Attached Figure Description

[0059] The present application will be further described below with reference to the accompanying drawings and embodiments:

[0060] Figure 1 This embodiment provides a schematic diagram of the architecture of a wafer-level HTOL reliability risk assessment and classification system.

[0061] Figure 2 This is a flowchart illustrating a wafer-level HTOL reliability risk assessment and classification method in one embodiment of this application;

[0062] Figure 3 This is a logic structure diagram of a wafer-level HTOL reliability risk assessment and classification system shown in one embodiment of this application. Detailed Implementation

[0063] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0064] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the layers related to this application and are not drawn according to the actual number, shape and size of the layers in the actual implementation. In the actual implementation, the form, number and proportion of each layer can be arbitrarily changed, and the layer layout may also be more complex.

[0065] Numerous details are explored in the following description to provide a more thorough explanation of embodiments of this application; however, it will be apparent to those skilled in the art that embodiments of this application may be practiced without these specific details.

[0066] Figure 1 This embodiment provides a schematic diagram of the architecture of a wafer-level HTOL reliability risk assessment and classification system, as shown below. Figure 1 As shown, the system adopts a modular architecture and is deployed as a whole in the existing wafer probe testing production line without the need for large-scale hardware modifications. The modules achieve data interaction and control linkage through an industrial bus. The system specifically includes the following four core units:

[0067] Wafer probe testing unit: This unit serves as the data entry point for the system, i.e., the hardware carrier for parameter acquisition. It holds the wafer under test, contacts the chip pads via a high-precision probe card, and uses the source measurement unit (SMU) and optical coupling module to acquire raw photoelectric parameters (such as dark current IV curves, MZM reverse bias leakage current, etc.) for all channels within the same die. The raw test data is then sent to the data processing unit.

[0068] Data Processing Unit: Serving as the intermediate processing stage of the system, this unit is the hardware carrier for feature extraction. It communicates with the wafer probe testing unit, receives raw test data, performs noise reduction and normalization on the data using a built-in industrial computing module, and extracts single-channel morphological features (such as the slope of the low-bias section of dark current) and multi-channel dispersion features within the same wafer, generating standardized feature vectors that are output to the risk assessment unit.

[0069] Risk Assessment Unit: This unit serves as the core of the system's decision-making process, housing the hardware implementation of the rule-based decision-making logic. It is equipped with storage media containing a library of physical degradation mechanism rules and parameter thresholds derived from the SRH physical model and hierarchical accelerated calibration experiments. This unit receives feature vectors, executes unsupervised physical rule-based decision-making logic, outputs the HTOL reliability risk score and risk level for a single chip, and supports dynamic updates to the threshold library based on data feedback from the accelerated calibration unit.

[0070] Sorting Execution Unit: As the execution terminal of the system, this unit is the hardware carrier for the hierarchical output function. It communicates with the risk assessment unit, receives risk level instructions, and controls the sorting robot to sort chips of different reliability into corresponding wafer storage boxes (such as the first storage box, the second storage box, and the third storage box), thus realizing physical sorting.

[0071] In addition, the system may optionally include an accelerated test calibration unit, which is connected to the risk assessment unit for receiving accelerated calibration test data of representative chips extracted from each batch, and for feedback calibration of the physical failure threshold and scoring threshold in the risk assessment unit based on the test results, so as to realize adaptive closed-loop control under process fluctuations.

[0072] Figure 2 This is a flowchart illustrating a wafer-level HTOL reliability risk assessment and classification method in one embodiment of this application, as shown below. Figure 2 As shown, a wafer-level HTOL reliability risk assessment and classification method in this application mainly includes the following steps:

[0073] S210 involves performing reliability parameter tests on all channels of each die in the wafer under test to obtain wafer-level optoelectronic parameter test data. The specific test process includes:

[0074] After the wafer under test is transferred to the probe station, under preset test accuracy constraints, the following tests are sequentially performed on each channel of each die of the wafer under test based on the probe test platform:

[0075] (1) Perform the following steps on each Ge-Si (germanium-silicon) photodetector. Reverse bias IV (dark current-voltage) scan, step size Record the complete IV curve.

[0076] (2) Test each MZM (Mach-Zehnder) modulator. Reverse bias leakage current under bias; This is the preset half-wave voltage.

[0077] (3) Test the resistance value of each thermo-photothermal heater at room temperature, and Temperature coefficient of resistance (TCR) in the range.

[0078] (4) Through on-chip test structure and end face coupling test, the on-chip insertion loss, optical port insertion loss and center wavelength of each channel are collected respectively.

[0079] The test accuracy constraints are as follows: This step uses the current measurement accuracy... High-precision SMU (Source Measurement Unit) execution Level leakage current test; each IV curve is tested 3 times, and median filtering is used to remove noise from a single test; voltage stabilization delay. This eliminates transient current interference during voltage establishment and ensures stable and reliable extraction of leakage current slope in the low bias segment.

[0080] S220, Extract the channel features of each grain from the test data;

[0081] Wherein, when the number of channels in the grain is one, the channel features include multiple single-channel morphological features;

[0082] When the grain has multiple channels, the channel features include multiple single-channel morphological features and multi-channel dispersion features, and the single-channel morphological features include risk assessment benchmark features;

[0083] For products with higher integration, additional feature dimensions such as optical crosstalk and thermal crosstalk can be added.

[0084] The channel features extracted in this application include two categories: single-channel morphological features and multi-channel dispersion features. The single-channel morphological features include the slope of the germanium-silicon photodetector, the breakdown voltage value, the absolute value of the reverse bias leakage current and the linearity of the bias voltage, the leakage current of the Mach-Zehnder modulator, the deviation rate of the temperature coefficient of resistance from the preset process baseline, and the insertion loss difference. When the number of channels of the die is multiple, the multi-channel dispersion features include the standard deviation and range of each single-channel morphological feature of multiple channels of each die, and include the maximum value of the feature difference between adjacent channels.

[0085] The specific extraction process of channel features includes:

[0086] S220-1, Extract the leakage current slope of the low-bias segment from the dark current-voltage curve to obtain the slope of the germanium-silicon photodetector, and extract the breakdown voltage value corresponding to the soft breakdown inflection point of the curve from the dark current-voltage curve.

[0087] Specifically, extract Leakage current slope in the low bias section And the voltage value corresponding to the soft breakdown inflection point of the curve.

[0088] S220-2, extract the linearity of the absolute value of the reverse-bias leakage current relative to the bias voltage and the Mach-Zehnder modulator leakage current from the reverse-bias leakage current test data.

[0089] S220-3, Calculate the deviation rate between the temperature coefficient of resistance and the preset process baseline. , wherein the deviation rate The formula for calculation is:

[0090]

[0091] In the formula, The temperature coefficient of resistance. This serves as the process baseline.

[0092] The process baseline is either a design simulation value or a historical statistical value from multiple batches. The rules for determining the baseline value are as follows:

[0093] For mature batches, the process baseline values ​​are obtained based on process design simulation or statistical data of historical qualified wafers from multiple batches.

[0094] When there is no historical data for a new product, the arithmetic mean of the TCR of the first 20 chips in this batch is taken as a temporary baseline. The system automatically verifies this baseline: if the TCR range of the sampled sample exceeds the upper limit of the process design tolerance, the sampling is automatically expanded to 30 chips and the baseline is recalculated to avoid extreme abnormal samples from skewing the baseline.

[0095] The mechanism and risk boundary of the process baseline are explained as follows: The TCR deviation rate of the thermo-optical heater reflects the uniformity of thin film doping and process defects at the metal-silicon interface. Under long-term HTOL high-temperature cycling, uneven doping will exacerbate local Joule heat concentration, indirectly accelerating the aging of the waveguide insulation layer and the thermal fatigue of the metal leads, which is an important auxiliary risk characteristic of thermal stress accumulation. Based on the simulation of the critical temperature difference for thin film thermal fatigue, a TCR deviation warning threshold is set: when the deviation is within ±2%, it is judged as a slight process deviation, which only slightly increases the individual risk score; when the deviation exceeds ±5%, it is judged as a thermal stress warning deviation, which significantly increases the individual risk score. This threshold does not trigger a veto, but only participates in the comprehensive scoring as a layered physical boundary.

[0096] S220-4, calculate the difference between the on-chip insertion loss and the optical port insertion loss for the same channel.

[0097] Specifically, the difference between the on-chip insertion loss and the optical port insertion loss of the same channel (this difference is the end-face coupling additional loss) is calculated to characterize the initial state of the end-face coupling structure. This difference directly reflects the coupling additional loss during the transmission of optical signals from inside the chip to the external optical fiber. If this difference is abnormally large in the CP stage, it often indicates the presence of microcracks, contamination, or film defects on the end face. These defects are easily further deteriorated under HTOL thermal stress and humid heat stress, and are important precursors to reliability failure.

[0098] S220-5, Multi-channel Discreteness Characteristics within the Same Grain: For all the single-channel parameters mentioned above, the standard deviation and range of all channels within the same grain are calculated separately as a quantitative characterization of global process stress non-uniformity, reflecting the overall uniformity of processes such as photolithography and annealing at the grain scale. Simultaneously, the maximum value of the difference between adjacent channels is calculated, and an error tolerance based on the repeatability accuracy of the test system is set. When this difference exceeds the error tolerance and is accompanied by specific physical characteristics (such as a synchronous abnormal increase in dark current in the channel or a sudden change in heater resistance), it is determined to be a non-systematic parameter jump caused by local micro-defects (such as particle contamination or local etching abnormalities). This indicator is highly sensitive to sudden physical damage, but the inherent noise introduced by the test system must be deducted during evaluation.

[0099] In their paper "Large-Scale Silicon-Based Optoelectronic Integrated Chip Technology and Challenges (Invited)" published in the 2024 issue of *Acta Optica Sinica* (Vol. 44, No. 15), Li Yu, Li Qiang, Liu Dapeng, Feng Junbo, and Guo Jin clearly pointed out that "the thickness and width of the TiN heater mainly affect the sheet resistance of the heater. When the thickness of the TiN heater is 100 nm, a thickness change of ±5 nm will cause a sheet resistance change of approximately ±0.75 Ω." Furthermore, "Large-scale optical computing network chips contain tens of thousands of TiN heaters. Phase modulation of the optical network based on design values ​​will lead to a decrease in the final computational accuracy of the system due to accumulated errors." Based on the process fluctuation patterns revealed in the aforementioned published literature, this invention extracts the thermal-optical heater TCR deviation rate as an auxiliary risk feature for thermal stress accumulation and sets an early warning threshold to participate in the comprehensive scoring.

[0100] S230, combining the channel characteristics, preset channel characteristic warning values ​​and channel characteristic weights, calculate the reliability score of each chip; and obtain the critical value of the pre-calibrated risk assessment benchmark characteristics; determine the classification of chips whose risk assessment benchmark characteristics exceed the critical value as the lowest level; for chips whose risk assessment benchmark characteristics do not exceed the critical value, classify them based on the reliability score.

[0101] (1) The methods for calculating reliability scores include:

[0102] S230-1, Calculate the deviation between the value of a single channel feature and the preset channel feature warning value, and assign a value to the single reliability score of the single channel feature based on the deviation. The larger the deviation between the value of the channel feature and the preset channel feature warning value, the higher the reliability risk of the channel feature and the lower the single reliability score.

[0103] The deviation calculation methods can include linear relative deviation, difference normalization, etc., which will not be elaborated here.

[0104] S230-2, based on the preset channel feature weights, performs a weighted summation of the individual reliability scores of multiple channel features to obtain the reliability score of the grain.

[0105] The channel feature weights are allocated based on the contribution of each feature parameter to the physical degradation of HTOL failure. An exemplary contribution coefficient allocation rule is as follows (not intended to limit the scope of this invention):

[0106] PD dark current low-bias slope: approximately 35% (directly reflects defect state density, and is the main degradation mechanism);

[0107] MZM reverse bias leakage current linearity: approximately 20% (corresponding to waveguide insulation quality);

[0108] Heater TCR deviation rate: approximately 15% (reflecting the degree of local thermal stress concentration);

[0109] Coupling loss difference: approximately 10% (characterizing the quality of the end face interface);

[0110] Total dispersion of multiple channels within the same grain: approximately 20% (verified by process simulation, the contribution of local hot spots caused by process inhomogeneity within the same grain to failure is approximately 25% of the sum of the aforementioned four items, rounded to 20%).

[0111] The aforementioned contribution coefficients (weights) can be adjusted within ±5% of the base value based on the failure mode analysis results of different process nodes. The initial values ​​of the contribution coefficients are obtained from TCAD process simulation and failure mode contribution analysis (FMEA), reflecting the inherent influence weight of each physical characteristic on the long-term degradation of the device. During the mass production ramp-up phase, the contribution coefficients can be iteratively converged and fine-tuned based on comparative data from multiple batches of accelerated calibration tests and 2000h HTOL verification results to ensure that the scoring system remains consistent with actual failure patterns.

[0112] Example calculation: If a chip's PD slope reaches 40% of the warning value (i.e., a safety margin of 60%, a single-item score of 60 points × 35% = 21 points), and its MZM leakage current reaches 60% of the warning value (i.e., a safety margin of 40%, a single-item score of 40 points × 20% = 8 points), while other characteristics are normal (assuming each of the other characteristics scores 100 points, totaling 45 points), then the overall score = 21 + 8 + 45 = 74 points (Level 2). This rule fully covers scenarios where multiple characteristics are simultaneously high, avoiding a disconnect between the classification results and the actual risk.

[0113] In one embodiment of this application, the risk assessment benchmark features include the slope of the germanium-silicon photodetector and the leakage current of the Mach-Zehnder modulator; the critical values ​​of the risk assessment benchmark features include the critical value of the slope of the germanium-silicon photodetector and the critical value of the leakage current of the Mach-Zehnder modulator.

[0114] (2) The process of calibrating the critical values ​​of the risk assessment benchmark characteristics includes:

[0115] Based on the Shockley-Reid-Hall defect evolution theory and the germanium-silicon PN junction physical model, S230-3 establishes a quantitative relationship between the slope of the low-bias segment of dark current and the interface state density:

[0116]

[0117] In the formula, It is the reverse dark current. The amount of electron charge. Intrinsic carrier concentration, The width of the exhaustion region, For defect capture section, The thermal velocity of charge carriers. The density of states at the interface;

[0118] Based on the SRH (Shockley-Reid-Hall) defect evolution theory and the Ge-SiPN junction physical model, the slope of the low-bias segment of the dark current is established. With interface state density Quantitative relationship: Under the same process platform and the same test temperature, All are constant values, therefore the dark current The size is essentially determined by the width of the exhaustion region. and interface state density A joint decision.

[0119] S230-4, in the quantitative formula, when the interface state density exceeds a preset density threshold, it is determined to be a defect state saturation critical point, and the depletion region width of the current process node is substituted into it. With defect capture section The theoretical critical value of the slope of the germanium-silicon photodetector was calculated.

[0120] Specifically, for The curve in the low bias voltage range Taking the derivative, we can know and They show a linear positive correlation. When Exceed At this point, the defect-assisted tunneling effect kicks in, and the device degradation rate changes from linear to exponential growth; this point is the defect-state saturation critical point. Substituting the depletion region width under this process node... Defect capture section Parameters, theoretical calculations yield the corresponding Theoretical critical value.

[0121] Those skilled in the art should understand that the aforementioned depletion region width Defect capture section The parameters are example values ​​for specific process nodes. For different silicon photonics process platforms (such as differences in SOI buried oxide layer thickness, differences in Ge-Si epitaxial doping concentration, etc.), the actual device structure parameters can be substituted into the SRH quantitative relationship to recalculate, and then calibrated through the layered accelerated calibration test to obtain the theoretical critical value that is suitable for the process node.

[0122] S230-5, based on the degradation activation energy of different devices, configure differentiated accelerated stress, perform accelerated calibration tests, and obtain calibration test data; and based on the calibration test data and the theoretical critical value of the slope of the germanium-silicon photodetector, determine the critical value of the slope of the germanium-silicon photodetector and the critical value of the leakage current of the Mach-Zehnder modulator, including:

[0123] S230-5-1, targeting the interface state degradation of germanium-silicon photodetectors, a first experiment was conducted using a first acceleration temperature and a first acceleration duration to obtain the dark current-voltage curves of germanium-silicon photodetectors and the reverse bias leakage current data of the Mach-Zehnder modulator for each test sample.

[0124] Specifically, regarding the degradation of Ge-Si PD interface states (activation energy) ,Pick Example): Based on the Arrhenius acceleration model Boltzmann constant , , Substitute into the calculation to obtain the acceleration factor (Right now The equivalent 85℃ standard HTOL duration is ≥1500h, covering the degradation behavior of the middle and later stages of the device.

[0125] In his invited paper "Reliability testing for silicon photonics and optoelectronics" presented at the 2024 IEEE International Reliability Physics Symposium (IRPS), Robert W. Herrick pointed out that the reliability assessment of optoelectronic devices needs to cover component-level testing and the engineering applications of different testing platforms. Different device types require different test stress conditions, which is in complete agreement with the core idea of ​​the "layered acceleration" of this invention.

[0126] S230-5-2, targeting thermal fatigue or electromigration degradation of metal leads, a second test was conducted using a second acceleration temperature and a second acceleration duration to obtain resistance drift data of the thermo-optic heater under high-temperature stress.

[0127] Specifically, this addresses thermal fatigue or electromigration of metal leads (taking... Example): Substitute into the calculation to obtain the acceleration factor The equivalent 85℃ is close to 2000h. In the article "Large-scale silicon-based optoelectronic integrated chip technology and challenges (invited)" published in the Journal of Optics, Vol. 44, No. 15, 2024, Li Yu, Li Qiang, Liu Dapeng, Feng Junbo, and Guo Jin pointed out that the sheet resistance of TiN heaters, as the core component of thermo-optical phase shifters, is affected by process parameters such as thickness and width, and exhibits obvious spatial distribution differences within a single chip (the median sheet resistance of 55 TiN heaters is 13.462Ω / sq, with a distribution range of 13.284~13.579Ω / sq). Different device types have significantly different sensitivities to process fluctuations, further confirming the necessity of the present invention's "differentiated configuration of accelerated stress according to device type".

[0128] S230-5-3, based on the general reliability assurance requirements standard for optoelectronic devices, divides the samples that have completed the first test into a failure group and a qualified group;

[0129] S230-5-4, Extract the dark current low-bias slope data of the germanium-silicon photodetector measured in the accelerated test of the samples of the failed group and the qualified group, and select the value that best distinguishes the failed group and the qualified group within a preset percentage range based on the theoretical critical value, as the critical value of the slope of the germanium-silicon photodetector.

[0130] S230-5-5, Based on the jump value of the reverse bias leakage current of the Mach-Zehnder modulator when dielectric breakdown occurs during the accelerated calibration test, determine the critical value of the leakage current of the Mach-Zehnder modulator.

[0131] In steps S230-5-3 to S230-5-5, several test samples are selected to perform the aforementioned accelerated calibration test. Based on the GR-468 standard, the samples are divided into a failure group and a pass group. By comparing the measured slope data of the two groups, the aforementioned theoretical critical value is fine-tuned within a range of ±10% to obtain the final physical failure critical value used for engineering veto. The core logic of this threshold setting is not to pursue absolute lifetime equivalence with 2000h HTOL, but rather to achieve advanced prediction of long-term failure risks by capturing the drift rate characteristics in the early stages of the accelerated phase.

[0132] In addition, if the process baseline drift exceeds the process design tolerance for 5 consecutive batches, the theoretical critical value will be updated again based on the SRH defect evolution theory and the Ge-Si PN junction physical model, and then a second calibration test will be performed. Regular production batches will only be fine-tuned within ±10% based on historical theoretical values, without the need to re-derive the theoretical values.

[0133] S230-5-6, take the average drift rate of the target duration before the first experiment as the first mapping index; take the linear fitting slope of the entire second experiment as the second mapping index;

[0134] S230-5-7, through statistical analysis of multiple batches of accelerated calibration test data, establish empirical lookup tables for the drift of the first mapping index, the second mapping index and the corresponding parameters after the standard high temperature working life test;

[0135] S230-5-8, for each drift rate in the experience lookup table, fit a normal distribution to the measured drift amount of multiple sets of standard high temperature working life tests, and take the upper limit of the 95% prediction interval on one side as a conservative estimate.

[0136] In steps S230-5-6 to S230-5-8, to adapt to the nonlinear characteristics of silicon photonic device degradation, a reliable mapping relationship of "accelerated stage drift rate → standard HTOL long-term degradation amplitude" is established: For the non-monotonic degradation characteristics of Ge-Si PD dark current, which may involve passivation followed by proliferation, the average drift rate in the first 72 hours of accelerated calibration is used as the mapping index (avoiding the initial passivation stage); for the monotonic degradation characteristics of the thermo-optical heater resistance, the linear fitting slope throughout the accelerated calibration test is used as the mapping index. Through statistical analysis of multiple batches of accelerated calibration test data, an empirical lookup table is established comparing the above mapping indices with the parameter drift after 2000 hours of HTOL.

[0137] Statistical definition: For each drift rate, multiple sets of measured drift values ​​over 2000 hours are fitted with a normal distribution. The upper limit of the 95% prediction interval on one side is taken as a conservative estimate (i.e., there is a 95% probability that future observed values ​​will be lower than this upper limit) to cover the impact of process fluctuations. This statistical method is used uniformly for both the PD and the heater to ensure that the mapping rules are reproducible.

[0138] (3) Dual Judgment Mechanism: Two sets of judgment logic are executed in parallel, with the priority of a veto being higher than the comprehensive score, including:

[0139] Hard judgment (one-vote veto): If any core feature touches the physical failure threshold value marked in step (1) above (such as the PD dark current slope touching the defect state saturation threshold, or the MZM reverse bias leakage current touching the dielectric breakdown threshold), then regardless of its comprehensive score result, the one-vote veto mechanism will be directly triggered, and the chip will be forcibly rated as level three (downgrade / consumer grade), because it indicates that the device will suffer irreversible sudden physical damage.

[0140] Soft judgment (comprehensive score): If no feature reaches the physical failure threshold, the classification is based on the quantitative score obtained from the comprehensive calculation.

[0141] If no physical failure threshold is reached due to any characteristic, the grading process includes:

[0142] S230-6, compare the reliability score with the score range of a preset multiple grading levels;

[0143] S230-7 When the reliability score falls within the score range of any one of the grading levels, the corresponding grading level is output, wherein the number of grading levels is determined according to the specific scenario.

[0144] For example, based on a preset scoring threshold, the chips are divided into three reliability levels and sorted into the corresponding categories:

[0145] Level 1 (Telecom Grade): Score ≥ 85 points, lowest failure risk, meets the stringent long-term reliability requirements of telecom grade optical modules;

[0146] Level 2 (Data Communication Level): Score of 60-85 points, failure risk is controllable, meeting the reliability requirements of 800G / 1.6T short-distance optical modules in data centers; among them, chips with a nominal rate of 1.6T but rated as Level 2 data communication level can be downgraded to match high reliability scenarios with 800G rate;

[0147] Level 3 (Downgrade / Consumer Grade): This level is divided into two categories. First, chips that trigger a veto mechanism are at risk of sudden physical damage and are directly classified as Level 3. Second, chips that do not trigger a veto but have a comprehensive score <60 points are at risk of insufficient expected lifespan and are also classified as Level 3. Chips of this level have a high failure risk and are not suitable for high-reliability scenarios. They can be downgraded for low-speed, consumer-grade scenarios or directly deemed unusable.

[0148] At this point, each die in the wafer under test has completed the entire risk assessment process, from channel testing and feature extraction to dual judgment and grade output. Based on the currently calibrated physical critical values ​​and the preset scoring warning values, the system can perform reliability classification of the production line wafers.

[0149] However, the silicon photonics chip manufacturing process itself has inherent fluctuations between batches and wafers. For example, the distribution of parameters such as Ge-Si epitaxial layer thickness, waveguide etching depth, and TiN heater sheet resistance will slowly drift with factors such as process chamber conditions, substrate batches, and ambient temperature and humidity. If the critical values ​​and warning values ​​remain fixed for a long time, the overall shift of the feature baseline caused by process fluctuations will directly distort the accuracy of risk assessment.

[0150] To this end, the system incorporates the following closed-loop calibration mechanism, which uses process fluctuation monitoring data as feedback to dynamically and adaptively adjust critical values ​​and scoring thresholds, ensuring that the evaluation criteria evolve in sync with the process status.

[0151] Set up a closed-loop calibration mechanism to adapt to batch process fluctuations:

[0152] Eight to twelve representative dies were selected from each batch of wafers to perform accelerated calibration tests and monitor the drift trend of key characteristic parameters.

[0153] The threshold calibration process is triggered when the drift amplitude of key characteristic parameters in three consecutive batches of accelerated calibration test samples exceeds three times the standard deviation of the historical mean. The historical mean is the arithmetic mean of the drift amplitudes of key characteristic parameters in the accelerated calibration test samples of at least five batches of qualified wafers at the same process node; the standard deviation is the standard deviation of the drift amplitudes of key characteristic parameters in the accelerated calibration test samples of at least five batches of qualified wafers at the same process node.

[0154] Based on the drift results, the physical failure threshold and scoring threshold are fine-tuned until the grading results of two consecutive batches have a consistency of ≥90% with the long-term HTOL (i.e., 2000h standard high-temperature working life) verification results, thus achieving adaptive closed-loop control under process fluctuations. If high-precision statistical estimation with a 95% confidence interval is required, the sampling can be expanded to more than 16 units. The routine screening on the production line uses a small sample and only performs relative threshold fine-tuning without rigorous statistical estimation.

[0155] If there is no historical batch data for a new product, it will be temporarily cancelled. The trigger condition is that the threshold is manually fine-tuned by engineers based on their experience, and the automatic calibration logic is enabled after enough batch data has been accumulated.

[0156] The S240 sorts dies of different reliability levels into different storage slots to connect with the subsequent packaging production line.

[0157] Finally, based on the risk score results, chips with different reliability levels are sorted into different storage slots and connected to the subsequent packaging production line.

[0158] The test results of this application will be shown below with a specific embodiment.

[0159] Experimental Design: Three batches (A, B, and C) of 800G silicon photonics wafers with different processes were selected. Sixteen wafers were randomly selected from each batch, resulting in a total of 48 valid experimental samples. Accelerated calibration tests were performed (PD: 150℃ / 168h, metal: 125℃ / 72h). Each batch of samples was matched to two groups based on initial parameter distribution, with eight wafers in each group: one group underwent 2000h standard HTOL verification (control group, 24 wafers in total), and the other group underwent risk assessment and grading at the CP stage using the method of this invention (experimental group, 24 wafers in total).

[0160] Calculation criteria for quantitative indicators:

[0161] 1. Predictive Consistency: This measures the consistency between the classification results of this scheme and the validation results of the 2000h standard HTOL. A higher consistency indicates better evaluation accuracy. The calculation formula is as follows:

[0162] 2. Reduction in Packaging Scrap Rate: The cost savings of this solution compared to traditional screening methods are quantified using the following formula:

[0163] 3. Wafer utilization improvement ratio: This quantifies the effectiveness of this solution in unlocking the value of wafers. The calculation formula is as follows:

[0164] Example of experimental statistical results:

[0165] Of the 24 samples in the experimental group, a total of 7 primary chips, 14 secondary chips, and 3 tertiary chips were screened out.

[0166] After 2000 hours of standard HTOL testing on 24 samples from the control group: the failure rate of samples classified as Level 1 in the experimental group was 0%; the failure rate of samples classified as Level 2 in the experimental group was 7.1% (1 out of 14 samples had excessive parameter drift); and the failure rate of samples classified as Level 3 in the experimental group was 66.7% (2 out of 3 samples showed dark current breakdown failure).

[0167] The comparison results showed that the experimental group's prediction accuracy reached 91.7%;

[0168] Traditional binary screening uses an industry-standard single-parameter threshold rule for dark current, which determines wafers as scrap if the dark current exceeds the specification limit. By introducing a hierarchical reuse mechanism, wafer utilization is improved by approximately 15% compared to traditional binary screening; and the scrap rate due to reliability issues after packaging is reduced by approximately 63% compared to the traditional process.

[0169] Conclusion: The above experimental data verify the significant effects of the method of the present invention in shortening the verification cycle, reducing scrap costs, and improving wafer utilization.

[0170] Note: The above are exemplary test data under typical process nodes. Actual values ​​may vary depending on the wafer foundry's process platform and device structure design, and do not constitute a limitation on the scope of protection of this invention.

[0171] The beneficial effects of this application include:

[0172] (1) Pre-assessment of reliability and shortening of verification cycle: The present invention moves the HTOL reliability assessment process from the 2000h aging process after packaging to the wafer CP test process. The complete assessment process of a single die only takes about 30 seconds. Based on the verification of 48 control test samples in the same batch: the traditional binary fixed parameter screening scheme has a prediction accuracy of about 72% for the long-term reliability of the chip, while the graded judgment scheme of the present invention has an accuracy of up to 91.7%, which can match the mass production rhythm of data center optical modules with a rapid iteration of 12 months.

[0173] (2) Unsupervised physical judgment, rapid deployment of new products: This solution adopts an unsupervised judgment architecture of forward derivation of SRH theory + hierarchical accelerated calibration, which does not require accumulating a large number of historical failure samples to complete model training; compared with the traditional supervised data-driven prediction scheme, the cycle from production to the establishment of a reliability assessment system for the new silicon photonics process is shortened from 3 to 6 months to 1 week, which is suitable for the high-frequency iteration requirements of high-speed silicon photonics new products.

[0174] (3) Multi-dimensional feature fusion reduces the probability of missed detection: After multiple rounds of accelerated calibration tests, the "single-channel curve feature + multi-channel dispersion of the same grain + critical value veto" joint judgment method is adopted. Compared with the traditional single-parameter binary screening, the detection rate of sudden device damage caused by process micro-defects is increased from about 30% to more than 85%, and the early failure missed detection rate of devices is reduced from about 12% to less than 2%, effectively avoiding material loss caused by batch failure after packaging.

[0175] In their article "Large-Scale Silicon-Based Optoelectronic Integrated Chip Technology and Challenges (Invited)" published in the 44th volume, 15th issue of the Chinese Journal of Optics in 2024, Li Yu, Li Qiang, Liu Dapeng, Feng Junbo, and Guo Jin pointed out that large-scale silicon-based optoelectronic integrated chips face multi-level consistency problems at the batch, wafer, die, and design area levels. The "multi-channel dispersion of the same die" feature proposed in this invention is a quantitative characterization of such multi-level process fluctuations, in order to solve the defect of existing solutions that do not utilize dispersion fingerprint recognition for reliability.

[0176] (4) Differentiated layered acceleration to improve threshold calibration accuracy: Dedicated acceleration conditions are configured for the 0.7eV and 1.0eV differential degradation activation energies of Ge-SiPD and metal lead devices. Compared with the traditional scheme of uniform acceleration of all devices, the calibration equivalent error of physical failure threshold is reduced by more than 40%, which solves the shortcoming of single acceleration conditions that cannot be adapted to multiple types of silicon photonic devices.

[0177] In his invited paper "Reliability testing for silicon photonics and optoelectronics" presented at the 2024 IEEE International Reliability Physics Symposium (IRPS), Robert W. Herrick pointed out that the reliability assessment of optoelectronic devices needs to cover component-level testing and the engineering application of different testing platforms. Traditional post-packaging aging test platforms have inherent limitations in meeting the pace of large-scale mass production. This invention moves the reliability assessment to the wafer CP stage, which is a systematic solution to this limitation.

[0178] (5) Closed-loop adaptive calibration, compatible with process fluctuations: Build The closed-loop calibration logic of statistical threshold and small batch sampling fine-tuning can still maintain a graded judgment consistency of over 90% when the wafer process baseline has a drift of ±5%, thus making up for the lack of robustness of traditional fixed CP baseline.

[0179] (6) In addition, the present invention has significant economic benefits in mass production scenarios: by pre-grading screening, the material loss caused by failure after packaging can be greatly reduced, and the edge qualified chips that are directly scrapped in the traditional solution can be graded and reused to data communication level, consumer level and other scenarios, which significantly improves the overall utilization rate of wafers and reduces the cost of terminal repair.

[0180] like Figure 3 As shown, this application also provides a wafer-level HTOL reliability risk assessment and classification system, including:

[0181] The test module is used to perform reliability parameter tests on all channels of each die in the wafer under test, and obtain wafer-level optoelectronic parameter test data;

[0182] The feature extraction module is used to extract the channel features of each grain from the test data. When the number of channels in the grain is one, the channel features include multiple single-channel morphology features. When the number of channels in the grain is multiple, the channel features include multiple single-channel morphology features and multi-channel dispersion features. The single-channel morphology features include risk assessment benchmark features.

[0183] The risk grading assessment module is used to calculate the reliability score of each chip by combining preset channel feature warning values ​​and weights; and to obtain the critical value of the pre-calibrated risk assessment benchmark feature; to determine the grading of the chip whose risk assessment benchmark feature value exceeds the critical value as the lowest level; and to grade the chip whose risk assessment benchmark feature value does not exceed the critical value based on the reliability score.

[0184] This application presents a wafer-level HTOL reliability risk assessment and classification method and system. It moves HTOL reliability assessment from post-packaging (requiring 2000 hours) to the wafer CP stage, with a single die assessment taking only about 30 seconds. This allows for the prediction of long-term reliability risks before chip packaging, avoiding the waste of end-to-end costs caused by post-packaging failures, and ensuring that reliability verification matches the rapid mass production pace of 800G / 1.6T silicon photonics chips. It breaks through the existing binary judgment mode of "qualified / scrapped" in the CP process, achieving three-level classification and reuse based on a dual mechanism of reliability scoring and critical value veto. This involves diverting edge-qualified chips that would be directly scrapped in traditional solutions to data communication-level, consumer-level, and other scenarios according to their level, maximizing wafer value and significantly reducing packaging material loss and end-product repair costs. Employing a rule-based judgment logic based on physical mechanisms, it eliminates the need to rely on historical failure samples to train the model, allowing for immediate deployment upon new product import, solving the problem that existing data-driven prediction solutions cannot be implemented in the new product stage. In addition, the present invention has significant economic benefits in mass production scenarios: by pre-classifying and screening, the material loss caused by failure after packaging can be greatly reduced. At the same time, edge qualified chips that are directly scrapped in traditional solutions can be graded and reused in data communication, consumer and other scenarios, which significantly improves the overall wafer utilization rate and reduces the cost of terminal repair.

[0185] This embodiment also provides an electronic terminal, including: a processor and a memory;

[0186] The memory is used to store computer programs, and the processor is used to execute the computer programs stored in the memory to cause the terminal to perform any of the methods in this embodiment.

[0187] As will be understood by those skilled in the art, the computer-readable storage medium described in this embodiment allows for the implementation of all or part of the steps in the above method embodiments by computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0188] The electronic terminal provided in this embodiment includes a processor, a memory, a transceiver, and a communication interface. The memory and the communication interface are connected to the processor and the transceiver and complete communication between them. The memory is used to store computer programs, the communication interface is used to perform communication, and the processor and the transceiver are used to run the computer programs, so that the electronic terminal performs the steps of the above method.

[0189] In this embodiment, the memory may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0190] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0191] In the above embodiments, although the present application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. The embodiments of the present application are intended to cover all such substitutions, modifications, and variations falling within the broad scope of the appended claims.

[0192] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A wafer-level HTOL reliability risk assessment and classification method, characterized in that, Including the following steps: Reliability parameters are tested for all channels of each die in the wafer under test to obtain wafer-level optoelectronic parameter test data; The channel features of each grain are extracted from the test data. When the number of channels in the grain is one, the channel features include multiple single-channel morphological features. When the number of channels in the grain is multiple, the channel features include multiple single-channel morphological features and multi-channel dispersion features. The single-channel morphological features include risk assessment benchmark features. Combining the channel characteristics, preset channel characteristic warning values, and channel characteristic weights, the reliability score of each chip is calculated; and the critical value of the pre-calibrated risk assessment benchmark characteristic is obtained; the chip whose risk assessment benchmark characteristic value exceeds the critical value is determined as the lowest level; for the chip whose risk assessment benchmark characteristic value does not exceed the critical value, the chip is classified based on the reliability score.

2. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, The risk assessment benchmark features include the slope of the germanium-silicon photodetector and the leakage current of the Mach-Zehnder modulator; the critical values ​​of the risk assessment benchmark features include the critical values ​​of the slope of the germanium-silicon photodetector and the critical values ​​of the leakage current of the Mach-Zehnder modulator.

3. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, After classifying based on the aforementioned reliability score, the following is also included: Diodes of different reliability levels are sorted into different storage locations to be used in subsequent packaging production lines.

4. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, Reliability parameters were tested for all channels of each die in the wafer under test to obtain wafer-level optoelectronic parameter test data, including: The wafer under test is fed into a probe testing platform, and under preset testing accuracy constraints, target test items are performed on each channel of each die of the wafer under test based on the probe testing platform. The target test items include: Perform a reverse bias dark current-voltage scan based on a preset scan step size for each germanium-silicon photodetector and record the complete dark current-voltage curve. Perform a reverse bias leakage current test on each Mach-Zehnder modulator under a preset half-wave voltage bias to obtain reverse bias leakage current test data. The resistance value at room temperature and the temperature coefficient of resistance within a preset temperature range were tested for each thermo-optical heater. By using on-chip test structure and end face coupling test, the on-chip insertion loss, optical port insertion loss and center wavelength of each channel were collected respectively. The test accuracy constraints include: using a high-precision measurement unit with a current measurement accuracy less than or equal to the target current value to perform leakage current testing; repeating the test multiple times for each set of dark current-voltage curves and using median filtering to remove noise from a single test; and ensuring that the voltage stabilization delay is greater than or equal to a preset duration.

5. The wafer-level HTOL reliability risk assessment and classification method according to claim 4, characterized in that, The single-channel morphological characteristics include the slope of the germanium-silicon photodetector, the breakdown voltage value, the absolute value of the reverse bias leakage current and the linearity of the bias voltage, the leakage current of the Mach-Zehnder modulator, the deviation rate of the temperature coefficient of resistance from the preset process baseline, and the insertion loss difference. The extraction of single-channel morphological features for each grain from the test data includes: The leakage current slope of the low bias segment is extracted from the dark current-voltage curve to obtain the slope of the germanium-silicon photodetector, and the breakdown voltage value corresponding to the soft breakdown inflection point of the curve is extracted from the dark current-voltage curve. Extract the absolute value of the reverse-bias leakage current and the linearity of the bias voltage, as well as the Mach-Zehnder modulator leakage current, from the reverse-bias leakage current test data. Calculate the deviation rate between the temperature coefficient of resistance and the preset process baseline. , wherein the deviation rate The formula for calculation is: In the formula, The temperature coefficient of resistance. This serves as the process baseline; Calculate the difference between the on-chip insertion loss and the optical port insertion loss for the same channel.

6. The wafer-level HTOL reliability risk assessment and classification method according to claim 5, characterized in that, The process baseline is the design simulation value or the historical statistical value of multiple batches.

7. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, When the number of channels in the grain is multiple, the multi-channel dispersion feature includes the standard deviation and range of each single-channel morphological feature of multiple channels in each grain, and includes the maximum value of the feature difference between adjacent channels.

8. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, Combining the aforementioned channel characteristics, preset channel characteristic warning values, and channel characteristic weights, a reliability score for each grain is calculated, including: The deviation between the value of a single channel feature and a preset channel feature warning value is calculated. Based on the deviation, a single reliability score for the single channel feature is assigned. The greater the deviation between the value of the channel feature and the preset channel feature warning value, the higher the reliability risk of the channel feature and the lower the single reliability score. The reliability score of the grain is obtained by weighted summation of the individual reliability scores of multiple channel features based on the preset channel feature weights.

9. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, The critical values ​​of the risk assessment benchmark characteristics are calibrated, including: Based on the Shockley-Reid-Hall defect evolution theory and the physical model of germanium-silicon PN junctions, a quantitative relationship between the slope of the dark current in the low-bias segment and the interface state density is established: In the formula, It is the reverse dark current. The amount of electron charge. Intrinsic carrier concentration, The width of the exhaustion region, For defect capture section, The thermal velocity of charge carriers. The density of states at the interface; In the quantitative formula, when the interface state density exceeds a preset density threshold, it is determined to be a defect state saturation critical point, and the depletion region width of the current process node is substituted into it. With defect capture section The theoretical critical value of the slope of the germanium-silicon photodetector was calculated. Differentiated accelerated stresses are configured based on the degradation activation energies of different devices, and accelerated calibration tests are performed to obtain calibration test data. Based on the calibration test data and the theoretical critical value of the slope of the germanium-silicon photodetector, the critical value of the slope of the germanium-silicon photodetector and the critical value of the leakage current of the Mach-Zehnder modulator are determined.

10. A wafer-level HTOL reliability risk assessment and classification method according to claim 9, characterized in that, Differentiated accelerated stresses are configured based on the degradation activation energies of different devices, and accelerated calibration tests are performed to obtain calibration test data. Based on the calibration test data and the theoretical critical value of the germanium-silicon photodetector slope, the critical value of the germanium-silicon photodetector slope and the critical value of the Mach-Zehnder modulator leakage current are determined, including: To address the interface state degradation of germanium-silicon photodetectors, a first experiment was conducted using a first acceleration temperature and a first acceleration duration, resulting in the dark current-voltage curves of the germanium-silicon photodetectors and the reverse bias leakage current data of the Mach-Zehnder modulators for each experimental sample. Based on the general reliability assurance requirements standard for optoelectronic devices, the samples that have completed the first test are divided into a failure group and a pass group; Extract the dark current low-bias slope data of the germanium-silicon photodetector measured in accelerated testing of the samples of the failed group and the qualified group, and select the value that best distinguishes the failed group and the qualified group within a preset percentage range based on the theoretical critical value, as the critical value of the slope of the germanium-silicon photodetector. The critical value of the leakage current of the Mach-Zehnder modulator is determined based on the jump value when the reverse bias leakage current of the Mach-Zehnder modulator undergoes dielectric breakdown during the accelerated calibration test.

11. A wafer-level HTOL reliability risk assessment and classification method according to claim 10, characterized in that, Also includes: To address thermal fatigue or electromigration degradation of metal leads, a second experiment was conducted using a second acceleration temperature and a second acceleration duration to obtain resistance drift data of the thermo-optical heater under high-temperature stress. The average drift rate of the target duration prior to the first experiment is taken as the first mapping index; The slope of the linear fit throughout the second experiment is taken as the second mapping index; By statistically analyzing data from multiple batches of accelerated calibration tests, empirical lookup tables were established for the drift of the first mapping index, the second mapping index, and the corresponding parameters after the standard high-temperature working life test. For each drift rate in the experience lookup table, the measured drift values ​​from multiple standard high-temperature working life tests are fitted with a normal distribution, and the upper limit of the 95% prediction interval on one side is taken as a conservative estimate.

12. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, The reliability score is used to classify the data, including: The reliability score is compared with the score range of multiple preset grading levels; When the reliability score falls within the range of any grade level, the corresponding grade level is output, wherein the number of grade levels is determined according to the specific scenario.

13. The wafer-level HTOL reliability risk assessment and classification method according to claim 1, characterized in that, The channel characteristics also include optical crosstalk characteristics and thermal crosstalk characteristics.

14. A wafer-level HTOL reliability risk assessment and classification system, characterized in that, include: The test module is used to perform reliability parameter tests on all channels of each die in the wafer under test, and obtain wafer-level optoelectronic parameter test data; The feature extraction module is used to extract the channel features of each grain from the test data. When the number of channels in the grain is one, the channel features include multiple single-channel morphology features. When the number of channels in the grain is multiple, the channel features include multiple single-channel morphology features and multi-channel dispersion features. The single-channel morphology features include risk assessment benchmark features. The risk grading assessment module is used to calculate the reliability score of each chip by combining preset channel feature warning values ​​and weights; and to obtain the critical value of the pre-calibrated risk assessment benchmark feature; to determine the grading of the chip whose risk assessment benchmark feature value exceeds the critical value as the lowest level; and to grade the chip whose risk assessment benchmark feature value does not exceed the critical value based on the reliability score.

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