Coverage analysis method for jump fault, electronic device, and storage medium

Abstract

The application belongs to the technical field of electronic design automation, and proposes a jump fault coverage analysis method, an electronic device and a storage medium. The method comprises the following steps: determining controllable points and observable points in a target circuit; at two adjacent time points, performing first controllability analysis and second controllability analysis on the target circuit respectively, obtaining a first controllable value of each target object at the first time point and a second controllable value of each target object at the second time point; at the second time point, performing observability analysis on the target circuit to obtain the observability of each target object; determining whether the jump fault of each target object is a testable fault according to the first controllable value and the second controllable value of each target object, determining whether the testable fault is a detectable fault according to the observability of each target object, and determining the coverage of the jump fault according to at least one of the testable fault and the detectable fault. The application can quickly and conveniently obtain the coverage of the circuit jump fault.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a coverage analysis method for transient faults, an electronic device, and a storage medium. Background Technology

[0002] With advancements in manufacturing and design technologies, the design methodology for integrated circuits (ICs) has undergone profound changes. From Computer-Aided Design (CAD) and Computer-Aided Engineering (CAE) to Electronic Design Automation (EDA), the degree of automation in design has increased significantly, and the complexity of designs has also grown considerably. Currently, EDA technology has become a powerful tool in modern electronic design. Without the support of EDA technology, it would be unimaginable to design and manufacture very large-scale integrated circuits. IC designers need to utilize EDA tools to develop complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviations, improve tape-out success rates, and save on tape-out costs.

[0003] As modern chips become smaller and larger in scale, testing them becomes increasingly difficult. Testing, being a crucial aspect of chip manufacturing, cannot be ignored. Design for Testability (DFT) is an EDA technique that emerged with the development of testing. It introduces test logic into chip design to improve testability, enabling the testing and analysis of potential faults within the chip.

[0004] For the rapidly developing large-scale integrated circuits, sequential circuits have become the dominant trend. The once-reliable stuck-at fault model is increasingly unable to guarantee the high reliability requirements of chips, while the high coverage requirements of delay fault models in at-speed mode are also becoming increasingly stringent. Transition faults, a type of delay fault model, characterize the failure of a faulty node in a circuit to complete the transition from 0 to 1 or from 1 to 0 within the expected timeframe due to delay. Compared to stuck faults, the detection of transition faults typically requires considering the transition conditions of the faulty node under different time states and whether the fault effect is observable, thus making its coverage analysis process more complex.

[0005] Currently, switching fault coverage analysis typically relies on methods such as Automatic Test Pattern Generation (ATPG) or simulation. This involves generating test vectors and simulating the circuit's operation under corresponding stimuli to determine whether a fault can be detected. However, as integrated circuit scale increases, the number of test vectors and the circuit states requiring analysis also increase, leading to longer analysis times and increased computational costs for switching fault coverage analysis. Summary of the Invention

[0006] This invention provides a method, electronic device, and storage medium for coverage analysis of jump faults, to at least solve the problem of high cost in jump fault coverage analysis caused by the reliance on test vector generation and dynamic simulation in related technologies. The technical solution of this invention is as follows: According to a first aspect of the present invention, a coverage analysis method for a jump fault is provided, comprising: determining controllable points and observable points in a target circuit, wherein the controllable points include a main input port and / or an output pin of a scanning device, and the observable points include a main output port and / or an input pin of a scanning device; at two adjacent time points, taking the controllable points and constant pins as starting points, performing a first controllability analysis and a second controllability analysis on the target circuit along the signal propagation direction, respectively, to obtain a first controllable value of each target object in the target circuit at the first time point and a second controllable value at the second time point, wherein the constant pin has a constant signal, the target object is a pin or port, and the controllable value is represented by... The method involves determining whether the signal of the target object can be controlled to be 0 and / or 1; at the second moment, starting from the observable point, performing observability analysis on the target circuit in the reverse signal propagation direction to obtain the observability of each target object, wherein the observability is used to characterize whether the signal change of the target object can be observed at the corresponding observable point; based on the first controllable value and the second controllable value of each target object, determining whether the jump fault of each target object is a testable fault, and based on the observability of each target object, determining whether the testable fault is a detectable fault, and based on at least one of the testable fault and the detectable fault, determining the coverage of the jump fault.

[0007] According to a second aspect of the present invention, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein, when executed by the processor, the processor causes the processor to perform a coverage analysis method for jump faults according to the present invention.

[0008] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the coverage analysis method for jump faults according to the present invention.

[0009] The technical solution provided by this invention brings at least the following beneficial effects: This invention analyzes the controllable values ​​of each target object in the target circuit at two adjacent time points and the observability at the second time point. Based on this, it can statically analyze the testability and detectability of switching faults and determine the coverage of switching faults. This improves the efficiency of switching fault coverage analysis, reduces the time and computational overhead required for coverage analysis, and provides chip design engineers with coverage reference values ​​before calculating delays and before static timing analysis. This helps them to make circuit modifications at an early stage, saving a lot of testing time and redesign time, thereby significantly reducing chip design costs.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention, but do not constitute an undue limitation of the invention.

[0012] Figure 1 This is a flowchart illustrating a coverage analysis method for jump faults according to an exemplary embodiment of the present invention; Figure 2 This is a circuit diagram illustrating an exemplary embodiment of the present invention; Figure 3 This is a schematic diagram illustrating a circuit extension according to an exemplary embodiment of the present invention; Figure 4 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0014] It should be noted that the steps in the specification and drawings of this invention are not limited to the specific order or sequence described. It should be understood that the steps used in this way can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in a sequence other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0015] Design for Test (DFT) refers to inserting various hardware logic elements during the initial chip design phase to improve chip testability (including controllability and observability). This logic generates test vectors to test large-scale chips. IC designers often use EDA tools to quickly insert DFT circuits into the design or perform DFT rule checks on the entire circuit to reliably achieve agile development. In DFT technology, faults are modeled at the transistor or gate level as physical defects. Based on the electrical characteristics of different defects (i.e., the observed physical phenomena, such as open circuits and short circuits), electrical laws are summarized and categorized into different fault models, such as fixed faults, delay faults, and bridging faults.

[0016] As mentioned earlier, transition faults are a type of time-delay fault model. In related technologies, transition fault coverage analysis typically relies on methods such as ATPG or simulation. This involves generating test vectors and simulating the circuit's operating state under corresponding stimuli to determine whether the fault can be detected. However, as the scale of integrated circuits increases, the number of test vectors and the circuit states that need to be analyzed also increase. For example, when dealing with a simple 4-bit input circuit, if simulation is used, 2 to the power of 4, or 16 logic value combinations, are required for analysis. This means the same circuit needs to be analyzed 16 times. Furthermore, due to its time-delay fault model, the delays of each path and gate also need to be calculated. In addition, the detection method of the transition needs to be observed. Each analysis requires at least two time points of circuit operation, further contributing to the excessively long testing time.

[0017] As requirements change at different design stages, EDA tools can analyze circuit designs using methods such as static analysis and dynamic analysis. Dynamic analysis typically simulates the circuit's operating state over time based on input stimuli, obtaining analysis results by simulating signal propagation and state changes within the circuit. Depending on the specific simulation type, timing information such as cell delays can also be considered. Because dynamic analysis requires time-by-time calculations of the circuit state for different stimuli, it can incur significant computational overhead, especially with large circuits or when handling numerous test scenarios. In contrast, static analysis typically does not require applying specific test stimuli or time-by-time simulations of the circuit's operation. Instead, it directly analyzes based on information such as circuit topology, logic relationships, and / or timing constraints, thus reducing computation time and resources required in some applications.

[0018] In view of the above problems, exemplary embodiments of the present invention provide a method, electronic device, and computer-readable storage medium for coverage analysis of circuit switching faults, which can obtain the coverage of circuit switching faults more quickly and conveniently based on static characteristics, thereby helping chip design engineers to discover problems earlier, which is of great cost saving.

[0019] In a first aspect of an exemplary embodiment of the present invention, a coverage analysis method for jump faults is provided, which will be described below with reference to Figures 1 to 3 Provide a detailed description.

[0020] According to an exemplary embodiment of the present invention, the coverage analysis method for switching faults is applicable to electronic design automation (EDA) software. The user terminal can load the EDA software, enabling it to determine controllable and observable points in the target circuit. Here, controllable points include the main input port and / or the output pin of the scanning device, and observable points include the main output port and / or the input pin of the scanning device. At two adjacent time points, starting from the controllable points and constant pins, a first controllability analysis and a second controllability analysis are performed on the target circuit along the signal propagation direction to obtain the first controllable value of each target object in the target circuit at the first time point and the second controllable value at the second time point. Here, the constant pin... With a constant signal, the target object is a pin or port, and the controllable value is used to characterize whether the signal of the target object can be controlled to 0 and / or 1; at the second moment, starting from the observable point, the observability analysis of the target circuit is performed in reverse signal propagation direction to obtain the observability of each target object. Here, observability is used to characterize whether the signal change of the target object can be observed at the corresponding observable point; based on the first controllable value and the second controllable value of each target object, it is determined whether the jump fault of each target object is a testable fault, and based on the observability of each target object, it is determined whether the testable fault is a detectable fault, and based on at least one of the testable fault and the detectable fault, the coverage of the jump fault is determined.

[0021] This method analyzes the controllable values ​​of each target object in the target circuit at two adjacent time points and the observability at the second time point. Based on this, it can statically analyze the testability and detectability of switching faults and determine the coverage of switching faults. This improves the efficiency of switching fault coverage analysis, reduces the time and computational overhead required for coverage analysis, and provides chip design engineers with coverage reference values ​​before calculating delays and static timing analysis. This helps them to make circuit modifications at an early stage, saving a lot of testing time and redesign time, thereby significantly reducing chip design costs.

[0022] The aforementioned user terminal can be such as a tablet computer, laptop computer, digital assistant, wearable device, etc. However, the implementation scenario of the fault coverage analysis method described above is only an example scenario. The fault coverage analysis method according to the exemplary embodiment of the present invention can also be applied to other application scenarios. For example, a user can request access to relevant data from a server via a network on a user terminal (e.g., mobile phone, desktop computer, tablet computer, etc.). The server can access the data by executing the fault coverage analysis method according to the exemplary embodiment of the present invention and return the result to the user terminal. Here, the server can be an independent server, a server cluster, a cloud computing platform, or a virtualization center, etc.

[0023] The following will refer to Figure 1 The specific steps of a coverage analysis method for jump faults according to an exemplary embodiment of the present invention are described. For example... Figure 1 As shown, the coverage analysis method for this jump fault may include the following steps: In step S110, controllable points and observable points in the target circuit can be determined.

[0024] According to an exemplary embodiment of the present invention, designers typically use HDL (Hardware Description Language) to complete the target circuit design. HDL describes the structure and behavior of digital system hardware in text form and can represent logic circuit diagrams, logic expressions, and the logic functions performed by the digital logic system. Thus, it can model multiple abstract design levels such as algorithm level, register transfer level, gate level, and switch level.

[0025] Here, controllable points may include primary input ports and / or output pins of the scanning device, while observable points may include primary output ports and / or input pins of the scanning device. Primary inputs are used in the circuit to receive main input signals; they are typically interfaces of modules or circuit units, representing the input terminals of the entire circuit. These inputs can be signals from other circuit modules or control signals from external systems. Primary outputs are used in the circuit to transmit main output signals. These output signals are the results or reactions directly generated from the circuit's functionality after the circuit design is completed, and are usually related to the logical operations or processing of the input signals. In some possible implementations, scanning devices may include, but are not limited to, scannable flip-flops (FF), black boxes with scan wraps, and memory with scan wraps.

[0026] Next, in step S120, at two adjacent moments, starting from the controllable point and the constant pin, the target circuit can be subjected to a first controllability analysis and a second controllability analysis along the signal propagation direction to obtain the first controllable value of each target object in the target circuit at the first moment and the second controllable value at the second moment.

[0027] Here, a constant pin can have a constant signal, the target object can be a pin or a port, and the controllable value can be used to characterize whether the signal of the target object can be controlled to 0 and / or 1. Further, a constant pin can be a pin whose signal remains at a constant value in the target circuit, such as a pin that is always 0 or always 1. The signal value of a constant pin does not change with the circuit's operating state; therefore, during controllability analysis, its controllable value can be directly determined based on its corresponding constant signal value. For controllable points that are not constant pins, their controllable values ​​can be assumed to include values ​​0 and 1. Furthermore, a value of 0 can be used to characterize that the signal of the target object can be controlled to 0, and a value of 1 can be used to characterize that the signal of the target object can be controlled to 1.

[0028] According to an exemplary embodiment of the present invention, two adjacent moments may include a first moment and a second moment. At the first moment, a first controllability analysis may be performed on the target circuit along the signal propagation direction. Then, at the second moment, a second controllability analysis may be performed on the target circuit along the signal propagation direction based on the results obtained from the first controllability analysis.

[0029] For the first controllability analysis, for the first moment, the first controllable value of the controllable point can be determined as including the value 0 and the value 1, and the first controllable value of the constant pin can be determined as the signal value of the constant pin. Starting from the controllable point and the constant pin, the first controllable value is transmitted in the target circuit along the signal propagation direction through a breadth-first search (BFS) traversal method until the first controllable value of each target object is obtained.

[0030] For the second controllability analysis, at the second time point, the first controllable value of the main input port and the constant pin can be maintained as the second controllable value of the main input port and the constant pin, and the second controllable value of the output pin of the scanning device can be re-determined based on the first controllable value of the input pin of the scanning device; starting from the controllable point and the constant pin, the second controllable value is transmitted in the target circuit along the signal propagation direction through a breadth-first search traversal method until the second controllable value of each target object is obtained.

[0031] Here, Breadth-First Search (BFS) is a method for traversing or searching a tree or graph. It starts from a node in the tree or graph and explores and traverses all its adjacent nodes in turn, then explores the adjacent nodes of those adjacent nodes, and so on, until all nodes have been traversed. Compared to Depth-First Search (DFS), which will be described later, BFS traversal can proceed layer by layer according to the circuit topology, processing nodes at the previous level before processing nodes at the next level. This is more suitable for controllability propagation that relies on multiple previous level inputs for subsequent calculations. Simultaneously, BFS can process multiple nodes at the same level in parallel, which is beneficial for improving the parallelism and processing efficiency of large-scale circuit analysis. Using BFS for controllability analysis allows for the propagation of controllable values ​​layer by layer according to the circuit topology, facilitating the analysis of subsequent logic units after the relevant input conditions are determined. It also allows for parallel processing of multiple analysis objects at the same level, thereby improving the efficiency of controllability analysis.

[0032] Furthermore, Chinese invention patent application number CN202411420941.0 discloses a method, apparatus, electronic device, storage medium and program product for analyzing the controllability of a circuit. Specifically, it proposes a scheme for transmitting controllable values ​​through BFS. The technical means of transmitting controllable values ​​in this invention can be referred to to determine the first and second controllable values ​​of each target object in the exemplary embodiment of this invention. For the sake of brevity, it will not be elaborated here.

[0033] According to an exemplary embodiment of the present invention, at the second time moment, the controllable point and the second controllable value of the constant pin can be determined based on the first controllable value obtained from the first controllability analysis. Here, the second controllable value of the main input port and the constant pin can be the same as that at the first time moment, that is, the first controllable value of the main input port and the constant pin can be maintained as the second controllable value of the main input port and the constant pin. Since the scanning device is used to transfer or maintain the circuit state between adjacent time moments, the output state of the scanning device at the second time moment is constrained by its input state at the first time moment. Therefore, the second controllable value of the output pin of the scanning device can be re-determined based on the first controllable value of the input pin of the scanning device and the corresponding state transfer relationship of the scanning device.

[0034] For example, for a scan trigger, if the first controllable value of its input pin includes only the value 0, it indicates that the signal of the input pin can be controlled to 0 but not to 1 at the first moment. After the scan trigger completes the corresponding state transmission, its output pin corresponds to the state of the input pin at the second moment. Therefore, the second controllable value of the output pin can be redefined from the initial values ​​of 0 and 1 to include only the value 0. Similarly, if the first controllable value of the input pin includes only the value 1, the second controllable value of the output pin can be determined to include only the value 1; if the first controllable value of the input pin includes both values ​​0 and 1, the second controllable value of the output pin can include both values ​​0 and 1. Furthermore, for other scanning devices such as black boxes with scanning packaging and memory with scanning packaging, the signal values ​​allowed to be obtained by the input pins at the first moment can be mapped to the signal values ​​allowed to be obtained by the output pins at the second moment, according to the scanning structure and state transmission relationship of the corresponding scanning device, to obtain the second controllable value of the output pin.

[0035] Next, in step S130, at the second time point, starting from the observable point, observability analysis can be performed on the target circuit in the reverse signal propagation direction to obtain the observability of each target object.

[0036] For observability analysis, the observability of an observable point can be defined as observable. Starting from the observable point, observability is propagated in the target circuit in the reverse direction of signal propagation using a depth-first search until the observability of each target object is obtained. Here, observability can be used to characterize whether the signal changes of the target object can be observed at the corresponding observable point.

[0037] Furthermore, Depth-First Search (DFS) is a method for traversing or searching a tree or graph. It traverses the tree or graph as deep as possible, then backtracks to the previous node, finding unexplored nodes and continuing the search. Compared to Breadth-First Search (BFS), DFS traversal, in circuit topologies with many branches and large search depths, does not require storing a large number of nodes at the same level simultaneously, generally incurring lower memory overhead. It is more suitable for continuous reverse tracing along specific signal paths. Observability analysis using DFS traversal allows for continuous tracing of signal paths in the reverse direction of signal propagation, reducing the storage overhead required to store a large number of nodes at the same level, and facilitating step-by-step propagation and backtracking analysis of each observable path.

[0038] According to an exemplary embodiment of the present invention, in the process of transmitting observability in the target circuit from an observable point through a depth-first search traversal method in the opposite direction of signal propagation, for any net, the observability of an input pin or output port connected to any net can be directly transmitted to an output pin or input port connected to any net; when transmitting observability via an output pin of a combinational logic unit to any input pin of a combinational logic unit, a second controllable value can be used to determine whether to transmit the observability of the output pin to any input pin through logical calculation; when transmitting observability to a non-combinatorial logic unit, the transmission of the current branch path can be stopped.

[0039] Here, when the observability is transmitted from the output pin of the combinational logic unit to any input pin of the combinational logic unit, it can be determined whether the signal change of any input pin can be transmitted to the output pin of the combinational logic unit based on the second controllable value of other input pins besides any input pin of the combinational logic unit and the logic function of the combinational logic unit. If the signal change of any input pin can be transmitted to the output pin of the combinational logic unit, the observability of the output pin of the combinational logic unit is transmitted to any input pin.

[0040] As an example, the combinational logic unit is an AND gate, which includes a first input pin in1, a second input pin in2, and an output pin out. Its logic function is out = in1 * in2. Suppose that during the observability analysis, the output pin out has been determined to be observable. Now it is necessary to determine whether its observability can be passed from the output pin out to the first input pin in1. At this time, the second controllable value of the second input pin in2, other than the first input pin in1, is obtained. If the second controllable value of the second input pin in2 includes the value 1, then when in2 is controlled to be 1, the change of the first input pin in1 from 0 to 1 or from 1 to 0 can cause a corresponding signal change in the output pin out. Therefore, the signal change of the first input pin in1 can be propagated to the output pin out, and the observability of the output pin out can be transferred to the first input pin in1. Conversely, if the second controllable value of the second input pin in2 only includes the value 0, then regardless of whether the first input pin in1 is 0 or 1, the output pin out remains 0. The signal change of the first input pin in1 is shielded by the signal value 0 of the second input pin in2 and cannot be propagated to the output pin out. Therefore, in this case, the observability of the output pin out is not transferred to the first input pin in1.

[0041] By combining the second controllable value of other input pins with the logic function of the combinational logic unit to determine whether a signal change of any input pin can affect the output pin, observability can be avoided from being erroneously propagated when the signal change is masked by other input states. This improves the accuracy of observability analysis and the accuracy of fault detection and coverage analysis based on the observability results.

[0042] Furthermore, when determining whether a signal change of any input pin can propagate to the output pin of the combinational logic unit based on the second controllable values ​​of other input pins besides any input pin of the combinational logic unit and the logic function of the combinational logic unit, any input pin can be set to 0 and 1 respectively according to the logic function of the combinational logic unit to obtain a first logic expression and a second logic expression; an XOR operation is performed on the first logic expression and the second logic expression to obtain a Boolean difference expression for any input pin; based on the second controllable values ​​of other input pins, at least one signal combination controllable by other input pins is determined, and the signal combination is substituted into the Boolean difference expression; if at least one signal combination makes the calculation result of the Boolean difference expression 1, it is determined that the signal change of any input pin can propagate to the output pin of the combinational logic unit. Here, at least one signal combination controllable by other input pins can be understood as, in addition to the input pin currently being analyzed, selecting a signal value from the signal values ​​that can actually be controlled to reach by each input pin according to the second controllable values ​​of the remaining input pins, and combining the selected signal values ​​to form the input state.

[0043] As an example, the combinational logic unit is a three-input AND gate, including a first input pin in1, a second input pin in2, a third input pin in3, and an output pin out. Its logic function is out = in1 * in2 * in3. To determine whether a signal change at the first input pin in1 can propagate to the output pin out, the first input pin in1 can be set to 0 and 1 respectively. When in1 = 0, the first logic expression out0 = 0 * in2 * in3 = 0; when in1 = 1, the second logic expression out1 = 1 * in2 * in3 = in2 * in3. Performing an XOR operation on the first and second logic expressions yields the Boolean difference expression out0 ⊕ out1 = in2 * in3 for the first input pin in1. The second controllable values ​​of the second input pin in2 and the third input pin in3 are then obtained. For example, if the second controllable values ​​of the second input pin in2 include 0 and 1, and the second controllable value of the third input pin in3 includes only 1, then the controllable signal combinations of the second input pin in2 and the third input pin in3 include (0, 1) and (1, 1). Substituting the above signal combinations into the Boolean difference expression, the result of the Boolean difference expression is 0 when in2=0 and in3=1; and 1 when in2=1 and in3=1. Since there is at least one controllable signal combination that makes the result of the Boolean difference expression 1, it is determined that the signal change of the first input pin in1 can propagate to the output pin out. Therefore, if the output pin out is observable, the observability of the output pin out can be passed to the first input pin in1.

[0044] Conversely, if the second controllable value of the third input pin in3 is only 0, then regardless of whether the second input pin in2 can be controlled to be 0 or 1, all controllable signal combinations will result in 0 after being substituted into the Boolean difference expression. This indicates that the signal change of the first input pin in1 will be shielded by the signal value 0 of the third input pin in3, thus determining that the signal change of the first input pin in1 cannot be propagated to the output pin out.

[0045] In this way, Boolean difference can be used to characterize the effect of signal change of any input pin on the output of combinational logic unit, and the second controllable value of other input pins can be used to constrain the value of the variable in Boolean difference, thereby avoiding the erroneous judgment that signal change can propagate based on the actual uncontrollable input state, and improving the accuracy of signal change propagation and observability analysis.

[0046] According to an exemplary embodiment of the present invention, before the first moment, constant propagation can also be performed on the target circuit to determine the constant pins in the target circuit and the constant paths in which the constant pins are located. Here, all target objects in the constant path have constant attributes. Further, constant propagation refers to starting from a pin or port in the target circuit with a constant signal value, and transmitting a constant signal value along the signal propagation direction according to the circuit connection relationship and the logic function of each logic unit, in order to determine other pins or ports that are constrained by the constant signal value and can only remain at 0 or 1. The signal propagation path formed by multiple target objects with constant signal values ​​during the constant propagation process can be called a constant path. In other words, each target object in the constant path is constrained by the upstream constant signal and the circuit logic function, and its signal can be determined to be a constant signal value 0 or signal value 1, that is, the signal value of the corresponding target object will not change arbitrarily in the analyzed state. For example, if an input pin of an AND gate is constant at signal value 0, then the output pin of the AND gate is constant at signal value 0, and the output pin can be determined to have constant attributes; if the output pin continues to keep the signal value of the downstream target object constant, then the corresponding downstream target object can also be determined to have constant attributes.

[0047] By propagating constants in the target circuit before the first moment, the constant pins in the target circuit and the constant paths formed by the constant pins can be determined in advance. This allows for the identification of target objects whose signal values ​​cannot be arbitrarily changed due to circuit structure and logic relationships. This provides accurate signal value constraints for subsequent controllability and observability analysis, avoiding the erroneous analysis of target objects that can only maintain constant signal values ​​as objects that can be controlled to 0 and 1, thus improving the accuracy of coverage analysis results.

[0048] Based on constant propagation prior to the first moment, during the process of transmitting observability in the target circuit from an observable point through a depth-first search traversal in the reverse signal propagation direction, if any observable point has a constant attribute, the observability of any observable point can be directly transmitted to the target object in the path within the constant path, starting from any observable point and proceeding in the reverse signal propagation direction using a depth-first search traversal. By directly transmitting observability along the reverse signal propagation direction using a DFS traversal in the constant path corresponding to observable points with constant attributes, the constant path relationships determined during the constant propagation stage can be utilized. This reduces the computational overhead of performing logical judgments or controllability analysis on each target object in the path, thereby reducing the computational overhead of observability analysis and improving its efficiency.

[0049] Next, in step S140, it can be determined whether the jump fault of each target object is a testable fault based on the first controllable value and the second controllable value of each target object, and whether the testable fault is a detectable fault based on the observability of each target object, and the coverage of the jump fault is determined based on at least one of the testable fault and the detectable fault.

[0050] Here, transition faults can include upward transition faults and downward transition faults. An upward transition fault can indicate that the transition from 0 to 1 did not complete within the expected delay, and a downward transition fault can indicate that the transition from 1 to 0 did not complete within the expected delay. Further, when determining whether a transition fault of each target object is a testable fault based on its first and second controllable values, for any target object, an upward transition fault is determined to be a testable fault if the first controllable value of the target object includes the value 0 and the second controllable value includes the value 1; otherwise, it is determined to be an untestable fault. Similarly, a downward transition fault is determined to be a testable fault if the first controllable value of the target object includes the value 1 and the second controllable value includes the value 0; otherwise, it is determined to be an untestable fault. Even further, when determining whether a testable fault is a detectable fault based on the observability of each target object, for any testable fault, it is determined to be a detectable fault if the observability of the target object corresponding to the testable fault is observable; otherwise, it is determined to be an undetectable fault.

[0051] By utilizing the first and second controllable values ​​of the target object at two adjacent time points, it can be determined whether it possesses the transition condition from 0 to 1 or from 1 to 0, thereby determining the testability of up-jump and down-jump faults. Further, by combining the observability of the corresponding target object, it can be determined whether the testable fault can be observed, thus completing the judgment of the detectability of the jump fault. Therefore, without relying on specific test vectors to perform dynamic simulations of each jump fault individually, jump faults can be classified based on static analysis results, improving the efficiency of jump fault analysis and providing accurate fault classification results for subsequent coverage calculations.

[0052] According to an exemplary embodiment of the present invention, the coverage of switching faults may include fault coverage and test coverage. Here, fault coverage can be used to characterize the proportion of detectable switching faults out of all switching faults, reflecting the overall detection level of all switching faults in the target circuit; test coverage can be used to characterize the proportion of detectable switching faults out of testable faults, that is, the proportion of faults that can be actually detected after excluding untestable faults that cannot be tested due to circuit structure, logic constraints, etc.

[0053] Furthermore, when determining the coverage of switching faults based on at least one of testable faults and detectable faults, the fault coverage can be determined based on the ratio of the number of detectable faults to the total number of switching faults; the test coverage can be determined based on the ratio of the number of detectable faults to the number of testable faults.

[0054] For each target object, one upward-jumping fault and one downward-jumping fault can be set. Therefore, all target objects in the target circuit are used as modeling objects for jumper faults. When analyzing upward-jumping faults and downward-jumping faults separately, the total number of jumper faults can be twice the number of target objects. For example, if the target circuit includes 100 target objects as fault modeling objects, the corresponding total number of jumper faults can be 200, including 100 upward-jumping faults and 100 downward-jumping faults. It should be understood that if some target objects are not modeling objects for jumper faults, the total number of jumper faults can be determined based on the actual target objects involved in fault modeling.

[0055] As an example, suppose that after analyzing the aforementioned 200 switching faults, 40 of them are determined to be untestable faults, and the remaining 160 are testable faults. Of the 160 testable faults, 120 are further determined to be detectable faults, and the remaining 40 are untestable faults. In this case, the ratio of the number of detectable faults to the total number of switching faults is 120 / 200 = 60%, resulting in a fault coverage rate of 60%; the ratio of the number of detectable faults to the number of testable faults is 120 / 160 = 75%, resulting in a test coverage rate of 75%.

[0056] By determining the fault coverage rate based on the ratio of the number of detectable faults to the total number of switching faults, and by determining the test coverage rate based on the ratio of the number of detectable faults to the number of testable faults, the fault detection status of the target circuit can be evaluated from two perspectives: all switching faults and the switching faults that can be tested. This provides a more comprehensive reflection of the switching fault coverage of the target circuit and makes it easier to distinguish between coverage loss caused by untestable faults and coverage loss caused by testable but undetectable faults.

[0057] For ease of understanding, please refer to the following: Figure 2 and Figure 3 Describe it. Figure 2 This is a circuit diagram illustrating an exemplary embodiment of the present invention. Figure 2 As shown, the example circuit includes scan flip-flop 1 (SFF1), scan flip-flop 2 (SFF2), AND gate 1 (AND1), AND gate 2 (AND2), and main output port (PO). Furthermore, AND2 has a constant pin at its input, which is assumed to have a constant input signal of 0.

[0058] Figure 3 This is a schematic diagram illustrating a circuit extension according to an exemplary embodiment of the present invention. Figure 3 As shown, it can be Figure 2 The example circuit is extended from one time point to two adjacent time points, including the first time point and the second time point. Instance units with the same name are essentially the same instance unit, only extended to different time points, resulting in multiple instance units with the same name. Here, the controllable points of the example circuit can be identified as the output pins SFF1 / Q of SFF1 and SFF2 / Q of SFF2, and the observable points as PO, the input pins SFF1 / D of SFF1, and the input pins SFF2 / D of SFF2.

[0059] As an example, the coverage of example circuit switching faults can be determined through the following main steps.

[0060] Step 1: First controllability analysis at the first moment. The first controllable values ​​of SFF1 / Q and SFF2 / Q are determined to include values ​​0 and 1, and the first controllable value of the constant pin is determined to include value 0. Starting from SFF1 / Q, SFF2 / Q, and the constant pin, the first controllable values ​​are passed through the example circuit along the signal propagation direction using BFS traversal. This yields the first controllable values ​​of AND1's input pins AND1 / IN1 and AND1 / IN2, and output pin AND1 / Z, which include values ​​0 and 1. The first controllable values ​​of AND2's input pin AND2 / IN1 and output pin AND2 / Z also include values ​​0. The first controllable value of AND2's other input pin AND2 / IN2 includes values ​​0 and 1. The first controllable values ​​of SFF1 / D and PO include values ​​0, and the first controllable value of SFF2 / D includes values ​​0 and 1.

[0061] Step 2: Second controllability analysis at the second time step. The second controllable value of the constant pin is kept to include the value 0. Based on the first controllable values ​​of SFF1 / D and SFF2 / D, the second controllable value of SFF1 / Q is determined to include the value 0, and the second controllable value of SFF2 / Q is determined to include both values ​​0 and 1. Starting from SFF1 / Q, SFF2 / Q, and the constant pin, the second controllable values ​​are passed along the signal propagation direction in the example circuit using a BFS traversal method, resulting in the second controllable values ​​of AND1 / IN1, AND1 / Z, AND2 / IN1, AND2 / IN2, AND2 / Z, SFF1 / D, SFF2 / D, and PO including the value 0, and the second controllable value of AND1 / IN2 including both values ​​0 and 1.

[0062] Step 3: Observability analysis at the second time step. The observability of SFF1 / D, SFF2 / D, and PO is determined to be observable. Starting from SFF1 / D, SFF2 / D, and PO, observability is propagated in the example circuit in the reverse direction of signal propagation using a DFS traversal method. The observability of AND1 / IN1, AND1 / Z, AND2 / IN1, AND2 / Z, SFF1 / Q, and the constant pin is determined to be observable, while the observability of AND1 / IN2, AND2 / IN2, and SFF2 / Q is determined to be unobservable.

[0063] Step 4: Fault Classification and Coverage Calculation. For ease of description, we will denote upward-jumping faults as T01 and downward-jumping faults as T10.

[0064] 1) Fault Classification: SFF1 / Q(T01): First time value 0 is controllable (√), second time value 1 is controllable (×), cannot be tested; SFF1 / Q(T10): First time value 1 is controllable (√), second time value 0 is controllable (√), testable; SFF1 / D(T01): First time value 0 is controllable (√), second time value 1 is controllable (×), cannot be tested; SFF1 / D(T10): First time value 1 is controllable (√), second time value 0 is controllable (×), cannot be tested; SFF2 / Q(T01): First time value 0 is controllable (√), second time value 1 is controllable (×), cannot be tested; SFF2 / Q(T10): First time value 1 is controllable (√), second time value 0 is controllable (√), testable; SFF2 / D(T01): First time value 0 is controllable (√), second time value 1 is controllable (×), cannot be tested; SFF2 / D(T10): First time value 1 is controllable (√), second time value 0 is controllable (√), testable; AND1 / IN1 (T01): A value of 0 at the first time step is controllable (√), and a value of 1 at the second time step is controllable (×); it cannot be tested. AND1 / IN1 (T10): The value 1 at the first time step is controllable (√), and the value 0 at the second time step is controllable (√). It can be tested. AND1 / IN2 (T01): The value 0 at the first time step is controllable (√), and the value 1 at the second time step is controllable (√). It can be tested. AND1 / IN2 (T10): The value 1 at the first time step is controllable (√), and the value 0 at the second time step is controllable (√). It can be tested. AND1 / Z(T01): The value 0 at the first time step is controllable (√), the value 1 at the second time step is controllable (×), and cannot be tested; AND1 / Z(T10): The value 1 at the first time step is controllable (√), the value 0 at the second time step is controllable (√), and can be tested; AND2 / IN1(T01): The value 0 at the first time step is controllable (√), the value 1 at the second time step is controllable (×), and cannot be tested; AND2 / IN1(T10): Value 1 at the first time step is controllable (×), value 0 at the second time step is controllable (√), cannot be tested; AND2 / IN2(T01): The value 0 at the first time step is controllable (√), the value 1 at the second time step is controllable (×), and cannot be tested; AND2 / IN2(T10): A value of 1 at the first time step is controllable (√), a value of 0 at the second time step is controllable (√), and can be tested; AND2 / Z(T01): The value 0 at the first time step is controllable (√), the value 1 at the second time step is controllable (×), and cannot be tested; AND2 / Z(T10): Value 1 at the first time step is controllable (×), value 0 at the second time step is controllable (√), cannot be tested; PO(T01): The value at the first time step is 0 and can be controlled (√), the value at the second time step is 1 and can be controlled (×), and cannot be tested; PO(T10): First time value 1 is controllable (×), second time value 0 is controllable (√), cannot be tested; Among testable faults: SFF1 / Q(T10): Observable and detectable; SFF2 / Q(T10): Unobservable, undetectable; SFF2 / D(T10): Observable and detectable; AND1 / IN1 (T10): Observable and detectable; AND1 / IN2 (T01): Unobservable, undetectable; AND1 / IN2 (T10): Unobservable, undetectable; AND1 / Z(T10): Observable and detectable; AND2 / IN2(T10): Unobservable, undetectable.

[0065] 2) Coverage calculation: Fault coverage: Detectable (4) / Total faults (22) = 18.18%; Test coverage: detectable (4) / detectable (8) = 50%.

[0066] It should be noted that although the implementation method is described using an example circuit in the exemplary embodiments of the present invention, the exemplary embodiments of the present invention are not limited to the examples described above. The implementation method described above using the example circuit can also be similarly applied to other circuits.

[0067] According to an exemplary embodiment of the present invention, the method for coverage analysis of switching faults can statically analyze the testability and detectability of switching faults by analyzing the controllable values ​​of each target object in the target circuit at two adjacent time points and the observability at the second time point, thereby determining the coverage of switching faults. This improves the efficiency of switching fault coverage analysis, reduces the time and computational overhead required for coverage analysis, and enables the provision of coverage reference values ​​to chip design engineers without calculating delays or before static timing analysis. This helps them to modify circuits at an early stage, saving a significant amount of testing and redesign time, thereby greatly reducing chip design costs.

[0068] In a second aspect of an exemplary embodiment of the present invention, an electronic device is provided, the electronic device comprising: a processor; and a memory for storing processor-executable instructions, wherein, when executed by the processor, the processor-executable instructions cause the processor to perform a coverage analysis method for jump faults according to an exemplary embodiment of the present invention.

[0069] Figure 4 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. Figure 4 As shown, the electronic device 10 includes a processor 101 and a memory 102 for storing processor-executable instructions. Here, when executed by the processor, the processor-executable instructions cause the processor to perform a fault coverage analysis method according to an exemplary embodiment of the present invention.

[0070] As an example, electronic device 10 is not necessarily a single device, but can be a collection of any means or circuits capable of executing the aforementioned instructions (or instruction sets) individually or in combination. Electronic device 10 can also be part of an integrated control system or system manager, or can be configured to interface with a server locally or remotely (e.g., via wireless transmission).

[0071] In electronic device 10, processor 101 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, processor 101 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0072] The processor 101 can execute instructions or code stored in the memory 102, which can also store data. Instructions and data can also be sent and received over a network via a network interface device, which can employ any known transmission protocol.

[0073] The memory 102 may be integrated with the processor 101, for example, by placing RAM or flash memory within an integrated circuit microprocessor. Alternatively, the memory 102 may include a separate device, such as an external disk drive, a storage array, or other storage device that can be used by any database system. The memory 102 and the processor 101 may be operatively coupled, or may communicate with each other, for example, via I / O ports, network connections, etc., enabling the processor 101 to read files stored in the memory 102.

[0074] In addition, the electronic device 10 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, mouse, touch input device, etc.). All components of the electronic device 10 can be connected to each other via a bus and / or network.

[0075] In an exemplary embodiment, a computer-readable storage medium may also be provided, which, when executed by a processor of an electronic device, enables the electronic device to perform the coverage analysis method for transient faults as described in the exemplary embodiment above. The computer-readable storage medium may be, for example, a memory including instructions. Optionally, the computer-readable storage medium may be: a read-only memory (ROM), a random access memory (RAM), a random access programmable read-only memory (PROM), an electrically erasable programmable read-only memory (EEPROM), a dynamic random access memory (DRAM), a static random access memory (SRAM), flash memory, non-volatile memory, a CD-ROM, a CD-R, a CD+R, a CD-RW, a CD+RW, a DVD-ROM, a DVD-R, a DVD+R, a DVD-RW, a DVD+RW, a DVD-RAM, a BD-ROM, a BD-R, or a BD-R... LTH, BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid-state drive (SSD), card storage (such as multimedia cards, secure digital (SD) cards, or ultra-fast digital (XD) cards), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and to provide the computer program and any associated data, data files, and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the aforementioned computer-readable storage medium can run in an environment deployed in computer devices such as clients, hosts, agent devices, servers, etc. Furthermore, in one example, the computer program and any associated data, data files, and data structures are distributed across a networked computer system, such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner through one or more processors or computers.

[0076] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0077] Furthermore, it should be noted that although several examples of each step have been described above with reference to the specific accompanying drawings, it should be understood that the embodiments of the present invention are not limited to the combinations given in the examples, and the steps appearing in different drawings can be combined, which will not be exhaustive here.

[0078] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the claims.

Claims

1. A coverage analysis method for jump faults, characterized in that, include: Identify controllable and observable points in the target circuit, wherein the controllable points include the main input port and / or the output pin of the scanning device, and the observable points include the main output port and / or the input pin of the scanning device; At two adjacent moments, starting from the controllable point and the constant pin, the target circuit is subjected to a first controllability analysis and a second controllability analysis along the signal propagation direction to obtain the first controllable value of each target object in the target circuit at the first moment and the second controllable value at the second moment. The constant pin has a constant signal, the target object is a pin or port, and the controllable value is used to characterize whether the signal of the target object can be controlled to 0 and / or 1. At the second moment, starting from the observable point, the observability analysis of the target circuit is performed in the reverse direction of signal propagation to obtain the observability of each target object. The observability is used to characterize whether the signal change of the target object can be observed at the corresponding observable point. Based on the first and second controllable values ​​of each target object, it is determined whether the jump fault of each target object is a testable fault, and based on the observability of each target object, it is determined whether the testable fault is a detectable fault, and based on at least one of the testable fault and the detectable fault, the coverage of the jump fault is determined.

2. The coverage analysis method for jump faults according to claim 1, characterized in that, The first controllability analysis includes: For the first moment, the first controllable value of the controllable point is determined to include a value of 0 and a value of 1, and the first controllable value of the constant pin is determined to be the signal value of the constant pin, wherein the value of 0 is used to characterize that the signal of the target object can be controlled to 0, and the value of 1 is used to characterize that the signal of the target object can be controlled to 1; Starting from the controllable point and the constant pin, the first controllable value is transmitted in the target circuit along the signal propagation direction using a breadth-first search traversal method until the first controllable value of each target object is obtained.

3. The coverage analysis method for jump faults according to claim 2, characterized in that, The second controllability analysis includes: For the second moment, the first controllable value of the main input port and the constant pin is maintained as the second controllable value of the main input port and the constant pin, and the second controllable value of the output pin of the scanning device is re-determined based on the first controllable value of the input pin of the scanning device; Starting from the controllable point and the constant pin, the second controllable value is transmitted in the target circuit along the signal propagation direction using a breadth-first search traversal method until the second controllable value of each target object is obtained.

4. The coverage analysis method for jump faults according to claim 1, characterized in that, The observability analysis includes: The observability of the observable point is determined as observable, and starting from the observable point, the observability is transmitted in the target circuit in the reverse direction of signal propagation using a depth-first search traversal method until the observability of each target object is obtained; wherein... For any net, the observability of the input pin or output port connected to the net is directly passed to the output pin or input port connected to the net. When passing observability from the output pin of a combinational logic unit to any input pin of the combinational logic unit, the observability of the output pin of the combinational logic unit is passed to any input pin based on the second controllable value of other input pins of the combinational logic unit besides the input pin and the logic function of the combinational logic unit. If the signal change of the input pin can be passed to the output pin of the combinational logic unit, the observability of the output pin of the combinational logic unit is passed to the input pin. When passing observability to a non-combinational logic unit, the current branch path is aborted.

5. The coverage analysis method for jump faults according to claim 4, characterized in that, Prior to the first moment, it also includes: Constant propagation is performed on the target circuit to determine the constant pins in the target circuit and the constant paths in which the constant pins are located, wherein all target objects in the constant paths have constant attributes. Specifically, starting from the observable point, observability is transmitted in the target circuit in the reverse direction of signal propagation using a depth-first search traversal method, including: If any observable point has a constant property, in the constant path, starting from any observable point, the observability of any observable point is directly transferred to the target object in the path in the opposite direction of signal propagation through a depth-first search traversal.

6. The coverage analysis method for jump faults according to claim 4, characterized in that, Determining whether a signal change at any input pin can propagate to the output pin of the combinational logic unit, based on a second controllable value of an input pin other than the input pin of the combinational logic unit and the logic function of the combinational logic unit, includes: Based on the logic function of the combinational logic unit, each input pin is set to 0 and 1 respectively to obtain the first logic expression and the second logic expression; Perform an XOR operation on the first logical expression and the second logical expression to obtain a Boolean difference expression for any of the input pins; Based on the second controllable value of the other input pin, determine at least one signal combination that is controllable by the other input pin, and substitute the signal combination into the Boolean difference expression; If at least one of the signal combinations results in the Boolean difference expression being 1, it is determined that the signal change of any input pin can propagate to the output pin of the combinational logic unit.

7. The coverage analysis method for jump faults according to claim 1, characterized in that, The transition faults include upward transition faults and downward transition faults. An upward transition fault indicates that the transition from 0 to 1 did not complete within the expected delay, and a downward transition fault indicates that the transition from 1 to 0 did not complete within the expected delay. Specifically, based on the first and second controllable values ​​of each target object, it is determined whether the jump fault of each target object is a testable fault, and based on the observability of each target object, it is determined whether the testable fault is a detectable fault, including: For any target object, if the first controllable value of the target object includes the value 0 and the second controllable value includes the value 1, the up-jump fault of the target object is determined as a testable fault. If the first controllable value of any target object includes the value 1 and the second controllable value includes the value 0, the down-jump fault of any target object is determined as a testable fault. For any testable fault, if the observability of the target object corresponding to the testable fault is observable, the testable fault is determined to be a detectable fault.

8. The coverage analysis method for jump faults according to claim 7, characterized in that, The coverage of the jump fault includes fault coverage and test coverage. The determination of the coverage of the jump fault based on at least one of the testable fault and the detectable fault includes: The fault coverage rate is determined based on the ratio of the number of detectable faults to the total number of transient faults; The test coverage is determined based on the ratio of the number of detectable faults to the number of testable faults.

9. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions. Wherein, when the processor-executable instructions are executed by the processor, they cause the processor to perform the coverage analysis method for jump faults according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the coverage analysis method for jump faults according to any one of claims 1 to 8.

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