A Waveform Measurement Method and System for SOC ATE Based on FPGA

Abstract

The application relates to the technical field of wafer measurement, and particularly discloses an SOC ATE waveform measurement method and system based on FPGA, which comprises the following steps: S1, configuring a high-speed data acquisition interface in the FPGA to latch a to-be-measured waveform at a preset rate; S2, converting serial data into parallel sampling data; S3, simultaneously feeding the parallel sampling data into a waveform frequency measurement module and a timing state sampling module; S4, the waveform frequency measurement module calculates and outputs a waveform frequency value by analyzing data jump; S5, the timing state sampling module extracts or calculates a logic level at a corresponding moment from the parallel data according to preset timing parameters and outputs the logic level; and S6, reporting the measurement result through a control interface. The method is realized in the FPGA by using a hardware description language (HDL), and only needs to update a configuration file of the FPGA, without changing hardware, so that upgrading and maintenance are quick and convenient.

Description

Technical Field

[0001] This invention relates to the field of wafer measurement technology, and more specifically to a FPGA-based SOC ATE waveform measurement method and system. Background Technology

[0002] In existing Automated Test Equipment (ATE) for SOCs, measuring key parameters of the output waveform (such as frequency and logic state at a specific timing) is a core function. Currently, the industry standard is to implement this function using a dedicated measurement ASIC chip. This ASIC typically integrates a high-speed analog front-end that converts the input analog waveform into a digital signal, and has built-in hardwired digital logic to process the converted data, thereby calculating the waveform's frequency and the signal state (logic "0" or "1") at a preset test timing.

[0003] However, this traditional approach based on dedicated ASICs has several significant drawbacks: High cost: The design, tape-out and production costs of dedicated ASICs are high, and their functions are fixed, making them unable to flexibly adapt to changes or upgrades in testing requirements, resulting in high overall costs for testing equipment.

[0004] Poor maintainability: Once an ASIC is manufactured, its functions are fixed. If design defects are found or new measurement functions need to be added, it must be redesigned and re-fabricated, which is time-consuming and costly, making equipment maintenance and upgrades difficult. Summary of the Invention

[0005] The purpose of this invention is to provide a FPGA-based SOC ATE waveform measurement method and system to solve the following technical problems.

[0006] The objective of this invention can be achieved through the following technical solutions: An FPGA-based SOC ATE waveform measurement system includes: High-speed data acquisition interface module: A high-speed serial deserializer implemented inside the FPGA receives the waveform signal under test from the ATE test channel and converts the high-speed serial data stream into a parallel data stream for processing by the internal logic of the FPGA; Waveform frequency measurement module: Receives parallel sampled data from the high-speed data acquisition interface module; has a built-in waveform logic state interval measurement algorithm, including an edge detector and a high-precision counter, to capture signal transition edges in the parallel sampled data and calculate the frequency of the waveform under test based on the high-frequency clock count difference; The timing state sampling module receives parallel sampling data from the high-speed data acquisition interface module; it has a built-in sampling point timing algorithm, which includes a timestamp counter and interpolation algorithm control logic. It receives the target test time issued by the ATE master control and obtains the logical state of the waveform at the specified time through time axis conversion, data buffering and digital interpolation. Control and Output Module: Receives configuration and measurement start / stop commands from the ATE main controller, coordinates the operation of each module, and sends back the waveform frequency and logic state measurement results at specified times to the ATE main controller.

[0007] As a further aspect of the present invention: the high-speed data acquisition interface module includes an ISERDES interface unit and a clock and reset management unit, wherein: ISERDES Interface Unit: Using the 1.6Gbps ISERDES IP core provided by the FPGA, the measured signal with single-ended or differential input is converted into 16-bit wide parallel data; Clock and Reset Management Unit: Provides synchronous clock and reset signals for the entire FPGA's internal measurement logic.

[0008] As a further aspect of the present invention, the specific steps of the waveform logic state interval measurement algorithm are as follows: Multiphase data buffering and edge detection: A multi-level deep shift register is built to buffer parallel sampled data, and the logic levels of adjacent sampling points are compared in real time to identify valid transitions of rising and falling edges; High-precision time interval calculation: Immediately after capturing the transition edge, latch the high-precision counter timestamp and calculate the clock count difference ΔT between two transition edges in the same direction; configure a custom debouncing window to filter out false transition triggers caused by waveform jitter; Real-time frequency conversion and moving average filtering: The instantaneous frequency is calculated according to the formula F=Fclk / ΔT, where Fclk is the high-frequency system clock frequency inside the FPGA; multiple sets of continuous frequency results are weighted averaged or filtered by a first-in-first-out buffer to output a stable frequency measurement value.

[0009] As a further aspect of the present invention, the specific steps of the sampling point timing algorithm are as follows: Global timeline alignment and phase resolution: Receive absolute test time T from ATE master controller test The sampling point index is obtained by converting the sampling clock frequency Fs. With phase offset φ=(T test ×Fs)-Index; Multiphase data buffering and window truncation: Parallel sampling data is continuously buffered through the dual-port ring DPRAM inside the FPGA, and the target sampling point and the sampling data of the previous and next neighboring areas are read according to the index; Fractional delay filtering and interpolation calculation: When the phase offset φ=0, the target sampling point level is read directly; when the phase offset φ≠0, linear interpolation is used for calculation.

[0010] As a further aspect of the present invention: the multiphase data buffer and edge detection specifically include: Data input: Each system clock cycle, new parallel sampled data is pushed into the shift register; Edge transition determination: Real-time monitoring of the data flow in the shift register. When the logic state of the current sampling point is inconsistent with that of the previous sampling point, it is determined that a valid edge transition has been captured. The valid edge transition includes rising edge and falling edge.

[0011] As a further aspect of the present invention: the high-precision time interval calculation specifically includes: Timestamp Snapshot: Within the same clock cycle that captures the transition edge, immediately read the current value of the system's high-frequency clock counter and use this as the timestamp T of the current edge. n ; Period difference calculation: Compare the current timestamp with the timestamp T of the previous captured same-direction transition edge. n-1 Performing the subtraction operation, we obtain the clock cycle count value ΔT=T between the two transition edges. n -T n-1 ; Metastability elimination and debouncing: Set a debouncing window. If multiple transitions occur consecutively within the set debouncing window, only the first valid transition is recorded.

[0012] As a further aspect of the present invention: the linear interpolation specifically includes: If the current sample value is V1 and the next sample value is V2, then the voltage value at the target time is: V target =V1×(1-φ)+V2×φ.

[0013] A method for measuring waveforms of a SOC ATE based on an FPGA includes the following steps: S1: Configure the high-speed data acquisition interface in the FPGA to latch the waveform to be measured at a preset rate; S2: Convert serial data into parallel sampled data; S3: Simultaneously send the parallel sampling data to the waveform frequency measurement module and the timing status sampling module; S4: The waveform frequency measurement module calculates and outputs the waveform frequency value by analyzing data jumps; S5: The timing status sampling module extracts or calculates the logic level at the corresponding moment from the parallel data according to the preset timing parameters and outputs it. S6: Report the measurement results through the control interface.

[0014] The beneficial effects of this invention are: Significantly reduced costs: Replacing expensive dedicated measurement ASICs with general-purpose FPGA chips greatly reduces hardware BOM costs, and the reprogrammable nature of FPGAs also avoids the risk of hardware obsolescence due to functional changes.

[0015] Excellent maintainability and flexibility: The measurement algorithm is implemented in the FPGA using a hardware description language (HDL). If defects need to be fixed, the algorithm optimized, or new measurement modes (such as duty cycle measurement, jitter analysis, etc.) need to be added, only the FPGA configuration file needs to be updated. No hardware changes are required, making upgrades and maintenance quick and convenient.

[0016] High performance and high stability: By fully utilizing the parallel processing capabilities and defined hardware timing of FPGAs, nanosecond or even sub-nanosecond measurement accuracy can be achieved, meeting the testing requirements of high-end SoCs. FPGA design avoids the latency uncertainties that may be introduced by software processing, ensuring stable and reliable operation.

[0017] Strong scalability: A single FPGA device typically contains a large number of I / O resources and abundant logic units, which can be easily expanded to realize parallel and synchronous waveform measurement of multiple test channels, thereby efficiently replacing the functions of multiple dedicated ASIC chips and achieving higher system integration. Attached Figure Description

[0018] The invention will now be further described with reference to the accompanying drawings.

[0019] Figure 1 This is a schematic diagram of the structure of a FPGA-based SOC ATE waveform measurement system according to the present invention; Figure 2 This is a schematic diagram of the waveform frequency measurement module of the present invention; Figure 3 This is a schematic diagram of the timing state sampling module of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The purpose of this invention is to provide a FPGA-based SOC ATE waveform measurement method and system to solve the problems of high cost and poor maintainability caused by traditional ASIC solutions.

[0022] This invention implements an equivalent waveform measurement algorithm within an FPGA, leveraging the FPGA's parallel processing capabilities and reconfigurability to achieve or even surpass the measurement performance of a dedicated ASIC, while significantly improving the flexibility, maintainability, and cost-effectiveness of the solution.

[0023] like Figure 1 As shown, an FPGA-based SOC ATE waveform measurement system includes: High-speed data acquisition interface module: This module consists of a high-speed serial deserializer implemented inside the FPGA (e.g., based on the 1.6Gbps ISERDES IP core or its equivalent functional logic). It receives the waveform signal under test from the ATE test channel and converts the high-speed serial data stream into a parallel data stream for processing by the FPGA's internal logic.

[0024] ISERDES Interface Unit: Using the 1.6Gbps ISERDES IP core provided by the FPGA vendor, the measured signal with single-ended or differential input is converted into 16-bit wide parallel data (the specific bit width can be adjusted according to the FPGA's internal clock frequency and data rate).

[0025] Clock and Reset Management Unit: Provides synchronous clock and reset signals for the entire FPGA's internal measurement logic.

[0026] Waveform Frequency Measurement Module: This module is implemented in hardware logic within the FPGA and receives parallel sampled data from the high-speed data acquisition interface module. The module internally presets and runs a waveform logic state (0 / 1) interval measurement algorithm. This algorithm detects the transition edges between consecutive logic "0"s and logic "1"s in the parallel sampled data and accurately calculates the time interval between these transition edges (based on the number of sampling clock cycles), thereby calculating the frequency of the input waveform in real time with high precision.

[0027] In practical work, such as Figure 2 As shown, it continuously monitors parallel data and has an internal edge detector to identify transitions from 0 to 1 and from 1 to 0. Once a transition is detected, a high-precision counter (driven by a high-speed system clock) is sampled and its value is recorded. By calculating the difference between the counter values ​​between consecutive same-direction transitions, the number of clock cycles of the waveform period can be obtained. Combined with the system clock frequency, the precise frequency of the waveform under test can be calculated. A digital filter can be added to enhance noise immunity.

[0028] In a preferred embodiment of the present invention, a waveform logic state (0 / 1) interval measurement algorithm is used for real-time edge capture and period estimation under high-multiplication oversampling. A sampling clock with a frequency much higher than the input signal frequency is used for intensive parallel sampling of the waveform, transforming traditional "time point measurement" into "state sequence analysis." By constructing multi-level shift registers in the FPGA hardware logic to buffer the sampled data, the specific moment when the logic state flips can be accurately located, and a high-frequency system clock is used as a "time scale" to achieve extremely high-resolution frequency measurement.

[0029] Specifically, the steps include the following: Based on the internal logic of the FPGA, the specific calculation process of this algorithm includes the following three key stages: Phase 1: Multiphase Data Buffering and Edge Detection Since the input is high-speed parallel sampling data (such as 8-channel or 16-channel parallel data of ADC), a high-speed shift register with an N-level depth is first built at the hardware level. Data input: Each system clock cycle, new parallel sampled data is pushed into the shift register; Edge detection: Real-time monitoring of the data flow in the shift register. When the logic state of the current sampling point is inconsistent with that of the previous sampling point (i.e., Data_current!=Data_previous), it is determined that a valid edge (rising edge or falling edge) has been captured. Even if the transition of the input waveform occurs between two system clocks, due to the continuity of parallel data, the transition will inevitably be captured in a register at a certain level, thus avoiding the "edge missed detection" problem that is easy to cause by traditional low-frequency sampling.

[0030] Phase Two: High-Precision Time Interval Calculation Once a valid transition edge is detected, the time interval calculation mechanism is immediately triggered: A timestamp snapshot is taken immediately within the same clock cycle when the transition edge is captured, and the current value of the system's high-frequency clock counter is read and used as the "timestamp" (T) of the current edge. n ); Period difference calculation: Compare the current timestamp with the timestamp of the previous captured edge in the same direction (T). n-1 Perform a subtraction operation to obtain the clock cycle count value between the two transition edges (ΔT=T). n -T n-1 ).

[0031] Metastability elimination and debouncing: To prevent false triggering caused by waveform jitter, an internal "debounce window" is configured. If multiple transitions occur consecutively within the set window, the algorithm only recognizes the first valid transition, thereby improving the robustness of the measurement.

[0032] Phase Three: Real-time Frequency Derivation & Filtering After obtaining the high-precision clock interval ΔT, the final mathematical conversion stage begins: Frequency estimation: Based on the formula F=Fclk / ΔT (where Fclk is the high-frequency system clock frequency inside the FPGA), the instantaneous frequency value of the current input waveform is calculated in real time.

[0033] Moving Average Filtering: In order to eliminate the small quantization errors that may exist in a single measurement, an internal first-in-first-out (FIFO) buffer is maintained. The weighted average or median value of the most recent N consecutive frequency calculation results is processed to finally output a smooth and stable frequency measurement result.

[0034] Timing State Sampling Module: This module is also implemented in hardware logic within the FPGA, receiving the same parallel sampled data. The module internally presets and runs a sampling point timing algorithm. Based on the precise test timing set by the ATE test program, this algorithm locates a specific sampling point in the corresponding parallel sampled data stream and directly reads or interpolates to calculate the signal logic state (0 or 1) at that moment, thereby achieving precise determination of the waveform state at any specified time.

[0035] In practical work, such as Figure 3 As shown, the ATE master controller writes one or more target sampling timestamps (relative to the start point of the test vector) to this unit via the configuration bus. Internally, it contains a timestamp counter synchronized with the test vector. When the timestamp counter matches a preset timestamp, the control logic latches the corresponding data bit from the current parallel data stream. For cases where the timestamp falls exactly between two sampling points, the final logic state can be determined using an interpolation algorithm (based on the states of the preceding and following sampling points).

[0036] In a preferred embodiment of the present invention, the aforementioned sampling point timing algorithm, as a hardware-level deterministic time sampling technique, is mainly used to establish a unified global time reference, mapping the abstract "test time" set by the ATE test program to a specific "sampling data index address". When the test time is out of sync with the physical sampling clock (i.e., there is a phase difference), the equivalent signal level at that specific moment is reconstructed using multiple adjacent sampling points through digital interpolation technology, thereby achieving "virtual sampling" that breaks through the physical sampling rate limit.

[0037] Specifically, the steps include the following: Based on the internal logic of the FPGA, the specific calculation process of this algorithm includes the following three key stages: Phase 1: Global Time Axis Alignment and Phase Resolution Unified time base: First, receive the absolute test time command from the ATE master (e.g., T). test =125.3ns).

[0038] Address conversion: Perform a division operation based on the sampling clock frequency (Fs) to convert the absolute time into the sampling point number (integer part) and the phase offset (fractional part).

[0039] Calculation formula: ; Phase difference: φ=(T test ×Fs)-Index; This step transforms "time" into "memory addressing" operations, which FPGAs excel at.

[0040] Phase Two: Polyphase Buffering Circular Buffer: A dual-port RAM (DPRAM) is allocated inside the FPGA to continuously write the latest parallel sampled data in a pipelined manner.

[0041] Window positioning: Based on the calculated index, the target sampling point and several neighboring sampling points (Context Window) are read from the buffer for subsequent interpolation calculations.

[0042] Phase 3: Fractional Delay Filtering and Interpolation When the phase difference φ is not 0, it means that the target time is not at the actual sampling point, and interpolation calculation is used at this time: Linear interpolation: If the current sample value is V1 and the next sample value is V2, then the voltage value at the target time is: V target =V1×(1-φ)+V2×φ; Higher-order interpolation (optional, for enhanced accuracy): To address high-frequency signal distortion, the algorithm can employ Lagrange interpolation or Farrow structure filters, using four or more sampling points before and after the curve to obtain results that are closer to the actual physical waveform than linear interpolation.

[0043] Control and Output Module: This module is responsible for receiving instructions from the ATE main controller (such as starting measurement, setting target timing, reading results, etc.), coordinating the work of the above modules, and outputting the measured frequency data and the status data of the specified timing point to the ATE main control system.

[0044] In practical work, a standard register mapping interface (such as APB, AXI-Lite, etc.) is implemented to receive configuration commands from the ATE master controller and temporarily store frequency measurement results and timing sampling results for the master controller to read.

[0045] A FPGA-based SOC ATE waveform measurement method includes: S1: Configure the high-speed data acquisition interface in the FPGA to latch the waveform under test at a predetermined rate (e.g., 1.6Gbps); S2: Convert serial data into parallel sampled data; S3: Simultaneously send the parallel sampling data to the waveform frequency measurement module and the timing status sampling module; S4: The waveform frequency measurement module calculates and outputs the waveform frequency value by analyzing data jumps; S5: The timing status sampling module extracts or calculates the logic level at the corresponding moment from the parallel data based on the timing parameters given externally and outputs it. S6: Report the measurement results through the control interface.

[0046] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A FPGA-based SOC ATE waveform measurement system, characterized in that, include: High-speed data acquisition interface module: A high-speed serial deserializer implemented inside the FPGA receives the waveform signal under test from the ATE test channel and converts the high-speed serial data stream into a parallel data stream for processing by the internal logic of the FPGA; Waveform frequency measurement module: Receives parallel sampled data from the high-speed data acquisition interface module; has a built-in waveform logic state interval measurement algorithm, including an edge detector and a high-precision counter, to capture signal transition edges in the parallel sampled data and calculate the frequency of the waveform under test based on the high-frequency clock count difference; Timing status sampling module: Receives parallel sampling data from the high-speed data acquisition interface module; The built-in sampling point timing algorithm includes a timestamp counter and interpolation algorithm control logic. It receives the target test time sent by the ATE master controller and obtains the logical state of the waveform at the specified time through time axis conversion, data buffering and digital interpolation. Control and Output Module: Receives configuration and measurement start / stop commands from the ATE main controller, coordinates the operation of each module, and sends back the waveform frequency and logic state measurement results at specified times to the ATE main controller.

2. The FPGA-based SOC ATE waveform measurement system according to claim 1, characterized in that, The high-speed data acquisition interface module includes an ISERDES interface unit and a clock and reset management unit, wherein: ISERDES Interface Unit: Using the 1.6Gbps ISERDES IP core provided by the FPGA, the measured signal with single-ended or differential input is converted into 16-bit wide parallel data; Clock and Reset Management Unit: Provides synchronous clock and reset signals for the entire FPGA's internal measurement logic.

3. The FPGA-based SOC ATE waveform measurement system according to claim 1, characterized in that, The specific steps of the waveform logic state interval measurement algorithm are as follows: Multiphase data buffering and edge detection: A multi-level deep shift register is built to buffer parallel sampled data, and the logic levels of adjacent sampling points are compared in real time to identify valid transitions of rising and falling edges; High-precision time interval calculation: Immediately after capturing the transition edge, latch the high-precision counter timestamp and calculate the clock count difference ΔT between two transition edges in the same direction; Configure a custom debouncing window to filter out false jumps caused by waveform jitter; Real-time frequency conversion and moving average filtering: The instantaneous frequency is calculated according to the formula F=Fclk / ΔT, where Fclk is the high-frequency system clock frequency inside the FPGA; multiple sets of continuous frequency results are weighted averaged or filtered by a first-in-first-out buffer to output a stable frequency measurement value.

4. The FPGA-based SOC ATE waveform measurement system according to claim 1, characterized in that, The specific steps of the sampling point timing algorithm are as follows: Global timeline alignment and phase resolution: Receive absolute test time T from ATE master controller test The sampling point index is obtained by converting the sampling clock frequency Fs. With phase offset φ=(T test ×Fs)-Index; Multiphase data buffering and window truncation: Parallel sampling data is continuously buffered through the dual-port ring DPRAM inside the FPGA, and the target sampling point and the sampling data of the previous and next neighboring areas are read according to the index; Fractional delay filtering and interpolation calculation: When the phase offset φ=0, the target sampling point level is read directly; when the phase offset φ≠0, linear interpolation is used for calculation.

5. The FPGA-based SOC ATE waveform measurement system according to claim 3, characterized in that, The multiphase data buffering and edge detection specifically include: Data input: Each system clock cycle, new parallel sampled data is pushed into the shift register; Edge transition determination: Real-time monitoring of the data flow in the shift register. When the logic state of the current sampling point is inconsistent with that of the previous sampling point, it is determined that a valid edge transition has been captured. The valid edge transition includes rising edge and falling edge.

6. The FPGA-based SOC ATE waveform measurement system according to claim 5, characterized in that, The high-precision time interval calculation specifically includes: Timestamp Snapshot: Within the same clock cycle that captures the transition edge, immediately read the current value of the system's high-frequency clock counter and use this as the timestamp T of the current edge. n ; Period difference calculation: Compare the current timestamp with the timestamp T of the previous captured same-direction transition edge. n-1 Performing the subtraction operation, we obtain the clock cycle count value ΔT=T between the two transition edges. n- T n-1 ; Metastability elimination and debouncing: Set a debouncing window. If multiple transitions occur consecutively within the set debouncing window, only the first valid transition is recorded.

7. The FPGA-based SOC ATE waveform measurement system according to claim 4, characterized in that, The linear interpolation specifically includes: If the current sample value is V1 and the next sample value is V2, then the voltage value at the target time is: V target =V1×(1-φ)+V2×φ.

8. A FPGA-based SOC ATE waveform measurement method, characterized in that, Includes the following steps: S1: Configure the high-speed data acquisition interface in the FPGA to latch the waveform to be measured at a preset rate; S2: Convert serial data into parallel sampled data; S3: Simultaneously send the parallel sampling data to the waveform frequency measurement module and the timing status sampling module; S4: The waveform frequency measurement module calculates and outputs the waveform frequency value by analyzing data jumps; S5: The timing status sampling module extracts or calculates the logic level at the corresponding moment from the parallel data according to the preset timing parameters and outputs it. S6: Report the measurement results through the control interface.

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