A new energy battery multi-channel electric variable synchronous acquisition and calibration device

Abstract

The application discloses a new energy battery multi-channel electric variable synchronous acquisition and calibration device, relates to the technical field of electric variable synchronous acquisition and calibration, and comprises a three-stage deterministic clock synchronization network, which is used for generating a global clock reference signal and distributing the global clock reference signal to each acquisition node through equal-length differential wiring, each node generates a local sampling clock and carries a time stamp after being locked through a digital phase-locked loop, the time stamp deviation of each node is continuously checked, and re-phase locking is triggered when the time stamp deviation exceeds a limit. According to the application, the three-stage deterministic clock synchronization network is matched with a full-parallel independent acquisition array, equal-length differential clock distribution and node-by-node phase locking checking are implemented, nanosecond-level synchronization precision of all channels is realized, inherent time difference of multiplexing polling is eliminated from an architecture level, and systematic errors of power calculation and SOC estimation caused by voltage and current time sequence misplacement under a large-current transient working condition are avoided.

Description

Technical Field

[0001] This invention relates to the field of synchronous acquisition and calibration of electrical variables, specifically to a multi-channel synchronous acquisition and calibration device for electrical variables in new energy batteries. Background Technology

[0002] In the entire life cycle operation of new energy battery systems, high-precision synchronous acquisition of multi-dimensional electrical variables such as voltage, current, and temperature is the core foundation for ensuring battery safety management, performance evaluation, and state estimation. Traditional acquisition schemes are limited by architecture and generally suffer from inherent shortcomings such as channel timing misalignment and difficulty in dynamically compensating for accuracy drift, which directly restricts the accuracy of the battery management system (BMS) in estimating the state of charge (SOC) and state of health (SOH) and the reliability of its dynamic response.

[0003] To address this pain point, a dedicated acquisition and calibration device integrating multi-channel parallel sampling, nanosecond-level synchronous triggering, and online automatic calibration functions has emerged. Relying on a built-in high-precision reference source, it compensates for the gain bias and consistency error of each channel in real time, controlling the measurement error to the ppm level. This provides high-confidence data support for accurate BMS state estimation and is suitable for vehicle power battery management, energy storage power station safety monitoring, and production line formation and capacity testing scenarios.

[0004] However, existing similar devices still have significant technical bottlenecks. First, they mostly adopt master-slave clock cascade and multiplexed polling architectures, resulting in microsecond to millisecond-level deviations in the sampling time of each channel. Under high-current transient conditions, the timing of voltage and current data is misaligned, causing systematic errors in power calculation and SOC estimation. Second, the calibration mechanism has shortcomings, relying heavily on offline factory calibration, using only a single voltage reference, without covering independent calibration of current and temperature channels, and without achieving ADC channel-by-channel gain and zero-point bias compensation. Accuracy degradation caused by temperature drift and device aging cannot be corrected in real time. Third, under high-voltage conditions, the isolation design is difficult to balance bandwidth and withstand voltage. Common-mode interference and channel crosstalk degrade the signal-to-noise ratio, and the channel scalability is insufficient, making it difficult to optimize sampling rate and accuracy in a coordinated manner. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries, comprising a three-level deterministic clock synchronization network, used to generate a global clock reference signal and distribute it to each acquisition node through equal-length differential traces. Each node generates a local sampling clock and attaches a timestamp after being locked by a digital phase-locked loop, continuously verifying the timestamp deviation of each node, and triggering re-phase-locking when the limit is exceeded. The fully parallel independent acquisition array includes N acquisition channel units, each channel is equipped with an independent analog-to-digital conversion unit, fully parallel sampling under hard trigger signal and no multiplexer between channels, each channel front end is equipped with signal conditioning circuit independently configured according to signal type and active shielding drive circuit to drive the inner shielding layer to the same potential as the core wire; The multi-dimensional online self-calibration module between operating conditions includes a multi-parameter reference source matrix, a calibration switching matrix, and a channel-by-channel error compensation engine. The calibration switching matrix senses the operating condition switching time through the BMS operating condition status line. Within the electrical stability window generated by the switching, each channel is sequentially switched to the voltage reference source, current reference source, and temperature reference source to collect readings and calculate the gain error and zero-point offset. Each channel performs calibration in a time-sharing manner, while the other channels sample normally during the calibration period. The channel-by-channel error compensation engine uses a third-order polynomial model with temperature as the variable to perform channel-by-channel dynamic compensation on the original ADC readings. The compensation coefficients are updated and stored after each calibration. The adaptive isolation and active anti-interference unit sets up a magnetically coupled digital isolator in each signal link to achieve independent isolation, and dynamically compensates for common-mode components by injecting compensation voltage through the reference terminal of the instrumentation amplifier in real time. The common-mode rejection ratio is adaptively adjusted according to the measured common-mode voltage. The edge-end multidimensional data fusion module embeds an FPGA within the acquisition unit to perform filtering and feature extraction on the compensated data. It packages the multidimensional electrical variables at the same time into a structured data packet with a unified timestamp and uploads it via the TSN bus.

[0007] Preferably, the three-level deterministic clock synchronization network includes a cryogenic crystal master clock unit, an equal-length differential clock distribution tree, and a local phase-locked loop and timestamp verification unit; the cryogenic crystal master clock unit uses an OCXO to output a 10MHz reference square wave with a frequency stability better than 0.01ppm; the equal-length differential clock distribution tree uses serpentine compensation to ensure that all differential traces are physically of equal length, with length errors controlled within ±0.1mm; the local phase-locked loop and timestamp verification unit has a timestamp resolution better than 1ns and a re-phase-locking threshold of 10ns.

[0008] Preferably, the independent analog-to-digital converter unit of the acquisition channel unit is 24-bit. The ADC is a type of ADC; the signal conditioning circuit includes a programmable gain amplifier (PGA) and an anti-aliasing filter. The voltage channel has a range of 0.5V and a gain of 1x, the current channel has a range of 0.50mV and a gain of 100x after passing through a shunt resistor, and the temperature channel uses a PT1000 three-wire system with an excitation current of 1mA. The active shielding drive circuit adopts a three-coaxial cable structure, the buffer amplifier operates as a unity-gain follower, and the outer shielding layer is grounded. The fully parallel independent acquisition array uses 8 channels as the basic acquisition unit, which are cascaded through an LVDS bus. After a new unit is connected, clock phase-locked loop and channel address mapping are automatically completed.

[0009] Preferably, the voltage reference source of the multi-parameter reference source matrix provides at least two known voltage signals, including a 0V zero-point reference range and a full-scale reference range; the current reference source provides at least two known constant current signals that are converted by a precision shunt resistor to cover the zero-point and full-scale points; and the temperature reference source uses a PT1000 and a constant temperature bath to provide at least two known temperature points corresponding to resistance signals.

[0010] Preferably, the error compensation model of the channel-by-channel error compensation engine is a third-order polynomial with temperature as the variable, wherein the temperature is obtained by actual measurement from the onboard temperature sensor, and the compensation coefficient is updated by least squares fitting after each online calibration by injecting no less than 4 known reference signals and stored in non-volatile memory.

[0011] Preferably, the magnetically coupled digital isolator uses a chip-level transformer-based magnetic coupling device with a bandwidth greater than 150MHz, an isolation withstand voltage greater than or equal to 5kV, and each channel's isolation power supply circuit is independent of each other; the common-mode voltage detection circuit is composed of a voltage divider network, and a compensation voltage proportional to the measured common-mode voltage is injected through the reference terminal of the instrumentation amplifier, so that the effective common-mode input voltage approaches zero.

[0012] Preferably, the FPGA performs configurable FIR or IIR filtering on the data of each channel. The number of FIR taps can be configured to be 32-256. It extracts voltage extreme values, current effective values, and temperature change rate features, and performs real-time judgment on voltage mutation and temperature over-limit to trigger hardware interrupt alarm. The structured data packet contains a unified timestamp and the voltage, current, and temperature data of all channels at that moment. The TSN bus adopts the IEEE 802.1 protocol, and the transmission delay is less than 100μs under reserved bandwidth.

[0013] Preferably, the test objects applicable to the device include lithium-ion batteries, lithium iron phosphate batteries, solid-state batteries, supercapacitors, and fuel cells.

[0014] A method for synchronous acquisition and calibration of multi-channel electrical variables in new energy batteries includes the following steps: S1. The temperature-controlled crystal oscillator main clock unit outputs a 10MHz reference square wave, which is distributed to each acquisition node through equal-length differential traces. After each node is locked by a digital phase-locked loop, it generates a local sampling clock with a timestamp attached. It continuously checks the timestamp deviation and triggers re-locking when the limit is exceeded. S2. Each acquisition channel unit starts sampling simultaneously under a hard trigger signal. The front-end signal conditioning circuit independently configures the range and filtering according to the signal type. The active shielding drive circuit drives the inner shielding layer to the same potential as the core wire. S3. The calibration switching matrix senses the time of operation switching through the BMS operating condition status line. Within the electrical stability window, each channel is switched to the voltage reference source, current reference source, and temperature reference source at each level to collect readings and compare them with known reference values ​​to calculate gain error and zero offset. Each channel is executed in time-sharing. When one channel is calibrated, the other channels are sampled normally. S4. The channel-by-channel error compensation engine reads the temperature of the onboard temperature sensor, retrieves the compensation coefficient of the current channel at the current temperature, and substitutes it into the error compensation model with temperature as the variable to calculate the compensated value. The S5 and FPGA perform digital filtering and feature extraction on the compensated data of each channel, and package the multidimensional electrical variables at the same time into a structured data packet with a unified timestamp. The data packet is then uploaded to the BMS or host computer via the IEEE 802.1 TSN protocol with reserved bandwidth.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In this invention, a deterministic clock synchronization network is used in conjunction with a fully parallel independent acquisition array. Equal-length differential clock distribution and node-by-node phase-locked loop verification achieve nanosecond-level synchronization accuracy across all channels. This eliminates the inherent time difference of multiplexing polling at the architectural level, avoiding systematic errors in power calculation and SOC estimation caused by voltage and current timing misalignment under high-current transient conditions. The multi-dimensional online self-calibration module covers all parameters including voltage, current, and temperature. Based on a third-order temperature compensation model and channel-by-channel coefficient fitting, it corrects temperature drift, device aging, and individual ADC discrete errors in real time without interrupting normal acquisition. This ensures that the measurement accuracy across the entire temperature range remains stable at the ppm level for a long period, significantly reducing equipment maintenance costs and downtime calibration losses. 2. This invention significantly improves signal reliability and system adaptability in high-voltage, high-interference scenarios through multi-level anti-interference design and edge-end data fusion architecture. The adaptive isolation and active anti-interference unit balances high bandwidth and high voltage withstand requirements with magnetically coupled digital isolation. Combined with dynamic common-mode active compensation and tri-coaxial active shielding technology, it synergistically improves the signal-to-noise ratio of weak signals from three dimensions: isolation protection, common-mode suppression, and cable crosstalk reduction, adapting to the strong electromagnetic operating environment of 800V high-voltage battery systems. The modular cascaded architecture supports flexible expansion of the number of channels without degradation of synchronization accuracy. The edge-end FPGA performs data filtering, feature extraction, and timing fusion, and with TSN deterministic transmission outputting structured data, it can directly support high-precision BMS state estimation. It is widely adaptable to the entire lifecycle of battery R&D, production line formation, energy storage operation and maintenance, and has strong engineering application value. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the workflow of a multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to the present invention. Figure 2This is a flowchart of the multi-dimensional online self-calibration process for working condition gaps in a multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1: Refer to Figures 1-2 As shown: The present invention provides a multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries, including a three-level deterministic clock synchronization network, a fully parallel independent acquisition array, a multi-dimensional online self-calibration module for working condition gaps, an adaptive isolation and active anti-interference unit, and an edge-end multi-dimensional data fusion module. The modules work together to achieve full-channel nanosecond-level synchronous sampling, full-parameter online self-calibration, and high-confidence data fusion output.

[0019] A three-level deterministic clock synchronization network serves as the global timing reference source. A 10MHz high-stability reference square wave signal is generated by a temperature-controlled crystal oscillator master clock unit, with a frequency stability better than 0.01ppm, eliminating the erosion of synchronization accuracy by clock jitter at its source. This reference square wave signal is distributed to each acquisition node via an equal-length differential clock distribution tree. In the PCB layout, all clock differential traces are physically equal in length through serpentine compensation. Regardless of the physical distance between nodes, the signal arrives at each node at a strictly consistent time, thus eliminating the propagation delay difference and jitter accumulated by the step-by-step forwarding in the master-slave clock cascade architecture. This solves the inherent defect in existing technologies where the sampling time of each channel has a microsecond to millisecond level deviation. Each acquisition node's local phase-locked loop (PLL) and timestamp verification unit are locked to the global reference signal transmitted via the equal-length differential traces using a digital phase-locked loop (DPLL) to generate a local sampling clock. Each sample is accompanied by a timestamp generated by a high-resolution timer, with a timestamp resolution better than 1ns. The local phase-locked loop and timestamp verification unit continuously compares the timestamp deviation of each acquisition node. When the maximum deviation exceeds 10ns, the corresponding node is automatically triggered to re-lock phase, enabling the synchronization mechanism to have self-checking and self-repairing capabilities. This ensures that the synchronization accuracy of the entire channel is always maintained at the nanosecond level throughout the entire operation, avoiding systematic deviations in power calculation and SOC estimation caused by timing misalignment of voltage and current data under high-current transient conditions.

[0020] A three-level deterministic clock synchronization network outputs a hard trigger signal to each acquisition channel unit of the fully parallel independent acquisition array, enabling all acquisition channel units to initiate sampling and conversion simultaneously. The fully parallel independent acquisition array comprises N structurally identical acquisition channel units, where N is an integer greater than or equal to 2. Each acquisition channel unit is equipped with an independent 24-bit Σ-Δ analog-to-digital converter. No multiplexers are used between channels, eliminating the inherent inter-channel sampling time difference in polling scans using multiplexers in existing technologies, thus eliminating the root cause of timing deviations at the architectural level. Each acquisition channel unit has a signal conditioning circuit at its front end, including a programmable gain amplifier (PGA) and an anti-aliasing filter. Ranges and filtering parameters are independently set for voltage, current, and temperature signals. The voltage channel range is set to 0.5V with a PGA gain of 1; the current channel range is 0.50mV after a shunt resistor with a PGA gain of 100; and the temperature channel uses a PT1000 three-wire connection with an excitation current of 1mA. All signals are acquired with high signal-to-noise ratio within their respective optimal ranges. Each acquisition channel unit is also equipped with an active shielding drive circuit, employing a three-coaxial cable structure, including a core wire, an inner shielding layer, and an outer shielding layer. A buffer amplifier drives the inner shielding layer to the same potential as the core wire using a unity-gain follower, ensuring zero potential difference between the core wire and the inner shielding layer. This eliminates leakage current caused by cable distributed capacitance and crosstalk between channels. The outer shielding layer is grounded to provide electromagnetic shielding, improving the signal-to-noise ratio of weak signals and resolving the defect in existing technologies where PCB parasitic capacitance coupling crosstalk severely erodes signal quality. The fully parallel independent acquisition array uses 8 channels as the basic acquisition unit. These basic acquisition units are cascaded via an LVDS deterministic high-speed bus. New units automatically complete clock phase-locking and channel address mapping upon connection, ensuring no degradation in synchronization accuracy when expanding the number of channels. This solves the problems of fixed channel numbers, difficulty in synchronous clock allocation during expansion, and increased bus load in existing technologies.

[0021] The multi-dimensional online self-calibration module for working condition gaps is the core innovation of this invention, comprising a multi-parameter reference source matrix, a calibration switching matrix, and a channel-by-channel error compensation engine. The multi-parameter reference source matrix consists of three types of precision reference sources: voltage, current, and temperature. This expands the calibration coverage from the single dimension of voltage (as in existing technologies) to include three electrical variables: voltage, current, and temperature, eliminating the long-standing blind spot of lacking independent calibration for the current and temperature channels. The voltage reference source provides at least two known voltage signals, including a 0V zero-point reference range and a full-scale voltage reference range. The current reference source uses a precision current source to output at least two known constant current signals, which are converted into known voltage signals by a precision shunt resistor and then injected into the current acquisition channel, covering the zero and full-scale points of the current channel. The temperature reference source uses a precision platinum resistance thermometer (PT1000) and a constant temperature bath to provide resistance signals corresponding to at least two known temperature points, which are injected into the temperature acquisition channel to achieve end-to-end calibration of the temperature acquisition link. A low-on-resistance analog switch matrix is ​​set before the front-end signal conditioning circuit of each acquisition channel unit. Under FPGA control, the analog switch matrix switches the acquisition channel input between the battery signal and the reference source. The calibration switching matrix senses the battery charging and discharging state switching time in real time through the BMS operating condition status line. When the battery switches from charging to resting or from discharging to resting, there is an electrical stability window of several milliseconds to tens of milliseconds. Within this window, the calibration switching matrix automatically executes the calibration process, sequentially switching each channel input to the voltage reference source, current reference source, and temperature reference source at each level, acquiring ADC readings and comparing them with known reference values ​​to calculate the gain error and zero-point bias of the current channel. Each channel performs calibration in a time-sharing manner. While one channel is being calibrated, the other channels continue normal sampling. The calibration process runs in parallel with normal acquisition, achieving completely uninterrupted online self-calibration. This solves the inherent shortcomings of existing technologies, such as calibration relying on offline calibration during shutdown and the inability to correct accuracy degradation caused by temperature drift and component aging during operation in real time. The channel-by-channel error compensation engine maintains a set of temperature-related compensation coefficients for each acquisition channel. It employs a third-order polynomial model with temperature as the variable to dynamically compensate the raw ADC readings channel by channel. The temperature is measured by an onboard temperature sensor. After each online calibration, the compensation coefficients are updated using least-squares fitting by injecting at least four known reference signals and stored in non-volatile memory. This compensation model simultaneously compensates for gain error, zero-point bias, temperature drift nonlinearity, and the nonlinearity of the analog-to-digital conversion transfer function. Each channel maintains its own independent compensation coefficients to accurately correct the individual discreteness of each ADC chip, rather than sharing a single set of parameters across all channels. This ensures that the measurement accuracy across the entire temperature range remains consistently at the ppm level, eliminating the need for downtime maintenance.

[0022] Adaptive isolation and active anti-interference units are distributed in the signal link of each acquisition channel unit, including magnetically coupled digital isolators, common-mode voltage active detection and compensation circuits, and active shielding drive circuits. The magnetically coupled digital isolators employ chip-level transformer-based magnetically coupled digital isolation devices with a bandwidth greater than 150MHz and an isolation withstand voltage greater than or equal to 5kV, far exceeding the bandwidth limitations of existing optocoupler isolation technologies. This simultaneously meets the dual requirements of high-speed ADC data transmission and the 400V to 800V safety isolation of electric vehicle high-voltage battery systems. Each acquisition channel unit is independently configured with a magnetically coupled digital isolator, and the isolation power supply circuits for each channel are independent, avoiding coupling interference between channels through the isolator power supply circuits. The common-mode voltage active detection and compensation circuit sets up a common-mode voltage detection circuit composed of a voltage divider network at the front end of each acquisition channel unit. It measures the common-mode component introduced by the total battery voltage in real time, and injects a compensation voltage proportional to the measured common-mode voltage through the reference terminal of the instrumentation amplifier, so that the effective common-mode input voltage approaches zero. The common-mode rejection ratio of the instrumentation amplifier is adaptively adjusted according to the measured common-mode voltage, rather than relying on fixed parameters. This achieves adaptive suppression of common-mode interference under dynamic operating conditions and solves the passive isolation defect of the fixed CMRR instrumentation amplifier in the prior art, which cannot adapt to dynamic common-mode interference. The active shielding drive circuit, which is the active shielding drive circuit in the acquisition channel unit, drives the inner shielding layer of the three coaxial cable to the same potential as the core wire through a buffer amplifier in a unity-gain follower manner. It works in conjunction with magnetic coupling digital isolation and dynamic common-mode compensation. The three protect the signal integrity from three aspects: isolation withstand voltage and bandwidth protection, active suppression of common-mode interference, and elimination of cable leakage current. The crosstalk suppression capability between channels and the signal-to-noise ratio of weak signals are significantly improved.

[0023] The edge-end multi-dimensional data fusion module receives the output data from each acquisition channel unit of the fully parallel independent acquisition array after compensation by a channel-by-channel error compensation engine. An FPGA is embedded within the basic acquisition unit to perform local preprocessing. The FPGA performs configurable FIR or IIR filtering on the compensated data of each channel. The number of FIR filter taps can be configured from 32 to 256 to eliminate switching noise and high-frequency interference. It extracts key features such as voltage extremes, current RMS values, and temperature change rates. Real-time judgment of voltage surges and temperature exceedances is performed, triggering hardware interrupt alarms to achieve real-time anomaly detection and rapid response at the edge. The FPGA fuses and aligns voltage, current, and temperature data collected simultaneously with a unified timestamp, packaging them into a structured data packet containing the unified timestamp and all channel voltage, current, and temperature data at that moment. The output is structured data with time alignment and multi-dimensional fusion completed at the data acquisition source, rather than the independent and fragmented raw sample values ​​of each channel. After receiving this data, the BMS can directly use it for dynamic estimation of state of charge, health status, and remaining service life without additional time alignment processing. This changes the communication bottlenecks and processing delays caused by the serial operation mode of acquiring raw data first and then uploading it to the host computer for processing in existing technologies. The structured data packet is uploaded to the BMS or host computer via the IEEE 802.1 Time-Sensitive Networking Protocol (TSN) deterministic communication unit. The TSN protocol provides microsecond-level deterministic transmission delay and supports bandwidth reservation. Data transmission does not experience jitter due to increased bus load; with reserved bandwidth, the transmission delay is less than 100μs, improving the system's response speed to transient conditions and the reliability of data transmission.

[0024] A three-level deterministic clock synchronization network ensures nanosecond-level synchronization accuracy across all channels, providing a deterministic timing foundation for the fully parallel independent acquisition array. The fully parallel independent acquisition array eliminates the root causes of timing deviations at the architectural level and provides high signal-to-noise ratio acquisition for various signals. The multi-dimensional online self-calibration module between operating conditions continuously maintains the measurement accuracy of various types of electrical variables in each channel during full-condition operation. The adaptive isolation and active anti-interference unit ensures signal integrity in high-voltage and strong interference environments. The edge-end multi-dimensional data fusion module outputs high-confidence data packets in a deterministic communication manner after completing multi-dimensional data alignment and feature extraction at the acquisition source. These five modules are interconnected and interlocked from the clock source, acquisition architecture, calibration mechanism, physical isolation to data processing, forming a complete closed-loop technical solution that achieves a breakthrough in which synchronization, accuracy, and channel scale are difficult to achieve simultaneously in existing technologies.

[0025] Example 2: According to Figures 1-2As shown, the three-level deterministic clock synchronization network includes a cryogenic crystal master clock unit, an equal-length differential clock distribution tree, and a local phase-locked loop and timestamp verification unit. The cryogenic crystal master clock unit uses an OCXO chip to output a 10MHz reference square wave with a frequency stability better than 0.01ppm. This high-stability source reference replaces the low-precision clock of ordinary crystal oscillators affected by temperature drift in existing technologies, laying the foundation for system-wide synchronization. The equal-length differential clock distribution tree uses serpentine compensation in the PCB layout to ensure all differential traces are physically of equal length, with trace length errors controlled within ±0.1mm. This ensures that the propagation time of the 10MHz reference square wave signal from the cryogenic crystal master clock unit to each acquisition node is strictly consistent, eliminating the accumulated delay difference caused by the cascaded forwarding of master and slave clocks in existing technologies. Regardless of the physical location of the acquisition nodes on the PCB, the time deviation of the received clock at each node is compressed to the sub-nanosecond level. The local phase-locked loop and timestamp verification unit sets up a digital phase-locked loop (DPLL) and a high-resolution timer at each acquisition node. The timestamp resolution is better than 1 ns. After locking the global reference, each node generates a local sampling clock and attaches a timestamp with each sampling. The local phase-locked loop and timestamp verification unit continuously compares the maximum deviation of the timestamps of each node. When the deviation exceeds the re-phase-locking threshold of 10 ns, the corresponding node is automatically triggered to re-execute phase-locking. This ensures that the synchronization accuracy is maintained in long-term operation without being degraded by occasional disturbances, and solves the problem of the lack of self-checking and error correction capabilities in the synchronization mechanism of the prior art.

[0026] Each acquisition channel unit of the fully parallel independent acquisition array is equipped with an independent 24-bit Σ-Δ analog-to-digital converter (ADC). No multiplexers are used between channels; each channel independently completes the ADC, avoiding the sampling time difference between channels caused by multiplexer polling switching. The signal conditioning circuit includes a programmable gain amplifier (PGA) and an anti-aliasing filter. Independent ranges and gains are set for voltage, current, and temperature signals: the voltage channel range is set to 0.5V with a PGA gain of 1; the current channel range is 0.50mV after a shunt resistor with a PGA gain of 100; and the temperature channel uses a PT1000 three-wire connection with a 1mA excitation current. All signals are acquired within their optimal range, resulting in high full-scale utilization, low quantization noise as a percentage of the effective signal, and improved signal-to-noise ratio. The active shielding drive circuit adopts a three-coaxial cable structure, including a core wire, an inner shielding layer, and an outer shielding layer. The buffer amplifier operates as a unity-gain follower, driving the inner shielding layer to the same potential as the core wire. The potential difference between the core wire and the inner shielding layer is zero, and the cable's distributed capacitance does not generate leakage current. The outer shielding layer is grounded to provide electromagnetic shielding, thus substantially improving the signal-to-noise ratio of weak signals, such as the AC impedance signal of a single battery cell. The fully parallel independent acquisition array uses 8 channels as the basic acquisition unit. Each basic acquisition unit is cascaded via an LVDS bus. When a new unit is added, clock phase-locking and channel address mapping are automatically completed. When the number of channels is expanded from 8 to more than 256, the synchronization accuracy does not degrade, solving the problems of fixed channel number, increased bus load during expansion, and difficulty in synchronous clock allocation in existing technologies.

[0027] The multi-parameter reference source matrix of the multi-dimensional online self-calibration module during operating conditions includes a voltage reference source, a current reference source, and a temperature reference source. The voltage reference source provides at least two known voltage signals, including a 0V zero-point reference range and a full-scale reference range, covering the two key calibration points of the voltage acquisition link: zero-point and full-scale. The current reference source provides at least two known constant current signals, which, after conversion by a precision shunt resistor, cover the zero-point and full-scale points of the current acquisition channel, enabling end-to-end calibration of the entire current acquisition link from signal conditioning to analog-to-digital conversion. The temperature reference source uses a precision platinum resistance thermometer PT1000 and a constant temperature bath to provide resistance signals corresponding to at least two known temperature points, which, after being injected into the temperature acquisition channel, achieve end-to-end calibration of the temperature acquisition link. The matrix composed of these three types of reference sources expands the calibration dimension from the single dimension of voltage in existing technologies to full coverage of voltage, current, and temperature, eliminating the blind spots of the long-standing lack of independent calibration for the current and temperature channels. The error compensation model of the channel-by-channel error compensation engine is a third-order polynomial with temperature as the variable. The temperature is obtained by actual measurement from the onboard temperature sensor. After each online calibration, the compensation coefficients are updated by least squares fitting using no less than four known reference signals and stored in non-volatile memory. Using at least four reference signals for least squares fitting ensures that all four coefficients of the third-order polynomial have sufficient data support, rather than relying solely on linear calibration at zero and full scale. This results in high fitting accuracy and captures the nonlinear characteristics of the analog-to-digital conversion transfer function. Embedding temperature as a variable in the compensation model allows gain error, zero-point bias, temperature drift nonlinearity, and transfer function nonlinearity to be compensated simultaneously in the same third-order polynomial, rather than separating temperature compensation from gain compensation. Each channel maintains an independent set of coefficients to accurately correct the individual discreteness of each ADC chip. Measurement accuracy remains consistently at the ppm level across the entire temperature range of -40℃ to 85℃, requiring no downtime maintenance.

[0028] The magnetically coupled digital isolator of the adaptive isolation and active anti-interference unit uses a chip-level transformer-based magnetic coupling device with a bandwidth greater than 150MHz and an isolation withstand voltage greater than or equal to 5kV. Each channel's isolation power supply circuit is independent. In existing technologies, optocoupler isolators typically have a bandwidth of less than 1MHz. The 24-bit data transmission rate of high-speed ADCs far exceeds the bandwidth capacity of optocouplers. The magnetically coupled digital isolator, with a bandwidth of over 150MHz, meets the real-time transmission requirements of 24-bit Σ-Δ ADC data output. Simultaneously, its isolation withstand voltage of over 5kV covers the safety isolation requirements of 400V to 800V high-voltage battery systems in electric vehicles, resolving the contradiction between bandwidth and withstand voltage in optocoupler solutions. The independent design of each channel's isolation power supply circuit avoids cross-coupling interference generated through the power supply circuit when multiple channels share the same isolation side power supply. The common-mode voltage detection circuit consists of a voltage divider network. It measures the common-mode component introduced by the total battery voltage in real time at the front end of each acquisition channel. A compensation voltage proportional to the measured common-mode voltage is injected through the reference terminal of the instrumentation amplifier, so that the effective common-mode input voltage approaches zero. The common-mode rejection ratio of the instrumentation amplifier is adaptively adjusted according to the measured common-mode voltage rather than relying on fixed parameters. When the total battery voltage rises from 200V to 800V, the compensation amount automatically changes accordingly, which solves the defect of the fixed CMRR instrumentation amplifier in the prior art that cannot adaptively suppress dynamic common-mode interference.

[0029] The FPGA in the edge-end multi-dimensional data fusion module performs configurable FIR or IIR filter filtering on the compensated data of each channel. The number of FIR filter taps can be configured from 32 to 256, and the filtering depth can be flexibly selected according to the signal spectrum characteristics and interference distribution. This allows for fast response with fewer taps in low-interference environments, or for steeper frequency domain cutoff characteristics by increasing the number of taps in high-interference environments. The FPGA simultaneously extracts key features such as voltage extreme values, current RMS values, and temperature change rates, and performs real-time judgment to trigger hardware interrupt alarms for voltage abrupt changes and temperature exceeding limits. Anomaly detection and feature extraction are completed at the data acquisition source, eliminating the need for the BMS to perform a full scan of the original waveform to obtain key status indicators. The structured data packet contains a unified timestamp and voltage, current, and temperature data for all channels at that moment. The voltage, current, and temperature data are fused and aligned with a unified timestamp at the data acquisition source. After receiving the data, the BMS can directly use it for dynamic estimation of SOC, SOH, and RUL without additional time alignment processing. The TSN bus adopts the IEEE 802.1 time-sensitive networking protocol, with a transmission delay of less than 100μs under reserved bandwidth. The TSN protocol provides deterministic transmission scheduling instead of CSMA contention-based bus arbitration, making data transmission delay predictable and not jittered due to increased bus load. This solves the problem of uncertain transmission delay of the CAN bus under high load in the prior art.

[0030] The tested objects include lithium-ion batteries, lithium iron phosphate batteries, solid-state batteries, supercapacitors, and fuel cells, covering the mainstream electrochemical energy storage and energy conversion devices in the current new energy field. Different types of tested objects can be adapted simply by adjusting the range and gain parameters in the signal conditioning circuit. The core synchronous acquisition and online calibration mechanism of the device is universal for all types of batteries.

[0031] Example 3: According to Figure 1 As shown, a method for synchronous acquisition and calibration of multi-channel electrical variables in new energy batteries includes the following steps: S1. The temperature-controlled crystal oscillator main clock unit outputs a 10MHz reference square wave, which is distributed to each acquisition node through equal-length differential traces. After each node is locked by a digital phase-locked loop, it generates a local sampling clock with a timestamp attached. It continuously checks the timestamp deviation and triggers re-locking when the limit is exceeded. S2. Each acquisition channel unit starts sampling simultaneously under a hard trigger signal. The front-end signal conditioning circuit independently configures the range and filtering according to the signal type. The active shielding drive circuit drives the inner shielding layer to the same potential as the core wire. S3. The calibration switching matrix senses the time of operation switching through the BMS operating condition status line. Within the electrical stability window, each channel is switched to the voltage reference source, current reference source, and temperature reference source at each level to collect readings and compare them with known reference values ​​to calculate gain error and zero offset. Each channel is executed in time-sharing. When one channel is calibrated, the other channels are sampled normally. S4. The channel-by-channel error compensation engine reads the temperature of the onboard temperature sensor, retrieves the compensation coefficient of the current channel at the current temperature, and substitutes it into the error compensation model with temperature as the variable to calculate the compensated value. The S5 and FPGA perform digital filtering and feature extraction on the compensated data of each channel, and package the multidimensional electrical variables at the same time into a structured data packet with a unified timestamp. The data packet is then uploaded to the BMS or host computer via the IEEE 802.1 TSN protocol with reserved bandwidth.

[0032] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-channel synchronous acquisition and calibration device for electrical variables in new energy batteries, characterized in that: It includes a three-level deterministic clock synchronization network, which generates a global clock reference signal and distributes it to each acquisition node through equal-length differential traces. Each node generates a local sampling clock and attaches a timestamp after locking it through a digital phase-locked loop. It continuously checks the timestamp deviation of each node and triggers re-locking when the limit is exceeded. The fully parallel independent acquisition array includes N acquisition channel units, each channel is equipped with an independent analog-to-digital conversion unit, fully parallel sampling under hard trigger signal and no multiplexer between channels, each channel front end is equipped with signal conditioning circuit independently configured according to signal type and active shielding drive circuit to drive the inner shielding layer to the same potential as the core wire; The multi-dimensional online self-calibration module between operating conditions includes a multi-parameter reference source matrix, a calibration switching matrix, and a channel-by-channel error compensation engine. The calibration switching matrix senses the operating condition switching time through the BMS operating condition status line. Within the electrical stability window generated by the switching, each channel is sequentially switched to the voltage reference source, current reference source, and temperature reference source to collect readings and calculate the gain error and zero-point offset. Each channel performs calibration in a time-sharing manner, while the other channels sample normally during the calibration period. The channel-by-channel error compensation engine uses a third-order polynomial model with temperature as the variable to perform channel-by-channel dynamic compensation on the original ADC readings. The compensation coefficients are updated and stored after each calibration. The adaptive isolation and active anti-interference unit sets up a magnetically coupled digital isolator in each signal link to achieve independent isolation, and dynamically compensates for common-mode components by injecting compensation voltage through the reference terminal of the instrumentation amplifier in real time. The common-mode rejection ratio is adaptively adjusted according to the measured common-mode voltage. The edge-end multidimensional data fusion module embeds an FPGA within the acquisition unit to perform filtering and feature extraction on the compensated data. It packages the multidimensional electrical variables at the same time into a structured data packet with a unified timestamp and uploads it via the TSN bus.

2. The multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to claim 1, characterized in that: The three-level deterministic clock synchronization network includes a temperature-controlled crystal master clock unit, an equal-length differential clock distribution tree, and a local phase-locked loop and timestamp verification unit. The temperature-controlled crystal oscillator master clock unit uses an OCXO to output a 10MHz reference square wave with a frequency stability better than 0.01ppm; the equal-length differential clock distribution tree uses serpentine compensation to ensure that all differential traces are physically equal in length, with the length error controlled within ±0.1mm; the local phase-locked loop and timestamp verification unit has a timestamp resolution better than 1ns and a re-phase-lock threshold of 10ns.

3. The multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to claim 1, characterized in that: The independent analog-to-digital converter unit of the acquisition channel unit adopts a 24-bit architecture. The signal conditioning circuit includes a programmable gain amplifier (PGA) and an anti-aliasing filter. The voltage channel has a range of 0.5V and a gain of 1x. The current channel has a range of 0.50mV and a gain of 100x after passing through a shunt resistor. The temperature channel uses a PT1000 three-wire system with an excitation current of 1mA. The active shielding drive circuit adopts a three-coaxial cable structure, the buffer amplifier operates as a unity-gain follower, and the outer shielding layer is grounded; the fully parallel independent acquisition array uses 8 channels as the basic acquisition unit, which is cascaded through the LVDS bus, and the clock phase-locked loop and channel address mapping are automatically completed after a new unit is connected.

4. The multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to claim 1, characterized in that: The voltage reference source of the multi-parameter reference source matrix provides no less than two known voltage signals, including a 0V zero-point reference range and a full-scale reference range; the current reference source provides no less than two known constant current signals, which are converted by a precision shunt resistor to cover the zero-point and full-scale points; the temperature reference source uses a PT1000 and a constant temperature bath to provide resistance signals corresponding to no less than two known temperature points.

5. The multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to claim 4, characterized in that: The error compensation model of the channel-by-channel error compensation engine is a third-order polynomial with temperature as the variable. The temperature is obtained by actual measurement from the onboard temperature sensor. After each online calibration, the compensation coefficient is updated by least squares fitting with no less than four known reference signals and stored in non-volatile memory.

6. The multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to claim 1, characterized in that: The magnetically coupled digital isolator uses a chip-level transformer-based magnetic coupling device with a bandwidth greater than 150MHz and an isolation withstand voltage greater than or equal to 5kV. The isolation power supply circuits of each channel are independent of each other. The common-mode voltage detection circuit is composed of a voltage divider network. A compensation voltage proportional to the measured common-mode voltage is injected through the reference terminal of the instrumentation amplifier, so that the effective common-mode input voltage approaches zero.

7. The multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to claim 1, characterized in that: The FPGA performs configurable FIR or IIR filtering on the data of each channel. The number of FIR taps can be configured from 32 to 256. It extracts voltage extreme values, current effective values, and temperature change rate features, and performs real-time judgment on voltage mutation and temperature over-limit to trigger hardware interrupt alarms. The structured data packet contains a unified timestamp and the voltage, current, and temperature data of all channels at that moment. The TSN bus adopts the IEEE 802.1 protocol, and the transmission delay is less than 100μs under reserved bandwidth.

8. The multi-channel electrical variable synchronous acquisition and calibration device for new energy batteries according to claim 1, characterized in that: The devices are applicable to test objects including lithium-ion batteries, lithium iron phosphate batteries, solid-state batteries, supercapacitors, and fuel cells.

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