Wafer defect detection method, computer readable storage medium

Abstract

The application discloses a wafer defect detection method and a computer readable storage medium. The detection method comprises the following steps: obtaining a surface height map of a wafer to be detected in a bare die state; calculating a focal plane adjustment parameter based on the surface height map; calculating an error between a focal plane of a photoetch machine and a surface of the wafer to be detected after the relative position between the focal plane of the photoetch machine and the wafer to be detected is adjusted according to the focal plane adjustment parameter, determining a leveling compensation residual error map based on the surface height map and the focal plane adjustment parameter; and detecting defects on the surface of the wafer to be detected based on the leveling compensation residual error map. Since the leveling compensation residual error map can reflect the error between the focal plane formed by the photoetch machine and the actual accurate focal plane in the photoetch process, and the height distribution range of the leveling compensation residual error map is smaller than that of the original surface height map and is more accurate, the defects that cannot be corrected by leveling can be effectively detected, and the detection accuracy is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor inspection technology, and more specifically to a method for detecting wafer defects and a computer-readable storage medium. Background Technology

[0002] As the core substrate in semiconductor manufacturing, the surface quality of wafers directly affects the performance and yield of semiconductor devices. Photolithography is one of the most critical processes in semiconductor manufacturing, its core being the precise transfer of circuit patterns onto the wafer surface. During photolithography, even minute undulations on the wafer surface can lead to pattern distortion or focusing failure. Therefore, precise alignment and leveling of the wafer are necessary before photolithography to ensure that the flatness and parallelism of the wafer surface meet process requirements. However, due to the complexity of the manufacturing process, various defects are prone to occur on the wafer surface. Even after leveling and compensation, uncorrectable height errors may still exist. If these defects are not detected and addressed in time, they will severely affect the electrical connectivity and functional circuitry of integrated circuits, ultimately leading to integrated circuit failure and causing significant economic losses.

[0003] Therefore, it is necessary to accurately detect defects on the wafer surface that cannot be corrected by leveling. Summary of the Invention

[0004] This invention provides a method for detecting wafer defects and a computer-readable storage medium, aiming to improve the detection accuracy of defects on the wafer surface that cannot be corrected by leveling.

[0005] According to a first aspect, one embodiment provides a method for detecting wafer defects, comprising:

[0006] Obtain the surface height map of the wafer under test in its bare die state;

[0007] Calculate the focal plane adjustment parameters based on the surface height map;

[0008] Based on the surface height map and the focal plane adjustment parameters, the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters is calculated, and the leveling compensation residual map is determined.

[0009] Defects on the surface of the wafer under test are detected based on the leveling compensation residual map.

[0010] In some embodiments, the method further includes calculating the focal plane adjustment parameters based on the surface height map:

[0011] The surface morphology of the wafer under test is fitted based on the surface height map to obtain the morphology fitting surface;

[0012] The surface height map is obtained by subtracting the surface height map from the shape fitting surface.

[0013] In some embodiments, the wafer to be tested includes multiple exposure fields, and the lithography machine is used to sequentially expose each exposure field row by row to form multiple exposure rows;

[0014] The calculation of focal plane adjustment parameters based on the surface height map includes:

[0015] Based on the surface height map, the focal plane adjustment parameters corresponding to each exposure row are calculated.

[0016] In some embodiments, the focal plane adjustment parameters corresponding to each exposure line are calculated in the following manner:

[0017] Based on the surface height of the exposure row and the surface height of several exposure rows adjacent to the exposure row, the focal plane adjustment parameters corresponding to the exposure row are calculated.

[0018] In some embodiments, the step of calculating the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine according to the focal plane adjustment parameters based on the surface height map and the focal plane adjustment parameters, and determining the leveling compensation residual map, includes:

[0019] The corresponding height compensation amount is calculated based on the focal plane adjustment parameters corresponding to each exposure line;

[0020] Based on the surface height of each exposure row and the corresponding height compensation amount, the error between the focal plane of the lithography machine and the surface of the exposure row is calculated after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters, and the leveling compensation residual map is determined.

[0021] In some embodiments, the focal plane adjustment parameters include translation adjustment along the Z-axis, rotation adjustment about the X-axis, and rotation adjustment about the Y-axis;

[0022] The step of calculating the corresponding height compensation amount based on the focal plane adjustment parameters corresponding to each exposure line includes:

[0023] The translation along the Z-axis caused by the rotation adjustment amount about the X-axis is determined as the first translation amount, and the translation along the Z-axis caused by the rotation adjustment amount about the Y-axis is determined as the second translation amount.

[0024] The corresponding height compensation amount is obtained by calculating the sum of the translation adjustment along the Z-axis, the first translation amount, and the second translation amount for each exposure line.

[0025] In some embodiments, both the surface height map and the leveling compensation residual map are three-channel warm and cool tone maps.

[0026] In some embodiments, detecting defects on the surface of the wafer under test based on the leveling compensation residual map includes:

[0027] The leveling compensation residual map is input into a pre-trained defect detection model to obtain the defect detection results on the surface of the wafer to be tested. The defect detection model is a neural network model.

[0028] In some embodiments, the defect detection results include a confidence score and size information of the defect; after obtaining the defect detection results of the wafer surface under test, the method further includes:

[0029] Based on the confidence score and size information of the defects, defects with confidence scores greater than the confidence score threshold and sizes greater than the size threshold are selected as the final defect detection results.

[0030] According to a second aspect, one embodiment provides a computer-readable storage medium including a program that can be executed by a processor to implement the detection method of any embodiment of the present application.

[0031] According to the wafer defect detection method and computer-readable storage medium of the above embodiments, by acquiring the surface height map of the wafer under test in the bare die state, calculating the focal plane adjustment parameters based on the surface height map, and calculating the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters, a leveling compensation residual map is determined. The obtained leveling compensation residual map can accurately reflect the error between the focal plane formed by the lithography machine and the actual precise focal plane during the lithography process. At the same time, the height distribution range of the leveling compensation residual map is smaller and more refined than the original surface height map. Based on the leveling compensation residual map, defects on the surface of the wafer under test can be effectively detected, which cannot be corrected by leveling, thus improving the detection accuracy. Attached Figure Description

[0032] Figure 1 This is a flowchart illustrating a method for detecting wafer defects according to one embodiment;

[0033] Figure 2 This is a surface height diagram of the wafer under test in a bare die state in one embodiment;

[0034] Figure 3 for Figure 2 Surface height map after correction by morphology fitting surface;

[0035] Figure 4This is a flowchart illustrating how, in one embodiment, based on a surface height map and focal plane adjustment parameters, the error between the focal plane of the lithography machine and the surface of the wafer under test is calculated after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters, and a leveling compensation residual map is determined.

[0036] Figure 5 This is a leveling compensation residual diagram obtained in one embodiment;

[0037] Figure 6 This is a structural diagram of YOLOv11;

[0038] Figure 7 This is a schematic diagram illustrating the visualization of defect detection results in one embodiment. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0040] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0041] The serial numbers assigned to components in this document, such as "first," "second," etc., are used only to distinguish the described objects and have no sequential or technical meaning. They should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. "A plurality of" means two or more. Unless otherwise specified, the terms "connection" and "linkage" in this invention include both direct and indirect connections (linkages).

[0042] Traditional wafer defect detection methods primarily rely on manual inspection or rule-based image processing techniques. Manual inspection suffers from inefficiency, subjectivity, and fatigue, making it unsuitable for large-scale production. While traditional rule-based image processing techniques (such as template matching and edge detection) have improved automation, they still lack sensitivity to minute defects in complex backgrounds, easily leading to missed detections. Furthermore, traditional methods also have other limitations, such as poor generalization ability, limited capacity to identify new defect types, and a difficulty in balancing detection accuracy and speed, failing to meet real-time detection requirements.

[0043] This invention provides a method for detecting wafer defects. It involves acquiring a surface height map of the wafer under test in its bare state, calculating focal plane adjustment parameters based on the surface height map, and then calculating the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine according to the focal plane adjustment parameters. A leveling compensation residual map is then determined, and defects on the surface of the wafer under test are detected based on this map. The leveling compensation residual map effectively detects defects that cannot be corrected by leveling, improving detection accuracy and avoiding missed detections. In some embodiments, wafer defect detection is based on deep learning algorithms. A deep learning-based neural network model is used to process the leveling compensation residual map to obtain the defect detection results on the surface of the wafer under test, which is particularly suitable for automated inspection of wafer surface quality in semiconductor manufacturing processes. By extracting image features through a neural network model, real-time detection of wafer defects can be achieved, offering high automation, strong generalization ability, high detection accuracy, and high speed.

[0044] Please refer to Figure 1 In one embodiment of the present invention, the method for detecting wafer defects includes steps 100 to 400, which are described in detail below.

[0045] Step 100: Obtain the surface height map of the wafer under test in the bare die state.

[0046] The surface height map can be a thermal map characterizing the height distribution on the surface of the wafer under test. The bare die state refers to the original state of the wafer surface before photoresist coating or other processing. The surface height map in the bare die state can provide three-dimensional information on the wafer surface morphology, including key information such as local flatness, global curvature, and roughness. Figure 2 A surface height diagram of the wafer under test in the bare die state is given in one embodiment.

[0047] The surface height map of a wafer under test can be obtained by measuring the height distribution of the wafer surface relative to a reference plane using a wafer surface shape measurement system. Different measurement schemes can be adopted depending on factors such as inspection requirements, process nodes, and feature dimensions, such as laser triangulation and structured light projection measurement. Laser triangulation is a measurement method based on geometric optics principles, calculating the height of the measured surface by the relationship between the incident and reflection angles of a laser beam. Structured light projection measurement is an active optical measurement method that reconstructs the three-dimensional morphology of the measured surface by projecting a specific grating pattern onto the measured surface and analyzing the pattern distortion.

[0048] Based on the height information of the wafer surface, focal plane adjustment parameters can be calculated to adjust the focal plane of the lithography machine, ensuring that the entire wafer is within the optimal depth of focus range. For stepper lithography machines, the focal plane needs to be adjusted in real time during the scanning process to compensate for the tilt and curvature of the wafer surface. In this case, the wafer surface shape measurement system can have extremely high measurement speed and real-time response capability, keeping up with the scanning speed of the lithography machine.

[0049] In some embodiments, before calculating the focal plane adjustment parameters based on the surface height map in step 200, the method further includes: fitting the surface morphology of the wafer to be tested based on the surface height map to obtain a morphology fitting surface; and subtracting the surface height map from the morphology fitting surface to obtain a surface height map corrected by the morphology fitting surface.

[0050] The surface morphology of the wafer under test can be fitted using a second-order Zernike polynomial. A Zernike polynomial is a two-dimensional orthogonal sequence of polynomials defined on a unit disk. A second-order Zernike polynomial contains three independent Zernike terms, each corresponding to a different type of optical aberration. These three Zernike terms are labeled Z3, Z4, and Z5, respectively.

[0051] The mathematical expression for term Z3 is: ;

[0052] The mathematical expression for term Z4 is: ;

[0053] The mathematical expression for term Z5 is: ;

[0054] Where (ρ,θ) are polar coordinates.

[0055] The complete mathematical expression for a second-order Zernike polynomial can be uniformly represented as:

[0056] ,

[0057] Here, c3, c4, and c5 are the coefficients of the corresponding Zernike terms, and their magnitudes indicate the severity of the corresponding aberrations. The second-order Zernike polynomial describes the quadratic deviation of the wavefront relative to the ideal sphere. The defocus term (Z4) represents the overall curvature change of the wavefront, while the astigmatic terms (Z3 and Z5) represent the curvature differences of the wavefront in different directions. These quadratic terms constitute the main part of the wavefront error and are key factors affecting image quality.

[0058] The surface height map, after correction by morphology fitting, can characterize the undulations of the wafer surface. Figure 3 Given Figure 2 Surface height map after topography fitting and surface correction. For example... Figure 2 As shown, the height of the wafer dies has a maximum value of 6262.23 nm, a minimum value of 5689.10 nm, and an average value of 5976.39 nm. The 3σ interval width is 304.75, and the average value plus the 3σ interval width is 6281.14 nm. The 99.7% confidence interval width is 484.78. Figure 3 The corrected height has a maximum value of 195.16 nm, a minimum value of -138.80 nm, an average value of 0.00 nm, a 3σ interval width of 115.82 nm, and the average value plus the 3σ interval width equals 115.82 nm. The 99.7% confidence interval width is 217.46 nm. It can be seen that the maximum, minimum, average, 3σ interval, and 99.7% confidence interval of the height have all decreased, indicating a narrower height distribution range. The focal plane adjustment parameters calculated based on the corrected surface height map can effectively reduce errors in the photolithography process. Using these focal plane adjustment parameters for wafer defect detection can improve detection accuracy.

[0059] Step 200: Calculate the focal plane adjustment parameters based on the surface height map.

[0060] Focal plane adjustment parameters are used to adjust the relative position of the focal plane of the lithography machine and the wafer under test, so that the focal plane of the lithography machine is close to / fits with the surface of the wafer under test. The adjustment of the relative position between the focal plane of the lithography machine and the wafer under test can be achieved by adjusting the orientation of the focal plane of the lithography machine and / or the orientation of the wafer under test. Therefore, the focal plane adjustment parameters can include the relative adjustment amount of the orientation between the focal plane of the lithography machine and the wafer under test, specifically including translation adjustment amounts and / or rotation adjustment amounts based on the X-axis, Y-axis, and Z-axis. It can be understood that the X-axis and Y-axis are two mutually perpendicular axes located on the plane of the wafer under test or the reference plane, and the Z-axis is an axis perpendicular to the plane of the wafer under test or the reference plane.

[0061] When a wafer exhibits global or local tilt, if the focal plane of the lithography machine's projection optics system remains horizontal, the distance from the focal plane to different locations on the wafer surface will vary, leading to defocusing in some areas. Therefore, tilt compensation is a crucial task in focal plane adjustment, aiming to keep the focal plane of the projection optics system parallel to the wafer surface or its local plane.

[0062] There are two main ways to achieve tilt compensation: adjusting the angle of the projection optics system and adjusting the angle of the wafer stage. Adjusting the projection optics system is typically achieved through a precise tilting mechanism, which can accurately control the orientation of the lens group within a tiny angular range (usually within a few hundred microradians). Adjusting the wafer stage angle involves changing the tilt angle of the wafer stage using a multi-axis actuator. This method is relatively simple in structure but requires consideration of motion inertia and response speed. Alternatively, the two methods can be combined. For example, for low-frequency tilt changes, the wafer stage angle can be primarily adjusted; for high-frequency tilt changes, the projection optics system angle can be primarily adjusted. This division of labor ensures system response speed while avoiding wear and fatigue caused by excessive movement of a single mechanism.

[0063] The adjustment amount of the angle of the projection optical system and the adjustment amount of the angle of the wafer stage can be represented by the rotation adjustment amount about the X-axis and the rotation adjustment amount about the Y-axis. Therefore, in some embodiments, the focal plane adjustment parameters include the rotation adjustment amount about the X-axis and the rotation adjustment amount about the Y-axis, and may also include the translation adjustment amount along the Z-axis, for adjusting the relative height between the focal plane of the projection optical system and the wafer.

[0064] In some embodiments, wafer bending needs to be compensated. Wafer bending can be caused by a variety of factors: internal material stress, clamping force distribution, temperature gradient, etc. The shape of the bending is also diverse, including spherical bending, cylindrical bending, saddle-shaped bending, etc. Bending compensation is more complex than tilt compensation, as it involves changes in the curvature of the wafer surface. Simply adjusting the angle is insufficient; the curvature of the focal plane needs to be adjusted.

[0065] In some embodiments, the curvature of the focal plane can be adjusted by field curvature adjustment of the projection optics system. Field curvature refers to the aberration of an optical system focusing light rays from different field angles at different axial positions; in lithography machines, field curvature is typically corrected to a minimum. In some embodiments, a controllable amount of field curvature can be introduced by actively controlling the spacing or shape of the lens group, so that the curvature of the focal plane matches the curvature of the wafer surface. Therefore, focal plane adjustment parameters may include the amount of field curvature.

[0066] In some embodiments, bending compensation can be achieved through segmented exposure. Please refer to [reference needed]. Figure 2 and Figure 3The wafer under test comprises multiple exposure fields. The areas divided by the horizontal and vertical black lines in the figure represent an exposure field. Segmented exposure divides an exposure field into multiple sub-regions, each using different focal plane adjustment parameters. This method is an effective bending compensation technique for severe bending. In some embodiments, the lithography machine (such as a stepper lithography machine) sequentially exposes each exposure field row by row during the lithography process to form multiple exposure rows (i.e., sub-regions). For each exposure row, the corresponding focal plane adjustment parameters are calculated. Step 200 includes: calculating the focal plane adjustment parameters corresponding to each exposure row based on the surface height map.

[0067] The surface height of each exposure row can be obtained from the surface height map, and the corresponding focal plane adjustment parameters can be calculated using the least squares method based on the surface height of the exposure row.

[0068] In some embodiments, to improve the accuracy of the focal plane adjustment parameters, in addition to considering the surface height of the current exposure line, several adjacent exposure lines are also taken into account. That is, the focal plane adjustment parameters corresponding to each exposure line are calculated in the following way: based on the surface height of the exposure line and the surface heights of several exposure lines adjacent to the exposure line, the focal plane adjustment parameters corresponding to the exposure line are calculated.

[0069] This can be achieved by calculating the surface height of the current exposure row and the average or weighted average of the surface heights of adjacent exposure rows, and then calculating the focal plane adjustment parameters based on the average or weighted average of the surface heights; or by calculating the preliminary focal plane adjustment parameters for each exposure row based on the surface height of each exposure row, and then calculating the average or weighted average of the focal plane adjustment parameters of each exposure row and its adjacent exposure rows as the final focal plane adjustment parameters.

[0070] Taking focal plane adjustment parameters, including translation adjustment along the Z-axis, rotation adjustment around the X-axis, and rotation adjustment around the Y-axis, as an example, assume the wafer under test contains 100 exposure fields, each complete exposure field containing 52 rows and 15 columns of dies. A stepper lithography machine will expose these 100 exposure fields sequentially. Taking one complete exposure field as an example, if the stepper lithography machine exposes row by row in a top-to-bottom or bottom-to-top order, then 52 exposures will be performed in this exposure field, forming 52 exposure rows, each containing 15 dies. Each row exposure corresponds to a set of focal plane adjustment parameters (Z, R...). x , R y ), where Z is the translation adjustment along the Z-axis, and R x R is the rotational adjustment amount around the X-axis. yThis refers to the rotation adjustment around the Y-axis. After obtaining the surface height map of the wafer under test, the surface height of each exposure row can be determined, and the corresponding translation adjustment around the Z-axis, as well as the rotation adjustment around the X-axis and the rotation adjustment around the Y-axis, can be calculated. The focal plane adjustment parameters (Z, R) are then used. x , R y In the calculation process, the surface height of the current exposure line and the surface heights of several adjacent exposure lines are considered. The corresponding focal plane adjustment parameters (Z, R) are calculated based on the overall height distribution of the current exposure line and several adjacent exposure lines. x , R y ).

[0071] Step 300: Based on the surface height map and focal plane adjustment parameters, calculate the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters, and determine the leveling compensation residual map.

[0072] Based on the focal plane adjustment parameters, the changes in the focal plane at various points on the surface of the wafer under test can be calculated after adjustment. By comparing the adjusted focal plane with the surface height of the wafer under test, the errors between the focal plane and the surface of the wafer under test can be obtained, forming a leveling compensation residual map. The leveling compensation residual map reflects the unavoidable errors between the focal plane of the lithography machine and the surface of the wafer under test even after leveling compensation.

[0073] Please refer to Figure 4 In some embodiments, step 300 includes the following steps 310-320.

[0074] Step 310: Calculate the corresponding height compensation amount based on the focal plane adjustment parameters corresponding to each exposure line.

[0075] The height compensation amount here refers to the compensation amount of the relative height between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters. In some embodiments, if the focal plane adjustment parameters include a translation adjustment amount along the Z-axis, a rotation adjustment amount around the X-axis, and a rotation adjustment amount around the Y-axis, then the corresponding height compensation amount is calculated based on the focal plane adjustment parameters corresponding to each exposure row, including: determining the translation amount along the Z-axis caused by rotation around the X-axis as the first translation amount, and determining the translation amount along the Z-axis caused by rotation around the Y-axis as the second translation amount; calculating the sum of the translation adjustment amount along the Z-axis, the first translation amount, and the second translation amount corresponding to each exposure row to obtain the corresponding height compensation amount.

[0076] Step 320: Based on the surface height of each exposure row and the corresponding height compensation amount, calculate the error between the focal plane of the lithography machine and the surface of the exposure row after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters, and determine the leveling compensation residual map.

[0077] For example, the error between the focal plane of the lithography machine and the surface of the exposure row can be obtained by subtracting the corresponding height compensation amount from the surface height of each exposure row. If each exposure row includes multiple grains, the height of each grain can be subtracted from the corresponding height compensation amount.

[0078] The leveling compensation residual map, determined based on the surface height map and focal plane adjustment parameters, can accurately reflect the error between the focal plane formed by the lithography machine and the actual precise focal plane during the lithography process. Figure 5 For based on Figure 3 The leveling compensation residual map obtained from the surface height map calculation shows a maximum height of 160.56 nm, a minimum height of -82.54 nm, an average height of 0.00 nm, a 3σ interval width of 31.95, and the average height plus the 3σ interval width equals 31.95 nm. The 99.7% confidence interval width is 164.22. It can be seen that the height distribution range is further reduced, which is beneficial for accurately representing the height deviation of the wafer surface under test.

[0079] In some embodiments, the surface height map and the leveling compensation residual map are both three-channel warm and cool tone maps, such as... Figure 2 , Figure 3 and Figure 5 As shown, the figure uses warm and cool color tones to depict the height distribution on the surface of the wafer under test. For the surface height map, cool blue indicates areas with lower height, and warm red indicates areas with higher height. For the leveling compensation residual map, cool blue indicates areas with lower error, and warm red indicates areas with higher error. Compared to the grayscale images obtained by optical imaging that are commonly used, this embodiment uses a three-channel warm and cool color tone map for defect detection on the wafer under test, making it easier to identify defects present on the wafer under test.

[0080] Step 400: Detect defects on the surface of the wafer under test based on the leveling compensation residual map.

[0081] For example, the presence of defects can be confirmed by manually observing the leveling and compensation residual map, or by using image processing techniques.

[0082] In some embodiments of this application, deep learning algorithms are used to detect defects on the surface of the wafer under test. Specifically, detecting defects on the surface of the wafer under test based on a leveling compensation residual map includes: inputting the leveling compensation residual map into a pre-trained defect detection model to obtain defect detection results on the surface of the wafer under test, wherein the defect detection model is a neural network model. The defect detection results include the location of the defect, and may also include the type, size information, and confidence score of the defect. In some embodiments, the types of defects include unevenness, large unevenness, small unevenness, scratches, residues, etc.

[0083] In some embodiments, the leveling compensation residual map can be preprocessed before being input into the defect detection model, including image denoising, contrast enhancement, and size normalization. Specifically, Gaussian filtering or median filtering can be used to remove image noise, histogram equalization can be applied to improve image contrast, the image can be standardized so that pixel values ​​are distributed within the [0, 1] interval, and the image size can be adjusted to the standard size required by the model (e.g., 640×640).

[0084] Defect detection models can employ YOLO (You Only Look Once) or similar models. Taking YOLOv11 as an example, it extracts multi-scale features from images through convolutional neural network layers, and then uses a detection head to detect defects based on these extracted features. The architecture of YOLOv11 is as follows... Figure 6 As shown, the model includes a backbone network, a neck network, and a detection head. The backbone network comprises CSPDarknet and C3K2 modules. The neck network includes the path aggregation network PANet and the SPFF (Spatial Pyramid Pooling Fast) module. The detection head includes a decoupled detection module and a C2PSA (Convolutional Pyramid Squeeze-and-Excitation Attention) module. YOLOv11 uses the C3K2 module as the basic feature extraction unit, employs the path aggregation network PANet to enhance the information transmission capability of the feature pyramid, integrates the SPFF module to achieve multi-scale feature fusion, and introduces the C2PSA attention mechanism to improve the model's attention to key defect regions.

[0085] The YOLO model outputs defect detection results including the location of the defect's bounding box (which indicates the defect's location and size), the defect type, and a confidence score (characterizing the defect's severity). The YOLO model employs a multi-task learning framework, enabling simultaneous defect location detection, defect classification, and defect severity assessment.

[0086] Depending on the actual needs, other neural network models can also be used. For example, when the number of defects of various types in the training image set is unbalanced and there are rare categories, RetinaNet can be used.

[0087] Before practical application, the defect detection model needs to be trained. First, a large number of surface height maps of wafers (e.g., no less than 10,000) are collected on the production line, covering various defects that cannot be corrected by leveling. Then, the leveling compensation residual map corresponding to each surface height map is calculated, and defects are labeled for each leveling compensation residual map. The leveling compensation residual map and its defect labels constitute the training image set, and the defect detection model is trained using the training image set.

[0088] The training image set can be divided into a training set, a validation set, and a test set. First, the defect detection model is trained using the training set. Then, it is evaluated using the validation set. If the performance of the defect detection model no longer improves, the current defect detection model is saved. If the performance of the defect detection model still improves, it is checked whether the number of training epochs has reached the threshold. If not, the defect detection model is trained again using the training set; if so, the current defect detection model is saved. Finally, the saved defect detection model is tested to complete the training process.

[0089] The training process can use the CIoU (Complete IoU) loss function to replace the traditional IoU loss to improve the accuracy of bounding box regression; apply adaptive image scaling technology to dynamically adjust inference parameters according to the size of the input image; and implement data augmentation strategies, including Mosaic augmentation, MixUp augmentation, and random rotation augmentation.

[0090] In some embodiments, non-maximum suppression processing can be performed on the detected bounding boxes to remove redundant bounding boxes whose overlap exceeds a set threshold.

[0091] In some embodiments, the defect detection results include the defect confidence score and size information. After obtaining the defect detection results of the wafer surface under test, the method further includes: based on the defect confidence score and size information, selecting defects with confidence scores greater than a confidence score threshold and sizes greater than a size threshold as the final defect detection results. This allows for the selection of high-quality defect detection results.

[0092] In some embodiments, the defect detection results can also be visualized. Taking the defect detection results including the defect's bounding box, type, and confidence score as an example, the visualization includes drawing the defect's bounding box on the leveling compensation residual map and labeling the defect's type and confidence score, such as... Figure 7 As shown, “Scratch” is the type of defect (scratch), and “0.97” is the confidence score.

[0093] This application also provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the wafer defect detection method of any embodiment of this application.

[0094] The wafer defect detection method and computer-readable storage medium provided in this application first calculate focal plane adjustment parameters based on a surface height map. Then, based on the surface height map and focal plane adjustment parameters, the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters is calculated. A leveling compensation residual map is then determined. Subsequently, the leveling compensation residual map is used to detect defects on the surface of the wafer under test. The obtained leveling compensation residual map accurately reflects the error between the focal plane formed by the lithography machine and the actual precise focal plane during the lithography process. The distribution of this error directly reflects the quality of the wafer. Simultaneously, the height distribution range of the leveling compensation residual map is smaller and more refined compared to the original surface height map. Detecting defects on the surface of the wafer under test based on this leveling compensation residual map can effectively detect defects that cannot be corrected by leveling, improving detection accuracy and avoiding missed detections.

[0095] In some embodiments, wafer defect detection is performed based on deep learning algorithms. Multi-scale features of the leveling compensation residual map are extracted using a deep learning-based neural network model. The defect detection results of the wafer surface under test are obtained based on the extracted multi-scale features. Real-time detection of wafer defects can be achieved, which not only has a high degree of automation and strong generalization ability, but also high detection accuracy and fast speed.

[0096] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles herein can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CDs, DVDs, Blu-ray discs, etc.), flash memory, and / or the like. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executing on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct the computer or other programmable data processing apparatus to operate in a particular manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture, including means for implementing the specified function. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that instructions executing on the computer or other programmable apparatus can provide steps for implementing the specified function.

[0097] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0098] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A method for detecting wafer defects, characterized in that, include: Obtain the surface height map of the wafer under test in its bare die state; Calculate the focal plane adjustment parameters based on the surface height map; Based on the surface height map and the focal plane adjustment parameters, the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters is calculated, and the leveling compensation residual map is determined. Defects on the surface of the wafer under test are detected based on the leveling compensation residual map.

2. The detection method as described in claim 1, characterized in that, Before calculating the focal plane adjustment parameters based on the surface height map, the following steps are also included: The surface morphology of the wafer under test is fitted based on the surface height map to obtain the morphology fitting surface; The surface height map is obtained by subtracting the surface height map from the shape fitting surface.

3. The detection method as described in claim 1 or 2, characterized in that, The wafer to be tested includes multiple exposure fields, and the lithography machine is used to sequentially expose each exposure field row by row to form multiple exposure rows; The calculation of focal plane adjustment parameters based on the surface height map includes: Based on the surface height map, the focal plane adjustment parameters corresponding to each exposure row are calculated.

4. The detection method as described in claim 3, characterized in that, The focal plane adjustment parameters for each exposure line are calculated in the following way: Based on the surface height of the exposure row and the surface height of several exposure rows adjacent to the exposure row, the focal plane adjustment parameters corresponding to the exposure row are calculated.

5. The detection method as described in claim 4, characterized in that, The step of calculating the error between the focal plane of the lithography machine and the surface of the wafer under test after adjusting the relative position of the focal plane of the lithography machine according to the focal plane adjustment parameters based on the surface height map and the focal plane adjustment parameters, and determining the leveling compensation residual map, includes: The corresponding height compensation amount is calculated based on the focal plane adjustment parameters corresponding to each exposure line; Based on the surface height of each exposure row and the corresponding height compensation amount, the error between the focal plane of the lithography machine and the surface of the exposure row is calculated after adjusting the relative position of the focal plane of the lithography machine and the wafer under test according to the focal plane adjustment parameters, and the leveling compensation residual map is determined.

6. The detection method as described in claim 5, characterized in that, The focal plane adjustment parameters include the translation adjustment along the Z-axis, the rotation adjustment around the X-axis, and the rotation adjustment around the Y-axis. The step of calculating the corresponding height compensation amount based on the focal plane adjustment parameters corresponding to each exposure line includes: The translation along the Z-axis caused by the rotation adjustment amount about the X-axis is determined as the first translation amount, and the translation along the Z-axis caused by the rotation adjustment amount about the Y-axis is determined as the second translation amount. The corresponding height compensation amount is obtained by calculating the sum of the translation adjustment along the Z-axis, the first translation amount, and the second translation amount for each exposure line.

7. The detection method according to any one of claims 1 to 6, characterized in that, Both the surface height map and the leveling compensation residual map are three-channel warm and cool tone maps.

8. The detection method as described in claim 1, characterized in that, The method of detecting defects on the surface of the wafer under test based on the leveled and compensated residual map includes: The leveling compensation residual map is input into a pre-trained defect detection model to obtain the defect detection results on the surface of the wafer to be tested. The defect detection model is a neural network model.

9. The detection method as described in claim 8, characterized in that, The defect detection results include the confidence score and size information of the defects; after obtaining the defect detection results of the wafer surface to be tested, the following are also included: Based on the confidence score and size information of the defects, defects with confidence scores greater than the confidence score threshold and sizes greater than the size threshold are selected as the final defect detection results.

10. A computer-readable storage medium, characterized in that, Includes a program that can be executed by a processor to implement the detection method as described in any one of claims 1 to 9.

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