Optical proximity correction method

Abstract

The application discloses an optical proximity effect correction method and relates to the technical field of semiconductors; the method comprises the following steps: performing global biasing on a design layout according to a process deviation value to obtain a biased layout; performing OPC correction simulation on the biased layout to obtain a simulation layout and a corrected biased layout; in the case that the simulation layout exceeds an expected process deviation, performing compensation on the corrected biased layout according to a mask error enhancement factor and the process deviation value to obtain a compensated layout; repeatedly performing the above-mentioned OPC correction simulation step on the compensated layout to update the simulation layout until the updated simulation layout meets the expected process deviation, and outputting an updated compensated layout corresponding to the updated simulation layout. The application corrects the process deviation that still exists after OPC correction, improves the correction accuracy of multiple feature patterns in the compensated layout, reduces the risk of bridging or necking that may be caused by different feature patterns, improves the pattern quality of the compensated layout, and speeds up the correction efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for correcting the optical proximity effect. Background Technology

[0002] As semiconductor process nodes enter the nanometer level, during photolithography and development, when the linewidth on the wafer is smaller than the exposure wavelength, the problem of pattern distortion becomes increasingly serious due to the diffraction effect and proximity effect of light. For example, the designed pattern may produce rounded corners and critical dimension variation (CDV) due to light interference during exposure. The mask pattern needs to be corrected to ensure that the final pattern on the wafer is consistent with the designed pattern. This correction process is called optical proximity correction (OPC).

[0003] When performing OPC correction on the layout, if the actual wafer pattern is larger or smaller than the design pattern, the mask layout will be biased as a whole. However, due to the different mask error enhancement factors (meef) of different feature patterns (corners, line ends, contact holes, and complex polygons) in 1D, 1.5D, and 2D, some patterns can be accurately corrected after overall biasing, but other structures will have excessively large meef values ​​due to effects such as corner rounding and line-end shorting in optical proximity, resulting in bridging or pinching. Summary of the Invention

[0004] To address the problems of the prior art, this invention provides a method for correcting the optical proximity effect. The technical solution is as follows: On one hand, the present invention provides a method for correcting the optical proximity effect, comprising: Based on the process deviation value, the design layout is globally biased to obtain an offset layout; the process deviation value is the difference between the design value of the design layout and the wafer development value obtained based on the design layout. The bias layout is subjected to OPC correction simulation to obtain the simulation layout and the corrected bias layout; If the simulated layout exceeds the expected process deviation, the corrected offset layout is compensated according to the mask error enhancement factor and the process deviation value to obtain a compensated layout; the mask error enhancement factor is the ratio between the variation value of the simulated layout and the shift value of the designed layout. Repeat the above OPC correction simulation steps for the compensation layout to update the simulation layout until the updated simulation layout meets the expected process deviation, and output the updated compensation layout corresponding to the updated simulation layout.

[0005] Furthermore, when the simulated layout exceeds the expected process deviation, the corrected offset layout is compensated based on the mask error enhancement factor and the process deviation value to obtain a compensated layout, including: If the simulated layout exceeds the expected process deviation, a layout compensation value is determined based on the mask error enhancement factor and the process deviation value; the layout compensation value is positively correlated with the absolute value of the process deviation value, and the layout compensation value is negatively correlated with the mask error enhancement factor; The corrected offset layout is compensated based on the layout compensation value to obtain the compensated layout.

[0006] Furthermore, the absolute value of the layout compensation value is positively correlated with the absolute value of the process deviation value, and the layout compensation value is negatively correlated with the mask error enhancement factor.

[0007] Further, in the case where the simulated layout exceeds the expected process deviation, determining the layout compensation value based on the mask error enhancement factor and the process deviation value includes: If the simulated layout exceeds the process deviation, the layout compensation value is determined based on the mask error enhancement factor, the process deviation value, and the weakness compensation value. The weakness compensation value is used to compensate for deviations caused by various mask error enhancement factors and / or various spacings between surrounding graphics and the target graphic in the corrected offset layout.

[0008] Furthermore, the weakness compensation value is associated with a process node; the process node includes at least one of 28nm, 40nm, 55nm, 65nm, 90nm, 110nm, 130nm, 150nm, and 180nm.

[0009] Furthermore, the layout compensation value satisfies at least one of the following characteristics: When the process deviation value is greater than zero, the layout compensation value is the difference between the ratio of the process deviation value to the mask error enhancement factor and the weakness compensation value. When the process deviation value is equal to zero, the layout compensation value is the process deviation value; When the process deviation value is less than zero, the layout compensation value is the sum of the weakness compensation value and the difference between the ratio of the process deviation value and the mask error enhancement factor.

[0010] Furthermore, the corrected bias layout includes multiple feature patterns, with different feature patterns corresponding to different mask error enhancement factors; when the simulated layout exceeds the expected process deviation, the corrected bias layout is compensated according to the mask error enhancement factor and the process deviation value to obtain a compensated layout, including: If the simulated layout exceeds the expected process deviation, a target pattern is selected in the corrected bias layout based on the mask error enhancement factor; the target pattern is at least one of the plurality of feature patterns; The target pattern is compensated based on the mask error enhancement factor and the process deviation value corresponding to the target pattern to obtain a compensated pattern; Based on different mask error enhancement factors, the above selection and compensation steps are repeated to compensate for each target pattern with different mask error enhancement factors in the corrected bias layout, thereby obtaining the compensated layout including each compensated pattern.

[0011] Furthermore, the selection of the target pattern in the corrected bias layout based on the mask error enhancement factor includes: Based on the simulation layout and the design layout, the mask error enhancement factor corresponding to each feature graphic is calculated. If the mask error enhancement factor meets the preset conditions, the corresponding feature pattern is determined as the target pattern.

[0012] Furthermore, the desired process error satisfies at least one of the following characteristics: When the feature graphics of the design layout include 1D graphics, the expected process error corresponding to the 1D graphics is -3nm to 3nm; When the feature pattern of the design layout includes a 1.5D pattern, the expected process error corresponding to the 1.5D pattern is -6nm to 6nm; When the feature pattern of the design layout includes a 2D pattern, the expected process error corresponding to the 2D pattern is -8nm to 8nm.

[0013] Furthermore, the OPC correction simulation performed on the bias layout to obtain the simulation layout includes: The offset layout is smoothed to obtain an initial simulation layout. The edge of the offset pattern is divided into multiple movable segments, and a cutting line is generated on each segment; the cutting line is orthogonal to the segment. Determine the edge placement error corresponding to the position of the cutting line; The positions of each segment are adjusted according to the edge placement error to update the offset layout, the initial simulation layout and the corresponding edge placement error, until the updated edge placement error meets the preset error, thus obtaining the simulation layout and the corrected offset layout.

[0014] Implementing this invention has the following beneficial effects: This invention, based on the mask error enhancement factor and process deviation value, further compensates the biased layout that still has process deviations after OPC correction to obtain a compensated layout. Then, the OPC correction simulation steps are repeated on the compensated layout to update the simulation layout until the updated simulation layout meets the desired process deviation. The compensated layout corresponding to the updated simulation layout is then output as the final mask layout. This is used for photolithography development on the actual wafer. This correction method effectively improves the accuracy of correcting various feature patterns in the final compensated layout, reduces the risk of bridging or necking that may occur with different feature patterns, reduces the error frequency after automatic calculation in existing OPC processes, and helps to accelerate correction and wafer fabrication efficiency, thereby improving the pattern quality of the compensated layout. Attached Figure Description

[0015] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below, wherein the same components are represented by the same reference numerals. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0016] Figure 1 A flowchart of an optical proximity effect correction method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the process deviation value in this invention; Figure 3 for Figure 2 A magnified view showing a partial comparison between the design layout and the actual wafer; Figure 4 A schematic diagram of feature graphs with different meef values; Figure 5 Example diagram of the compensation process for feature graphics with large meef values ​​after OPC correction; Figure 6 This is a schematic diagram of the compensation path for the optical proximity effect correction method in a specific embodiment of the present invention.

[0017] The corresponding reference numerals in the attached figures are: 1-Design layout, 2-Offset layout, 3-Modified offset layout, 4-Simulated layout, 41-Fragment, 42-Cut line 5 - Target graphic, 6 - Compensation layout. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, and therefore should not be construed as limiting the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that, in the description of this invention, the following definitions of terms shall apply unless a different definition is given elsewhere in the claims or this specification. All numerical values, whether explicitly indicated or not, are defined herein as being modified by the term "about." The term "about" generally refers to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​to produce substantially the same properties, functions, results, etc. A range of numerical values ​​indicated by a low value and a high value is defined as including all numerical values ​​within that range and all subranges included within that range.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms and need not be used to describe a specific order or sequence. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion. When discussing a second element, component, region, layer, or portion, it does not imply that the invention necessarily includes a first element, component, region, layer, or portion. It should be understood that such uses of terms can be interchanged where appropriate so that embodiments of the invention can be implemented in a sequence other than the following illustrations or descriptions. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, or product that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, or products.

[0021] To address the issue that existing methods for offsetting the layout during process deviations can lead to inaccurate corrections of different feature patterns, resulting in issues like pattern bridging or necking, this invention provides an optical proximity effect correction method. First, an initial design layout is globally offset based on the process deviation value, resulting in an offset layout. The process deviation value is the difference between the design value of the layout and the wafer development value based on that layout. Next, OPC correction simulation is performed on the offset layout to obtain a simulated layout and a corrected offset layout. If the simulated layout exceeds the desired process deviation, the corrected offset layout is compensated based on a mask error enhancement factor and the process deviation value, resulting in a compensated layout. The mask error enhancement factor is the ratio between the change in the simulated layout and the shift in the design layout. Then, the OPC correction simulation steps are repeated on the compensated layout to update it until the updated simulation layout meets the desired process deviation. Finally, the updated compensated layout corresponding to the updated simulation layout is output as the final mask layout for photolithography development of the actual wafer.

[0022] Thus, when the simulated layout still exhibits process deviations exceeding the expected process deviations after the OPC process, this invention, based on the mask error enhancement factor and the process deviation value, continues to compensate the biased layout that still has process deviations after OPC correction to obtain a compensated layout. Then, the OPC correction simulation steps are repeated on the compensated layout to update the simulation layout until the updated simulation layout meets the expected process deviations. The compensated layout corresponding to the updated simulation layout is then output as the final mask layout, and photolithography is performed on the actual wafer. This correction method effectively improves the accuracy of correcting various feature patterns in the final compensated layout, reduces the risk of bridging or necking that may occur with different feature patterns, reduces the error frequency after automatic calculation in existing OPC processes, facilitates faster correction and wafer fabrication efficiency, and improves the pattern quality of the compensated layout.

[0023] The following is combined with Figure 1-4 The optical proximity effect correction method of the present invention will be described in detail.

[0024] First, such as Figure 1 As shown, based on the process deviation value, the design version is... Figure 1 Perform a global bias to obtain the biased version. Figure 2 .

[0025] Design version Figure 1 This includes various types of feature graphics, such as 1D graphics, 1.5D graphics, and 2D graphics, as shown in Table 1 below, which provides examples of common feature graphics. Throughout the correction process, the feature graphics can be carried over to the layout after corrections in subsequent steps, for example, in the design layout. Figure 1 The 1D graphics in the image, after global offset, are displayed on the offset version. Figure 2 The graphics are still 1D, and will not be discussed further.

[0026] Table 1 Common OPC Test Feature Graphs

[0027] Global bias is a layout size correction method in the etching process, which is achieved by adjusting the design layout. Figure 1 A fixed displacement (Bias value) is uniformly added or subtracted from the edges of all feature patterns to pre-compensate for dimensional shrinkage or expansion caused by subsequent photolithography and etching. In other words, it is used to offset systematic linewidth errors, so that the physical dimensions formed on the final wafer after photolithography and development are consistent with the target pattern. Figure 1 Note: This global bias step is a preprocessing step, belonging to the design version. Figure 1 Regular coarse correction.

[0028] Next, as Figure 1 As shown, for the bias version Figure 2 Perform OPC correction simulation to obtain the simulation version. Figure 4 And the corrected bias version Figure 3 .

[0029] This OPC correction simulation step is based on the global bias and modifies the design board. Figure 1 Further fine-tuning was performed to ensure that, after simulation with OPC correction, the biased version based on the correction... Figure 3 The lithographic pattern on the real wafer obtained by photolithography can match the desired target pattern 5.

[0030] Specifically, in some exemplary embodiments, the bias version Figure 2 Perform OPC correction simulation to obtain the simulation version. Figure 4 include: For the bias version Figure 2 Smoothing was performed to obtain the initial simulation version. Figure 4 ; The bias plate Figure 2 The edge is divided into multiple movable segments 41, and a cutting line 42 is generated on each segment 41; the cutting line 42 is orthogonal to the segment 41. Determine the edge placement error corresponding to the position of the cutting line 42; Adjust the position of each segment 41 according to the edge placement error to update the offset version. Figure 2 The initial simulation version Figure 4 And the corresponding edge placement error, until the updated edge placement error meets the preset error, to obtain the simulation version. Figure 4 and the modified bias version Figure 3 .

[0031] Smoothing refers to the process of smoothing the discrete displacements of feature edges in the layout using mathematical filtering or constraint optimization algorithms during the model-based OPC iteration. This process aims to eliminate jagged distortions and control curvature continuity, resulting in a smoother initial simulation layout. Figure 4 It satisfies both imaging accuracy and composite mask manufacturing rules.

[0032] In some exemplary embodiments, the bias plate is also subjected to a smoothing process before the smoothing process is performed. Figure 2 Flexible target constraint processing is performed to obtain the constrained bias version. Figure 2 This is used to discretize continuous edges into independently optimizable segments 41; then, the constrained bias version is further processed. Figure 2 A smoothing calculation is performed to obtain a smooth pattern, which serves as the initial simulation version. Figure 4 It is a simulation of the pattern and morphology on a real wafer.

[0033] bias version Figure 2 The edge is divided into multiple movable segments 41. Each segment 41 can move inward or outward, and an orthogonal cutting line 42 is generated on each segment 41. The cutting line 42 is used to locate the edge placement error (EPE) of the current segment 41, that is, to locate the position for calculating the EPE value of the current segment 41.

[0034] Among them, edge placement error (EPE) is the initial simulation result. Figure 4 Compared to the current bias version Figure 2 If there is a deviation between the design values, the EPE value of the current segment 41 is calculated at the position of the cutting line 42. The EPE value is multiplied by the preset feedback value to obtain the line width movement amount. This line width movement amount is the movement amount of the current segment 41 next to adjust the position of the current segment 41. This process is repeated multiple times until the EPE value of the current segment 41 meets the preset error, thus completing the OPC correction of the current segment 41. The number of iterations for each segment 41 varies depending on the process node. The number of iterations can be set according to the process node, and can be selected from 8 to 10 times to reduce the calculation time while improving the accuracy of the correction.

[0035] In some exemplary embodiments, the linewidth movement amount is less than or equal to the movement threshold each time. If the calculated linewidth movement amount is less than or equal to the movement threshold, the calculated linewidth movement amount is used as the next movement amount of the current segment 41; if the calculated linewidth movement amount is greater than the movement threshold, the movement threshold is used as the next movement amount of the current segment 41. For example, the EPE value at the current cutting line 42 position is 20nm, the preset feedback value is 0.6, and the movement threshold is 10nm, then the linewidth movement amount is 12nm. Since the linewidth movement amount is greater than the movement threshold, the segment 41 can only move outward by 10nm.

[0036] Repeat the above steps of calculating the EPE value, calculating the linewidth expansion value, and adjusting the position of segment 41 for each segment 41 to achieve the effect of adjusting the position of the entire offset plate. Figure 2 The update ultimately yields a feature graph composed of 41 adjusted segments, which is the corrected bias version obtained from the OPC correction simulation. Figure 3 This is beneficial for improving the bias version of the correction. Figure 3 This improves accuracy and reduces computation time.

[0037] Next, as Figure 1 As shown, in the simulation version Figure 4 In cases where the process deviation exceeds the expected deviation, the corrected offset version is adjusted based on the mask error enhancement factor and the process deviation value. Figure 3 Compensation will be provided to obtain the compensated version. Figure 6 .

[0038] Specifically, process deviation refers to the unified design version Figure 1 Corresponding simulation version Figure 4 The deviation between the measured value and the measured value of the developed pattern on the actual wafer is considered to be within the allowable process deviation; if the current simulation version Figure 4 If the process deviation is within the expected process deviation range, it means that no further correction or compensation is needed; if the current simulation version Figure 4 The process deviation exceeds the expected process deviation range, indicating that the corrected bias version obtained from this OPC correction is incorrect. Figure 3 This can still result in significant errors, leading to inaccurate layouts on the final actual wafer. In such cases, the offset pattern is corrected based on the mask error enhancement factor and process deviation value. Figure 3 The compensation step is performed to further correct and improve the accuracy of the final etching.

[0039] Specifically, different feature patterns correspond to different expected process errors.

[0040] In some exemplary implementations, in the design version Figure 1 When the feature pattern includes a 1D pattern, the expected process error corresponding to the 1D pattern is -3nm to 3nm; it can be understood that the expected process error corresponding to the 1D pattern can be any value from -3nm to 3nm; for example, the expected process error corresponding to the 1D pattern can be -3nm, -2.5nm, -2nm, -1nm, 0nm, 1m, 2m, 3nm, etc.

[0041] In some exemplary implementations, in the design version Figure 1 When the feature pattern includes a 1.5D pattern, the expected process error corresponding to the 1.5D pattern is -6nm to 6nm; it can be understood that the expected process error corresponding to the 1.5D pattern can be any value from -6nm to 6nm; for example, the expected process error corresponding to the 1.5D pattern can be -6nm, -5nm, -4.5nm, -4nm, -2.5nm, -1nm, 0nm, 1m, 2m, 3nm, 4nm, 5nm, 6nm, etc.

[0042] In some exemplary implementations, in the design version Figure 1 When the feature pattern includes a 2D pattern, the expected process error corresponding to the 2D pattern is -8nm to 8nm; it can be understood that the expected process error corresponding to the 2D pattern can be any value from -8nm to 8nm; for example, the expected process error corresponding to the 2D pattern can be -8nm, -7nm, -5.5nm, -4nm, -3nm, -2nm, -1nm, 0nm, 1m, 2m, 3nm, etc.

[0043] Thus, for different feature patterns, the expected process error is different. Therefore, the feature patterns that exceed the expected process deviation are selected from a variety of feature patterns. Only the feature patterns that meet the compensation conditions, that is, those that exceed the expected process deviation, are compensated in a targeted manner. This effectively improves the accuracy of compensation, enhances the accuracy and reliability of the final mask pattern, and speeds up the correction efficiency.

[0044] It should be noted that the process deviation value (K) is from the design version. Figure 1 Design values ​​and design-based versions Figure 1 The difference between the developed wafer values ​​can specifically be the design board. Figure 1 The difference between the design value and the wafer development value is the empirical value, which is the empirical data accumulated through multiple existing experiments or completed production processes. The wafer development value and the design value can be directly obtained to calculate the process deviation value K.

[0045] Based on the design version Figure 1 In the case of simulation, a process deviation value K exists between the obtained simulation layout and the final desired wafer development layout. Only then will a global bias be applied to the design layout, resulting in deviations in local areas of the biased layout after global bias, i.e., the existence of a process deviation value. The step of applying a global bias to the design layout to obtain a biased layout is a prerequisite for the optical proximity effect correction method of this embodiment of the invention. After obtaining the biased layout by applying a global bias to the design layout based on the process deviation value, the OPC correction simulation step, compensation step, and iterative update are continued to gradually correct and obtain an updated compensation layout, thereby improving the pattern quality of the final wafer development.

[0046] The mask error enhancement factor (meef, hereinafter referred to as meef value) is a simulation version. Figure 4 The change value and the design version Figure 1 The ratio between the shift values ​​is used to quantify the degree to which the mask pattern linewidth error amplifies the linewidth error in the actual wafer image. Among these, the design pattern... Figure 1 The movement value is in the design version. Figure 1 The movement value of the selected target graphic 5 among various feature graphics can be input through the control panel and implemented through Boolean operations to modify the design. Figure 1 The expansion or contraction; simulation version Figure 4 The change value is based on the design version of the expansion or contraction. Figure 1 The simulation version obtained by simulation Figure 4 Compared to the original design version Figure 1 The displacement value at the same position in the selected target graphic 5.

[0047] In some optional implementations, a CD bar is used for auxiliary measurement to obtain the simulation version. Figure 4And / or the size of the feature pattern in the actual wafer, the CD bar is a dedicated bar test structure used in the OPC correction process to measure critical dimensions to reduce the adverse effects of layout complexity on measurement.

[0048] In some exemplary implementations, the simulation version Figure 4 Changes in value, design version Figure 1 The moving value, design version Figure 1 Both the design value and the wafer development value can be selected as single-sided data values; for example, the design board. Figure 1 One characteristic graphic element is isolated lines. In the OPC process, the measured value of this isolated line is its line width. Correspondingly, the design version... Figure 1 The movement value is the change value on one side of this independent line, in the simulation version. Figure 4 The change value is a simulation version of the independent line. Figure 4 The change value on one side, design version Figure 1 The design value is half the line width of the independent line, and the wafer development value is also half the line width of the developed pattern obtained by photolithography using the independent line as a mask pattern.

[0049] In some exemplary implementations, when determining the simulation version Figure 4 In determining whether the process deviation exceeds the expected process deviation, the process deviation and the expected process deviation can optionally use one-sided data values ​​or two-sided data values. When judging by one-sided data values, the one-sided data value can be directly measured or the two-sided data value can be measured and then halved.

[0050] For example, due to the design version Figure 1 and simulation version Figure 4 Due to the complexity of the design, it is impossible to simulate all the feature graphics in the layout to obtain specific MEEF values ​​for compensation. Therefore, auxiliary measurements are taken using a CD bar to obtain the design layout values. Figure 1 The difference between the design value and the wafer development value, such as Figure 2 and Figure 3 As shown, assuming the design version on the left... Figure 1 The design value (linewidth) of this line is 195nm, while the wafer development value of this line on the actual wafer to the right is 182.5nm. This means the size difference between dense lines and independent lines is approximately 12nm, with a corresponding single-sided difference of approximately 6nm. Therefore, the process deviation value K can be determined to be 6nm. At this point, Boolean operations are used to adjust the design board... Figure 1 The line width of the line is increased by 1nm on one side, and the design graphic after the increase is simulated. If the simulation version Figure 4Expanding by 1nm, we can determine the meef value of this feature pattern in the current layout environment as 1nm / 1nm=1; correspondingly, if the desired wafer development value is 195nm, then the design board... Figure 1 The mid-feature graphics (i.e., lines) require a 6nm outward expansion on one side, making the design board... Figure 1 The design value for this feature pattern is 207nm.

[0051] However, this meef value is used for the entire design. Figure 1 Global compensation can result in feature patterns with a meef value that is not 1. Their design values ​​and wafer development values ​​remain inconsistent, ultimately leading to bridging or necking of the patterns in the actual wafer. This is then reflected in the simulation version. Figure 4 If the deviation exceeds the limit of the process deviation, further adjustments are made to the biased version based on the meef value and the process deviation value K. Figure 3 Each feature image with different MEEF values ​​is compensated to different degrees to obtain a compensated version. Figure 6 This can greatly improve the accuracy of compensation and enhance the pattern quality of the final mask layout.

[0052] Specifically, different feature patterns correspond to different mask error enhancement factors; in some exemplary embodiments, the same feature pattern is affected by surrounding patterns, and the meef value may be the same or different; for example, such as Figure 4 As shown, assuming the design version Figure 1 The feature pattern is enlarged by 1 nm on one side. Figure 4 (a) Simulation version Figure 4 The feature pattern is also expanded by 1 nm on one side, and the meef value of this feature pattern is 1; Figure 4 (b) is the design version Figure 1 The feature pattern is enlarged by 1 nm on one side in the simulation version. Figure 4 The feature pattern expands by 0.5 nm on one side, and the meef value of this feature pattern is 0.5. Figure 4 (c) is the design version Figure 1 The feature pattern is enlarged by 1 nm on one side in the simulation version. Figure 4 The feature pattern expands by 2nm on one side, and the meef value of this feature pattern is 2. Figure 4 (d) and Figure 4 (e) Compared to Figure 4 (c) If there are other feature shapes around the target feature shape, and these other feature shapes have different sizes, positions, shapes, and distances from the target feature shape 5, then due to the optical proximity effect, the target feature shape 5 will be affected. Figure 4 (d) and Figure 4 The meef values ​​for (e) are 2.5 and 2.2, respectively, compared with Figure 4 (c) has a different meef value.

[0053] Specifically, in some exemplary embodiments, the step described in the simulation version Figure 4 In cases where the process deviation exceeds the expected deviation, the corrected offset version is adjusted based on the mask error enhancement factor and the process deviation value. Figure 3 Compensation will be provided to obtain the compensated version. Figure 6 include: In the simulation version Figure 4 In cases where the process deviation exceeds the expected deviation, the mask error enhancement factor is applied to the corrected bias plate. Figure 3 Select target graphic 5 from the plurality of feature graphics; the target graphic 5 is at least one of the plurality of feature graphics. Based on the mask error enhancement factor and the process deviation value corresponding to the target pattern 5, the target pattern 5 is compensated to obtain a compensated pattern; Based on different mask error enhancement factors, the above selection and compensation steps are repeated to modify the bias version. Figure 3 Compensation is performed on each of the target patterns 5 with different mask error enhancement factors to obtain the compensated version including each compensated pattern. Figure 6 .

[0054] In this step, different target graphics 5 are selected for compensation based on the meef value, and the bias version of the entire correction is selected. Figure 3 Among multiple feature graphics, target graphic 5, which requires further compensation, is calculated. Its meef value and process deviation value K are then calculated, and compensation is performed to complete the compensation of target graphic 5, resulting in the corresponding compensated graphic. Then, the steps of selecting target graphic 5 based on its meef value and performing compensation for target graphic 5 are repeated sequentially or simultaneously on other feature graphics. In other words, the entire corrected offset version is ultimately completed through compensation of multiple local areas. Figure 3 The compensation will be improved in the final compensation version. Figure 6 The accuracy and reliability.

[0055] Specifically, in some exemplary embodiments, the mask error enhancement factor is based on the corrected bias version. Figure 3 The selected target graphic 5 includes: According to the simulation version Figure 4 With the aforementioned design version Figure 1 Calculations are performed to obtain the mask error enhancement factors corresponding to each of the aforementioned feature graphics; If the mask error enhancement factor meets the preset conditions, the corresponding feature pattern is determined as the target pattern 5.

[0056] In this step, the meef value corresponding to each feature graphic is calculated. Based on the different meef values, it is determined whether the feature graphic needs further correction and compensation, and the feature graphic that needs further correction and compensation is identified as target graphic 5. In this way, it is not necessary to perform exhaustive compensation on all feature graphics, but only to compensate some feature graphics, which helps to speed up the compensation efficiency and tape-out efficiency, and improve the accuracy and pattern quality of the final mask layout.

[0057] In some exemplary implementations, the preset condition is that the meef value is not equal to a preset value, which is an adjustable value that can be adjusted according to the specific correction scenario.

[0058] For example, the preset value is 1, that is, the preset condition is that the meef value is not equal to 1. After simulation with global bias and OPC correction, the corrected bias version Figure 3 For feature patterns with a meef value of 1, the expected process deviation is basically satisfied and no further compensation is needed; however, for feature patterns with a meef value not equal to 1, such as... Figure 5 As shown, by selecting the left edge of the vertical direction of the "T" shaped structure in the 2D graphic with a meef value not equal to 1, the target graphic 5 is determined. This target graphic 5, after being globally offset, suffers from necking due to a large meef value. Therefore, the offset version is corrected. Figure 3 The target graphic 5 is compensated to improve the error caused by excessively large meef values ​​in the local graphic due to the previous global bias. This allows the target graphic 5 to be better corrected in subsequent OPC correction simulations, thus improving the compensation version. Figure 6 The quality makes the compensated version Figure 6 The actual wafer layout and design pattern obtained after photolithography and development Figure 1 Maintain consistency to address the necking risk that may occur in actual wafer production.

[0059] Specifically, the aforementioned in the simulation version Figure 4 In cases where the process deviation exceeds the expected deviation, the corrected offset version is adjusted based on the mask error enhancement factor and the process deviation value. Figure 3 Compensation will be provided to obtain the compensated version. Figure 6 include: In the simulation version Figure 4 If the process deviation exceeds the expected deviation, a layout compensation value is determined based on the mask error enhancement factor and the process deviation value. The corrected offset plate is based on the layout compensation value. Figure 3 Compensation is performed to obtain the compensated version. Figure 6 .

[0060] In this step, after calculating the meef value and process deviation value, the layout compensation value is determined based on the meef value and process deviation value K, thus quantifying the layout compensation value. This layout compensation value is used to compensate for and correct the offset plate. Figure 3 To the corrected bias version Figure 3 Expand or shrink to obtain a compensated version. Figure 6 In this way, by quantifying the compensation process, the impact of the previous global bias on each local feature graphic can be reduced, thereby reducing the overall layout error.

[0061] It should be noted that, given the presence of multiple different feature graphics in the layout, the calculation of the meef value and process deviation value K is also specific to each of these different feature graphics. The resulting meef value is the set of meef values ​​for each target graphic 5 (or each feature graphic), and the process deviation value is also the set of K values ​​for each target graphic 5. Correspondingly, the layout compensation value is also the set of local layout compensation values ​​for multiple selected target graphics 5. Thus, by gradually performing local compensation on each target graphic 5, the offset of the entire corrected layout is achieved. Figure 3 The compensation received was a compensated version. Figure 6 .

[0062] In some exemplary embodiments, this step may specifically include: In the simulation version Figure 4 In cases where the process deviation exceeds the expected deviation, the mask error enhancement factor is applied to the corrected bias plate. Figure 3 Select target graphic 5; Based on the mask error enhancement factor and the process deviation value corresponding to the target pattern 5, the local layout compensation value of the target pattern 5 is determined; The target graphic 5 is compensated according to the local map compensation value to obtain the compensated graphic; Based on different mask error enhancement factors, the above selection step, compensation value determination step, and compensation step are repeated to modify the bias version. Figure 3 Compensation is performed on each of the target patterns 5 with different mask error enhancement factors to obtain the compensated version including each compensated pattern. Figure 6 .

[0063] Specifically, in some exemplary embodiments, the absolute value of the layout compensation value is positively correlated with the absolute value of the process deviation value; in some preferred embodiments, the absolute value of the layout compensation value is proportional to the absolute value of the process deviation value.

[0064] Specifically, in some exemplary embodiments, the layout compensation value is negatively correlated with the mask error enhancement factor; in some preferred embodiments, the layout compensation value is inversely proportional to the mask error enhancement factor.

[0065] In this way, by using process deviation values ​​and meef values, after global biasing, it is possible to identify target patterns that have necking or excessive EPE due to large meef values, such as grooves or line ends in the "T" structure of 2D patterns, and perform special compensation. This effectively reduces the impact of global biasing on local feature patterns, reduces overall grinding errors, and thus reduces the time required for manual verification and secondary special processing. This improves the progress and efficiency of the entire OPC correction process, reduces OPC correction running time, and helps to improve overall etching efficiency and the pattern quality of the final real wafer.

[0066] Specifically, for 1.5D and 2D graphics, the meef value varies with the distance between the surrounding feature graphics and the target graphic 5, where, assuming the design version... Figure 1 The target graphic 5 moves 1 / 2 of a distance x (table header row), and the distance between the surrounding feature graphics and the target graphic 5 is y (table header column). As shown in Table 2, when the distance y is the same, the meef value is 3.3 when the 1 / 2 movement distance is 3nm; 4 when the 1 / 2 movement distance is 5nm; and 5 when the 1 / 2 movement distance is 7nm. That is, the meef value is calculated after the first simulation, and the simulation version is implemented based on the meef value and the process deviation value K. Figure 4 The actual amount of movement (i.e., the change value) is not precise.

[0067] Table 2 x and y for simulation version Figure 4 Impact of actual changes

[0068] In some preferred embodiments, a weakness compensation value is introduced during the compensation process; correspondingly, the weakness compensation value is introduced in the simulation version. Figure 4 In cases where the process deviation exceeds the expected deviation, the layout compensation value is determined based on the mask error enhancement factor and the process deviation value, including: In the simulation version Figure 4 If the process deviation exceeds the stated tolerance, the layout compensation value is determined based on the mask error enhancement factor, the process deviation value, and the weakness compensation value; the weakness compensation value is used to compensate for multiple mask error enhancement factors and / or the corrected offset. Figure 3 The deviation caused by the various spacings between the surrounding graphics and the target graphics 5.

[0069] Among them, affected by the design version Figure 1Due to complexity limitations, target graphic 5 is influenced by surrounding feature graphics, which not only leads to different MEEF values ​​but also affects the accuracy of the graphic compensation value. Therefore, additional compensation is provided through a weakness compensation value. This weakness compensation value is an empirical value derived from simulations using a large amount of data, resulting in a compensated version after final compensation. Figure 6 Based on this compensation version Figure 6 The real wafer development values ​​obtained by photolithography development meet the process allowable deviations, greatly improving the accuracy and reliability of the layout compensation values, which is conducive to improving wafer fabrication efficiency and improving the layout quality of the real wafer.

[0070] Specifically, the weakness compensation value is associated with the process node, and the value varies depending on the process node. In some exemplary embodiments, the weakness compensation value is 0.1 times the logarithm of the process node. Therefore, in the above-mentioned preliminary compensation using only the meef value and process deviation value K, the simulation version... Figure 4 Based on the fact that the change value approaches the expected change value, further compensation is provided through the weakness compensation value, a classic compensation value derived from a large number of simulations, so that the simulation version... Figure 4 The change value is closer to the expected change value, improving the compensation step and the resulting compensation version. Figure 6 The accuracy and reliability.

[0071] In some exemplary embodiments, the process node includes at least one of 28nm, 40nm, 55nm, 65nm, 90nm, 110nm, 130nm, 150nm, and 180nm. This means the optical proximity effect correction method is applicable to a variety of mature process nodes, has a wide range of applications, and can provide different degrees of compensation for different process nodes to improve the compensation performance at each process node. Figure 6 The accuracy and reliability of the correction.

[0072] Specifically, due to the layout load type, the lengths in the same direction of the structure of different feature graphics are different. For example, the lengths in the longitudinal direction of the "T" structure are different. At the same time, there are minimum feature sizes of the current process node such as 1D, 1.5D and 2D. Correspondingly, the meef values ​​are also different. Therefore, for different situations, compensation is carried out according to the different cases of process deviation value K.

[0073] In some exemplary embodiments, when the process deviation value is greater than zero, the layout compensation value is the difference between the ratio of the process deviation value to the mask error enhancement factor and the weakness compensation value.

[0074] In some exemplary embodiments, when the process deviation value is equal to zero, the layout compensation value is the process deviation value.

[0075] In some exemplary embodiments, when the process deviation value is less than zero, the layout compensation value is the difference between the sum of the weakness compensation value and the ratio of the process deviation value to the mask error enhancement factor.

[0076] That is, in some exemplary embodiments, the layout compensation value Y satisfies the following formula:

[0077] Where Y is the layout compensation value; X is the mask error enhancement factor; and K is the process deviation value.

[0078] Thus, through the design version Figure 1 After applying a global bias, target graphics that may have necking or bridging in each feature graphic are identified. OPC correction simulation is then performed on the simulation version. Figure 4 If the deviation still exceeds the expected process deviation, calculate the meef value and the process deviation value K, and substitute them into the formula for the layout compensation value Y above according to different process nodes to obtain the layout compensation value. The layout compensation value is then used to correct the offset of the OPC. Figure 3 Compensation will be provided to obtain the compensated version. Figure 6 This effectively reduces the risk of necking or bridging, provides accurate and reliable compensation, and significantly improves correction efficiency and compensation-based versions. Figure 6 The quality of the pattern after photolithography development.

[0079] Next, regarding the compensation version Figure 6 Repeat the above OPC correction simulation steps to update the simulation version. Figure 4 Up to the latest simulation version Figure 4 If the desired process deviation is met, the updated simulation version will be output. Figure 4 The corresponding updated compensation map.

[0080] Compared with the above bias version Figure 2 The OPC correction simulation steps are similar, using this compensation version. Figure 6 As a biased version of the new round of OPC correction simulation steps Figure 2 For example, regarding this compensation version Figure 6 The steps for performing OPC correction simulation include: adjusting the compensation version. Figure 6 Smoothing is performed to obtain an updated initial simulation version. Figure 4 Compensation version Figure 6 The edge is cut into multiple movable segments 41, and cutting lines 42 are generated on each segment 41; the edge placement error corresponding to the position of the cutting lines 42 is determined; the position of each segment 41 is adjusted according to the edge placement error to update the compensation version. Figure 6 Updated initial simulation version Figure 4And the corresponding edge placement error. If the updated edge placement error does not meet the preset error, then the position of each segment 41 is adjusted according to the updated edge placement error, and this is repeated 8 to 10 times until the updated edge placement error meets the preset error, thus obtaining the updated simulation version. Figure 4 And its corresponding updated compensation map.

[0081] At this point, if the updated simulation version Figure 4 If the desired process deviation is met, the updated compensation pattern is used as the final mask pattern for wafer photolithography and development; if the updated simulation pattern... Figure 4 If the deviation still exceeds the expected process deviation, the above compensation steps and OPC correction simulation steps are repeated on the updated compensation layout until the latest updated simulation layout is reached. Figure 4 If the desired process deviation is met, then the latest updated simulation version will be used. Figure 4 The latest updated compensation pattern is used as the final mask pattern for wafer photolithography and development.

[0082] Taking the "T" structure of a 2D graphic as an example, the initial design version Figure 1 Perform a global bias to obtain the biased version. Figure 2 ; then, for the offset version Figure 2 Perform OPC correction simulation to obtain the corrected bias version. Figure 3 and simulation version Figure 4 Next, in the simulation version Figure 4 In the event of process deviations exceeding expectations, according to the simulation version Figure 4 and design version Figure 1 Calculations are performed to obtain the meef values ​​corresponding to each feature shape. If the meef value meets a preset condition (e.g., meef value ≠ 1), the left edge of the vertical direction of the "T"-shaped structure is automatically selected as target shape 5. Based on the meef value of target shape 5, the process deviation value K, and the weakness compensation value, the formula for layout compensation value is substituted into the formula to calculate and determine the layout compensation value. The layout compensation value is then used to correct the offset plate. Figure 3 Compensation will be provided, and a compensated version will be obtained. Figure 6 Next, regarding the compensation version Figure 6 Repeat the above OPC correction simulation steps to update the simulation version. Figure 4 If the updated simulation version Figure 4 If the deviation still exceeds the expected process deviation, repeat the above compensation steps until a newer simulation version is available. Figure 4 To meet the expected process deviation, the latest updated simulation version will be used. Figure 4 The corresponding latest compensation version Figure 6 As the final mask layout output, it facilitates photolithography development based on the updated compensation layout to obtain the true wafer layout, greatly reducing the risk of pattern necking or bridging, and improving product quality and yield.

[0083] like Figure 6 As shown, the shaded area represents the initial design. Figure 1 The area on the left boundary of the diagram is a schematic of outward expansion compensation. This is based on the design version. Figure 1 The actual wafer layout obtained by photolithography and development is smaller than the design layout. Figure 1 The OPC correction simulation expands the layout boundary, where the outermost left line segment represents the corrected offset board after OPC correction. Figure 3 Boundary, the boundary with the design version Figure 1 The difference between the two values ​​(indicated by the double-headed arrow) is the process deviation value K; however, if it still exceeds the expected process deviation, the layout compensation value Y is further calculated to correct the offset. Figure 3 The boundary is folded inward (i.e., the area indicated by the one-way arrow), resulting in a compensated version. Figure 6 This compensation version Figure 6 The boundary lies at the corrected bias version Figure 3 Borders and Design Edition Figure 1 Between the boundaries.

[0084] Conversely, the right boundary of the diagram represents an inward-shrinking compensation area, which is shown in the design version. Figure 1 The actual wafer layout obtained by photolithography and development is larger than the design layout. Figure 1 The OPC correction simulation shrinks the layout boundary, where the innermost line segment on the right represents the corrected offset plate after OPC correction. Figure 3 Boundary, the boundary with the design version Figure 1 The difference between the two values ​​(indicated by the double-headed arrow) is the process deviation value K; however, if it still exceeds the expected process deviation, the layout compensation value Y is further calculated to correct the offset. Figure 3 The boundary expands outward (i.e., the area indicated by the one-way arrow) to obtain the compensated version. Figure 6 This compensation version Figure 6 The boundary lies at the corrected bias version Figure 3 Borders and Design Edition Figure 1 Between the boundaries.

[0085] The present invention also provides a method for fabricating a semiconductor structure, which is based on a compensated pattern obtained by the optical proximity effect correction method described above. This method can greatly improve the morphological accuracy of the semiconductor structure and increase the fabrication efficiency and yield.

[0086] The present invention also provides a semiconductor structure, which is prepared based on the semiconductor structure preparation method described above. This semiconductor structure has high morphological accuracy and excellent performance.

[0087] This invention also provides a semiconductor device, including any of the semiconductor structures described in this invention.

[0088] This invention also provides an electronic device, which includes any of the semiconductor structures described in this invention, or any of the semiconductor devices described in this invention. The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, vehicle terminal, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or it can be an intermediate product having the semiconductor device, such as a device motherboard having the semiconductor device. The use of the semiconductor device in this electronic device correspondingly improves its performance.

[0089] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0090] The above description is merely some embodiments of the present invention and is not intended to limit the present invention. Those skilled in the art should understand that the present invention can have various changes and improvements, and any modifications, equivalent substitutions and improvements made in accordance with the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A method for correcting the optical proximity effect, characterized in that, include: Based on the process deviation value, the design layout is globally offset to obtain the offset layout; The process deviation value is the difference between the design value of the design layout and the wafer development value obtained based on the design layout; The bias layout is subjected to OPC correction simulation to obtain the simulation layout and the corrected bias layout; If the simulated layout exceeds the expected process deviation, the corrected offset layout is compensated according to the mask error enhancement factor and the process deviation value to obtain a compensated layout. The mask error enhancement factor is the ratio between the variation value of the simulated layout and the shift value of the designed layout; Repeat the above OPC correction simulation steps for the compensation layout to update the simulation layout until the updated simulation layout meets the expected process deviation, and output the updated compensation layout corresponding to the updated simulation layout.

2. The optical proximity effect correction method according to claim 1, characterized in that, When the simulated layout exceeds the expected process deviation, the corrected offset layout is compensated based on the mask error enhancement factor and the process deviation value to obtain a compensated layout, including: If the simulated layout exceeds the expected process deviation, a layout compensation value is determined based on the mask error enhancement factor and the process deviation value. The corrected offset layout is compensated based on the layout compensation value to obtain the compensated layout.

3. The optical proximity effect correction method according to claim 2, characterized in that, The absolute value of the layout compensation value is positively correlated with the absolute value of the process deviation value, and the layout compensation value is negatively correlated with the mask error enhancement factor.

4. The optical proximity effect correction method according to claim 2, characterized in that, When the simulated layout exceeds the expected process deviation, determining the layout compensation value based on the mask error enhancement factor and the process deviation value includes: If the simulated layout exceeds the process deviation, the layout compensation value is determined based on the mask error enhancement factor, the process deviation value, and the weakness compensation value. The weakness compensation value is used to compensate for deviations caused by various mask error enhancement factors and / or various spacings between surrounding graphics and the target graphic in the corrected offset layout.

5. The optical proximity effect correction method according to claim 4, characterized in that, The weakness compensation value is associated with a process node; the process node includes at least one of 28nm, 40nm, 55nm, 65nm, 90nm, 110nm, 130nm, 150nm, and 180nm.

6. The optical proximity effect correction method according to claim 4, characterized in that, The layout compensation value satisfies at least one of the following characteristics: When the process deviation value is greater than zero, the layout compensation value is the difference between the ratio of the process deviation value to the mask error enhancement factor and the weakness compensation value. When the process deviation value is equal to zero, the layout compensation value is the process deviation value; When the process deviation value is less than zero, the layout compensation value is the sum of the weakness compensation value and the difference between the ratio of the process deviation value and the mask error enhancement factor.

7. The optical proximity effect correction method according to any one of claims 1-6, characterized in that, The corrected bias layout includes multiple feature patterns, and different feature patterns correspond to different mask error enhancement factors; When the simulated layout exceeds the expected process deviation, the corrected offset layout is compensated based on the mask error enhancement factor and the process deviation value to obtain a compensated layout, including: If the simulated layout exceeds the expected process deviation, a target pattern is selected in the corrected bias layout based on the mask error enhancement factor; the target pattern is at least one of the plurality of feature patterns; The target pattern is compensated based on the mask error enhancement factor and the process deviation value corresponding to the target pattern to obtain a compensated pattern; Based on different mask error enhancement factors, the above selection and compensation steps are repeated to compensate for each target pattern with different mask error enhancement factors in the corrected bias layout, thereby obtaining the compensated layout including each compensated pattern.

8. The optical proximity effect correction method according to claim 7, characterized in that, The selection of the target pattern in the corrected bias layout based on the mask error enhancement factor includes: Based on the simulation layout and the design layout, the mask error enhancement factor corresponding to each feature graphic is calculated. If the mask error enhancement factor meets the preset conditions, the corresponding feature pattern is determined as the target pattern.

9. The optical proximity effect correction method according to any one of claims 1-6, characterized in that, The desired process error satisfies at least one of the following characteristics: When the feature graphics of the design layout include 1D graphics, the expected process error corresponding to the 1D graphics is -3nm to 3nm; When the feature pattern of the design layout includes a 1.5D pattern, the expected process error corresponding to the 1.5D pattern is -6nm to 6nm; When the feature pattern of the design layout includes a 2D pattern, the expected process error corresponding to the 2D pattern is -8nm to 8nm.

10. The optical proximity effect correction method according to any one of claims 1-6, characterized in that, The OPC correction simulation of the bias layout yields the following simulation layout: The offset layout is smoothed to obtain an initial simulation layout. The edge of the offset pattern is divided into multiple movable segments, and a cutting line is generated on each segment; the cutting line is orthogonal to the segment. Determine the edge placement error corresponding to the position of the cutting line; The positions of each segment are adjusted according to the edge placement error to update the offset layout, the initial simulation layout and the corresponding edge placement error, until the updated edge placement error meets the preset error, thus obtaining the simulation layout and the corrected offset layout.

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