A time-to-digital converter suitable for continuous narrow pulse time measurement

Abstract

The application discloses a time-to-digital converter suitable for continuous narrow pulse time measurement, wherein a delay chain is composed of N delay units in cascade; a flip-flop group is composed of N flip-flops; an edge detection unit determines the segments where the rising edges and the falling edges of each narrow pulse are located according to the state data latched by the flip-flop group; a segment summation unit accumulates and sums up the number of logical '1' output by the flip-flop group in the corresponding segment to obtain the offset of the edge in the corresponding segment; an encoding unit determines the position of the edge in the delay chain according to the segment where the edge is located and the offset of the corresponding segment, and outputs the rising edge position and the falling edge position of multiple narrow pulses; and a coarse time counting unit counts the period of a clock signal to provide a coarse time measurement result. The time-to-digital converter provided by the application can realize double-edge synchronous measurement of a narrow pulse width signal without multiple delay chains.

Description

Technical Field

[0001] This invention relates to the field of time digital measurement technology, and in particular to a time-to-digital converter suitable for continuous narrow pulse time measurement. Background Technology

[0002] A time-to-digital converter (TDC) is a device that converts time intervals into digital outputs. It is widely used in high-energy physics experiments, lidar detection, medical PET imaging, and precision scientific metrology. Current high-precision TDCs typically employ an architecture combining coarse counting and fine time measurement. This means coarse time measurement is performed using a counter, while fine time measurement is achieved through interpolation. In the fine time measurement section, time interpolation based on delay chains is one of the mainstream solutions.

[0003] However, traditional delay chain-based time-delay converters (TDCs) have some limitations when measuring narrow pulse signals. First, due to the sampling mechanism, traditional TDCs struggle to effectively capture pulses with widths much smaller than the system's master clock period. Second, traditional TDCs typically only recognize a single type of signal edge; to measure pulse width, two independent channels are needed to capture the rising and falling edges separately, increasing system complexity. Third, within a single measurement cycle, traditional TDCs can generally only process a single event. When faced with multiple narrow pulses occurring consecutively within a short period, the dead time limitation prevents the simultaneous capture and measurement of multiple pulse edges.

[0004] Therefore, there is an urgent need for a time-to-digital converter that can measure narrow pulses with pulse widths much smaller than the clock cycle and can simultaneously capture the edges of multiple narrow pulses within a single measurement cycle.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a time-to-digital converter suitable for continuous narrow pulse time measurement, thereby solving the aforementioned technical problems in the prior art. The time-to-digital converter of this invention features a simple structure, low resource consumption, and no dead time in the measurement, making it suitable for applications requiring simultaneous capture and measurement of all pulse edges in high-density narrow pulse trains.

[0007] The objective of this invention is achieved through the following technical solution: A time-to-digital converter suitable for continuous narrow pulse time measurement, the time-to-digital converter comprising a delay chain, a trigger group, an edge detection unit, a segmented summation unit, an encoding unit, and a coarse time counting unit, wherein: The delay chain consists of N cascaded delay units. Multiple narrow pulses contained in the narrow pulse signal under test enter from the input end of the delay chain and are passed along the delay chain step by step. The pulse width of the narrow pulse is less than the system master clock period. The trigger group consists of N triggers, and the N triggers are connected one-to-one with the output terminals of N delay units; the trigger group is used to latch the output state of each delay unit in the delay chain at the trigger edge of the clock signal. The edge detection unit is connected to the trigger group and is used to determine the segments where the rising and falling edges of each narrow pulse are located based on the state data latched by the trigger group, and output the segment information where the edge is located. The edge detection unit further includes a cross-cycle state processing circuit, which stores the most recently detected edge type, keeps the edge type unchanged when no new edge is detected, and selects and outputs the edges detected in the current measurement cycle based on the edge type to determine the edge sequence. The segmented summation unit includes n sub-adders, which are connected one-to-one with the n segments determined by the edge detection unit. They are used to accumulate and sum the number of logic "1"s output by the flip-flop group in the corresponding segment to obtain the offset of the edge in the corresponding segment. The input terminal of the encoding unit is connected to the edge detection unit and the segmented summation unit respectively, and is used to determine the position of the edge in the delay chain according to the segment where the edge is located and the offset of the corresponding segment, and output the rising edge position and falling edge position of multiple narrow pulses in one measurement cycle. The coarse time counting unit is used to count the period of the clock signal to provide coarse time measurement results.

[0008] Compared with the prior art, the time-to-digital converter provided by the present invention can realize the synchronous measurement of narrow pulse width signals on both sides without multiple delay chains, and can process multiple continuous narrow pulses simultaneously within one measurement cycle, overcoming the technical limitations of traditional TDC when measuring narrow pulse widths and high-density narrow pulse trains that are much smaller than the clock cycle. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1This is a schematic diagram of the structure of a time-to-digital converter suitable for continuous narrow pulse time measurement provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the edge detection unit structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the configuration of the output selection circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the segmented summation unit described in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the encoding unit described in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0012] First, the following explanations are provided for the terms that may be used in this article: The term "and / or" means that either or both can be achieved simultaneously. For example, X and / or Y means that it includes both "X" or "Y" as well as the three cases of "X and Y".

[0013] The terms "comprising," "including," "containing," "having," or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction conditions, processing conditions, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be interpreted as including not only the expressly listed technical feature element, but also other technical feature elements that are not expressly listed and are well-known in the art.

[0014] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0015] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention belong to prior art known to those skilled in the art. For example... Figure 1 The diagram shown is a schematic representation of a time-to-digital converter for continuous narrow pulse time measurement provided in an embodiment of the present invention. The time-to-digital converter includes a delay chain, a trigger group, an edge detection unit, a segmented summation unit, an encoding unit, and a coarse time counting unit, wherein: The delay chain consists of N cascaded delay units. Multiple narrow pulses contained in the narrow pulse signal under test enter from the input end of the delay chain and are passed along the delay chain step by step. The pulse width of the narrow pulse is less than the system master clock period. The trigger group consists of N triggers, and the N triggers are connected one-to-one with the output terminals of N delay units; the trigger group is used to latch the output state of each delay unit in the delay chain at the trigger edge of the clock signal. The edge detection unit is connected to the trigger group and is used to determine the segments where the rising and falling edges of each narrow pulse are located based on the state data latched by the trigger group, and output the segment information where the edge is located. The edge detection unit further includes a cross-cycle state processing circuit, which stores the most recently detected edge type, keeps the edge type unchanged when no new edge is detected, and selects and outputs the edges detected in the current measurement cycle based on the edge type to determine the edge sequence. The segmented summation unit includes n sub-adders, which are connected one-to-one with the n segments determined by the edge detection unit. They are used to accumulate and sum the number of logic "1"s output by the flip-flop group in the corresponding segment to obtain the offset of the edge in the corresponding segment. The input terminal of the encoding unit is connected to the edge detection unit and the segmented summation unit respectively, and is used to determine the position of the edge in the delay chain according to the segment where the edge is located and the offset of the corresponding segment, and output the rising edge position and falling edge position of multiple narrow pulses in one measurement cycle. The coarse time counting unit is used to count the period of the clock signal to provide coarse time measurement results.

[0016] In a specific implementation, each delay unit in the delay chain has a defined delay time t. cell Each time the signal passes through a delay unit, t is generated. cell Time delay; The delay chain is divided into n segments along the signal transmission direction, and each segment contains m delay units, satisfying the relationship: N = n×m; N is the total number of delay units; The delay time of a single segment is m×t cell The total delay time of the delay chain is N×t, which is less than the narrowest pulse width of the narrow pulse signal to be tested. cell Satisfying Relationship: T <N×t cell <(n / (n-1))×T; Where T is the system master clock period.

[0017] The delay unit can be any of the following structures: Buffer; logic gate; data selector; adder unit based on carry chain structure.

[0018] When implemented in a Field Programmable Gate Array (FPGA), the carry chain resources at the device's underlying layer can be fully utilized to form a delay chain, thereby achieving a smaller unit delay. When implemented in an Application-Specific Integrated Circuit (ASIC), inverter chains or buffer chains can be used as delay units.

[0019] In a specific implementation, when the narrow pulse signal is transmitted in the delay chain in the trigger group, the output of the delay unit that it passes through is logic "1", and the output of the delay unit that has not been reached or has left is logic "0". Therefore, the result latched by the trigger group is a thermometer code consisting of logic "1" and "0", which reflects the position information of each narrow pulse signal in the delay chain.

[0020] like Figure 2 The diagram shown is a schematic representation of the edge detection unit according to an embodiment of the present invention. The edge detection unit includes multiple tap input terminals and a detection logic circuit, wherein: The plurality of tap input terminals are respectively connected to the output terminal of the starting delay unit of each segment in the delay chain, and the output terminal of the end of the delay chain; The detection logic circuit is used to detect the position of the logic state change of the narrow pulse signal in the delay chain according to the logic state of the multiple tap input terminals, and to determine the delay chain segment where the rising edge and falling edge of each narrow pulse are located.

[0021] Specifically, with Figure 2 Taking the i-th segment as an example: when the i-th tap input is detected to be logic "1" and the (i+1)-th tap input is logic "0", it indicates that the signal changes from "1" to "0" in the i-th segment, that is, the falling edge is located in the i-th segment. At this time, the falling edge indicator signal S of the i-th segment... fallValid; when the i-th tap input is detected to be logic "0" and the (i+1)-th tap input is logic "1", it indicates that the signal changes from "0" to "1" in the i-th segment, that is, the rising edge is located in the i-th segment. At this time, the rising edge indicator signal S of the i-th segment... rise efficient.

[0022] Within one measurement cycle, the edge detection unit detects all n+1 tap input terminals from the end to the beginning of the delay chain to capture the edges of multiple narrow pulse signals that may appear in the delay chain. This logical detection sequence from the end to the beginning is opposite to the direction of signal propagation in the delay chain, but consistent with the temporal order of signal edges, making it easier to correctly distinguish between the rising and falling edges of the same pulse.

[0023] Furthermore, since the measurement is performed periodically, when a pulse has a large pulse width or appears near the boundary of the measurement cycle, its rising and falling edges may occur in two adjacent measurement cycles. To solve the problem of correct matching of these cross-cycle edges, the edge detection unit is equipped with a cross-cycle state processing circuit, such as... Figure 2 As shown, the cross-cycle state processing circuit includes a state memory circuit and an output selection circuit, wherein: The state memory circuit is used to store the most recently detected edge type and keep the edge type unchanged when no new edge is detected. The output selection circuit, the state memory circuit, and all segmented S fall and S rise The signal connection is used to select and output edge signals detected in the current measurement cycle based on the edge types stored in the state memory circuit, so that the output edge type sequence satisfies the constraint relationship of alternating rising and falling edges; wherein, S fall To indicate the falling edge signal; S rise This indicates the rising edge signal.

[0024] like Figure 3 The diagram shows a configuration of the output selection circuit according to an embodiment of the present invention. In the current measurement cycle, the output selection circuit, according to the control signal S1, masks the edge information detected before the first valid edge in the current measurement cycle. Specifically, if the edge type stored in the state memory circuit is a rising edge, then the first valid edge of the current measurement cycle is a falling edge, that is, all edge information before the first falling edge is masked; if the edge type stored in the state memory circuit is a falling edge, then the first valid edge of the current measurement cycle is a rising edge, that is, all edge information before the first rising edge is masked.

[0025] This cross-cycle state memory and output selection mechanism ensures the correct connection of edge information between adjacent measurement cycles, avoids repeated measurement or misjudgment of the same edge, and thus supports continuous and correct measurement of high-density narrow pulse trains.

[0026] like Figure 4 The diagram shown is a schematic of the segmented summation unit according to an embodiment of the present invention. In the segmented summation unit, the sub-adders are implemented using a multi-level adder tree structure to complete the summation operation of the thermometer codes within the segments in a short time. After the edge detection unit determines the segment where the edge is located, the corresponding sub-adder accumulates and sums the number of logic "1" output by the flip-flop group in that segment. The result is the offset of the edge in that segment. Because in the thermometer code latched by the trigger group, the logic value characteristics of the edge position are: logic "0" before the rising edge and logic "1" after the rising edge; logic "1" before the falling edge and logic "0" after the falling edge. Therefore, for a rising edge, the offset within a segment is equal to the number of logic "1"s within that segment; for a falling edge, the offset within a segment is equal to the number of logic "0"s within that segment, which is the segment length minus the number of logic "1"s.

[0027] In a specific implementation, when a rising edge is detected in the encoding unit, the starting delay unit number of the segment where the rising edge is located is added to the number of logic "1"s in the corresponding segment to obtain the position of the rising edge. When a falling edge is detected, the position of the falling edge is obtained by adding the starting delay cell number of the segment containing the falling edge to the difference between the segment length and the number of logic "1"s in the corresponding segment.

[0028] like Figure 5 The diagram shown is a structural schematic of the encoding unit according to an embodiment of the present invention. Taking the i-th segment as an example, the encoding unit is connected to the edge detection unit and the segment summation unit. The encoding unit first processes the S output by the edge detection unit. rise Signal and S fall The signal undergoes a logical OR operation to generate an edge presence flag. When the edge presence flag corresponding to a certain segment is valid, it confirms the presence of a pulse edge within that segment. Subsequently, the encoding unit reads the S corresponding to that segment. rise Signal to determine edge type: If S rise If the signal is valid, the edge is determined to be a rising edge, and the starting delay unit number of the segment is added to the sum of the logic "1" outputs of the corresponding sub-adder to obtain the position of the rising edge in the delay chain; if S riseIf the signal is invalid, the edge is determined to be a falling edge. The position of the falling edge in the delay chain is obtained by adding the starting delay unit number of the segment to the segment length minus the sum of logic "1" outputs of the corresponding sub-adder.

[0029] In this manner, the encoding unit synchronously outputs the rising and falling edge positions of multiple narrow pulses present in the delay chain within one measurement cycle. This calculation method combines segment-level coarse positioning with intra-segment fine positioning, obtaining precise edge position information through only addition operations.

[0030] In a specific implementation, the coarse time counting unit is implemented by a multi-bit binary counter, which continuously accumulates the clock cycle during system operation; when a measurement is completed, the count value of the coarse time counting unit and the edge position measurement result output by the encoding unit together constitute a complete timestamp.

[0031] Specifically, the rising edge time t of the narrow pulse signal under test rise Represented as: t rise = N coarse ×T clk - P rise ×t cell ; Where, N coarse T represents the count value of the coarse time counting unit. clk For clock cycles; P rise The rising edge position number output by the encoding unit; t cell The delay time for a single delay unit; Falling edge time t fall Represented as; t fall = N coarse ×T clk – P fall ×t cell ; Among them, P fall This is the falling edge position number output by the encoding unit; Therefore, the pulse width Δt of the narrow pulse signal to be measured can be obtained as: Δt = t fall - t rise .

[0032] For multiple consecutive narrow pulse signals, the rising and falling edges of each pulse can be obtained one by one using the method described above.

[0033] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0034] In summary, the time-to-digital converter (TDC) for continuous narrow pulse time measurement provided in this embodiment of the invention achieves simultaneous capture and measurement of the rising and falling edges of narrow pulse signals by a single delay chain. This is achieved by dividing the cascaded delay chain into multiple segments and utilizing the segment-level coarse positioning of the edge detection unit and the segment-level fine positioning of the segment summation unit. Compared with the traditional scheme that uses two independent TDCs to measure the rising and falling edges separately, this invention requires only one delay chain and a set of triggers, significantly reducing hardware resource consumption. Furthermore, since the measurement of the rising and falling edges shares the same delay chain and clock sampling system, it avoids the channel inconsistency problem that may exist between multiple TDCs, thus improving measurement accuracy.

[0035] Furthermore, by adjusting the number of segments *n* in the delay chain and the number of delay units in each segment, this invention can flexibly adapt to different application requirements. When it is necessary to measure narrower pulse widths or resolve smaller pulse intervals, the number of segments can be appropriately increased and the length of each segment decreased to improve the resolution of edge detection. The edge detection unit in this invention effectively solves the problem of edge misjudgment caused by the measurement cycle boundary through a cross-cycle state memory and output selection mechanism, enabling it to correctly capture and match the rising and falling edges of each pulse even in high-density narrow pulse train measurement scenarios.

[0036] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A time-to-digital converter suitable for continuous narrow pulse time measurement, characterized in that, The time-to-digital converter includes a delay chain, a trigger group, an edge detection unit, a segmented summation unit, an encoding unit, and a coarse time counting unit, wherein: The delay chain consists of N cascaded delay units. Multiple narrow pulses contained in the narrow pulse signal under test enter from the input end of the delay chain and are passed along the delay chain step by step. The pulse width of the narrow pulse is less than the system master clock period. The trigger group consists of N triggers, and the N triggers are connected one-to-one with the output terminals of N delay units; the trigger group is used to latch the output state of each delay unit in the delay chain at the trigger edge of the clock signal. The edge detection unit is connected to the trigger group and is used to determine the segments where the rising and falling edges of each narrow pulse are located based on the state data latched by the trigger group, and output the segment information where the edge is located. The edge detection unit further includes a cross-cycle state processing circuit, which stores the most recently detected edge type, keeps the edge type unchanged when no new edge is detected, and selects and outputs the edges detected in the current measurement cycle based on the edge type to determine the edge sequence. The segmented summation unit includes n sub-adders, which are connected one-to-one with the n segments determined by the edge detection unit. They are used to accumulate and sum the number of logic "1"s output by the flip-flop group in the corresponding segment to obtain the offset of the edge in the corresponding segment. The input terminal of the encoding unit is connected to the edge detection unit and the segmented summation unit respectively, and is used to determine the position of the edge in the delay chain according to the segment where the edge is located and the offset of the corresponding segment, and output the rising edge position and falling edge position of multiple narrow pulses in one measurement cycle. The coarse time counting unit is used to count the period of the clock signal to provide coarse time measurement results.

2. The time-to-digital converter for continuous narrow pulse time measurement according to claim 1, characterized in that, Each delay unit in the delay chain has a defined delay time t. cell Each time the signal passes through a delay unit, t is generated. cell Time delay; The delay chain is divided into n segments along the signal transmission direction, and each segment contains m delay units, satisfying the relationship: N = n×m; N is the total number of delay units; The delay time of a single segment is m×t cell The total delay time of the delay chain is N×t, which is less than the narrowest pulse width of the narrow pulse signal to be tested. cell Satisfying Relationship: T < N×t cell < (n / (n-1))×T; Where T is the system master clock period.

3. The time-to-digital converter for continuous narrow pulse time measurement according to claim 2, characterized in that, The delay unit can be any of the following structures: Buffer; logic gate; data selector; adder unit based on carry chain structure.

4. The time-to-digital converter for continuous narrow pulse time measurement according to claim 1, characterized in that, In the trigger group, when the narrow pulse signal is transmitted in the delay chain, the delay unit that it passes through outputs logic "1", and the delay unit that has not been reached or has left outputs logic "0". Therefore, the result latched by the trigger group is a thermometer code consisting of logic "1" and "0", which reflects the position information of each narrow pulse signal in the delay chain.

5. The time-to-digital converter for continuous narrow pulse time measurement according to claim 1, characterized in that, The edge detection unit includes multiple tap input terminals and detection logic circuitry, wherein: The plurality of tap input terminals are respectively connected to the output terminal of the starting delay unit of each segment in the delay chain, and the output terminal of the end of the delay chain; The detection logic circuit is used to detect the position of the logic state change of the narrow pulse signal in the delay chain according to the logic state of the multiple tap input terminals, and to determine the delay chain segment where the rising edge and falling edge of each narrow pulse are located.

6. The time-to-digital converter for continuous narrow pulse time measurement according to claim 5, characterized in that, The cross-cycle state processing circuit includes a state memory circuit and an output selection circuit, wherein: The state memory circuit is used to store the most recently detected edge type and keep the edge type unchanged when no new edge is detected. The output selection circuit, the state memory circuit, and all segmented S fall and S rise The signal connection is used to select and output edge signals detected in the current measurement cycle based on the edge types stored in the state memory circuit, so that the output edge type sequence satisfies the constraint relationship of alternating rising and falling edges; wherein, S fall To indicate the falling edge signal; S rise This indicates the rising edge signal.

7. The time-to-digital converter for continuous narrow pulse time measurement according to claim 1, characterized in that, In the segmented summation unit, the sub-adders are implemented using a multi-level adder tree structure to complete the summation operation of the thermometer codes within the segments in a short time. After the edge detection unit determines the segment where the edge is located, the corresponding sub-adder accumulates and sums the number of logic "1"s output by the flip-flop group in that segment. The result is the offset of the edge in that segment. For a rising edge, the offset within a segment is equal to the number of logic "1"s in that segment; for a falling edge, the offset within a segment is equal to the number of logic "0"s in that segment, which is the segment length minus the number of logic "1"s.

8. The time-to-digital converter for continuous narrow pulse time measurement according to claim 1, characterized in that, In the encoding unit, when a rising edge is detected, the starting delay unit number of the segment where the rising edge is located is added to the number of logic "1"s in the corresponding segment to obtain the position of the rising edge; When a falling edge is detected, the position of the falling edge is obtained by adding the starting delay cell number of the segment containing the falling edge to the difference between the segment length and the number of logic "1"s in the corresponding segment.

9. The time-to-digital converter for continuous narrow pulse time measurement according to claim 1, characterized in that, The coarse time counting unit is implemented by a multi-bit binary counter, which continuously accumulates and counts the clock cycles during system operation. When a measurement is completed, the count value of the coarse time counting unit and the edge position measurement result output by the encoding unit together constitute a complete timestamp.

10. The time-to-digital converter for continuous narrow pulse time measurement according to claim 9, characterized in that, The rising edge time t of the narrow pulse signal under test rise Represented as: t rise = N coarse ×T clk - P rise ×t cell ; Where, N coarse T represents the count value of the coarse time counting unit. clk For clock cycles; P rise The rising edge position number output by the encoding unit; t cell The delay time for a single delay unit; Falling edge time t fall Represented as; t fall = N coarse ×T clk – P fall ×t cell ; Among them, P fall This is the falling edge position number output by the encoding unit; Therefore, the pulse width Δt of the narrow pulse signal to be measured can be obtained as: Δt = t fall - t rise 。

Images