A time service server and a time service method

Abstract

The application discloses a kind of time service server and time service method. Time service server includes: satellite receiving circuit, receives and demodulates satellite signal, exports standard second pulse;High-stability frequency standard circuit exports reference frequency signal;High-precision time-frequency measurement and domestication circuit generates time-frequency deviation data according to the second pulse and reference frequency signal collected;Core main control circuit, high-precision time-frequency measurement and domestication circuit are used to send time-frequency deviation data to core main control circuit, and core main control circuit is used to calculate correction amount according to time-frequency deviation data, and according to correction amount, output control signal to correct reference frequency signal;Multi-protocol signal output circuit, core main control circuit is also used to distribute the reference frequency signal after correction to multi-protocol signal output circuit, and multi-protocol signal output circuit is used to export multi-channel standardized time-frequency signal according to the reference frequency signal after correction. The reliability of the time service server of the application is high, the time-keeping accuracy is high and the multi-protocol output.

Description

Technical Field

[0001] This invention relates to the field of time synchronization technology for power systems, and more particularly to a time synchronization server and a time synchronization method. Background Technology

[0002] In critical industrial scenarios such as power, rail transportation, industrial automation, and communication base stations, the requirements for time synchronization accuracy, timekeeping stability, and system redundancy reliability across the entire network are extremely high. This necessitates relying on high-precision time bases to achieve SOE event recording, equipment fault tracing, and multi-device data alignment. Existing timekeeping servers generally suffer from numerous technical deficiencies: First, most of them are single-satellite timing modes with no redundant receiving mechanism. They are prone to loss of lock when satellite signals are blocked or interfered with, resulting in poor reliability.

[0003] Second, local timekeeping often uses ordinary crystal oscillators, which cause large time drifts after satellite loss of lock, achieving only millisecond-level timekeeping accuracy, which cannot meet the long-term timekeeping requirements at the nanosecond level.

[0004] Third, the frequency standard discipline algorithm is simple, with large phase jitter, weak dynamic compensation capability, and poor time synchronization stability.

[0005] Fourth, the protocol output is singular, making it difficult to simultaneously adapt to the diverse timing needs of industrial and network equipment. Summary of the Invention

[0006] This invention provides a time synchronization and timekeeping server and a time synchronization and timekeeping method to solve the technical problems of poor reliability and low timekeeping accuracy of existing time synchronization and timekeeping servers.

[0007] According to one aspect of the present invention, a time synchronization and timekeeping server is provided, the time synchronization and timekeeping server comprising: Satellite receiving circuit, used to receive and demodulate satellite signals and output standard second pulse; High-stability frequency reference circuit, used to output a reference frequency signal; A high-precision time-frequency measurement and discipline circuit is connected to the satellite receiving circuit and the high-stability frequency standard circuit, respectively, and is used to generate time-frequency deviation data based on the collected second pulse and the reference frequency signal; The core main control circuit is connected to the high-precision time and frequency measurement and discipline circuit. The high-precision time and frequency measurement and discipline circuit is used to send the time and frequency deviation data to the core main control circuit. The core main control circuit is used to calculate the correction amount based on the time and frequency deviation data and output the control signal based on the correction amount to correct the reference frequency signal. A multi-protocol signal output circuit is connected to the core main control circuit. The core main control circuit is also used to distribute the corrected reference frequency signal to the multi-protocol signal output circuit. The multi-protocol signal output circuit is used to output multiple standardized time-frequency signals according to the corrected reference frequency signal.

[0008] Optionally, the core main control circuit includes: an FPGA timing unit and an ARM processor, wherein the FPGA timing unit is connected to the ARM processor; The high-precision time-frequency measurement and discipline circuit is used to send the time-frequency deviation data to the FPGA timing unit. The FPGA timing unit is used to upload the time-frequency deviation data to the ARM processor. The ARM processor calculates the correction amount based on the time-frequency deviation data and sends it down to the FPGA timing unit. The FPGA timing unit is also used to output a control signal according to the correction amount to correct the reference frequency signal, and to distribute the corrected reference frequency signal to the multi-protocol signal output circuit.

[0009] Optionally, the time synchronization and timekeeping server further includes: a redundant power supply circuit, which is connected to the satellite receiving circuit, the high-stability frequency standard circuit, the high-precision time and frequency measurement and discipline circuit, the main control circuit, and the multi-protocol signal output circuit; The redundant power supply circuit is used to provide dual independent power supplies for the satellite receiving circuit, the high-stability frequency standard circuit, the high-precision time and frequency measurement and discipline circuit, the main control circuit, and the multi-protocol signal output circuit, and automatically switches to the other power supply when one power supply fails.

[0010] Optionally, the ARM processor is further configured to use a Kalman filter algorithm to filter the received time-frequency deviation data; The ARM processor is also used to calculate the frequency and phase correction of the reference frequency signal based on the filtered time-frequency deviation data using an incremental PID algorithm and send it to the FPGA timing unit.

[0011] Optionally, the ARM processor has a built-in dual-source intelligent time decision mechanism for real-time monitoring of the satellite signal's lock status and for controlling the high-stability frequency standard circuit as the core timekeeping source when the satellite signal fails.

[0012] According to another aspect of the present invention, a time synchronization and timekeeping method is provided, applied to a time synchronization and timekeeping server as described in any one of the preceding aspects, the time synchronization and timekeeping method comprising: The satellite receiver circuit receives satellite signals and outputs standard second pulses, while the high-stability frequency standard circuit outputs a reference frequency signal. The high-precision time-frequency measurement and discipline circuit generates time-frequency deviation data from the collected second pulse and the reference frequency signal, and sends it to the core main control circuit. The core main control circuit calculates the correction amount based on the time-frequency deviation data, outputs a control signal based on the correction amount to correct the reference frequency signal, and distributes the corrected reference frequency signal to the multi-protocol signal output circuit. The multi-protocol signal output circuit outputs multiple standardized time-frequency signals based on the corrected reference frequency signal.

[0013] Optionally, the step of calculating a correction amount based on the time-frequency deviation data through the core main control circuit, outputting a control signal based on the correction amount to correct the reference frequency signal, and distributing the corrected reference frequency signal to the multi-protocol signal output circuit includes: The time-frequency deviation data is received by the FPGA timing unit and uploaded to the ARM processor. The ARM processor calculates the correction amount based on the time-frequency deviation data and sends it to the FPGA timing unit. The FPGA timing unit outputs a control signal according to the correction amount to correct the reference frequency signal, and then distributes the corrected reference frequency signal to the multi-protocol signal output circuit.

[0014] Optionally, the step of calculating the correction amount based on the time-frequency deviation data using the ARM processor and sending it to the FPGA timing unit includes: The time-frequency deviation data is filtered using the Kalman filter algorithm to obtain filtered time-frequency deviation data. Based on the filtered time-frequency deviation data and the incremental PID control algorithm, the frequency and phase correction of the reference frequency signal are calculated and sent to the FPGA timing unit.

[0015] Optionally, the state equation of the Kalman filter algorithm is X(k)=A·X(k-1)+W(k), and the observation equation of the Kalman filter algorithm is Z(k)=H·X(k)+V(k); Where X(k) is the phase deviation and frequency deviation state quantity at time k, A is the state transition matrix; W(k) is the system process noise, Z(k) is the measured phase deviation observation value of the FPGA timing unit, H is the observation matrix, and V(k) is the observation noise.

[0016] The technical solution of this invention provides a high-precision, high-reliability, multi-protocol adaptable BeiDou / GPS timekeeping server that supports network redundancy and linkage. It achieves a dual-redundant timing architecture by setting up a satellite receiving circuit to provide an external time reference and a high-stability frequency standard circuit to provide a local timekeeping reference. It utilizes high-precision time and frequency measurement and a discipline circuit to collect deviations, and a core main control circuit for closed-loop correction. The satellite receiving circuit and the high-stability frequency standard circuit respectively realize external satellite timekeeping and local atomic timekeeping. The multi-protocol signal output circuit can output multiple standardized time and frequency signals, compatible with the timekeeping access requirements of various industrial devices. In summary, this invention effectively solves the problems of poor reliability and single protocol output in existing timekeeping servers, providing a timekeeping server with high reliability, high timekeeping accuracy, and multi-protocol output.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a time synchronization and timekeeping server according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of another time synchronization and timekeeping server provided according to an embodiment of the present invention; Figure 3 This is an overall flowchart of a core algorithm provided according to an embodiment of the present invention; Figure 4 This is a flowchart of a time synchronization and timekeeping method provided according to an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic diagram of a time synchronization and timekeeping server according to an embodiment of the present invention, with reference to... Figure 1 According to an embodiment of the present invention, a time synchronization and timekeeping server is provided, which includes: Satellite receiving circuit 10 is used to receive and demodulate satellite signals and output standard second pulses; High-stability frequency reference circuit 20 is used to output a reference frequency signal; The high-precision time and frequency measurement and discipline circuit 30 is connected to the satellite receiving circuit 10 and the high-stability frequency standard circuit 20, respectively, and is used to generate time and frequency deviation data based on the collected second pulse and reference frequency signal; The core main control circuit 40 is connected to the high-precision time and frequency measurement and discipline circuit 30. The high-precision time and frequency measurement and discipline circuit 30 is used to send the time and frequency deviation data to the core main control circuit 40. The core main control circuit 40 is used to calculate the correction amount based on the time and frequency deviation data and output the control signal based on the correction amount to correct the reference frequency signal. The multi-protocol signal output circuit 50 is connected to the core main control circuit 40. The core main control circuit 40 is also used to distribute the corrected reference frequency signal to the multi-protocol signal output circuit 50. The multi-protocol signal output circuit 50 is used to output multiple standardized time and frequency signals according to the corrected reference frequency signal.

[0023] Specifically, the satellite receiving circuit 10 serves as the external time traceability entry point for the time synchronization and timing server, and is the core time reference source under normal time synchronization conditions. This circuit is compatible with multi-band signal reception from both the BeiDou and GPS dual-satellite systems. It can demodulate, reduce noise, and shape space satellite signals, continuously and synchronously outputting standard 1PPS second pulses and TOD time messages to the backend high-precision time and frequency measurement and discipline circuit 30 and the core main control circuit 40, providing the entire system with absolutely accurate raw time coordinates. All subsequent core timing operations, such as local frequency standard calibration, time and frequency deviation calculation, and time reference discipline updates, use the valid satellite time signal output by this circuit as a reference, forming the basis for tracing the timing accuracy of the entire system. In one embodiment, the satellite receiving circuit 10 adopts a BeiDou-3 B1+GPS L1 dual-mode multi-band RF receiving module, with built-in RF filtering and signal isolation transformers.

[0024] The high-stability frequency standard circuit 20 establishes a local high-stability time and frequency reference for the timekeeping server, forming a dual-redundant timing architecture of "external satellite timekeeping + local atomic timekeeping" with the front-end satellite receiving circuit 10, working in conjunction with the entire timing system. After the device is powered on, the rubidium atomic clock on this circuit continuously outputs a highly stable 10MHz reference frequency, providing high-frequency clock support for all timing processing modules of the entire device. Under normal satellite signal lock-in conditions, this circuit, as the object to be calibrated, works with the high-precision time and frequency measurement and discipline circuit 30 to complete the dynamic correction of frequency and phase, ensuring that the local frequency standard is highly synchronized with the satellite standard time. When the satellite signal encounters abnormal conditions such as obstruction, electromagnetic interference, or loss of lock-in, this circuit immediately and seamlessly takes over the satellite time reference, upgrading to the core timekeeping source of the entire device, ensuring that the device can still maintain high-precision autonomous timekeeping for a long time after being disconnected from external satellite signals, making up for the lack of reliability of the single satellite timekeeping method. In one embodiment, the high-stability frequency standard circuit 20 uses a commercially available miniaturized rubidium atomic clock with a standard output of 10MHz sine frequency and supports external voltage-controlled frequency / phase adjustment.

[0025] The high-precision time-frequency measurement and discipline circuit 30 acquires the 1PPS pulse output from the satellite receiving circuit 10 and the 10MHz frequency standard signal output from the high-stability frequency standard circuit 20, respectively, and captures the timing phase difference of the two channels in parallel in hardware to complete the raw sampling of nanosecond-level time difference and frequency difference; the acquired raw time-frequency deviation data is uploaded to the core main control circuit 40 in real time. In one embodiment, the high-precision time-frequency measurement and discipline circuit 30 adopts a high-speed phase acquisition chip, which supports 0.1ns-level time difference sampling.

[0026] The core control circuit 40 processes the time-frequency deviation data using a Kalman filter algorithm, filtering out satellite jitter and electromagnetic noise to obtain a smooth and stable satellite time reference. Based on the filtered deviation, it runs an incremental PID algorithm to calculate the rubidium clock frequency and phase correction. Upon receiving correction commands, it outputs an analog control voltage to correct the 10MHz output frequency and synchronization phase of the rubidium atomic clock in real time, completing closed-loop discipline and continuously reducing the time deviation between the local frequency standard and the satellite standard. Finally, the calibrated and corrected unified high-precision time-frequency reference signal is multi-channel synchronously shaped and distributed to the multi-protocol signal output circuit.

[0027] The multi-protocol signal output circuit 50 receives the calibrated high-precision time and frequency reference distributed by the core main control circuit 40, and completes signal level conversion, electrical isolation, and protocol encoding; it can synchronously and in parallel output multiple standardized time and frequency signals, including NTP network time synchronization messages and IEEE1588 PTP precision time synchronization signals, and is compatible with the synchronous access requirements of various terminals in the power, rail transit, industrial automation, and communication industries.

[0028] The technical solution of this invention provides a high-precision, high-reliability, multi-protocol adaptable BeiDou / GPS timekeeping server that supports network redundancy and linkage. It achieves a dual-redundant timing architecture by setting up a satellite receiving circuit to provide an external time reference and a high-stability frequency standard circuit to provide a local timekeeping reference. It utilizes high-precision time and frequency measurement and a discipline circuit to collect deviations, and a core main control circuit for closed-loop correction. The satellite receiving circuit and the high-stability frequency standard circuit respectively realize external satellite timekeeping and local atomic timekeeping. The multi-protocol signal output circuit can output multiple standardized time and frequency signals, compatible with the timekeeping access requirements of various industrial devices. In summary, this invention effectively solves the problems of poor reliability and single protocol output in existing timekeeping servers, providing a timekeeping server with high reliability, high timekeeping accuracy, and multi-protocol output.

[0029] Figure 2 This is a schematic diagram of the structure of another time synchronization and timekeeping server provided according to an embodiment of the present invention, with reference to... Figure 2 Optionally, the core main control circuit 40 includes: an FPGA timing unit 41 and an ARM processor 42, wherein the FPGA timing unit 41 is connected to the ARM processor 42. The high-precision time-frequency measurement and discipline circuit 30 is used to send the time-frequency deviation data to the FPGA timing unit 41. The FPGA timing unit 41 is used to upload the time-frequency deviation data to the ARM processor 42. The ARM processor 42 calculates the correction amount based on the time-frequency deviation data and sends it down to the FPGA timing unit 41. The FPGA timing unit 41 is also used to output a control signal according to the correction amount to correct the reference frequency signal, and to distribute the corrected reference frequency signal to the multi-protocol signal output circuit 50.

[0030] Specifically, the core main control circuit 40 is composed of an FPGA timing unit 41 and an ARM processor 42. The two interact bidirectionally with data and control commands through an internal high-speed AXI bus, with clear division of labor and closed-loop collaboration.

[0031] The FPGA timing unit 41 is the underlying hardware execution layer. It receives the raw time-frequency deviation data uploaded by the high-precision time-frequency measurement and discipline circuit 30 in parallel hardware, performs pulse preprocessing without software delay, and filters out instantaneous satellite glitches and noise in hardware. It then transmits the raw deviation data uplink to the ARM processor 42. It receives PID correction control commands from the ARM processor 42, outputs DAC analog control signals, and dynamically corrects the 10MHz output frequency and synchronization phase of the rubidium atomic clock. Finally, it performs multi-channel phase synchronization shaping on the calibrated unified standard timing and distributes it to the multi-protocol signal output circuit 50 to ensure phase consistency across multiple outputs. In one embodiment, the FPGA timing unit 41 uses a domestically produced high-speed timing FPGA (XC7A series).

[0032] The ARM processor 42 serves as the upper-layer algorithm decision layer. It receives time-frequency deviation data uploaded by the FPGA timing unit 41, runs a Kalman filter algorithm to filter out random jitter and electromagnetic interference pulse noise from the satellite signal, eliminates abnormal timing jumps, and stabilizes the original satellite time reference. Based on the accurate time-frequency deviation after filtering and smoothing, it runs an incremental PID closed-loop control algorithm to calculate the rubidium atomic clock frequency and phase correction, which is then sent to the FPGA timing unit 41 for execution. It incorporates a dual-source intelligent time decision mechanism to monitor the satellite signal lock status and signal-to-noise ratio in real time, smoothly switching to the rubidium clock local reference in case of satellite failure, without any time step jumps throughout the process. It also coordinates the overall system business logic: NTP / PTP network protocol stack processing, human-machine interaction, overall system fault monitoring, redundant power supply / Ethernet redundancy switching management, and parameter storage. In one optional solution, the ARM processor 42 uses a quad-core industrial ARM processor.

[0033] By adopting a collaborative architecture of FPGA timing unit and ARM processor, the FPGA, as the underlying hardware execution layer, is responsible for high-speed parallel acquisition and hardware-level pulse processing, while the ARM, as the upper-level algorithm decision layer, is responsible for complex filtering and PID calculation. The two interact through a high-speed bus, with clear division of labor and closed-loop collaboration, balancing hardware real-time performance and algorithm flexibility.

[0034] Continue to refer to Figure 2 Optionally, the time synchronization and timekeeping server also includes: a redundant power supply circuit 60, which is connected to the satellite receiving circuit 10, the high-stability frequency standard circuit 20, the high-precision time and frequency measurement and discipline circuit 30, the main control circuit 40, and the multi-protocol signal output circuit 50. The redundant power supply circuit 60 provides dual independent power supplies for the satellite receiving circuit 10, the high-stability frequency standard circuit 20, the high-precision time and frequency measurement and discipline circuit 30, the main control circuit 40, and the multi-protocol signal output circuit 50, and automatically switches to the other power supply when one of the power supplies fails.

[0035] Specifically, the redundant power supply circuit 60 provides uninterrupted power supply for all functional circuits of the entire device, serving as the hardware foundation for the stable operation of the entire timing system. This circuit adopts a dual-path independent power supply architecture, monitoring the voltage, current, and operating status of both power supplies in real time, continuously supplying power to all core modules such as satellite reception, frequency standard output, time and frequency measurement and training, core control, and signal output. When any power supply fails, experiences a power outage, or exhibits abnormal voltage drop, the circuit can achieve seamless automatic redundancy switching, ensuring uninterrupted operation of the entire device. By employing a dual-path independent power supply architecture and real-time monitoring of the two power supplies, seamless automatic redundancy switching is achieved in the event of a single power supply failure, completely avoiding interruptions in timing acquisition, calibration, and output due to single power supply failures, ensuring 24 / 7 uninterrupted high-precision time synchronization and timekeeping operation of the equipment. In one embodiment, the redundant power supply circuit 60 uses two 220V AC to 12V DC isolated power supply modules with built-in fault detection and fast switching MOSFETs, achieving a power fault switching time of less than 100ns with no pulse loss.

[0036] The multi-protocol signal output circuit is also used to adapt and convert multiple standardized time and frequency signals and output multiple types of synchronization signals.

[0037] Specifically, the multi-protocol signal output circuit serves as the external output carrier for the high-precision timing signals of the entire device. It fully inherits the unified time and frequency reference calibrated and optimized by the main control circuit, achieving adaptation and stable output of multi-standard timing signals, including protocol conversion, NTP network timing, PTP precision timing, and other types of synchronization signals. This circuit is equipped with multiple independent industrial Ethernet ports, compatible with ERPS and MRP industrial ring network redundancy protocols, and monitors network link connectivity, data transmission status, and ring network topology status in real time. When a single network port link is disconnected, a network failure occurs, or the ring network topology changes, the circuit can complete the redundant link switching within ≤30ms, continuously and stably transmitting NTP and PTP network timing messages, effectively avoiding the problem of downstream terminal synchronization offline and timing loss caused by a single network link failure. The multi-protocol signal output circuit and the redundant power supply circuit form a dual redundancy guarantee of hardware power supply and network link, achieving a highly adaptable working state with accurate and stable internal timing and continuous and reliable external timing links.

[0038] By setting up a multi-protocol signal output circuit, the calibrated unified time and frequency reference can be converted into multiple types of synchronization signals such as NTP network time synchronization and PTP precision time synchronization for external output, meeting the time synchronization needs of different network devices.

[0039] Continue to refer to Figure 2 The high-precision time synchronization and timekeeping server's hardware circuitry includes: a satellite receiving circuit 10, a high-stability frequency standard circuit 20, a high-precision time and frequency measurement and discipline circuit 30, a core main control circuit 40, a multi-protocol signal output circuit 50, and a redundant power supply circuit 60. All of the above circuits are uniformly powered by the redundant power supply circuit 60, and are linked in a closed-loop manner according to the following: external time traceability, local reference backup, nanosecond-level time and frequency acquisition, FPGA+ARM collaborative algorithm processing, multi-system timing output, and network redundant transmission.

[0040] Optionally, the ARM processor is also used to filter the received time-frequency deviation data using a Kalman filter algorithm; The ARM processor is also used to utilize an incremental PID algorithm to calculate the frequency and phase correction of the reference frequency signal based on the filtered time-frequency deviation data and send it to the FPGA timing unit.

[0041] Specifically, the ARM processor receives the time-frequency deviation data uploaded by the FPGA timing unit, runs the Kalman filter algorithm to filter out random jitter and electromagnetic interference pulse noise of the satellite signal, eliminate abnormal timing jumps, and stabilize the original satellite time reference; based on the accurate time-frequency deviation after filtering and smoothing, it runs the incremental PID closed-loop control algorithm to calculate the rubidium atomic clock frequency and phase correction amount, and sends them to the FPGA timing unit for execution.

[0042] By employing Kalman filtering to optimally estimate the time-frequency deviation, random jitter of satellite signals and electromagnetic interference noise are filtered out, providing a smooth and reliable input for precise PID control. The incremental PID algorithm avoids the shortcomings of traditional positional PID, such as large overshoot and high steady-state error, effectively suppressing the second pulse output jitter to within 0.5ns, achieving nanosecond-level timekeeping accuracy.

[0043] Optionally, the ARM processor has a built-in dual-source intelligent time decision mechanism to monitor the lock status of satellite signals in real time, and to control the high-stability frequency standard circuit as the core timekeeping source when the satellite signal fails.

[0044] Specifically, the ARM processor incorporates a dual-source intelligent time decision-making mechanism, which monitors the satellite signal lock status and signal-to-noise ratio in real time. In the event of satellite failure, it smoothly switches to the rubidium clock local reference, using a highly stable frequency standard circuit as the core timekeeping source, with no time jumps throughout the process. The ARM processor monitors the satellite signal lock status and signal-to-noise ratio in real time. When the satellite signal is normal, it outputs a unified timing sequence with the satellite reference as the primary source and the rubidium clock as the secondary source. When the satellite loses lock, it dynamically reduces the weight of the satellite reference and smoothly switches to the rubidium clock local timekeeping reference, without any time jumps.

[0045] With a built-in dual-source intelligent time decision mechanism, the satellite signal lock status and signal-to-noise ratio are monitored in real time. When the satellite fails, it smoothly switches to the local rubidium clock reference without any time step jumps. This ensures that the equipment can maintain high-precision autonomous timekeeping for a long time after being disconnected from external satellite signals, making up for the lack of reliability of a single satellite timekeeping method.

[0046] Figure 3 This is an overall flowchart of a core algorithm provided according to an embodiment of the present invention, for reference. Figure 3 The core algorithm of this invention includes the following levels: Signal acquisition layer: Parallel acquisition of three time reference signals, namely GNSS dual-mode 1PPS second pulse / TOD time message signal, external IRIG-B time signal, and local 10MHz frequency standard divided 1PPS signal, to complete hardware synchronous sampling of multiple time sources.

[0047] High-precision time difference detection layer: Through the nanosecond-level phase measurement IP core of the FPGA timing unit, the reference time source is compared with the local frequency standard time phase, and the real-time phase deviation value and frequency deviation value with a resolution of 0.1ns are output.

[0048] Filtering and noise reduction layer: The real-time deviation sequence is input into the Kalman filter algorithm to filter out random jitter and industrial interference noise of satellite signals, and output the best estimate of the smooth and true frequency standard drift state.

[0049] Intelligent discipline adjustment layer: Based on the filtered and accurate deviation data, the frequency standard adjustment increment is dynamically calculated through an adaptive incremental PID algorithm, and the phase and frequency of the 10MHz frequency standard are corrected in real time to complete closed-loop discipline.

[0050] Loss-of-lock compensation layer: Real-time monitoring of time source status. When the satellite signal is locked normally, the discipline parameters and drift model are continuously updated iteratively. When the satellite signal is lost, the historical temperature-aging drift fitting model is called to dynamically compensate for the frequency standard drift error.

[0051] Multi-source smooth switching layer: Through a 1ms periodic state machine decision, based on signal priority, signal-to-noise ratio, and phase fluctuation, seamless switching between GNSS and local frequency standards is achieved without phase jumps.

[0052] Protocol output layer: The tamed high-precision time base is output as multiple standardized time signals (NTP and PTP) through hardware encoding to achieve high-precision time synchronization across the entire network.

[0053] The high-precision time synchronization and timekeeping server provided in this embodiment of the invention can achieve the following performance indicators: 1. Satellite lock-on synchronization accuracy: ≤5ns; 2. When all satellites are out of lock and offline, the error is ≤0.2μs for 24 hours and ≤0.8μs for 72 hours. 3. Phase consistency of multiple outputs: ≤2ns; 4. Power failure switching time: <100ns, no pulse loss; 5. Ethernet ring network fault switching time: ≤30ms; 6. Operating temperature range: -40℃ to 70℃ wide temperature range; 7. Output signal type: IRIG-B (DC), multiple 1PPS, 10MHz 8. Satellite receiving system: Compatible with both BeiDou-3 and GPS.

[0054] Figure 4 This is a flowchart of a time synchronization and timekeeping method provided according to an embodiment of the present invention, with reference to... Figure 4 In an embodiment of the present invention, a time synchronization and timekeeping method is also provided, applied to the time synchronization and timekeeping server in any embodiment of the present invention. The time synchronization and timekeeping method includes: S110: Receives satellite signals through satellite receiving circuit and outputs standard second pulses; outputs reference frequency signals through high-stability frequency standard circuit.

[0055] Specifically, when the equipment is powered on, the redundant power supply circuit supplies power to all modules; the satellite receiving circuit receives BeiDou + GPS satellite signals, demodulates and outputs 1PPS and TOD messages, which are then sent to the high-precision time and frequency measurement and discipline circuit; the high-stability frequency standard circuit, with its rubidium atomic clock, starts up upon power-on and stably outputs a 10MHz reference frequency.

[0056] S120: The high-precision time and frequency measurement and discipline circuit generates time and frequency deviation data from the collected second pulse and reference frequency signal, and sends it to the core main control circuit.

[0057] Specifically, the high-precision time and frequency measurement and discipline circuits acquire two timing signals in parallel: 1PPS from the satellite and 10MHz from the rubidium clock. The hardware captures nanosecond-level time and frequency deviation data and uploads it to the core main control circuit.

[0058] S130: The core main control circuit calculates the correction amount based on the time-frequency deviation data, outputs the control signal based on the correction amount to correct the reference frequency signal, and distributes the corrected reference frequency signal to the multi-protocol signal output circuit.

[0059] Specifically, the core control circuit uses a Kalman filter algorithm to process the time-frequency deviation data, filtering out satellite jitter and electromagnetic noise to obtain a smooth and stable satellite time reference. Based on the filtered deviation, an incremental PID algorithm is run to calculate the rubidium clock frequency and phase correction. Upon receiving correction commands, an analog control voltage is output to correct the 10MHz output frequency and synchronization phase of the rubidium atomic clock in real time, completing closed-loop discipline and continuously reducing the time deviation between the local frequency standard and the satellite standard. Finally, the calibrated and corrected unified high-precision time-frequency reference signal is multi-channel synchronously shaped and distributed to the multi-protocol signal output circuit.

[0060] S140: The multi-protocol signal output circuit outputs multiple standardized time and frequency signals based on the corrected reference frequency signal.

[0061] Specifically, the multi-protocol signal output circuit receives the calibrated, unified high-precision reference frequency signal distributed by the core main control circuit, completes signal level conversion, electrical isolation, and protocol encoding, and can synchronously and in parallel output signals including IRIG-B time code, NTP network time transmission messages, and IEEE1588 PTP precision time transmission signals.

[0062] Throughout the entire operation, the redundant power supply circuit monitors the status of both power supplies in real time. In the event of a single power supply failure, it seamlessly switches to the backup power supply, ensuring uninterrupted timing processing and signal output across the entire link. The Ethernet redundant circuit monitors the network link status in real time, and in the event of a link failure, it completes redundancy switching within ≤30ms, continuously and stably outputting network authorization messages.

[0063] Through dual-source closed-loop training of satellite time synchronization and local timekeeping, it achieves full-link timing guarantee of high-precision synchronous time synchronization when the satellite signal is normal and high-stability local timekeeping after the satellite loses lock; the multi-channel standardized time and frequency signal output is compatible with the synchronous access needs of various terminals in the power, rail transit, industrial automation and communication industries.

[0064] The time synchronization and timekeeping method provided in this embodiment of the invention is used to control the time synchronization and timekeeping server provided in any embodiment of the invention. Therefore, the time synchronization and timekeeping method provided in this embodiment of the invention also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0065] Optionally, the core main control circuit calculates the correction amount based on the time-frequency deviation data, outputs a control signal based on the correction amount to correct the reference frequency signal, and distributes the corrected reference frequency signal to the multi-protocol signal output circuit, including: The timing deviation data is received by the FPGA timing unit and uploaded to the ARM processor. The ARM processor calculates the correction amount based on the timing deviation data and sends it to the FPGA timing unit. The FPGA timing unit outputs a control signal based on the correction amount to correct the reference frequency signal, and then distributes the corrected reference frequency signal to the multi-protocol signal output circuit.

[0066] Specifically, the FPGA timing unit transmits the raw deviation data uplink to the ARM processor. The ARM processor runs a Kalman filter algorithm to remove satellite jitter and electromagnetic noise, obtaining a smooth and stable satellite time reference. Based on the filtered deviation, an incremental PID algorithm is run to calculate the rubidium clock frequency and phase correction, which are then sent back to the FPGA timing unit. The FPGA timing unit receives the correction command and outputs an analog control voltage to correct the 10MHz output frequency and synchronization phase of the rubidium atomic clock in real time, completing closed-loop discipline and continuously reducing the time deviation between the local frequency standard and the satellite standard.

[0067] The FPGA timing unit receives the raw deviation data in parallel hardware and completes pulse preprocessing and glitch filtering without software delay, ensuring the real-time performance and reliability of time and frequency acquisition. The ARM processor is responsible for complex algorithm calculations and overall system business logic coordination. This division of labor and collaborative architecture improves the overall performance and stability of the system.

[0068] Optionally, the ARM processor calculates the correction amount based on the time-frequency deviation data and sends it to the FPGA timing unit, including: The Kalman filter algorithm is used to filter the time-frequency deviation data to obtain the filtered time-frequency deviation data. Based on the filtered time-frequency deviation data and the incremental PID control algorithm, the frequency and phase correction of the reference frequency signal are calculated and sent to the FPGA timing unit.

[0069] Specifically, the Kalman filter removes random jitter and industrial interference noise from the satellite signal, outputting a smooth and accurate optimal estimate of the frequency standard drift state; the incremental PID dynamically calculates and adjusts the increment based on the precise deviation after filtering, correcting the phase and frequency of the frequency standard output frame by frame, achieving closed-loop dynamic discipline, and balancing dynamic response speed and steady-state accuracy.

[0070] To address the issues of large jitter, high steady-state error, and poor adaptability to satellite jumps in traditional single PID discipline algorithms, this invention proposes a Kalman filter + incremental PID dynamic discipline fusion algorithm. Simultaneously, a multi-source time reference state machine smooth switching algorithm is designed to ensure nanosecond-level time synchronization and microsecond-level long-term timekeeping accuracy from an algorithmic perspective.

[0071] Time-Frequency Deviation Kalman Filter Noise Reduction Algorithm: GNSS satellite signals are subject to random jitter due to weather, obstruction, and electromagnetic interference. Directly using these signals for training can lead to frequent fluctuations in the frequency standard phase. This invention employs Kalman filtering to optimally estimate the real-time phase deviation sequence, filtering out random noise and preserving the true frequency standard drift trend.

[0072] Optionally, the state equation of the Kalman filter algorithm is X(k)=A·X(k-1)+W(k), and the observation equation of the Kalman filter algorithm is Z(k)=H·X(k)+V(k); Where X(k) is the phase deviation and frequency deviation state quantity at time k, A is the state transition matrix; W(k) is the system process noise, Z(k) is the measured phase deviation observation value of the FPGA timing unit, H is the observation matrix, and V(k) is the observation noise.

[0073] Specifically, by iteratively updating the optimal estimate, filtering out random satellite jitter noise, and outputting smooth and accurate frequency standard drift data, it provides a reliable input for precise PID control and effectively suppresses 1PPS output jitter to within 0.5ns.

[0074] A complete Kalman filter mathematical model is constructed by using state equations and observation equations. By iteratively updating the optimal estimate, random satellite jitter noise is filtered out, and smooth and accurate frequency standard drift data is output, providing reliable input for precise PID control and ensuring nanosecond-level time synchronization accuracy from the algorithm level.

[0075] Incremental PID Intelligent Discipline Algorithm: This embodiment of the invention employs an incremental PID algorithm for dynamic closed-loop discipline of a 10MHz frequency standard, avoiding the shortcomings of traditional positional PID algorithms, such as large overshoot and high steady-state error. Based on the precise phase deviation after filtering, the frequency adjustment increment is calculated in real time, and the output phase and frequency of the frequency standard are corrected frame by frame.

[0076] The formula for calculating incremental PID is as follows: Δu(k)=Kp·[e(k)-e(k-1)]+Ki·e(k)+Kd·[e(k)-2e(k-1)+e(k-2)] Where e(k) is the phase deviation at the current time, e(k-1) is the phase deviation at the previous time, e(k-2) is the phase deviation at the time before that, Kp, Ki, and Kd are three dynamic adaptive parameters of the incremental PID control algorithm, which can automatically switch parameter levels according to the satellite signal quality, and Δu(k) is the frequency standard adjustment increment.

[0077] When the satellite signal is stable, the algorithm reduces the integral and derivative parameters to ensure steady-state accuracy; when the satellite signal fluctuates greatly, the proportional adjustment parameter is increased to quickly correct drift, balancing dynamic response speed and steady-state accuracy.

[0078] Multi-source time reference state machine smooth switching algorithm: This embodiment of the invention designs a two-level time source priority state machine: the first priority is GNSS dual-mode satellite, and the second priority is local high-stability frequency standard. The system completes a time source quality decision every 1ms, and the decision dimensions include signal validity status, phase deviation fluctuation, and signal-to-noise ratio.

[0079] The switching process adopts a pre-synchronous smooth transition mechanism: the time source that is about to fail will not be cut off immediately. The new time source completes phase pre-alignment in advance. The seamless switching is completed when the time phase deviation between the two channels approaches 0. The overall switching delay is ≤1ms, and there are no time jumps, phase changes, or output interruptions throughout the process.

[0080] Intelligent compensation timekeeping algorithm for lost-lock: When the GNSS satellite signal is completely lost and there is no external input, the system activates the historical parameter modeling compensation timekeeping mechanism. The equipment automatically records the temperature drift and aging drift curves during the long-term training process, establishes a drift fitting model, dynamically predicts the frequency standard drift based on the operating temperature and operating time, and performs phase compensation in real time, which greatly improves the long-term timekeeping accuracy after lost-lock, achieving an ultra-high stability timekeeping index of 500ns / 24h.

[0081] The high-precision time synchronization server and its method provided in this invention can be widely applied in industrial scenarios with high requirements for time accuracy and reliability, such as power system time synchronization, rail transit signal synchronization, industrial automation control, and communication base station clock synchronization. This invention employs a dual-redundancy architecture of BeiDou / GPS dual-mode satellite reception and rubidium atomic clock local time synchronization, combined with a Kalman filter and incremental PID fusion discipline algorithm, achieving nanosecond-level time synchronization accuracy and microsecond-level long-term time synchronization capability.

[0082] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A time synchronization and timekeeping server, characterized in that, include: Satellite receiving circuit, used to receive and demodulate satellite signals and output standard second pulse; High-stability frequency reference circuit, used to output a reference frequency signal; A high-precision time-frequency measurement and discipline circuit is connected to the satellite receiving circuit and the high-stability frequency standard circuit, respectively, and is used to generate time-frequency deviation data based on the collected second pulse and the reference frequency signal; The core main control circuit is connected to the high-precision time and frequency measurement and discipline circuit. The high-precision time and frequency measurement and discipline circuit is used to send the time and frequency deviation data to the core main control circuit. The core main control circuit is used to calculate the correction amount based on the time and frequency deviation data and output the control signal based on the correction amount to correct the reference frequency signal. A multi-protocol signal output circuit is connected to the core main control circuit. The core main control circuit is also used to distribute the corrected reference frequency signal to the multi-protocol signal output circuit. The multi-protocol signal output circuit is used to output multiple standardized time-frequency signals according to the corrected reference frequency signal.

2. The time synchronization and timekeeping server according to claim 1, characterized in that, The core main control circuit includes: an FPGA timing unit and an ARM processor, wherein the FPGA timing unit is connected to the ARM processor; The high-precision time-frequency measurement and discipline circuit is used to send the time-frequency deviation data to the FPGA timing unit. The FPGA timing unit is used to upload the time-frequency deviation data to the ARM processor. The ARM processor calculates the correction amount based on the time-frequency deviation data and sends it down to the FPGA timing unit. The FPGA timing unit is also used to output a control signal according to the correction amount to correct the reference frequency signal, and to distribute the corrected reference frequency signal to the multi-protocol signal output circuit.

3. The time synchronization and timekeeping server according to claim 1, characterized in that, Also includes: A redundant power supply circuit is connected to the satellite receiving circuit, the high-stability frequency standard circuit, the high-precision time and frequency measurement and discipline circuit, the main control circuit, and the multi-protocol signal output circuit. The redundant power supply circuit is used to provide dual independent power supplies for the satellite receiving circuit, the high-stability frequency standard circuit, the high-precision time and frequency measurement and discipline circuit, the main control circuit, and the multi-protocol signal output circuit, and automatically switches to the other power supply when one power supply fails.

4. The time synchronization and timekeeping server according to claim 2, characterized in that, The ARM processor is also used to filter the received time-frequency deviation data using the Kalman filter algorithm; The ARM processor is also used to calculate the frequency and phase correction of the reference frequency signal based on the filtered time-frequency deviation data using an incremental PID algorithm and send it to the FPGA timing unit.

5. The time synchronization and timekeeping server according to claim 4, characterized in that, The ARM processor has a built-in dual-source intelligent time decision mechanism, which is used to monitor the locking status of the satellite signal in real time, and control the high-stability frequency standard circuit as the core timekeeping source when the satellite signal fails.

6. A time synchronization and timekeeping method, applied to a time synchronization and timekeeping server as described in any one of claims 1-5, characterized in that, The time synchronization and timekeeping methods include: The satellite receiver circuit receives satellite signals and outputs standard second pulses, while the high-stability frequency standard circuit outputs a reference frequency signal. The high-precision time-frequency measurement and discipline circuit generates time-frequency deviation data from the collected second pulse and the reference frequency signal, and sends it to the core main control circuit. The core main control circuit calculates the correction amount based on the time-frequency deviation data, outputs a control signal based on the correction amount to correct the reference frequency signal, and distributes the corrected reference frequency signal to the multi-protocol signal output circuit. The multi-protocol signal output circuit outputs multiple standardized time-frequency signals based on the corrected reference frequency signal.

7. The time synchronization and timekeeping method according to claim 6, characterized in that, The step of calculating a correction amount based on the time-frequency deviation data through the core main control circuit, outputting a control signal based on the correction amount to correct the reference frequency signal, and distributing the corrected reference frequency signal to the multi-protocol signal output circuit includes: The time-frequency deviation data is received by the FPGA timing unit and uploaded to the ARM processor. The ARM processor calculates the correction amount based on the time-frequency deviation data and sends it to the FPGA timing unit. The FPGA timing unit outputs a control signal according to the correction amount to correct the reference frequency signal, and then distributes the corrected reference frequency signal to the multi-protocol signal output circuit.

8. The time synchronization and timekeeping method according to claim 7, characterized in that, The step of calculating the correction amount based on the time-frequency deviation data using the ARM processor and sending it to the FPGA timing unit includes: The time-frequency deviation data is filtered using the Kalman filter algorithm to obtain filtered time-frequency deviation data. Based on the filtered time-frequency deviation data and the incremental PID control algorithm, the frequency and phase correction of the reference frequency signal are calculated and sent to the FPGA timing unit.

9. The time synchronization and timekeeping method according to claim 8, characterized in that, The state equation of the Kalman filter algorithm is X(k)=A·X(k-1)+W(k), and the observation equation of the Kalman filter algorithm is Z(k)=H·X(k)+V(k); Where X(k) is the phase deviation and frequency deviation state quantity at time k, A is the state transition matrix; W(k) is the system process noise, Z(k) is the measured phase deviation observation value of the FPGA timing unit, H is the observation matrix, and V(k) is the observation noise.

Images