An embodied intelligent control method and system based on an AI accelerator supporting multi-operator generalization and intelligent search, a terminal, and a storage medium

Abstract

The application discloses a kind of based on supporting multi-operator generalization and intelligent search AI accelerator somatic intelligent control method, system, terminal and storage medium, the method includes: according to input uniform framework, input form uniformity is carried out to somatic perception operator, and input operator is obtained;According to input operator, initial operator mapping configuration is obtained by optimal operator mapping search;According to initial operator mapping configuration and input operator, simulation is carried out, and task period and resource utilization are obtained, and according to task period and resource utilization, target operator mapping configuration is obtained by optimal operator mapping iterative search processing, and target control signal is obtained by action control signal generation processing according to target operator mapping configuration and target instruction.The application converts different types of operators into unified simulation input, searches the optimal operator mapping configuration according to the simulation input, and optimizes the search strategy according to the simulation results, improving the action data generation efficiency of somatic intelligence.

Description

Technical Field

[0001] This invention relates to the field of autonomous driving technology, and in particular to an embodied intelligent control method, system, terminal, and computer-readable storage medium based on an AI accelerator that supports multi-operator generalization and intelligent search. Background Technology

[0002] Embodied intelligence (such as robots and robotic arms) typically generates motion data through embodied intelligence models. To meet real-time and energy efficiency requirements, the industry commonly uses AI accelerators to accelerate the training and inference of embodied intelligence models. To improve the acceleration effect of AI accelerators, it is necessary to select the set of operator mapping configurations that best optimize the AI ​​accelerator's performance.

[0003] Existing AI accelerator-based embodied intelligence control methods typically perform an exhaustive search in a high-dimensional design space to obtain the optimal operator mapping configuration, and then use the optimal operator mapping configuration to accelerate the embodied intelligence model through an AI accelerator, thereby improving the efficiency of embodied intelligence action data generation. However, this AI accelerator-based embodied intelligence control method relies on exhaustive search, and the search overhead increases sharply with the parameter scale, leading to a decrease in the acceleration effect of the AI ​​accelerator and a reduction in the efficiency of embodied intelligence action data generation.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] The main objective of this invention is to provide an embodied intelligence control method, system, terminal, and computer-readable storage medium based on an AI accelerator that supports multi-operator generalization and intelligent search. This invention aims to solve the problems in existing embodied intelligence control methods based on AI accelerators, which rely on exhaustive search. The search overhead increases dramatically with the parameter scale, leading to a decrease in the acceleration effect of the AI ​​accelerator and a reduction in the efficiency of embodied intelligence action data generation.

[0006] To achieve the above objectives, the present invention provides an embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search, comprising the following steps: Obtain a preset configuration, perform input framework generation processing based on the preset configuration to obtain a unified input framework, and obtain an embodied perception operator. Perform input form unification processing on the embodied perception operator based on the unified input framework to obtain an input operator. Based on the input operator, perform an optimal operator mapping search process to obtain the initial operator mapping configuration; Simulation is performed based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate. Then, the search strategy is updated based on the task cycle and the resource utilization rate to obtain the target search strategy. Based on the target search strategy and the input operator, an optimal operator mapping iterative search process is performed to obtain the target operator mapping configuration, obtain the target instruction, determine the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, and through the AI ​​accelerator and the built-in embodied intelligence model, perform action control signal generation processing based on the target operator mapping configuration and the target instruction to obtain the target control signal, and control the target embodied intelligence to complete the physical action based on the target control signal.

[0007] Optionally, in the embodied intelligent control method based on an AI accelerator that supports multi-operator generalization and intelligent search, the preset configuration includes tensor definition information and loop information; The process of obtaining a preset configuration, generating an input framework based on the preset configuration to obtain a unified input framework, obtaining an embodied perception operator, and performing input form unification processing on the embodied perception operator based on the unified input framework to obtain an input operator specifically includes: Obtain the tensor definition information, perform tensor shape definition processing based on the tensor definition information, and obtain the tensor shape; Obtain the loop information, perform loop structure definition processing based on the loop information, and obtain the loop structure; Based on the tensor definition information and the loop information, data access relationship definition processing and data reuse feature definition processing are performed to obtain data access relationship and data reuse feature; A unified input framework is obtained based on the tensor shape, the loop structure, the data access relationship, and the data reuse feature. An embodied perception operator is then obtained. The embodied perception operator is subjected to unified input form processing based on the unified input framework to obtain the input operator.

[0008] Optionally, the embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search, wherein the step of performing optimal operator mapping search processing based on the input operator to obtain an initial operator mapping configuration specifically includes: Based on the computational flow graph of the input operator, a mapping space generation process is performed to obtain a candidate mapping space; Obtain the historical record database, perform similar record filtering processing on the historical record database according to the input operator, and if similar records are obtained, use the historical operator mapping configuration corresponding to the similar records as the initial operator mapping configuration; If no similar record is obtained, random sampling is performed in the candidate mapping space to obtain multiple random mapping configurations, and a Bayesian optimized proxy model is determined. The optimal configuration selection process is performed on the multiple random mapping configurations through the Bayesian optimized proxy model to obtain the optimal operator mapping configuration. The optimal operator mapping configuration is used as the initial operator mapping configuration, and the optimal operator mapping configuration and the input operator are written into the historical record database.

[0009] Optionally, the embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search, wherein the step of acquiring a historical record database, performing similar record filtering processing on the historical record database according to the input operator, and if similar records are obtained, using the historical operator mapping configuration corresponding to the similar records as the initial operator mapping configuration, specifically includes: Obtain the historical record database, and perform type matching processing based on the operator type of the input operator and multiple historical records in the historical record database to obtain multiple type matching degrees; Tensor similarity is calculated based on the tensor dimension of the input operator and multiple historical records to obtain multiple tensor similarities; Based on the hardware parameters of the input operator and multiple historical records, normalized distance calculation is performed to obtain multiple parameter differences; Obtain the scoring weights, and sum the multiple type matching degrees, multiple tensor similarities, and multiple parameter differences according to the scoring weights to obtain multiple similarity scores; The maximum value of multiple similarity scores is filtered to obtain the target similarity, and a similarity threshold is obtained. If the target similarity is greater than the similarity threshold, the target historical record corresponding to the target similarity is taken as the similar record, and the target historical record corresponding to the target similarity is configured as the initial operator mapping configuration.

[0010] Optionally, the embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search, wherein the step of performing simulation based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization, and performing search strategy update processing based on the task cycle and the resource utilization to obtain the target search strategy, specifically includes: Obtain the core node set, and perform topology graph construction processing based on the core node set to obtain the core topology graph; The input operator is partitioned to obtain multiple tensor blocks, and a mapping process is performed on the multiple tensor blocks and multiple cores in the core node set to obtain the core mapping relationship. Based on the core-particle mapping relationship, communication event construction processing is performed to obtain multiple communication events, and based on the multiple communication events and the core-particle topology map, path generation processing is performed to obtain multiple communication paths; Based on multiple communication events and multiple communication paths, periodic calculation and resource statistics are performed to obtain the task cycle and resource utilization rate. Then, based on the task cycle and the resource utilization rate, the search strategy is updated to obtain the target search strategy.

[0011] Optionally, the embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search, wherein the step of updating the search strategy according to the task cycle and the resource utilization rate to obtain the target search strategy specifically includes: Based on the task cycle and resource utilization rate, a bottleneck judgment is performed to obtain the first analysis result; Based on the resource utilization rate, a memory access bottleneck is identified and processed to obtain the second analysis result; Based on the task cycle, a communication bottleneck is identified and processed to obtain the third analysis result; Based on the task cycle, a synchronous waiting judgment process is performed to obtain the fourth analysis result; Based on the first analysis result, the second analysis result, the third analysis result, and the fourth analysis result, an optimization strategy is constructed to obtain the target search strategy.

[0012] Optionally, the embodied intelligence control method based on an AI accelerator supporting multi-operator generalization and intelligent search, wherein the step of performing optimal operator mapping iterative search processing according to the target search strategy and the input operator to obtain the target operator mapping configuration, acquiring the target instruction, determining the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, and using the AI ​​accelerator and the built-in embodied intelligence model to perform action control signal generation processing according to the target operator mapping configuration and the target instruction to obtain the target control signal, and controlling the target embodied intelligence to complete physical actions according to the target control signal, specifically includes: Obtain a preset number of iterations, perform optimal operator mapping iterative search processing according to the target search strategy and the input operator, and obtain the target operator mapping configuration when the number of iterations equals the preset number of iterations. The AI ​​accelerator and the built-in embodied intelligence model of the target embodied intelligence are determined. The built-in embodied intelligence model is deployed and processed by the AI ​​accelerator according to the target operator mapping configuration to obtain the target embodied intelligence model. The target instruction is obtained, and the target embodied intelligence model performs signal generation and processing based on the target instruction to obtain the target control signal. The target embodied intelligence is then controlled to complete physical actions based on the target control signal.

[0013] Furthermore, to achieve the above objectives, the present invention also provides an embodied intelligent control system based on an AI accelerator supporting multi-operator generalization and intelligent search, wherein the embodied intelligent control system based on an AI accelerator supporting multi-operator generalization and intelligent search includes: The operator unification module is used to obtain a preset configuration, perform input framework generation processing according to the preset configuration to obtain a unified input framework, obtain an embodied perception operator, and perform input form unification processing on the embodied perception operator according to the unified input framework to obtain an input operator. A configuration search module is used to perform optimal operator mapping search processing based on the input operator to obtain the initial operator mapping configuration; The simulation module is used to perform simulation based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate, and to perform search strategy update processing based on the task cycle and resource utilization rate to obtain the target search strategy; The action generation module is used to perform optimal operator mapping iterative search processing according to the target search strategy and the input operator to obtain the target operator mapping configuration, acquire the target instruction, determine the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, and through the AI ​​accelerator and the built-in embodied intelligence model, perform action control signal generation processing according to the target operator mapping configuration and the target instruction to obtain the target control signal, and control the target embodied intelligence to complete the physical action according to the target control signal.

[0014] Furthermore, to achieve the above objectives, the present invention also provides a terminal, wherein the terminal includes: a memory, a processor, and an embodied intelligent control program based on an AI accelerator supporting multi-operator generalization and intelligent search, stored in the memory and executable on the processor. When the embodied intelligent control program based on the AI ​​accelerator supporting multi-operator generalization and intelligent search is executed by the processor, it implements the steps of the embodied intelligent control method based on the AI ​​accelerator supporting multi-operator generalization and intelligent search as described above.

[0015] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores an embodied intelligent control program based on an AI accelerator supporting multi-operator generalization and intelligent search, and when the embodied intelligent control program based on the AI ​​accelerator supporting multi-operator generalization and intelligent search is executed by a processor, it implements the steps of the embodied intelligent control method based on the AI ​​accelerator supporting multi-operator generalization and intelligent search as described above.

[0016] In this invention, a preset configuration is obtained; an input framework generation process is performed based on the preset configuration to obtain a unified input framework; an embodied perception operator is obtained; the input form of the embodied perception operator is unified based on the unified input framework to obtain an input operator; an optimal operator mapping search process is performed based on the input operator to obtain an initial operator mapping configuration; simulation is performed based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate; a search strategy update process is performed based on the task cycle and the resource utilization rate to obtain a target search strategy; an optimal operator mapping iterative search process is performed based on the target search strategy and the input operator to obtain a target operator mapping configuration; a target instruction is obtained; an AI accelerator and a built-in embodied intelligence model of the target embodied intelligence are determined; and action control signal generation processing is performed based on the AI ​​accelerator and the built-in embodied intelligence model, based on the target operator mapping configuration and the target instruction, to obtain a target control signal; and the target embodied intelligence is controlled to complete physical actions based on the target control signal. This invention converts different types of operators into a unified simulation input, searches for the optimal operator mapping configuration based on the simulation input, and optimizes the search strategy based on the simulation results to obtain the target operator mapping configuration for accelerating embodied intelligence models, thereby improving the efficiency of action data generation for embodied intelligence. Attached Figure Description

[0017] Figure 1 This is a flowchart of a preferred embodiment of the embodied intelligent control method of the present invention based on an AI accelerator that supports multi-operator generalization and intelligent search; Figure 2 This is a system architecture diagram of the embodied intelligent control method of the AI ​​accelerator that supports multi-operator generalization and intelligent search, based on the present invention. Figure 3 This is a flowchart of the Bayesian optimization search process of the embodied intelligent control method of the AI ​​accelerator that supports multi-operator generalization and intelligent search in this invention. Figure 4 This is a schematic diagram of reinforcement learning search based on the embodied intelligent control method of the AI ​​accelerator that supports multi-operator generalization and intelligent search in this invention; Figure 5 This is a flowchart of the multi-core interconnection and mapping extension process of the embodied intelligent control method for AI accelerators that support multi-operator generalization and intelligent search, as presented in this invention. Figure 6 This is a schematic diagram of the tile-level pipeline and double-buffered model cycle estimation based on the embodied intelligent control method of AI accelerators that support multi-operator generalization and intelligent search, according to the present invention. Figure 7 This is a hierarchical simulation flowchart of the embodied intelligent control method of the AI ​​accelerator that supports multi-operator generalization and intelligent search, based on the present invention. Figure 8 This is a structural diagram of a preferred embodiment of the embodied intelligent control system of the present invention based on an AI accelerator that supports multi-operator generalization and intelligent search; Figure 9 This is a structural diagram of a preferred embodiment of the terminal of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] Embodied intelligence (such as robots and robotic arms) typically generates motion data through embodied intelligence models. To meet real-time and energy efficiency requirements, the industry commonly uses AI accelerators to accelerate the training and inference of embodied intelligence models. To improve the acceleration effect of AI accelerators, it is necessary to select the set of operator mapping configurations that best optimize the AI ​​accelerator's performance.

[0020] Existing AI accelerator-based embodied intelligence control methods typically perform an exhaustive search in a high-dimensional design space to obtain the optimal operator mapping configuration, and then use the optimal operator mapping configuration to accelerate the embodied intelligence model through an AI accelerator, thereby improving the efficiency of embodied intelligence action data generation. However, this AI accelerator-based embodied intelligence control method relies on exhaustive search, and the search overhead increases sharply with the parameter scale, leading to a decrease in the acceleration effect of the AI ​​accelerator and a reduction in the efficiency of embodied intelligence action data generation.

[0021] To address the aforementioned issues, this invention proposes an embodied intelligence control method based on an AI accelerator that supports multi-operator generalization and intelligent search. This method converts different types of operators into a unified simulation input, searches for the optimal operator mapping configuration based on the simulation input, and optimizes the search strategy based on the simulation results to obtain the target operator mapping configuration for accelerating the embodied intelligence model, thereby improving the efficiency of action data generation for embodied intelligence.

[0022] The embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search, as described in the preferred embodiment of the present invention, is as follows: Figure 1 As shown, the embodied intelligent control method based on an AI accelerator that supports multi-operator generalization and intelligent search includes the following steps: Step S10: Obtain a preset configuration, perform input framework generation processing according to the preset configuration to obtain a unified input framework, and obtain an embodied perception operator. Perform input form unification processing on the embodied perception operator according to the unified input framework to obtain the input operator.

[0023] Specifically, the preset configuration includes tensor definition information and loop information; the tensor definition information is obtained, and tensor shape definition processing is performed based on the tensor definition information to obtain a tensor shape; the loop information is obtained, and loop structure definition processing is performed based on the loop information to obtain a loop structure; data access relationship definition processing and data reuse feature definition processing are performed based on the tensor definition information and the loop information to obtain data access relationship and data reuse feature.

[0024] like Figure 2 As shown, the present invention sets up a hardware abstraction layer configuration module, which is used to receive, parse and uniformly represent the hardware parameters of the target AI accelerator, and provide a unified hardware constraint input for other modules.

[0025] The hardware abstraction layer configuration module includes the following parameters: Storage tier parameters: storage capacity, bandwidth, and access latency at each level; Computational unit parameters: computational unit type (pulsating array, vector unit), matrix unit size, media access control (MAC) computing power, vector unit throughput; Interconnection and topology parameters: number of cores, core type, interconnection topology between cores, link bandwidth and link delay; Clock and data type parameters: operating clock frequency, data type.

[0026] like Figure 2 As shown, this invention sets up an operator library and an operator generalization description module. The operator generalization description module is used to convert different types of operators such as matrix multiplication, convolution, and attention in the operator library into a unified analyzable, simulable, and searchable operator representation. This module defines a unified computational flow graph (UCFG) to define the tensor shape, loop structure, data access relationship, and data reuse characteristics of operators, so that different operators can be uniformly processed by subsequent multi-level storage hierarchy simulators and intelligent search optimizers.

[0027] The unified computation flow graph includes the following information: Tensor definition information: gives the shape and data type of the input tensor, output tensor, and intermediate tensor of the operator; for example, matrix multiplication includes input matrix A[M, K], input matrix B[K, N], and output matrix C[M, N]; convolution includes input feature map, convolution kernel weights, and output feature map; attention operator includes Q, K, V, attention score matrix, normalized (Softmax) intermediate result, and output tensor.

[0028] Calculate loop description information: Define the loop variables, loop boundaries, and loop nesting relationships of operators; for example, matrix multiplication can be represented by three loop dimensions: M, N, and K; convolution can be represented by batch, output channel, output spatial location, input channel, and convolution kernel spatial dimensions; attention can be represented by loop dimensions such as batch size, sequence length, hidden layer dimension, and number of heads.

[0029] Tensor access relationships: Specifies the index relationship between each tensor element and the loop variable, used to determine which data will be accessed repeatedly when different loop dimensions change. For example, in matrix multiplication, A[m,k] is determined by m and k, B[k,n] by k and n, and C[m,n] by m and n; this access relationship is used to subsequently estimate the amount of data moved from input data, weight data, output parts, and intermediate tensors.

[0030] Data reuse characteristics: Reflecting the reuse relationship of tensors in different cyclic dimensions, including input reuse, weight reuse, output part reuse, and intermediate tensor reuse; for example, in matrix multiplication, A[m,k] can be reused in different n dimensions, B[k,n] can be reused in different m dimensions, and C[m,n] can be reused in different k-dimensional accumulation processes.

[0031] Working set and access volume estimation rules: Based on tensor access relationships and reuse characteristics, estimation rules for working set size and data access volume are generated; for example, for matrix multiplication C=A×B, its basic working set can be represented as WorkSet=M×K+K×N+M×N, where M×K represents the data size of input matrix A, K×N represents the data size of input matrix B, and M×N represents the data size of output matrix C or part of the sum.

[0032] Operator Dimension Mapping: For operators reducible to matrix multiplication, the module provides their equivalent dimension mapping for easier processing by the subsequent simulator. For example, the convolution operator can be mapped as follows: M = C_out; N = H_out × W_out; K = C_in × K_H × K_W; Where C_out represents the number of output channels, H_out×W_out represents the number of spatial locations of the output feature map, and C_in×K_H×K_W represents the input channels and convolution kernel unrolling dimension required for each output element. The platform can also choose a direct convolution model as needed without performing convolution kernel unrolling.

[0033] After determining the information contained in the unified computation flow graph, the definitions of operator tensor shape, loop structure, data access relationship and data reuse characteristics are completed, resulting in a unified simulator input framework.

[0034] Furthermore, a unified input framework is obtained based on the tensor shape, the loop structure, the data access relationship, and the data reuse feature, and an embodied perception operator is obtained. The embodied perception operator is then subjected to unified input form processing based on the unified input framework to obtain the input operator.

[0035] The embodied awareness operators used for neural network training are packaged into a structured data form according to a previously defined unified computational flow graph and input into the simulator. This structured data form includes the operator's tensor definitions, loop structures, access relationships, reusable features, and dimensionality mappings, but does not include searchable parameters such as specific partitioning, sorting, and data flow (which are generated, evaluated, and selected in subsequent steps). This design allows different operators to be processed by the simulator within the same framework using the same interface, thereby improving the consistency and scalability of multi-operator modeling.

[0036] Step S20: Perform optimal operator mapping search processing based on the input operator to obtain the initial operator mapping configuration.

[0037] Specifically, a mapping space generation process is performed based on the computational flow graph of the input operator to obtain a candidate mapping space; a historical record database is obtained, and type matching processing is performed based on the operator type of the input operator and multiple historical records in the historical record database to obtain multiple type matching degrees; tensor similarity calculation processing is performed based on the tensor dimension of the input operator and multiple historical records to obtain multiple tensor similarities; normalized distance calculation processing is performed based on the hardware parameters of the input operator and multiple historical records to obtain multiple parameter differences; a scoring weight is obtained, and a weighted sum is performed on the multiple type matching degrees, multiple tensor similarities, and multiple parameter differences based on the scoring weight to obtain multiple similarity scores.

[0038] like Figure 2 As shown, the present invention sets up an intelligent search engine (also called an intelligent search optimizer), which is used to automatically find the operator mapping configuration with optimal or near-optimal performance in a large-scale mapping design space. The operator mapping configuration includes, but is not limited to, storage block parameters at all levels, loop execution order, data flow mode, parallel partitioning method, and prefetch or write-back strategy.

[0039] like Figure 2As shown, this invention also includes a multi-level memory hierarchy simulator, which comprises a main simulator, an L2 block simulator, an L1 block simulator, and an L0 block simulator. The multi-level memory hierarchy simulator is used to estimate the execution cycle, data migration amount, bandwidth utilization, computing array utilization, and cross-core communication overhead of operators, given hardware parameters, a unified operator computation flow graph, and candidate operator mapping configuration. This module is the core of the intelligent search optimizer's performance evaluation, used for rapid simulation of different block parameters, loop order, data flow patterns, and multi-core mapping strategies.

[0040] When a new search task is received, the similarity between the task and historical tasks is first calculated. The similarity can be calculated based on features such as operator type, tensor dimension, hardware storage capacity, bandwidth, array size, etc. If a highly similar historical task is found, the historical optimal configuration can be directly reused.

[0041] Specifically, features such as operator type, tensor shape, and hardware parameters of the new task are extracted to construct a feature vector; historical cache records are traversed to calculate the weighted similarity score between the new task and each historical record.

[0042] For operator type matching, the highest weight is assigned. For tensor dimension differences, the similarity is calculated as the ratio of the current operator dimension to the operator dimension in the history. For hardware parameter differences (storage capacity, bandwidth, array size), the normalized distance is calculated. Different weights are assigned to operator type, tensor dimension differences, and hardware parameter differences, and the results are weighted and summed to obtain a comprehensive score. Records with a comprehensive score exceeding a preset threshold (e.g., 0.85) are judged as highly similar tasks.

[0043] Furthermore, the maximum value of the multiple similarity scores is filtered to obtain the target similarity, and a similarity threshold is obtained. If the target similarity is greater than the similarity threshold, the target historical record corresponding to the target similarity is taken as the similar record, and the target historical record corresponding to the target similarity is configured as the initial operator mapping configuration.

[0044] If multiple highly similar historical tasks exist, the historical task with the highest score is selected, and its optimal mapping configuration is directly extracted as the initial candidate configuration for the current task. This configuration includes storage block parameters at each level, loop execution order, data flow pattern, and parallel partitioning strategy. This configuration is input into a multi-level storage hierarchy simulator for rapid verification. If the verification passes and the performance meets expectations, it is directly output as the recommended result; if the verification performance degrades (due to minor differences between tasks), the historical optimal configuration is used as the starting point for subsequent searches for fine-tuning.

[0045] Furthermore, if no similar records are obtained, random sampling is performed in the candidate mapping space to obtain multiple random mapping configurations, and a Bayesian optimized surrogate model is determined. The Bayesian optimized surrogate model is used to perform optimal configuration selection processing on the multiple random mapping configurations to obtain the optimal operator mapping configuration. The optimal operator mapping configuration is used as the initial operator mapping configuration, and the optimal operator mapping configuration and the input operator are written into the historical record database.

[0046] If there is no single historical task with high similarity, but there are multiple historical tasks with moderate similarity (e.g., similarity between 0.6 and 0.85), extract the top k high-performance configurations with moderate similarity from each historical task and combine them to form an initial sample set. Use this sample set as the initial training data for subsequent searches, so that the search engine has a certain performance prediction capability at the beginning of the search and avoids random sampling from scratch.

[0047] In one implementation, the intelligent search optimizer employs Bayesian optimization to search the mapped configuration space. Bayesian optimization is suitable for scenarios with high simulation costs, numerous search space dimensions, and objective functions that are difficult to analytically differentiate. This invention treats each complete simulation as a costly objective function evaluation, and reduces the number of actual simulations by constructing a surrogate model to predict the performance of different configurations.

[0048] First, a candidate mapping space is generated based on the computational flow graph of the input operator. Then, the surrogate model (Gaussian process, random forest, or gradient boosting tree) is pre-trained or transferred using the selected historical simulation data (including configuration parameters and the corresponding number of simulation cycles). Specifically, the difference between the configuration parameter distribution of the historical data and the candidate mapping space of the current task is normalized and aligned. The aligned historical data is then used to update the prior distribution or initial parameters of the surrogate model, enabling the surrogate model to converge faster in the search space of the current task.

[0049] Next, as follows Figure 3As shown, initial sampling is performed using random sampling or sampling based on preset rules; the simulator is invoked to obtain the real period; a surrogate model is trained using the sampled configurations and their simulation results; based on the predicted mean and uncertainty output by the surrogate model, the acquisition function value is calculated, and the acquisition function can be selected from EI (Expected Improvement), UCB (Upper Confidence Bound), and PI (Probability of Improvement); one or more candidate configurations with the largest acquisition function value are selected as the simulation objects for the next round; the candidate configurations are input into the simulator to obtain the real simulation results, and these results are added to the historical sample set; the selection process is repeated until the preset number of simulations, search time budget, or convergence condition is reached, and the mapping configuration with the best performance during the selection process is output as the optimal operator mapping configuration.

[0050] In another embodiment, the present invention can also employ reinforcement learning methods for design space exploration; the present invention models the mapping configuration search process as a sequential decision problem. The reinforcement learning agent progressively selects configuration parameters, a simulator acts as the environment to evaluate the performance of the complete configuration, and returns a reward signal based on the evaluation results.

[0051] like Figure 4 As shown, the reinforcement learning model uses state S to represent the currently determined partial mapping configuration, the set of parameters to be selected, operator shape features, hardware resource features, and historical search result features; action A represents selecting a configuration value from the candidate parameter set, such as selecting the block size of a certain level of storage, selecting the loop order, selecting the data flow mode, etc. During training, the agent interacts with the simulator in multiple rounds. The reinforcement learning algorithm can adopt DQN (Deep Q-Network), PPO (Proximal Policy Optimization), Actor-Critic, or other policy optimization methods. After training, the policy network can quickly generate candidate mapping configurations for new operator shapes and hardware parameters. In each round, the agent selects each configuration parameter in sequence, forms a complete configuration, and then calls the simulator to obtain performance results. The reward R is calculated from the simulation results, usually set as a negative value of the number of execution cycles, or set as a normalized combination of indicators such as throughput, energy efficiency, and computational utilization. The policy network parameters are updated according to the reward R. Compared to performing a large-scale search every time, reinforcement learning models can reuse the experience gained during previous training, reducing configuration generation time to milliseconds or even microseconds.

[0052] After completing the search for the current task, the operator type, tensor shape, hardware parameters, search space definition, optimal mapping configuration obtained from the search, and the corresponding number of simulation cycles and utilization metrics are stored in the historical cache database. If the same or highly similar task record already exists in the cache, it is updated to the configuration with better performance to ensure that the cache always retains the optimal result. At the same time, the cached data is periodically deduplicated and compressed to avoid the decrease in retrieval efficiency caused by redundant records.

[0053] Through the intelligent search engine, this invention can quickly obtain high-performance mapping schemes without exhausting the entire design space, thereby reducing the search time for AI accelerator operator mapping configuration from the traditional hours or days to minutes, and improving the stability and portability of search results.

[0054] Step S30: Perform simulation based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate, and perform search strategy update processing based on the task cycle and resource utilization rate to obtain the target search strategy.

[0055] Specifically, a set of core node nodes is obtained; a topology graph is constructed based on the core node set to obtain a core topology graph; the input operator is partitioned to obtain multiple tensor blocks; a mapping relationship is constructed based on the multiple tensor blocks and multiple core nodes in the core node set to obtain a core mapping relationship; a communication event is constructed based on the core mapping relationship to obtain multiple communication events; a path generation process is performed based on the multiple communication events and the core topology graph to obtain multiple communication paths; and periodic calculation and resource statistics are performed based on the multiple communication events and multiple communication paths to obtain the task cycle and resource utilization rate.

[0056] like Figure 2 As shown, this invention includes a multi-chiplet interconnect extension module. This module is used for structured modeling of chiplet architectures, 2.5D / 3D packaging architectures, and multi-computing chiplet collaborative execution scenarios. It also provides the multi-level memory hierarchy simulator and intelligent search optimizer with the topology, communication events, and mapping constraints required for cross-chiplet execution. The multi-chiplet interconnect extension module describes the hardware topology, tensor partitioning method, communication event generation rules, routing model, and search space constraints of the multi-chiplet system, establishing a multi-chiplet communication and mapping model. Upon receiving this information, the multi-level memory hierarchy simulator calculates the execution cycle, communication cycle, and synchronization wait time corresponding to the configuration.

[0057] like Figure 5As shown, the present invention selects the initial operator mapping configuration through an intelligent search optimizer; the multi-core interconnect extension module performs hardware topology modeling, tensor partitioning and mapping, communication event generation, and routing and dependency modeling according to the initial operator mapping configuration; the modeling information of the multi-core interconnect extension module is sent to the multi-level storage hierarchy simulator, and simulation is performed in combination with the initial operator mapping configuration. The simulation results are used to feed back to the intelligent search optimizer to optimize the search scheme.

[0058] When the target hardware is a chiplet or multi-chiplet architecture, the multi-level memory hierarchy simulator works in conjunction with the multi-chiplet interconnect extension module. The simulator not only calculates the memory access and computation cycles within a single chiplet, but also calculates the parallel execution process of the multi-chiplet based on the tensor partitioning method and the mapping relationship from tile to chiplet. Here, a tile represents a sub-tensor block obtained by cutting a large tensor along one or more dimensions, which is the basic data unit that can be accommodated and processed at one time in each level of the memory hierarchy.

[0059] First, the multi-core system is abstracted as a topology graph G=(V,E), where V represents the set of core nodes, and the node types include computing cores, storage cores, cache cores, and I / O cores, etc.; E represents the set of interconnection links between cores.

[0060] Each kernel node should include at least the following attributes: kernel type, local storage capacity, local computing power, supported data flow patterns, supported communication types, and the set of links with neighboring kernels. Each interconnect link should include at least the following attributes: link bandwidth, link base latency, link direction, whether the link supports bidirectional communication, currently available bandwidth of the link, and routing constraints or link priority.

[0061] The multi-core interconnect extension module supports partitioning operator tensors according to different dimensions and mapping them to multiple cores for execution, for example: For matrix multiplication C=A×B, it can be partitioned along M, N or K dimensions; Convolution operators can be partitioned along the batch dimension, output channel dimension, spatial dimension, or input channel dimension. Attention operators can be partitioned along the batch / head dimension, the sequence dimension, or the hidden dimension.

[0062] The module generates a tile-to-chiplet mapping based on the partitioning method. For each chiplet, the module records the range of the tensor block tile it is responsible for, the required input block, the required weight block, the intermediate result block, and the output block. This mapping serves as the input for subsequent multi-level memory hierarchy simulator calculations of local memory access, computation cycles, and cross-chiplet communication cycles.

[0063] Based on the tensor partitioning method and core mapping relationship, a cross-core communication event set CommEvent={source, destination, data_type, data_size, route_policy, dependency} is automatically generated. Here, source represents the source core, destination represents the target core or set of target cores, data_type represents the communication data type (e.g., input block, weight block, intermediate result, partial / or output block), data_size represents the amount of communication data, route_policy represents the routing strategy, and dependency represents the dependency between the communication event and the computation stage. Through these communication event generation rules, the platform explicitly defines the communication requirements during multi-core execution, enabling subsequent simulators to evaluate communication overhead item by item.

[0064] Based on the topology graph, a set of candidate paths is generated between any source core and the target core, and basic information such as path hop count, link set and available bandwidth are calculated; then, a candidate routing path is generated for each communication event.

[0065] For a communication event from source core i to target core j, calculate the source core and target core, candidate path, path hop count, set of links traversed, minimum available bandwidth on the path, and whether it shares a link with other communication events.

[0066] For a communication path from source core i to target core j, it may contain one or more links (the path is equal to one link only when the two cores are directly adjacent).

[0067] The multi-core interconnect extension module also describes the dependencies between communication events and computation phases. For example, it stipulates that local computation can only begin for the corresponding core after a certain input block communication is completed; cross-core reduction can only begin after a certain part of the computation is completed; subsequent attention computation can only continue after the Softmax global normalization parameter synchronization is completed; and related buffers can only be released after the output block write-back is completed. These dependencies can be represented as a directed dependency graph, where nodes include local computation events, data transmission events, reduction events, synchronization events, and write-back events, representing sequential dependencies. The multi-level memory hierarchy simulator can perform timeline simulations based on this dependency graph to estimate whether communication and computation can overlap and the final total cycle time.

[0068] Therefore, for a communication event from source core i to target core j, the communication period CommCycle can be expressed as: CommCycle(i,j)=Latency(i,j)+DataSize / EffectiveBW(i,j); Latency(i,j) is determined by the interconnection topology, path hop count, and link base delay; DataSize represents the amount of communication data; EffectiveBW(i,j) represents the effective bandwidth after considering link bandwidth, routing path, and contention.

[0069] The simulator calculates the data traffic on each link based on the communication events generated by the multi-core interconnect extension module, including point-to-point communication, broadcast, multicast, reduction, and write-back communication. When multiple communication flows share the same link, the simulator estimates the additional cycles caused by link congestion based on bandwidth allocation, time-slice scheduling, or priority strategies.

[0070] For architectures that support overlapping communication and computation, the chiplet stage cycle can be represented as: ChipletStageCycle=max(LocalComputeCycle, LocalMemoryCycle, RemoteCommCycle)+SyncCycle; Among them, LocalComputeCycle represents the local computation cycle, LocalMemoryCycle represents the local memory access cycle, RemoteCommCycle represents the cross-core communication cycle, and SyncCycle represents the waiting cycle caused by reduction, barrier synchronization, or load imbalance. For global reduction, global normalization, or synchronization stages that cannot overlap with computation, the simulator counts them as independent stages in the total cycle.

[0071] Ultimately, the total execution cycle of the multi-core process can be expressed as: TotalCycle=max(ChipletCycle_1, ChipletCycle_2,…, ChipletCycle_n)+GlobalSyncCycle; Where ChipletCycle_i represents the cycle required for the i-th chip to complete its local task and related communication, and GlobalSyncCycle represents the additional cycle caused by global synchronization, cross-chip reduction, or final result write-back.

[0072] When the multi-level storage hierarchy simulator performs simulations, each complete operator consists of multiple L2 tiles (L2-level blocks), each L2 tile contains multiple L1 tiles (L1-level blocks), and each L1 tile contains multiple L0 tiles (L0-level blocks). This hierarchical structure can reflect the relationships of tile residency, sub-tile iteration, and data reuse at different storage levels, avoiding the mismodeling of L2, L1, and L0 blocks as having the same update frequency. The simulator traverses each level of tiles sequentially according to the loop order in the candidate configuration and calls the next level simulator level by level.

[0073] Specifically, the complete operator space is traversed according to the L2 layer block parameters, and the internal execution cycle of each L2 tile is estimated; each L2 tile is further divided into multiple L1 tiles, and the execution cycle of each L1 tile is estimated; each L1 tile is further divided into multiple L0 tiles, and the computation cycle of each L0 tile is estimated; according to the type of the underlying computation unit, the execution cycle of the pulsating array, the execution cycle of the vector unit, or a combination of both is calculated.

[0074] like Figure 6 As shown, in the pipeline of each stage of the simulator, there are read cycle R, calculation cycle C and write-back cycle W. Starting from the second block, the overlap cycle is the maximum value of the read cycle of the current block and the calculation cycle of the previous block plus the write-back cycle of the previous block. Therefore, the calculation method for the complete simulation cycle of each stage is specifically the sum of the read cycle of the first block, multiple overlap cycles and the calculation and write-back cycles of the last block.

[0075] like Figure 7 As shown, the computation cycle of each level of the simulator can be broken down into the sum of the read, computation, and write-back cycles of the next level of the simulator.

[0076] Therefore, the complete operator-level simulation cycle consists of all L2 tile read, computation, and write-back cycles. If L2-level double buffering is supported, the total simulation cycle (SimulatorCycle) can be expressed as: SimulatorCycle=FirstL2ReadCycle+ΣTileCycle_L2+LastL2ComputeAndWriteCycle; Where FirstL2ReadCycle represents the first L2 tile read cycle, LastL2ComputeAndWriteCycle represents the last L2 tile calculation and write-back cycle, and TileCycle_L2 represents the overlapping cycle of multiple L2 tile reads, calculations, and write-backs, which can be represented as: TileCycle_L2=max(CurrentL2ReadCycle,PreviousL2ComputeCycle)+PreviousL2WriteCycle; Among them, CurrentL2ReadCycle represents the cycle required to read the newly added L2 tile data, PreviousL2ComputeCycle represents the calculation cycle of the previous L2 tile, and PreviousL2WriteCycle represents the write-back cycle of the previous L2 tile. If the hardware or implementation does not support L2 level overlap, the read cycle, calculation cycle and write-back cycle can be accumulated serially.

[0077] The L2TileSimulatorCycle describes the execution process of multiple L1 Tiles within an L2 tile, and can be represented as: L2TileSimulatorCycle=FirstL1ReadCycle+Σ(max(CurrentL1ReadCycle, PreviousL1ComputeCycle)+PreviousL1WriteCycle)+LastL1ComputeAndWriteCycle; Here, FirstL1ReadCycle represents the reading cycle of the first L1 tile, CurrentL1ReadCycle represents the cycle required to read new L1 tile data from L2, PreviousL1ComputeCycle represents the calculation cycle of the previous L1 tile, PreviousL1WriteCycle represents the cycle of outputting or partially writing back to L2 from the previous L1 tile, and LastL1ComputeAndWriteCycle represents the calculation and write-back cycle of the last L1 tile.

[0078] The L1 Tile Simulator Cycle describes the execution process of multiple L0 tiles within an L1 tile, and can be represented as: L1TileSimulatorCycle=FirstL0ReadCycle+Σ(max(CurrentL0ReadCycle, PreviousL0ComputeCycle)+PreviousL0WriteCycle)+LastL0ComputeAndWriteCycle; Here, FirstL0ReadCycle represents the first L0 tile read cycle, CurrentL0ReadCycle represents the cycle required to read new L0 tile data from L1, PreviousL0ComputeCycle represents the calculation cycle of the previous L0 tile, PreviousL0WriteCycle represents the cycle of outputting or partially writing back to L1 from the previous L0 tile, and LastL0ComputeAndWriteCycle represents the calculation and write-back cycle of the last L0 tile.

[0079] The L0 Tile simulation cycle is determined by the execution time of the underlying computational units. For operators such as matrix multiplication and convolution, which are based on matrix multiplication and accumulation, a systolic array execution cycle can be used; for vector-type operators such as Softmax, normalization, activation functions, and element-wise addition, a vector unit execution cycle can be used; for operators that simultaneously involve matrix computation and vector processing, serial accumulation or pipelined overlap can be selected based on the execution dependency. The specific form used depends on the operator type, whether the hardware execution units can be parallelized, and whether there is a data dependency between the two types of computation.

[0080] After completing the full simulation of the operator mapping scheme, the multi-level memory hierarchy simulator outputs the following multi-level quantitative evaluation results: Execution cycle decomposition by layer: L0 Tile simulation cycle, L1 Tile simulation cycle, L2 Tile simulation cycle, and total simulation cycle; Data migration and reuse statistics: total data read volume at each level of storage, total data write-back volume at each level of storage, and bandwidth utilization rate at each level of storage; Multi-core communication overhead decomposition: local computation cycle, local memory access cycle, data traffic statistics and effective bandwidth after congestion reduction on each link for each core, total cross-core communication cycle and proportion of various communication events, communication and computation overlap rate, and synchronization waiting cycle; Computational resource utilization: Computational array utilization (actual effective MAC cycles / total execution cycles), load balancing among cores (slowest core cycle / average core cycle).

[0081] Further, a bottleneck judgment process is performed based on the task cycle and the resource utilization rate to obtain a first analysis result; a memory access bottleneck judgment process is performed based on the resource utilization rate to obtain a second analysis result; a communication bottleneck judgment process is performed based on the task cycle to obtain a third analysis result; a synchronization waiting judgment process is performed based on the task cycle to obtain a fourth analysis result; and an optimization strategy is constructed based on the first analysis result, the second analysis result, the third analysis result, and the fourth analysis result to obtain a target search strategy.

[0082] The simulation results are fed back to the intelligent search engine in a structured form. The intelligent search engine performs bottleneck analysis based on the simulation results, determines the performance bottleneck of the current candidate solution, and adjusts the subsequent search direction accordingly.

[0083] When the utilization rate of the computing array exceeds a first preset threshold (e.g., 85%), and the memory access cycle or communication cycle is less than a second preset threshold, it is determined that the current configuration is at a computing bottleneck. The computing units of the cores under the current configuration are fully utilized, and the search direction is adjusted to increase the number of cores for further parallel computing, or to adjust the partitioning dimension to increase the independent computing granularity of each core and reduce the reduction frequency. Subsequent searches prioritize exploring computing partitioning schemes with a larger number of cores or coarser granularity.

[0084] When the utilization rate of storage bandwidth at each level approaches saturation and the utilization rate of the computing array is less than the third threshold (e.g., 50%), it is determined that the current configuration is experiencing a memory access bottleneck. This indicates that the current configuration is limited by data migration speed. The search direction is adjusted to increase the size of each block level to improve data reuse and reduce redundant memory accesses, or to adjust the loop order so that data reuse occurs at higher bandwidth storage levels, or to try different data flow patterns (such as switching from output-resident to weight-resident). In subsequent searches, the candidate range of block parameters is narrowed down, prioritizing configurations with high reuse rates.

[0085] When the proportion of communication cycles to total cycles exceeds the fourth threshold (e.g., 40%) and link congestion is severe, it is determined that the current configuration is at a communication bottleneck. It is determined that the cross-core communication overhead under the current configuration is too high. Adjust the tensor partitioning dimension (e.g., switch from partitioning along M dimensions to partitioning along N dimensions to reduce the amount of broadcast data), or adjust the routing strategy (select a less congested path or use a multicast tree instead of multiple point-to-point transmissions), or reduce the number of cores to reduce the number of communication hops, or adjust the broadcast tree / reduction tree structure to reduce the link load of intermediate nodes. If the traffic of a link exceeds 80% of its bandwidth, it is marked as a congested link, and in subsequent searches, avoid generating mapping schemes that require a large number of passes through this link.

[0086] If the proportion of synchronization waiting period to total period is greater than the fifth threshold (e.g., 20%), the current configuration is determined to be in a synchronization waiting state. It is determined that the load is unbalanced among the cores. The search direction is adjusted to optimize the tensor partitioning ratio (e.g., allocate uneven tile sizes according to the core's computing power, rather than evenly dividing them), or allow a more aggressive communication and computing overlap strategy to reduce explicit synchronization. The load balance index is included in the reward function, and candidate configurations with excessive load differences are penalized.

[0087] Next, the intelligent search engine transforms the simulation results into scalar objective function values ​​(or reinforcement learning reward signals) to drive the iteration of the search algorithm.

[0088] Step S40: Perform optimal operator mapping iterative search processing according to the target search strategy and the input operator to obtain the target operator mapping configuration, obtain the target instruction, determine the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, and perform action control signal generation processing according to the target operator mapping configuration and the target instruction through the AI ​​accelerator and the built-in embodied intelligence model to obtain the target control signal, and control the target embodied intelligence to complete the physical action according to the target control signal.

[0089] Specifically, a preset number of iterations is obtained, and an optimal operator mapping iterative search process is performed based on the target search strategy and the input operator. When the number of iterations equals the preset number of iterations, the target operator mapping configuration is obtained.

[0090] Pre-set termination conditions. When the termination conditions are met, the iterative search stops, and the final configuration for the AI ​​accelerator is obtained. For example, reaching the preset maximum number of simulations, no improvement in the objective function value for multiple consecutive rounds, or reaching the preset search time budget.

[0091] Furthermore, the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence is determined. The built-in embodied intelligence model is deployed and processed by the AI ​​accelerator according to the target operator mapping configuration to obtain the target embodied intelligence model. The target instruction is obtained, and the target embodied intelligence model performs signal generation processing according to the target instruction to obtain the target control signal. The target embodied intelligence is then controlled to complete physical actions according to the target control signal.

[0092] like Figure 2 As shown, this invention includes an output module, which outputs the best-performing operator mapping configuration from historical samples after the search terminates. The output mapping configuration includes the number of chiplets, tensor partitioning method, tile-to-chiplet mapping relationship, routing strategy, block parameters at each level, loop order and data flow mode, as well as the corresponding simulation cycle, communication overhead and resource utilization indicators.

[0093] The built-in embodied intelligence model (e.g., vision-language-action model) is deployed on the AI ​​accelerator; the embodied intelligence body's sensors collect environmental images and depth information and receive external language commands. The AI ​​accelerator sequentially executes the visual encoder's convolution or visual Transformer feature extraction, cross-modal projection layer matrix multiplication alignment, and policy Transformer attention inference according to the operator mapping configuration output by the output module, and outputs action control signals; the control signals drive the embodied intelligence body's joint actuators or moving chassis to complete the corresponding physical actions.

[0094] This invention converts different types of operators into a unified simulation input, searches for the optimal operator mapping configuration based on the simulation input, and optimizes the search strategy based on the simulation results to obtain the target operator mapping configuration for accelerating embodied intelligence models, thereby improving the efficiency of action data generation for embodied intelligence.

[0095] Furthermore, such as Figure 8 As shown, based on the above-described embodied intelligent control method for AI accelerators supporting multi-operator generalization and intelligent search, this invention also provides an embodied intelligent control system based on an AI accelerator supporting multi-operator generalization and intelligent search, wherein the embodied intelligent control system based on an AI accelerator supporting multi-operator generalization and intelligent search includes: The operator unification module 51 is used to obtain a preset configuration, perform input framework generation processing according to the preset configuration to obtain a unified input framework, obtain an embodied perception operator, and perform input form unification processing on the embodied perception operator according to the unified input framework to obtain an input operator. The configuration search module 52 is used to perform optimal operator mapping search processing based on the input operator to obtain the initial operator mapping configuration; The simulation module 53 is used to perform simulation based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate, and to perform search strategy update processing based on the task cycle and the resource utilization rate to obtain the target search strategy. The action generation module 54 is used to perform optimal operator mapping iterative search processing according to the target search strategy and the input operator to obtain the target operator mapping configuration, obtain the target instruction, determine the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, and perform action control signal generation processing according to the target operator mapping configuration and the target instruction through the AI ​​accelerator and the built-in embodied intelligence model to obtain the target control signal, and control the target embodied intelligence to complete the physical action according to the target control signal.

[0096] Furthermore, such as Figure 9 As shown, based on the above-mentioned embodied intelligent control method and system for AI accelerators that support multi-operator generalization and intelligent search, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Figure 9 Only some of the terminal components are shown; however, it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0097] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory. In other embodiments, the memory 20 may be an external storage device of the terminal, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc. Further, the memory 20 may include both internal and external storage devices. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code installed on the terminal. The memory 20 can also be used to temporarily store data that has been output or will be output. In one embodiment, the memory 20 stores an embodied intelligent control program 40 based on an AI accelerator supporting multi-operator generalization and intelligent search. This embodied intelligent control program 40 can be executed by the processor 10 to implement the embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search in this application.

[0098] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor, or other data processing chip, used to run program code stored in the memory 20 or process data, such as executing the embodied intelligent control method based on an AI accelerator that supports multi-operator generalization and intelligent search.

[0099] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display 30 is used to display information on the terminal and to display a visual user interface.

[0100] In one embodiment, when the processor 10 executes the embodied intelligent control program 40 based on the AI ​​accelerator supporting multi-operator generalization and intelligent search stored in the memory 20, it implements the steps of the embodied intelligent control method based on the AI ​​accelerator supporting multi-operator generalization and intelligent search as described above.

[0101] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores an embodied intelligent control program based on an AI accelerator that supports multi-operator generalization and intelligent search, and the embodied intelligent control program based on an AI accelerator that supports multi-operator generalization and intelligent search, when executed by a processor, implements the steps of the embodied intelligent control method based on an AI accelerator that supports multi-operator generalization and intelligent search as described above.

[0102] In summary, this invention provides an embodied intelligent control method, system, and terminal based on an AI accelerator supporting multi-operator generalization and intelligent search. The method includes: obtaining a preset configuration; performing input framework generation processing based on the preset configuration to obtain a unified input framework; obtaining embodied perception operators; performing input form unification processing on the embodied perception operators based on the unified input framework to obtain input operators; performing optimal operator mapping search processing based on the input operators to obtain an initial operator mapping configuration; and performing simulation based on the initial operator mapping configuration and the input operators to obtain the task cycle and resources. The resource utilization rate is used to update the search strategy based on the task cycle and the resource utilization rate to obtain the target search strategy. Based on the target search strategy and the input operators, an optimal operator mapping iterative search is performed to obtain the target operator mapping configuration. Target instructions are obtained, and the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence is determined. Through the AI ​​accelerator and the built-in embodied intelligence model, action control signal generation processing is performed based on the target operator mapping configuration and the target instructions to obtain the target control signal. The target embodied intelligence is then controlled to complete physical actions based on the target control signal. This invention converts different types of operators into a unified simulation input, searches for the optimal operator mapping configuration based on the simulation input, and optimizes the search strategy based on the simulation results to obtain the target operator mapping configuration for accelerating the embodied intelligence model, thereby improving the efficiency of action data generation for embodied intelligence.

[0103] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal. Unless otherwise specified, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or terminal that includes that element.

[0104] Of course, those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware (such as a processor, controller, etc.). The program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The computer-readable storage medium can be a memory, magnetic disk, optical disk, etc.

[0105] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search, characterized in that, The embodied intelligent control method based on an AI accelerator that supports multi-operator generalization and intelligent search includes: Obtain a preset configuration, perform input framework generation processing based on the preset configuration to obtain a unified input framework, and obtain an embodied perception operator. Perform input form unification processing on the embodied perception operator based on the unified input framework to obtain an input operator. Based on the input operator, perform an optimal operator mapping search process to obtain the initial operator mapping configuration; Simulation is performed based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate. Then, the search strategy is updated based on the task cycle and the resource utilization rate to obtain the target search strategy. Based on the target search strategy and the input operator, an optimal operator mapping iterative search process is performed to obtain the target operator mapping configuration, obtain the target instruction, determine the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, and through the AI ​​accelerator and the built-in embodied intelligence model, perform action control signal generation processing based on the target operator mapping configuration and the target instruction to obtain the target control signal, and control the target embodied intelligence to complete the physical action based on the target control signal.

2. The embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search according to claim 1, characterized in that, The preset configuration includes tensor definition information and loop information; The process of obtaining a preset configuration, generating an input framework based on the preset configuration to obtain a unified input framework, obtaining an embodied perception operator, and performing input form unification processing on the embodied perception operator based on the unified input framework to obtain an input operator specifically includes: Obtain the tensor definition information, perform tensor shape definition processing based on the tensor definition information, and obtain the tensor shape; Obtain the loop information, perform loop structure definition processing based on the loop information, and obtain the loop structure; Based on the tensor definition information and the loop information, data access relationship definition processing and data reuse feature definition processing are performed to obtain data access relationship and data reuse feature; A unified input framework is obtained based on the tensor shape, the loop structure, the data access relationship, and the data reuse feature. An embodied perception operator is then obtained. The embodied perception operator is subjected to unified input form processing based on the unified input framework to obtain the input operator.

3. The embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search according to claim 1, characterized in that, The step of performing an optimal operator mapping search based on the input operator to obtain an initial operator mapping configuration specifically includes: Based on the computational flow graph of the input operator, a mapping space generation process is performed to obtain a candidate mapping space; Obtain the historical record database, perform similar record filtering processing on the historical record database according to the input operator, and if similar records are obtained, use the historical operator mapping configuration corresponding to the similar records as the initial operator mapping configuration; If no similar record is obtained, random sampling is performed in the candidate mapping space to obtain multiple random mapping configurations, and a Bayesian optimized proxy model is determined. The optimal configuration selection process is performed on the multiple random mapping configurations through the Bayesian optimized proxy model to obtain the optimal operator mapping configuration. The optimal operator mapping configuration is used as the initial operator mapping configuration, and the optimal operator mapping configuration and the input operator are written into the historical record database.

4. The embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search as described in claim 3, characterized in that, The process of acquiring the historical record database involves filtering similar records in the historical record database according to the input operator. If similar records are obtained, the historical operator mapping configuration corresponding to the similar records is used as the initial operator mapping configuration. Specifically, this includes: Obtain the historical record database, and perform type matching processing based on the operator type of the input operator and multiple historical records in the historical record database to obtain multiple type matching degrees; Tensor similarity is calculated based on the tensor dimension of the input operator and multiple historical records to obtain multiple tensor similarities; Based on the hardware parameters of the input operator and multiple historical records, normalized distance calculation is performed to obtain multiple parameter differences; Obtain the scoring weights, and sum the multiple type matching degrees, multiple tensor similarities, and multiple parameter differences according to the scoring weights to obtain multiple similarity scores; The maximum value of multiple similarity scores is filtered to obtain the target similarity, and a similarity threshold is obtained. If the target similarity is greater than the similarity threshold, the target historical record corresponding to the target similarity is taken as the similar record, and the target historical record corresponding to the target similarity is configured as the initial operator mapping configuration.

5. The embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search according to claim 1, characterized in that, The process involves performing simulations based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate, and then updating the search strategy based on the task cycle and resource utilization rate to obtain the target search strategy. Specifically, this includes: Obtain the core node set, and perform topology graph construction processing based on the core node set to obtain the core topology graph; The input operator is partitioned to obtain multiple tensor blocks, and a mapping process is performed on the multiple tensor blocks and multiple cores in the core node set to obtain the core mapping relationship. Based on the core-particle mapping relationship, communication event construction processing is performed to obtain multiple communication events, and based on the multiple communication events and the core-particle topology map, path generation processing is performed to obtain multiple communication paths; Based on multiple communication events and multiple communication paths, periodic calculation and resource statistics are performed to obtain the task cycle and resource utilization rate. Then, based on the task cycle and the resource utilization rate, the search strategy is updated to obtain the target search strategy.

6. The embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search according to claim 5, characterized in that, The step of updating the search strategy based on the task cycle and the resource utilization rate to obtain the target search strategy specifically includes: Based on the task cycle and resource utilization rate, bottleneck judgment is performed to obtain the first analysis result; Based on the resource utilization rate, a memory access bottleneck is identified and processed to obtain the second analysis result; Based on the task cycle, a communication bottleneck is identified and processed to obtain the third analysis result; Based on the task cycle, a synchronous waiting judgment process is performed to obtain the fourth analysis result; Based on the first analysis result, the second analysis result, the third analysis result, and the fourth analysis result, an optimization strategy is constructed to obtain the target search strategy.

7. The embodied intelligent control method based on an AI accelerator supporting multi-operator generalization and intelligent search according to claim 1, characterized in that, The process of performing optimal operator mapping iterative search based on the target search strategy and the input operator to obtain the target operator mapping configuration, acquiring target instructions, determining the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, generating action control signals based on the target operator mapping configuration and the target instructions using the AI ​​accelerator and the built-in embodied intelligence model to obtain target control signals, and controlling the target embodied intelligence to complete physical actions based on the target control signals, specifically includes: Obtain a preset number of iterations, perform optimal operator mapping iterative search processing according to the target search strategy and the input operator, and obtain the target operator mapping configuration when the number of iterations equals the preset number of iterations. The AI ​​accelerator and the built-in embodied intelligence model of the target embodied intelligence are determined. The built-in embodied intelligence model is deployed and processed by the AI ​​accelerator according to the target operator mapping configuration to obtain the target embodied intelligence model. The target instruction is obtained, and the target embodied intelligence model performs signal generation and processing based on the target instruction to obtain the target control signal. The target embodied intelligence is then controlled to complete physical actions based on the target control signal.

8. An embodied intelligent control system based on an AI accelerator supporting multi-operator generalization and intelligent search, characterized in that, The embodied intelligent control system based on an AI accelerator that supports multi-operator generalization and intelligent search includes: The operator unification module is used to obtain a preset configuration, perform input framework generation processing according to the preset configuration to obtain a unified input framework, obtain an embodied perception operator, and perform input form unification processing on the embodied perception operator according to the unified input framework to obtain an input operator. A configuration search module is used to perform optimal operator mapping search processing based on the input operator to obtain the initial operator mapping configuration; The simulation module is used to perform simulation based on the initial operator mapping configuration and the input operator to obtain the task cycle and resource utilization rate, and to perform search strategy update processing based on the task cycle and resource utilization rate to obtain the target search strategy; The action generation module is used to perform optimal operator mapping iterative search processing according to the target search strategy and the input operator to obtain the target operator mapping configuration, acquire the target instruction, determine the built-in embodied intelligence model of the AI ​​accelerator and the target embodied intelligence, and through the AI ​​accelerator and the built-in embodied intelligence model, perform action control signal generation processing according to the target operator mapping configuration and the target instruction to obtain the target control signal, and control the target embodied intelligence to complete the physical action according to the target control signal.

9. A terminal, characterized in that, The terminal includes a memory, a processor, and an embodied intelligent control program based on an AI accelerator that supports multi-operator generalization and intelligent search, stored in the memory and executable on the processor. When the processor executes the embodied intelligent control program based on an AI accelerator that supports multi-operator generalization and intelligent search, it implements the steps of the embodied intelligent control method based on an AI accelerator that supports multi-operator generalization and intelligent search as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an embodied intelligent control program based on an AI accelerator that supports multi-operator generalization and intelligent search. When the embodied intelligent control program based on an AI accelerator that supports multi-operator generalization and intelligent search is executed by a processor, it implements the steps of the embodied intelligent control method based on an AI accelerator that supports multi-operator generalization and intelligent search as described in any one of claims 1-7.

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