A signal processing method and system

Abstract

The application discloses a signal processing method and system, and relates to the technical field of signal processing. An interface circuit acquires a first source signal used for representing a device fault state, and transmits corresponding sub-signals to a processor through a first signal chain and a second signal chain. The second signal chain extracts and performs logical NOT operation on a logic value, so that the first input signal and the second input signal received by the processor have opposite logic change directions. When the transmission time periods of the two input signals are located in a target time window in a same operation cycle, the processor outputs first prompt information used for indicating that corresponding fault processing is completed. The method can establish a reciprocal logic relationship between two input signals based on the same source signal, and constrain the time relationship between the two input signals through the target time window in the same operation cycle, thereby improving the accuracy of fault processing completion prompt.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a signal processing method and system. Background Technology

[0002] With the development of industrial control, automation equipment, and safety monitoring systems, signal processing systems are typically required to monitor and diagnose equipment malfunctions during operation. A signal processing system usually includes signal acquisition circuits, a signal chain, and a processor. Signals generated by external devices are transmitted to the processor via the signal chain. The processor analyzes and processes the received signals and outputs corresponding alerts based on the analysis results. In applications involving safe equipment operation, accurate signal acquisition and reliable signal processing are crucial for accurately determining whether equipment malfunctions exist.

[0003] During equipment fault monitoring, input signals from different signal sources are sent to the processor via corresponding signal chains. The processor determines whether a fault exists in the equipment based on multiple input signals and outputs corresponding prompts. However, when using the above signal transmission and processing method, the status determination result obtained by the processing unit often differs from the actual fault state of the equipment, thereby reducing the accuracy of the prompts. Summary of the Invention

[0004] This application provides a signal processing method and system to improve the accuracy of prompt information.

[0005] In a first aspect, embodiments of this application provide a signal processing method. This method is applied to a signal processing system. The signal processing system includes an interface circuit and a processor. The interface circuit and the processor are connected via multiple signal chains, including a first signal chain and a second signal chain. The interface circuit acquires a first source signal. The first source signal indicates a change in a logic value from a first logic value to a second logic value, where the first logic value and the second logic value are different values ​​in binary logic. The logic value indicated by the first source signal is used to characterize whether a device has a fault. A first input signal is a sub-signal of the first source signal transmitted to the processor via the first signal chain. The first signal chain transmits the first input signal to the processor. The first input signal indicates a change in a logic value from a first logic value to a second logic value. A second input signal is a sub-signal of the first source signal that is transmitted to the processor after logic value extraction and a logical NOT operation on the second signal chain. The second signal chain includes a value-taking circuit and a logical NOT circuit. The value-taking circuit determines a logic value based on the first source signal, and the logical NOT circuit performs a logical NOT operation on the logic value determined by the value-taking circuit. The second signal chain transmits the second input signal to the processor. The second input signal is used to indicate that the logic value changes from a second logic value to a first logic value. The processor determines a first transmission period for the first input signal to be transmitted to the processor and a second transmission period for the second input signal to be transmitted to the processor. When both the first and second transmission periods fall within the target time window of the same operating cycle, the processor outputs a first prompt message. The first prompt message is used to indicate that the fault corresponding to the first source signal has been processed.

[0006] In this embodiment, both the first signal chain and the second signal chain use the first source signal as their signal source. The first signal chain forms the first input signal according to the original logical change direction of the first source signal. The second signal chain extracts the logical value of the first source signal and performs a logical NOT operation to form the second input signal, so that the first and second input signals have opposite logical change directions. Since the two input signals originate from the same first source signal, the signal processing system does not need to control two independent external input signals separately, which reduces the possibility that the two external input signals may not undergo opposite logical changes as expected. Simultaneously, the processor determines whether to output the first prompt information based on whether the transmission periods of the two input signals are both within the target time window of the same operating cycle. Therefore, the signal processing method provided in this application can avoid outputting prompt information when the transmission period of a certain input signal falls outside the target time window, thereby improving the accuracy of fault handling completion prompts.

[0007] In one possible implementation, the second signal chain further includes a logic value determination circuit. The logic value determination circuit determines whether the logic value indicated by the second input signal is valid. The processor receives the second input signal that has been confirmed as valid by the logic value determination circuit. Thus, the logic value determination circuit can screen the second input signal for validity before it participates in the fault handling completion determination, reducing the likelihood of invalid logic values ​​participating in the fault handling completion determination and triggering error messages.

[0008] In one possible implementation, a logic value determination circuit determines a quality bit corresponding to the first source signal. The quality bit characterizes whether the logic value indicated by the first source signal is valid. When the quality bit indicates that the logic value indicated by the first source signal is valid, the logic value determination circuit outputs a second input signal. Thus, the signal processing system can use the quality bit corresponding to the first source signal to determine the validity of the logic value and only transmit the second input signal, formed by a logical NOT operation, to the processor when the logic value is valid, thereby avoiding invalid logic values ​​from participating in the generation of the prompt message and improving the reliability of the prompt message.

[0009] In one possible implementation, both the first and second input signals begin transmitting to the processor within the target time window and both complete their transmission within the target time window. This allows the processor to use the complete transmission time of both input signals as a time condition, rather than relying solely on partial transmission times, thereby reducing the time-period judgment bias caused by transmission periods crossing the target time window boundary.

[0010] In one possible implementation, the multiple signal chains further include a third signal chain and a fourth signal chain. An interface circuit acquires a second source signal. The second source signal indicates a change in a logic value from a first logic value to a second logic value. The logic value indicated by the second source signal characterizes whether a device malfunctions. A third input signal is a sub-signal of the second source signal transmitted to the processor via the third signal chain. The third signal chain transmits the third input signal to the processor. The third input signal indicates a change in a logic value from a first logic value to a second logic value. A fourth input signal is a sub-signal of the second source signal that is transmitted to the processor after logic value extraction and a logical NOT operation on the fourth signal chain. The fourth signal chain includes a value-taking circuit and a logical NOT circuit. The value-taking circuit in the fourth signal chain determines the logic value based on the second source signal, and the logical NOT circuit in the fourth signal chain performs a logical NOT operation on the logic value determined by the value-taking circuit. The fourth input signal indicates a change in a logic value from a second logic value to a first logic value. When the transmission periods of the third and fourth input signals to the processor both fall within the target time window of the same operating cycle, the processor outputs a second prompt message in parallel while outputting the first prompt message. The second prompt message indicates that the fault corresponding to the second source signal has been processed. In this way, the signal processing system can establish corresponding inverse signal chains for multiple source signals and determine whether each group of input signals meets the corresponding target time window within the same operating cycle. This enables independent judgment and parallel prompting of the completion status of fault processing for multiple source signals, improving the signal processing system's ability to process multiple fault-related signals.

[0011] In one possible implementation, the signal processing system further includes a terminal. When the transmission periods of the first, second, third, and fourth input signals all fall within the same operating cycle, the terminal displays a fault record in the interactive interface. The fault record includes equipment faults. Thus, the terminal can display equipment faults when the condition of the same operating cycle is met, establishing a correlation between the fault record and the transmission cycle of the corresponding input signal, thereby providing a basis for centralized viewing and subsequent verification of fault information.

[0012] In one possible implementation, the signal processing system further includes a lamp confirmation circuit. The lamp confirmation circuit includes a lamp confirmation switch. Before the processor receives the first input signal, when the logic value indicated by the first source signal changes from a second logic value to the first logic value, the processor outputs a first alarm message. The first alarm message indicates that the alarm status corresponding to the first source signal has not been manually confirmed. When the lamp confirmation switch is manually triggered, the lamp confirmation circuit generates a lamp confirmation signal. The lamp confirmation signal indicates that the alarm status corresponding to the first source signal has been manually confirmed. When the processor receives the lamp confirmation signal, the processor outputs a second alarm message. The second alarm message indicates that the fault corresponding to the first source signal is being processed.

[0013] In this way, the processor can change the output mode of the alarm information according to the light confirmation signal. The unconfirmed alarm state and the confirmed alarm state correspond to different output forms. The signal processing system can determine whether the alarm state has been confirmed according to the different output forms.

[0014] In one possible implementation, the signal processing system is implemented by a microprocessor unit, or MPU. The microprocessor unit acquires a first input signal and a second input signal according to a pre-set program scan cycle, and performs logical judgments and outputs prompt information within the program scan cycle. Thus, the program scan cycle of the microprocessor unit can provide a unified time reference for determining whether the first and second input signals are in the same operating cycle, thereby improving the determinism of the prompt information output timing.

[0015] Secondly, embodiments of this application provide a signal processing system. The signal processing system includes an interface circuit, a processor, and multiple signal chains connecting the interface circuit and the processor. The multiple signal chains include a first signal chain and a second signal chain.

[0016] The interface circuit is used to acquire a first source signal. The first source signal is used to indicate that the logic value changes from a first logic value to a second logic value, and the logic value indicated by the first source signal is used to characterize whether the device has a fault.

[0017] The first signal chain transmits a first input signal to the processor. The first input signal is a sub-signal from the first source signal that is transmitted to the processor via the first signal chain. This first input signal indicates that the logic value changes from a first logic value to a second logic value. The second signal chain includes a fetching circuit and a NOT circuit. The second input signal is a sub-signal from the first source signal that is processed by extracting the logic value and performing a NOT operation on the second signal chain before being transmitted to the processor. The fetching circuit determines the logic value based on the first source signal, and the NOT circuit performs a NOT operation on the logic value determined by the fetching circuit. The second input signal indicates that the logic value changes from a second logic value to a first logic value.

[0018] The processor receives a first input signal and a second input signal, and outputs a first prompt message when the transmission periods of both input signals to the processor are within the target time window of the same operating cycle. The first prompt message indicates that the fault corresponding to the first source signal has been processed.

[0019] In one possible implementation, the second signal chain further includes a logic value determination circuit. The logic value determination circuit determines whether the logic value indicated by the second input signal is valid. The second input signal received by the processor is a second input signal with a valid logic value.

[0020] In one possible implementation, the logic value determination circuit is used to determine the quality bit corresponding to the first source signal. The quality bit is used to characterize whether the logic value indicated by the first source signal is valid. When the quality bit indicates that the logic value indicated by the first source signal is valid, the logic value determination circuit outputs a second input signal.

[0021] In one possible implementation, the start time of the first input signal and the completion time of the second input signal arriving at the processor are both within the target time window.

[0022] In one possible implementation, the multiple signal chains further include a third signal chain and a fourth signal chain. The interface circuit is also used to acquire a second source signal. The second source signal is used to indicate a change in a logic value from a first logic value to a second logic value, and the logic value indicated by the second source signal is used to characterize whether a device malfunctions. The processor is also used to receive a third input signal and a fourth input signal. The third input signal is a sub-signal of the second source signal transmitted to the processor via the third signal chain, and the third input signal is used to indicate a change in a logic value from the first logic value to the second logic value. The fourth input signal is a sub-signal of the second source signal that has undergone logic value extraction and a logical NOT operation on the fourth signal chain and is then transmitted to the processor. The fourth signal chain includes a value-taking circuit and a logical NOT circuit. The value-taking circuit in the fourth signal chain is used to determine a logic value based on the second source signal, and the logical NOT circuit in the fourth signal chain is used to perform a logical NOT operation on the logic value determined by the value-taking circuit in the fourth signal chain. The fourth input signal is used to indicate a change in a logic value from the second logic value to the first logic value. The processor is also configured to, during the output of the first prompt message, and provided that the time periods for the transmission of the third and fourth input signals to the processor both fall within the target time window of the same operating cycle, simultaneously execute the output of the second prompt message. The second prompt message is used to indicate that the fault corresponding to the second source signal has been resolved.

[0023] In one possible implementation, the signal processing system further includes a terminal for displaying fault records in an interactive interface when the transmission periods of the first input signal, the second input signal, the third input signal, and the fourth input signal are all within the same operating cycle. The fault records include faults that have occurred in the device.

[0024] In one possible implementation, the signal processing system further includes a lamp confirmation circuit. The lamp confirmation circuit includes a lamp confirmation switch. Before the processor receives the first input signal, the processor outputs a first alarm message when the logic value indicated by the first source signal changes from a second logic value to the first logic value. The first alarm message indicates that the alarm status corresponding to the first source signal has not been manually confirmed. The lamp confirmation circuit generates a lamp confirmation signal when the lamp confirmation switch is manually triggered. The lamp confirmation signal indicates that the alarm status corresponding to the first source signal has been manually confirmed. Upon receiving the lamp confirmation signal, the processor outputs a second alarm message. The second alarm message indicates that the fault corresponding to the first source signal is being processed.

[0025] In one possible implementation, the processor is an MPU (microprocessor unit). The microprocessor unit acquires a first input signal and a second input signal according to a pre-set program scan cycle, and performs logical judgments and outputs prompt information within the program scan cycle.

[0026] The signal processing system provided in the second aspect corresponds to the signal processing method provided in the first aspect. Therefore, the technical effects of the second aspect and its various embodiments can be found in the first aspect and its various embodiments, and will not be repeated here. Attached Figure Description

[0027] Figure 1 This is a schematic diagram illustrating an application scenario of a signal processing system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a signal processing system 20 provided in an embodiment of this application; Figure 3 A signaling interaction diagram of a signal processing method provided in an embodiment of this application; Figure 4 A schematic diagram of signaling interaction for another signal processing method provided in an embodiment of this application; Figure 5 This application provides a schematic diagram illustrating the interaction between a terminal 50 and a signal processing system. Figure 6 A timing diagram illustrating an alarm information output provided in an embodiment of this application; Figure 7 This is a simulation and debugging diagram of an alarm algorithm provided in an embodiment of this application; Figure 8 This is a schematic diagram of the hardware structure of an alarm testing system provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are some, but not all, embodiments of this application. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0029] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a method of distinction used in describing objects with the same attributes in the embodiments of this application.

[0030] To facilitate understanding and explanation, the technical terms mentioned in the embodiments of this application will be introduced below.

[0031] The logic value can be a binary logic quantity used to represent the state of a source signal or input signal. In the embodiments of this application, the logic value may include a first logic value and a second logic value, which are different values ​​in binary logic. For example, the first logic value can be logic 1, and the second logic value can be logic 0. In another possible embodiment, the first logic value can also be logic 0, and the second logic value can be logic 1. This application does not limit the specific binary values ​​corresponding to the first and second logic values. When the logic value of the first source signal changes from the first logic value to the second logic value, it can indicate that the device state corresponding to the first source signal has changed. The logic value of the second source signal can also represent a change in the corresponding device state in the same way. The correspondence between the device state and the specific logic value can be set according to the device type, signal definition, or control logic; this application does not limit this.

[0032] The runtime cycle can be the time period corresponding to one preset signal processing procedure executed by the processor. The processor can repeatedly execute one or more of the following processes according to the preset runtime cycle: input signal acquisition, logic processing, status judgment, and prompt information output. One runtime cycle can serve as a time reference for determining whether different input signals belong to the same signal processing procedure. In one possible embodiment, the processor can be implemented by a microprocessor unit (MPU). The MPU can run the corresponding algorithm configuration according to a pre-configured program scan cycle. This program scan cycle can be used as the runtime cycle in the embodiments of this application. The specific duration of the runtime cycle can be set according to the processor performance, algorithm configuration scale, and device control requirements; this application does not limit this.

[0033] See Figure 1 , Figure 1 This illustration shows an application scenario diagram of a signal processing system provided in an embodiment of this application. The application scenario may include a signal source device 10, a signal processing system 20, a prompting terminal 30, a light confirmation circuit 40, and a terminal 50.

[0034] The signal source device 10 can be a device that generates equipment status signals. The signal source device 10 can be industrial equipment, equipment status detection circuit, switch signal output device, or other devices capable of generating equipment status signals. The signal source device 10 can generate a source signal according to the operating status of the corresponding equipment and send the source signal to the signal processing system 20. The logic value of the source signal can be used to characterize whether the equipment is faulty. When the equipment status changes, the logic value of the source signal generated by the signal source device 10 can change accordingly.

[0035] The signal processing system 20 can acquire the source signal generated by the signal source device 10 and can form multiple input signals based on the source signal. The signal processing system 20 can perform transmission, logic value processing, and time relationship judgment on the multiple input signals formed by the source signal, and can output corresponding prompt information according to the processing results.

[0036] The prompting terminal 30 can receive prompt information output by the signal processing system 20 and generate corresponding prompt output based on the prompt information. The prompting terminal 30 can be used to indicate the fault handling status of the device corresponding to the source signal, and can represent the prompt information through light status, pulse signal status, or other identifiable output status. The prompt information can be status output information generated by the processor based on the logical and temporal relationships of the input signals, and can be in the form of digital signals, state variables, pulse signals, or other data formats that can characterize the corresponding device status.

[0037] The lamp confirmation circuit 40 can be used to generate a lamp confirmation signal. The lamp confirmation circuit 40 may include a lamp confirmation switch. The lamp confirmation signal can be an electrical signal generated in response to the lamp confirmation switch being triggered, and the lamp confirmation signal is used to indicate that the alarm status has been manually confirmed. The lamp confirmation switch can be a physical button, a virtual button displayed on a touch screen, or other components capable of receiving user trigger operations. When the lamp confirmation switch is triggered, the lamp confirmation circuit 40 can generate a lamp confirmation signal and send the lamp confirmation signal to the signal processing system 20. After receiving the lamp confirmation signal, the signal processing system 20 can adjust the output status of the corresponding alarm information according to the lamp confirmation signal.

[0038] Terminal 50 can interact with signal processing system 20. Terminal 50 can be a computer, engineering workstation, or other device with data receiving and information display functions. Signal processing system 20 can send device status information, fault information, or prompt information to terminal 50, and terminal 50 can display the corresponding fault record in the interactive interface based on the received information.

[0039] like Figure 1 As shown, signal source device 10 can be connected to signal processing system 20, lamp confirmation circuit 40 can be connected to signal processing system 20, prompt terminal 30 can be connected to signal processing system 20, and terminal 50 can establish a communication connection with signal processing system 20.

[0040] Figure 1 The prompting terminal 30 and terminal 50 can correspond to different information output methods. Prompt terminal 30 can be used to directly generate status prompts based on prompt information generated by the processor, while terminal 50 can be used to display fault records or device status information through an interactive interface. In one possible embodiment, prompting terminal 30 and terminal 50 can also be integrated into the same device, as long as the device can implement the corresponding prompt output function and information display function; this application does not impose any limitations on this.

[0041] In this embodiment, the signal source device 10, the lamp confirmation circuit 40, the prompt terminal 30, and the terminal 50 are mainly used to illustrate a device connection relationship that can be applied to the signal processing system 20. Figure 1 The number of devices and connections shown are merely an example. The signal processing system 20 may also be connected to other numbers or types of peripheral devices, provided it can perform source signal input, signal processing, alarm status confirmation, and processing result output; this application does not limit this.

[0042] See Figure 2 , Figure 2 An exemplary structure of a signal processing system 20 is shown. The following describes... Figure 2 The signal processing system 20 shown is as Figure 1 The following description uses a specific implementation of the signal processing system 20 as an example. The signal processing system 20 may include an interface circuit 201, a first signal chain 202, a second signal chain 203, and a processor 204. The interface circuit 201 and the processor 204 can be connected through the first signal chain 202 and the second signal chain 203. The second signal chain 203 may include a value fetching circuit 2031 and a logic NOT circuit 2032.

[0043] Interface circuit 201 can be used to receive status signals generated by external devices. When the operating status of the external device changes, the corresponding status signal can undergo a logical value change. Interface circuit 201 can provide the received status signal to the corresponding signal chain for subsequent processing by signal processing system 20. Interface circuit 201 may include a digital input interface, a signal acquisition interface, or other interface structures capable of receiving device status signals. The specific implementation of interface circuit 201 is not limited.

[0044] The first signal chain 202 and the second signal chain 203 can serve as signal transmission or signal processing paths between the interface circuit 201 and the processor 204. Different signal chains can be configured with different circuit structures according to the processing requirements of the corresponding signals. The first signal chain 202 may include signal transmission lines, inter-board communication paths, or other structures capable of signal transmission. The second signal chain 203 may include a value-taking circuit 2031 and a logic NOT circuit 2032.

[0045] The value-taking circuit 2031 can be used to extract the corresponding logic value from the data input to the second signal chain 203. The logic-not circuit 2032 can be used to perform a logic-not operation on the input binary logic value. The value-taking circuit 2031 and the logic-not circuit 2032 can serve as signal processing circuits in the second signal chain 203. The specific connection method and circuit implementation can be set according to the hardware structure of the signal processing system 20, and this application does not limit them.

[0046] Processor 204 can receive input signals transmitted via one or more signal chains and perform corresponding logic processing, status judgment, or output control. Processor 204 can implement the corresponding signal processing functions through program execution or algorithm configuration. Processor 204 can repeatedly execute the corresponding signal processing logic according to a pre-configured operating cycle. In equipment fault monitoring scenarios, different status signals can be transmitted to processor 204 via corresponding signal chains, and processor 204 can determine the fault state or fault handling state of the corresponding equipment based on the received multiple input signals.

[0047] This application's embodiments are applicable to scenarios involving equipment fault monitoring and fault handling status indication. Some existing solutions use multiple independent input signals to jointly determine the equipment status. Different input signals may have differences in the timing of signal changes, transmission process, or signal state, leading to inconsistencies between the fault handling judgment result obtained by the processor and the actual fault handling situation of the equipment.

[0048] Based on this, both the first signal chain and the second signal chain in this application use the first source signal as the signal source. A sub-signal from the first source signal is transmitted to the processor via the first signal chain. The processor receives this sub-signal as the first input signal. The logic NOT circuit performs a logic NOT operation on the extracted logic value. The signal after the logic NOT operation is transmitted to the processor via the second signal chain, and the processor receives this signal as the second input signal. Because the logic NOT circuit directly inverts the logic value from the first source signal, the first input signal and the second input signal have opposite logical change directions. Compared to using a relay to invert the first source signal, the logic NOT circuit completes the logic NOT operation within the signal chain faster, which reduces the possibility of asynchronous changes in the two inverse signals due to delay. Simultaneously, the processor outputs the first prompt information only when the transmission periods of both the first and second input signals fall within the target time window of the same operating cycle.

[0049] Since both the first and second input signals originate from the same source signal, and the logic value corresponding to the second input signal is obtained by performing a logical NOT operation on the logic value of the first source signal using a logical NOT circuit, the processor can determine the device fault state corresponding to the first source signal based on two input signals with opposite logical change directions, reducing false alarms or missed alarms caused by abnormal input signal states. Simultaneously, the processor constrains the time relationship between the two input signals by determining that the time periods for both the first and second input signals to be transmitted to the processor fall within the same operating cycle's target time window. Therefore, this application can constrain the fault handling completion judgment process based on the logical inverse relationship and transmission time relationship of the two input signals, thereby reducing the possibility of discrepancies between the judgment result and the actual fault handling status of the device, and improving the accuracy of the fault handling completion prompt.

[0050] Reference Figure 3 , Figure 3 A schematic diagram of signaling interaction of a signal processing method according to an embodiment of this application is shown. Figure 3 The method shown can be applied to Figure 1 The signal processing system shown can also be applied to other applicable signal processing systems, and this application does not limit it. This embodiment uses... Figure 3 The method shown is applied to Figure 2 The signal processing system shown is used as an example for illustration. See [link / reference] Figure 3 The method may include steps S301 to S308.

[0051] S301: Interface circuit 201 acquires the first source signal.

[0052] The first source signal can be a status signal used to characterize whether a device is faulty. The first source signal can indicate a change in a logic value from a first logic value to a second logic value; the first logic value and the second logic value are different values ​​in binary logic. The logic value indicated by the first source signal can be used to characterize whether a device is faulty.

[0053] As an example, the first logic value can be 0, and the second logic value can be 1. An electronic device can assign a logic value of 0 to a state where the device is not faulty, and a logic value of 1 to a state where the device is faulty. In this example, the first source signal indicates that when the logic value changes from 0 to 1, the first source signal is used to characterize the change from a fault-free state to a faulty state.

[0054] The interface circuit 201 can obtain a first source signal through a signal input interface connected to an external device. In practical applications, the interface circuit 201 can be implemented by a digital input board or other interface components with digital signal acquisition capabilities, and this application does not limit this.

[0055] After the interface circuit 201 acquires the first source signal, the different sub-signals in the first source signal are transmitted through the first signal chain 202 and the second signal chain 203 respectively.

[0056] S302: The first signal chain 202 transmits the first input signal, which is the first sub-signal of the first source signal.

[0057] The first signal chain 202 can transmit the first sub-signal in the first source signal to the processor 204. The first sub-signal received by the processor 204 is the first input signal. The change in the logic value corresponding to the first input signal is consistent with the change in the logic value corresponding to the first source signal, that is, the first logic value changes to the second logic value.

[0058] The first signal chain 202 can transmit the first input signal to the processor 204 through a signal transmission line, an inter-board communication path, or a data transmission path within the signal processing system. The specific hardware implementation and transmission method of the first signal chain 202 can be configured according to the device structure of the signal processing system, and this application does not limit it in this regard.

[0059] S303: The value retrieval circuit 2031 in the second signal chain 203 extracts the logic value indicated by the second sub-signal of the first source signal.

[0060] The sub-signal transmitted via the second signal chain 203 in the first source signal can be used as the second sub-signal. The value extraction circuit 2031 can extract the logic value of the second sub-signal to determine the logic value corresponding to the second sub-signal. This logic value can be used as the input for the logic NOT circuit 2032 to perform the logic NOT operation.

[0061] The value-taking circuit 2031 can process the second sub-signal to determine its corresponding logic value. This logic value can be provided to the logic NOT circuit 2032 for subsequent logic NOT operations.

[0062] This application does not limit the specific circuit structure of the value-determining circuit 2031. Where the corresponding logic value can be determined from the second sub-signal, the value-determining circuit 2031 may also employ other signal processing structures capable of achieving the same function.

[0063] S304: The logic NOT circuit 2032 performs a logic NOT operation on the logic value determined by the value taking circuit 2031.

[0064] The logic NOT circuit 2032 can receive the logic value determined by the value taking circuit 2031 and perform a logic NOT operation on the logic value.

[0065] The NOT operation can convert a first logic value into a second logic value, or vice versa. Therefore, the logic value obtained by the NOT operation is the opposite of the logic value determined by the value-taking circuit 2031.

[0066] For example, when the first logic value is 0 and the second logic value is 1, the logic value determined by the value-taking circuit 2031 is 0, and the logic-not circuit 2032 can obtain the logic value 1 after performing a logic-not operation. When the logic value determined by the value-taking circuit 2031 is 1, the logic-not circuit 2032 can obtain the logic value 0 after performing a logic-not operation. The above specific values ​​are only examples, and this application does not limit the first logic value and the second logic value to correspond to 0 or 1 respectively.

[0067] Therefore, the value-taking circuit 2031 first determines the logic value corresponding to the second sub-signal, and then the logic NOT circuit 2032 performs a logic NOT operation only on the logic value. This can form a second input signal with the opposite logic change direction to the first input signal while maintaining the source relationship of the first source signal, thereby reducing the situation where the logic relationship is inconsistent when two independent external signals form mutually inverse inputs.

[0068] S305: The logic value judgment circuit determines whether the logic value is valid based on the quality bit corresponding to the second sub-signal.

[0069] The second signal chain 203 may also include a logic value judgment circuit. The logic value judgment circuit is used to determine whether the logic value of the second sub-signal is valid, and the processor 204 receives the second input signal that has been validated and whose logic value is valid.

[0070] The second sub-signal can indicate a logic value and the corresponding quality bit. The quality bit is used to characterize whether the logic value indicated by the second sub-signal is valid. The logic value determination circuit can determine the quality bit corresponding to the second sub-signal and determine whether the corresponding logic value is valid based on the value of the quality bit.

[0071] In this embodiment, the logic value judgment circuit may be arranged in various ways in the second signal chain 203. Correspondingly, the processing flow of the second sub-signal in the second signal chain 203 may also have various situations. Three possible implementation examples are provided below.

[0072] In the first implementation example, the logic value determination circuit is located before the value extraction circuit 2031. The value extraction circuit 2031 can first extract the quality bit of the second sub-signal, and the logic value determination circuit determines whether the logic value indicated by the second sub-signal is valid based on the quality bit. If the quality bit indicates that the logic value is valid, the value extraction circuit 2031 then extracts the logic value and provides the extracted logic value to the logic NOT circuit 2032 to perform a logic NOT operation. If the quality bit indicates that the logic value is invalid, the signal is not used as a valid second input signal for subsequent processing.

[0073] In a second implementation example, the logic value determination circuit is located after the logic NOT circuit 2032. The value extraction circuit 2031 extracts the logic value of the second sub-signal, the logic NOT circuit 2032 performs a logic NOT operation on this logic value, and the logic value determination circuit determines whether the signal after the logic NOT operation is valid based on the quality bit indicated by the second sub-signal. If the quality bit indicates that the logic value is valid, the signal can be transmitted to the processor 204 as a valid second input signal. If the quality bit indicates that the logic value is invalid, the signal is not used as a valid second input signal in subsequent processing.

[0074] As a third implementation example, the logic value determination circuit and the value extraction circuit 2031 are arranged in parallel. The value extraction circuit 2031 extracts the logic value of the second sub-signal and provides the extracted logic value to the logic NOT circuit 2032 to perform a logic NOT operation. The logic value determination circuit determines whether the logic value is valid based on the quality bit indicated by the second sub-signal. The value extraction circuit 2031 and the logic value determination circuit perform their respective operations in parallel. When the quality bit indicates that the logic value is valid, the signal output by the logic NOT circuit 2032 is transmitted to the processor 204 as a valid second input signal. When the quality bit indicates that the logic value is invalid, the signal output by the logic NOT circuit 2032 is not used as a valid second input signal for subsequent processing.

[0075] It should be noted that the above three implementation examples are only illustrative and are not intended to limit the scope of protection of this application.

[0076] In one possible implementation, the second sub-signal can employ a data structure that includes both a logic value and a quality bit. The logic value determination circuit can determine the quality bit from the data corresponding to the second sub-signal and obtain a determination result based on the correspondence between the quality bit and the valid state of the logic value.

[0077] For example, the second sub-signal can indicate binary signal (BS) type data. BS type data can include a logic value and a quality bit, wherein the quality bit is used to characterize whether the logic value is valid. When the quality bit is 0, the quality status can be "Good", and the corresponding logic value can be determined to be valid; when the quality bit is 1, the quality status can be "Bad", and the corresponding logic value can be determined to be invalid. The above quality bit values ​​and their correspondences are only an example, and this application does not limit the specific encoding method of the quality bit.

[0078] S306: The second signal chain 203 transmits the second input signal, which is the second sub-signal of the first source signal.

[0079] If the corresponding logic value is determined to be valid in step S305, the second signal chain 203 can transmit the second input signal to the processor 204. The second input signal can indicate that the logic value changes from the second logic value to the first logic value, and the first input signal indicates that the logic value changes from the first logic value to the second logic value. Therefore, the first input signal and the second input signal have opposite directions of logic change.

[0080] It should be noted that both the first and second input signals originate from the first source signal. The first input signal is transmitted to the processor 204 via the first signal chain 202, and the second input signal is transmitted to the processor 204 after undergoing logic value determination and logic NOT operations via the second signal chain 203. The inverse relationship between the two input signals does not depend on two independent external signal sources generating them separately.

[0081] S307: When the transmission periods of the first input signal and the second input signal are both within the target time window of the same operating cycle, the processor 204 outputs the first prompt information.

[0082] The execution cycle can be one cycle in which the processor 204 executes the corresponding signal processing program. In one possible implementation, the processor 204 can be implemented by an MPU board, which can run the configuration file at a fixed cycle.

[0083] The target time window can be the time range within a running cycle used to determine the time relationship between the first input signal and the second input signal. The specific start time, end time, and duration of the target time window can be set according to the program execution mode and signal transmission mode of the processor 204, and this application does not limit this. The processor 204 can determine the current running cycle and the target time window corresponding to the current running cycle, and respectively determine the first transmission period corresponding to the first input signal and the second transmission period corresponding to the second input signal. The first transmission period can include the time range from the start time when the first input signal begins to arrive at the processor 204 to the completion time when the first input signal completely arrives at the processor 204. The second transmission period can include the time range from the start time when the second input signal begins to arrive at the processor 204 to the completion time when the second input signal completely arrives at the processor 204.

[0084] For example, the processor 204 can determine whether the first transmission period and the second transmission period completely fall within the same target time window. The first transmission period completely falling within the target time window may include the start time of the first input signal not being earlier than the window start time of the target time window, and the completion time of the first input signal not being later than the window end time of the target time window. The second transmission period completely falling within the target time window may include the start time of the second input signal not being earlier than the window start time of the target time window, and the completion time of the second input signal not being later than the window end time of the target time window. When the first transmission period is within the target time window of the first running cycle, and the second transmission period is within another running cycle different from the first running cycle, even if the first and second transmission periods respectively satisfy their respective target time windows, the processor 204 can still determine that the first and second input signals do not meet the time conditions of this step.

[0085] When processor 204 determines that both the first input signal and the second input signal meet the target time window conditions, it can output a first prompt message. The first prompt message can be used to indicate that the fault corresponding to the first source signal has been processed.

[0086] In practical applications, the first prompt message can be a signal or status data that characterizes the completion status of fault handling. The specific data format and output method of the first prompt message can be set by the processor 204 according to the output interface and alarm logic of the signal processing system, and this application does not limit this.

[0087] Therefore, the processor 204 simultaneously constrains the first transmission period and the second transmission period within the same target time window in the same operating cycle, and requires that the complete transmission periods of both input signals fall within the target time window. This can reduce the combination and judgment of signal changes across operating cycles and the situation where the transmission period crosses the window boundary, thereby improving the accuracy of the correspondence between the first prompt information and the actual fault handling process.

[0088] It should be noted that the numbering of steps S301 to S307 is mainly used to distinguish different processing steps, and is not intended to require that each step be executed in strict order. While satisfying the data dependencies between steps, the execution order of some steps can be adjusted, and the execution processes of some steps can at least partially overlap in time. For example, after the interface circuit 201 acquires the first source signal, the process of the first sub-signal in the first source signal being transmitted through the first signal chain 202, and the process of the second sub-signal performing logical value extraction, logical NOT operation, and transmission in the second signal chain 203, can be executed at least partially in parallel. The start time and processing duration of the first signal chain 202 and the second signal chain 203 can be different, as long as the time periods for the first input signal and the second input signal to be transmitted to the processor 204 are both within the target time window of the same operating cycle. Step S307 is also not limited to starting only after all steps S302 to S306 have been executed. During the process of receiving the first input signal and the second input signal, the processor 204 can record or determine the transmission time corresponding to the first input signal and the second input signal, and after obtaining the information for judging the time relationship, determine whether the transmission time periods of the first input signal and the second input signal are both within the target time window of the same operating cycle.

[0089] in addition, Figure 3 The illustrated embodiments do not necessarily require all steps to be performed. For example, Figure 3 The following description uses an implementation where the second sub-signal carries a quality bit, and step S305 determines the validity of the corresponding logic value based on the quality bit. The quality bit and the validity determination performed based on it are optional processing methods for the second signal chain 203. In another possible embodiment, the second sub-signal may not carry a quality bit, or the second signal chain 203 may not perform a validity determination based on the quality bit. In this case, after the value-taking circuit 2031 extracts the logic value indicated by the second sub-signal, the logic negation circuit 2032 performs a logic negation operation on that logic value, and the second signal chain 203 transmits the sub-signal after the logic negation operation as the second input signal to the processor 204. Figure 3 The processing related to quality position determination is only used to illustrate one possible implementation, and this application does not limit it. Alternatively, in other embodiments, step S305 may not be required.

[0090] The above embodiments use a first source signal as an example to illustrate the processing procedure of a signal processing system for a single source signal. In practical applications, devices may have multiple faults simultaneously, and the signal processing system needs to be able to process and provide alerts for multiple source signals separately. Therefore, this application also provides extended implementations for multiple source signals.

[0091] Combination Figure 4 Taking the second source signal as an example, this illustrates how the signal processing system processes the second source signal in parallel and outputs the corresponding second prompt information while outputting the first prompt information. Figure 4 The method shown can be applied to Figure 2 The signal processing system shown can also be applied to other applicable signal processing systems, and this application does not limit it.

[0092] S401: Interface circuit 201 acquires the second source signal.

[0093] The second source signal can be another status signal used to characterize whether a fault exists in the device. The second source signal can indicate a change in logic value from a first logic value to a second logic value, and the logic value indicated by the second source signal can be used to characterize whether the device has a fault different from the fault corresponding to the first source signal.

[0094] After the interface circuit 201 acquires the second source signal, different sub-signals in the second source signal can enter the third signal chain and the fourth signal chain respectively. Among them, the first sub-signal of the second source signal transmitted through the third signal chain can be used as the third sub-signal, and the second sub-signal of the second source signal processed by the fourth signal chain can be used as the fourth sub-signal.

[0095] The second source signal and the first source signal may correspond to different fault states, different devices, or different state signals in the same device. This application does not limit this.

[0096] S402: The third signal chain transmits the third input signal, which is a sub-signal of the second source signal.

[0097] The third signal chain can transmit the first sub-signal from the second source signal to the processor 204, whereby the processor 204 receives the first sub-signal as the third input signal. Both the second source signal and the third input signal are used to indicate a change in logic value from a first logic value to a second logic value. In other words, the third signal chain does not need to perform a NOT operation on the third sub-signal to change the logic direction.

[0098] The third signal chain can transmit the third input signal through signal transmission lines, inter-board communication paths, or data transmission paths within the signal processing system; this application does not limit this.

[0099] S403: The value extraction circuit in the fourth signal chain extracts the logic value indicated by the second sub-signal of the second source signal.

[0100] The sub-signal processed by the fourth signal chain in the second source signal can be used as the second sub-signal of the second source signal. The value-taking circuit in the fourth signal chain can perform value-taking processing on the second sub-signal of the second source signal to determine the logic value corresponding to the second sub-signal of the second source signal.

[0101] The value-taking circuit can process the second sub-signal of the second source signal to determine the logic value indicated by the second sub-signal of the second source signal. This logic value can be provided to the logic NOT circuit for subsequent logic NOT operations.

[0102] This application does not limit the specific circuit structure of the value-determining circuit. Where the corresponding logic value can be determined from the second sub-signal of the second source signal, the value-determining circuit may also employ other signal processing structures capable of achieving the same function.

[0103] S404: The NOT circuit in the fourth signal chain performs a NOT operation on a given logical value.

[0104] The NOT circuit in the fourth signal chain can perform a NOT operation on the logic value determined by S403, so that the logic value obtained by the NOT operation is opposite to the logic value determined by S403.

[0105] The fourth input signal transmitted subsequently in the fourth signal chain can have the opposite logical change direction to the third input signal. Specifically, the third input signal indicates a change in logical value from a first logical value to a second logical value, and the fourth input signal indicates a change in logical value from a second logical value to a first logical value.

[0106] S405: The logic value judgment circuit in the fourth signal chain determines whether the logic value is valid based on the quality bit corresponding to the second source signal.

[0107] The fourth signal chain may also include a logic value determination circuit. This logic value determination circuit can be a functional circuit in the fourth signal chain used to determine whether the logic value corresponding to the second source signal is valid.

[0108] The second source signal can indicate a logic value and the corresponding quality bit. The logic value determination circuit can determine the quality bit corresponding to the second source signal and determine whether the corresponding logic value is valid based on the value of the quality bit.

[0109] In one possible implementation, the second source signal can simultaneously indicate a data structure containing both logic values ​​and quality bits. The logic value determination circuit can determine the quality bits from the data indicated by the second source signal and obtain a determination result based on the correspondence between the quality bits and the valid states of the logic values.

[0110] For example, the second source signal can use BS type data. BS type data can include a logic value and a quality bit, wherein the quality bit is used to characterize whether the corresponding logic value is valid. When the quality bit is 0, the quality status can be Good, and the corresponding logic value can be determined to be valid; when the quality bit is 1, the quality status can be BAD, and the corresponding logic value can be determined to be invalid. The above quality bit values ​​and their correspondences are only an example, and this application does not limit the specific encoding method of the quality bits.

[0111] If the logic value corresponding to the quality bit is valid, the fourth signal chain can continue to transmit the fourth input signal. If the logic value corresponding to the quality bit is invalid, the corresponding signal may not be used as a valid fourth input signal in subsequent processing; this application does not impose any limitations on this.

[0112] Thus, the fourth signal chain can exclude signals with invalid logical values ​​before the fourth input signal is transmitted to the processor 204, so that the parallel prompt judgment corresponding to the second source signal is based on valid logical values, thereby reducing the interference of invalid signals on the output of the second prompt information.

[0113] S406: The fourth signal chain transmits the fourth input signal, which is a sub-signal of the second source signal.

[0114] If S405 determines that the corresponding logic value is valid, the fourth signal chain can transmit the fourth input signal to the processor 204.

[0115] The fourth input signal indicates that the logic value changes from the second logic value to the first logic value. The third input signal indicates that the logic value changes from the first logic value to the second logic value; therefore, the third and fourth input signals have opposite directions of logic change.

[0116] Both the third and fourth input signals originate from the second source signal. The third input signal is transmitted to the processor 204 via the third signal chain, and the fourth input signal is transmitted to the processor 204 after undergoing logical value determination and logical NOT operations via the fourth signal chain. The inverse relationship between the two input signals does not depend on two independent external signal sources generating them separately.

[0117] Therefore, both the third and fourth input signals originate from the second source signal, and the fourth input signal forms a logical change direction opposite to that of the third input signal through a logical NOT operation. This can provide input signals with consistent sources and opposite logical directions for judging the faults corresponding to the second source signal, reducing the impact of inconsistent logical relationships between independent external signals on the judgment results.

[0118] S407: During the output of the first prompt information, when the transmission periods of the third input signal and the fourth input signal are both within the target time window of the same operating cycle, the processor 204 outputs the second prompt information in parallel.

[0119] The processor 204 can continue to receive the third input signal and the fourth input signal while outputting the first prompt information according to S307, and determine the transmission time period corresponding to the third input signal and the fourth input signal.

[0120] The processor 204 can determine whether the transmission periods of the third input signal and the fourth input signal are both within the same operating cycle corresponding to the first input signal and the second input signal, and further determine whether the transmission periods of the third input signal and the fourth input signal are both within the target time window of the operating cycle.

[0121] The third and fourth input signals do not necessarily need to be located in the same operating cycle. Instead, they need to be consistent with the operating cycle in which the processing corresponding to the first prompt information is located. The processor 204 can process the input signal corresponding to the first source signal and the input signal corresponding to the second source signal respectively within that operating cycle.

[0122] During the process of processor 204 outputting the first prompt message, when the time periods during which the third input signal is transmitted to processor 204 and the time periods during which the fourth input signal is transmitted to processor 204 both fall within the target time window of the same operating cycle, processor 204 can execute the output operation of the second prompt message in parallel. The second prompt message can be used to indicate that the fault corresponding to the second source signal has been processed.

[0123] In one possible implementation, the processor 204 can begin outputting the second prompt while the first prompt is in the output state, and maintain the output of both the first and second prompts until the output process of the corresponding prompt is complete. Therefore, the output of the second prompt does not need to wait for the output process of the first prompt to finish, and the processor 204 can execute the output operations of the first and second prompts in parallel.

[0124] As an example, processor 204 can process multiple sets of inverse input signals within one operating cycle. When the time periods during which the first and second input signals are transmitted to processor 204 both fall within the target time window of that operating cycle, processor 204 can output a first prompt message. While the first prompt message is being output, when the time periods during which the third and fourth input signals are transmitted to processor 204 also fall within the target time window of the same operating cycle, processor 204 can simultaneously output a second prompt message. The first prompt message indicates that the fault corresponding to the first source signal has been processed, and the second prompt message indicates that the fault corresponding to the second source signal has been processed.

[0125] In this way, the processor 204 can determine the processing completion status of the corresponding fault according to the inverse input signals corresponding to different source signals within the same running cycle, and can output the corresponding prompt information in parallel when the input signals corresponding to multiple faults meet the time conditions. This avoids the fact that the prompt information of the later fault must wait for the output of the previous prompt information before it can be output, so that the processing results of multiple fault states can be prompted separately within the same running cycle.

[0126] It should be noted that the numbering of steps S401 to S407 is mainly used to distinguish different processing steps, and is not intended to require that each step be executed in strict order. While satisfying the data dependencies between steps, the execution order of some steps can be adjusted, and the execution processes of some steps can at least partially overlap in time. For example, after the interface circuit 201 acquires the second source signal, the process of the first sub-signal in the second source signal being transmitted through the third signal chain and the process of the second sub-signal performing logical value extraction, logical NOT operation, and transmission in the fourth signal chain can be executed at least partially in parallel. The start time and processing duration of the third and fourth signal chains can be different, as long as the time periods for the transmission of the third and fourth input signals to the processor 204 are both within the target time window of the same operating cycle. Step S407 is also not limited to starting only after all steps S402 to S406 have been executed. During the process of receiving the third input signal and the fourth input signal, the processor 204 can record or determine the transmission time corresponding to the third input signal and the fourth input signal, and after obtaining the information for judging the time relationship, it can determine whether the transmission periods of the third input signal and the fourth input signal are both within the target time window of the same operating cycle.

[0127] in addition, Figure 4The following description uses an implementation where the second sub-signal carries a quality bit, and step S405 determines the validity of the corresponding logic value based on the quality bit. The quality bit and the validity determination performed based on it are optional processing methods for the fourth signal chain. In another possible embodiment, the second sub-signal may not carry a quality bit, or the fourth signal chain may not perform a validity determination based on the quality bit. After the value-taking circuit extracts the logic value indicated by the second sub-signal, the logic NOT circuit can perform a logic NOT operation on that logic value, and the fourth signal chain transmits the sub-signal after the logic NOT operation as the fourth input signal to the processor 204. This application does not limit whether the fourth signal chain performs a validity determination based on the quality bit.

[0128] Reference Figure 5 , Figure 5 This paper illustrates an interaction diagram between a terminal 50 and a signal processing system according to an embodiment of this application. The following section describes the interaction between the terminal 50 and... Figure 1 The following explanation uses the signal processing system 20 as an example for interaction. The signal processing system 20 may include a main control chassis and an I / O chassis, which can communicate with each other. The terminal 50 can communicate with the signal processing system 20 to realize algorithm logic configuration, download file transfer, and online communication during the operation of the signal processing system 20.

[0129] Terminal 50 can be a computer device equipped with software configuration tools. The software configuration tools can include software functions for configuring different functional modules, among which the alarm algorithm configuration module can be developed based on formal techniques. The alarm algorithm configuration module can provide a graphical configuration interface, and the logical relationships corresponding to the alarm algorithm can be configured graphically.

[0130] In one possible implementation, the alarm algorithm configuration module can be implemented using a formal development language. The formal development language can be Lustre (file system) language, or any other formal development language capable of describing algorithm logic according to preset syntax and semantic rules; this application does not limit this. The software configuration tool can convert and compile the graphically configured algorithm logic according to the syntax and semantic rules corresponding to the formal development language.

[0131] Therefore, software configuration tools can complete the conversion and compilation of graphical algorithm logic according to the syntax and semantic rules of formal development languages, so that the graphical configuration content and the downloaded execution content have a clear conversion relationship, providing a consistent logical basis for the configuration and subsequent execution of alarm algorithm logic.

[0132] After the software configuration tool completes the algorithm logic configuration, it can compile the configuration results to generate the corresponding download file. The download file may include configuration information for configuring the main control chassis and related boards in the input / output (I / O) chassis. The specific configuration information in the download file can be set according to the algorithm logic, board functions, and signal processing requirements, and this application does not impose any limitations on this.

[0133] In one possible implementation, terminal 50 can connect to the MPU board in the main control chassis via a communication link and transfer the generated download file to the MPU board. For example, terminal 50 can establish a communication connection with the MPU board via a network cable and complete the download file transfer through this communication connection. Other communication methods capable of file transfer can also be used between terminal 50 and the MPU board, and this application does not limit this to any particular method.

[0134] After receiving the downloaded file, the MPU board can complete the configuration corresponding to its own function based on the configuration information in the downloaded file. The MPU board can also transmit the configuration information corresponding to the signal conditioning unit (SCU) board and the corresponding boards in the I / O chassis to the corresponding boards based on the configuration information in the downloaded file. The SCU board and I / O board complete the configuration based on the received corresponding configuration information.

[0135] In one possible implementation, the downloaded file may include configuration information corresponding to the MPU board, SCU board, and I / O board, respectively. The MPU board can configure the relevant boards in the main control chassis and I / O chassis according to the configuration information corresponding to each board. The specific configuration content corresponding to different boards can be set according to the signal acquisition, signal processing, communication, or output functions undertaken by the corresponding board; this application does not limit this.

[0136] In this way, the downloaded files can be received uniformly by the MPU board, and the MPU board can transmit the configuration information corresponding to different boards to the SCU board and I / O board respectively. This allows the relevant boards in the main control chassis and I / O chassis to complete the corresponding configuration based on the same algorithm configuration result, thereby reducing the situation where the configuration content is inconsistent when the relevant boards are configured separately.

[0137] After downloading and configuring, the MPU board can execute the algorithm logic corresponding to the downloaded file according to the pre-set runtime cycle. During the execution of the algorithm logic, the MPU board can interact with the SCU board and the I / O boards in the I / O chassis to obtain corresponding input signals or transmit corresponding processing results.

[0138] In this way, the MPU board executes the algorithm logic corresponding to the downloaded file according to the pre-set operating cycle, which can provide a unified time reference for whether multiple input signals are in the same operating cycle, thereby improving the determinism of the timing of prompt information output.

[0139] In one possible implementation, terminal 50 can also interact online with signal processing system 20. During the execution of the downloaded file, signal processing system 20 can provide operational status data to terminal 50. Terminal 50 can then display the operational status of the algorithm logic and the operational information of related boards based on the received operational status data.

[0140] Therefore, the terminal 50 can obtain the algorithm logic and related board operation information during the execution of the downloaded file in the signal processing system 20, making the execution process of the downloaded algorithm observable and providing information for algorithm debugging and operation inspection.

[0141] In this way, terminal 50 can complete the graphical configuration, compilation and download of alarm algorithm logic. MPU board can complete the configuration of itself and related boards according to the downloaded file, and execute the corresponding algorithm logic according to the preset running cycle. The graphically configured alarm algorithm can run in signal processing system 20 according to the corresponding algorithm logic.

[0142] Reference Figure 6 , Figure 6 A timing diagram of an alarm information output in an embodiment of this application is shown. Figure 6 It can be used to describe the timing relationship between each input signal and the alarm output signal when the processor executes the alarm algorithm logic. Figure 6 The alarm (alarm1, A1) in the code can represent the alarm trigger signal corresponding to the first source signal, the alarm indication output (alarmannunciation, AA) can represent the alarm output signal corresponding to the alarm information output by the processor, the local acknowledgment (localacknowledge, LACK) can represent the lamp acknowledgment signal, and the lamp reset signal (Lamp Reset Signal, LARE) can represent the lamp reset signal.

[0143] For ease of explanation, we can denote the moment when LACK generates a valid trigger as t1, and the moment when A1 changes from an active state to an inactive state and LARE generates a valid trigger as t2. The signal changes before and after time t1 and t2 are explained below.

[0144] Before time t1, A1 can change from an invalid state to a valid state. In one possible implementation, this state change can correspond to a change in the logic value indicated by the first source signal from a second logic value to a first logic value. After detecting this logic value change, the processor can output a first alarm message. The first alarm message is used to indicate that the alarm state corresponding to the first source signal has not been manually confirmed.

[0145] In one possible implementation, when the second logic value corresponds to a low level and the first logic value corresponds to a high level, the change of A1 from an invalid state to an valid state can be manifested as a rising edge change. The above correspondence between the high and low levels and the first and second logic values ​​is only an example, and this application does not limit the specific level states corresponding to the first and second logic values.

[0146] As an example, the first alarm message can be represented by the AA outputting flashing pulses at a first frequency. The first frequency can be set according to the alarm prompting method, the processor's operating configuration, or actual application requirements; this application does not limit the specific value of the first frequency. For example, the first frequency can be 2Hz.

[0147] At time t1, the lamp confirmation switch is manually triggered, and the lamp confirmation circuit generates a LACK. The LACK can be a rising-edge valid pulse signal. After receiving the LACK, the processor can determine that the alarm status corresponding to the first source signal has been manually confirmed and outputs a second alarm message. The second alarm message indicates that the fault corresponding to the first source signal is being processed.

[0148] In one possible implementation, when the processor outputs the second alarm information, it can adjust AA from a state of outputting flashing pulses at the first frequency to a continuously active state. After time t1 and before time t2, A1 can remain active, and AA can remain continuously active, to distinguish it from the flashing output state when the alarm state has not yet been manually confirmed.

[0149] At time t2, A1 can change from a valid state to an invalid state, and simultaneously, LARE can generate a valid trigger. The state change of A1 corresponds to a change in the logical value indicated by the first source signal from a first logical value to a second logical value. After this logical value change occurs in the first source signal, the first sub-signal in the first source signal can be transmitted to the processor via the first signal chain. The first input signal received by the processor correspondingly indicates a change in the logical value from the first logical value to the second logical value. The second sub-signal in the first source signal can undergo logical value extraction and logical NOT operations via the second signal chain. The second input signal received by the processor correspondingly indicates a change in the logical value from the second logical value to the first logical value.

[0150] In one possible implementation, when the first logic value corresponds to a high level and the second logic value corresponds to a low level, the change of the first source signal from the first logic value to the second logic value at time t2 can be represented by a falling edge change. The first input signal can correspondingly represent a falling edge change. After the second signal chain 203 performs a logical NOT operation on the logic value corresponding to the second sub-signal, the second input signal can correspondingly represent a rising edge change. Therefore, in this implementation, the falling edge of the first input signal and the rising edge of the second input signal can respectively characterize the logic value changes generated by the two inverse input signals near t2.

[0151] In one possible implementation, the start time of the first input signal arriving at the processor and the completion time of its arrival at the processor can both fall within the target time window, as can the start time of the second input signal arriving at the processor and the completion time of its arrival at the processor. Therefore, the changes in the logic values ​​corresponding to the first and second input signals can participate in the fault handling completion determination within the same operating cycle. In other words, the processor does not determine that the fault corresponding to the first source signal has been handled solely based on the change of A1 from a valid state to an invalid state at time t2. The processor can also determine whether to output a first prompt message based on whether the first and second input signals obtained from the same first source signal have corresponding inverse logic changes, and whether the transmission periods of the two input signals both fall within the target time window of the same operating cycle.

[0152] Specifically, if the time intervals during which the first input signal and the second input signal are transmitted to the processor both fall within the target time window of the same operating cycle, the processor can output a first prompt message. The first prompt message can be used to indicate that the fault corresponding to the first source signal has been resolved. If the first input signal and the second input signal do not simultaneously satisfy the above-mentioned time relationship, the processor 204 may not output the first prompt message based on the two input signals in this instance.

[0153] As an example, the first prompt message can be represented by adjusting the output state of the AA (Automatic Input Array). When the processor outputs the first prompt message, the AA can be adjusted from a continuously active state to output flashing pulses at a second frequency. The specific value of the second frequency is not limited. For example, the second frequency can be 0.5Hz. Therefore, after the first input signal and the second input signal satisfy the above logical and timing relationships, the AA can output flashing pulses at the second frequency to indicate that the fault corresponding to the first source signal has been processed.

[0154] The specific values ​​of the first and second frequencies are merely examples. In practical applications, the first and second frequencies can be set according to the alarm logic, the prompting method, and the operating configuration of the signal processing system; this application does not impose any limitations on this.

[0155] In this way, the processor can distinguish different processing stages, such as alarm status not yet confirmed, fault being processed, and fault processing completed, based on different AA output states. It then outputs a corresponding fault processing completion notification after the first and second input signals meet the target time window conditions within the same operating cycle. Since different processing stages correspond to different AA output states, the signal processing system can determine the corresponding alarm processing stage based on the current output state of the AA, reducing the possibility of state confusion between different alarm processing stages. Furthermore, the fault processing completion notification needs to be generated after the two mutually inverse input signals meet the corresponding time conditions, reducing the likelihood of determining fault processing completion based solely on the state change of a single alarm signal, thereby improving the accuracy of fault processing completion status judgment and notification.

[0156] Reference Figure 7 , Figure 7 A simulation and debugging diagram of an alarm algorithm according to an embodiment of this application is shown. After the software configuration tool in the terminal completes the alarm algorithm logic configuration, the configured alarm algorithm logic can be simulated and debugged before downloading the corresponding configuration file. The software configuration tool can simulate the input states corresponding to different alarm processing stages by setting logic values ​​and quality bits to the input variables bound to the alarm algorithm logic, and determine whether the configured alarm algorithm logic runs as expected by observing the changes in the output variables corresponding to the alarm algorithm logic.

[0157] Figure 7The alarm algorithm structure shown may include a logic value extraction module 701, a logic NOT module 702, a quality bit extraction module 703, a logic value judgment module 704, and a processor 705. The processor 705 can receive A1, LACK, alarm acknowledge (HACK), lamp test (LTST), and a second input signal formed after processing by the aforementioned modules, and can output a first prompt message and a horn alarm variable. Here, A1 can represent the alarm trigger state, LACK can represent the lamp acknowledge signal, LARE can represent the lamp reset signal, and AA can represent the alarm output signal. HACK can represent the input related to alarm sound reset, LTST can represent the input related to lamp test, and HOAPP can represent the output corresponding to the alarm sound. This embodiment mainly focuses on simulating and debugging the processing relationship between A1, LACK, LARE, and AA. Other inputs and outputs can be simulated in the same or similar ways according to the corresponding alarm functions, and this application does not limit this.

[0158] In one possible implementation, the software configuration tool can represent the variables participating in the simulation using data that includes both logical values ​​and quality bits. The logical value characterizes the current state of the corresponding variable, and the quality bit characterizes whether the logical value is valid. For example, A1, LACK, LARE, and AA can use BS type data. BS type data can include both logical values ​​and quality bits. A quality bit of 0 indicates a quality status of "Good" and a valid logical value; a quality bit of 1 indicates a quality status of "BAD" and an invalid logical value.

[0159] In this application, BS type data can be represented using a combination of logical values ​​and quality bits. For example, in 1@0, the value 1 before the @ symbol can represent a logical value of 1, and the value 0 after the @ symbol can represent a quality bit of 0 and a quality status of Good. Correspondingly, 0@0 can represent a logical value of 0 and a valid logical value. The above data representation and the specific values ​​of the logical values ​​and quality bits are merely examples and are not limited in this application. The specific encoding method used for the quality bits and the specific values ​​corresponding to the valid status are not limited.

[0160] In one possible implementation, the software configuration tool can also configure a parameter dt to characterize the alarm algorithm's execution cycle. The parameter dt can be used to determine the execution cycle corresponding to the processor 705 executing the alarm algorithm logic once. For example, dt can use milliseconds as the time unit, and dt can be greater than 0 and not greater than 250 milliseconds. The specific value of the parameter dt can be set according to the processor performance, the alarm algorithm logic, and testing requirements; this application does not limit this. If the alarm algorithm logic subsequently runs on the MPU board, the parameter dt can correspond to the execution cycle of the alarm algorithm logic on the MPU board once.

[0161] This embodiment provides an example of alarm algorithm simulation and debugging. The software configuration tool can sequentially simulate the state changes of the first source signal, the triggering of the lamp confirmation signal, and the recovery of the first source signal, and determine the processing result of the alarm algorithm logic based on the changes of A1, LACK, LARE, and AA.

[0162] In the first debugging phase, the software configuration tool can force the simulation input corresponding to the first source signal to change its logic value from the second logic value to the first logic value, and make the corresponding quality bit valid. As an example, the second logic value can be 0, the first logic value can be 1, the quality bit can be 0 and the corresponding quality state can be Good, and the simulation input corresponding to the first source signal can be represented as 1@0. After the simulation input corresponding to the first source signal undergoes the above change, one channel of the first source signal can directly form A1 and be transmitted to the processor 705. A1 can change from 0 to 1 and generate a rising edge. This rising edge can be used to simulate the occurrence of the alarm state corresponding to the first source signal. When the processor 705 executes the corresponding alarm algorithm logic, it can output the first alarm information based on the state change of the first source signal from the second logic value to the first logic value. The first alarm information can be used to indicate that the alarm state corresponding to the first source signal has not been manually confirmed.

[0163] In the second debugging phase, the software configuration tool can force the simulation input corresponding to LACK to change from an invalid state to an valid state, and then back to an invalid state, thereby simulating the lamp confirmation signal generated after the lamp confirmation switch is triggered.

[0164] As an example, the software configuration tool can control the logic value corresponding to LACK to change in the order of 0, 1, 0. During the logic value change, LACK generates a pulse signal containing a rising edge. The quality bit of LACK can remain valid during this process. In actual operation, when the lamp confirmation switch is manually triggered, the lamp confirmation circuit 40 can generate LACK. After receiving LACK, the processor 705 can determine that the alarm status corresponding to the first source signal has been manually confirmed and output a second alarm message. The second alarm message can be used to indicate that the fault corresponding to the first source signal is being processed.

[0165] In the third debugging phase, the software configuration tool can again force the simulation input corresponding to the first source signal to change from the first logic value to the second logic value, while maintaining the validity of the corresponding quality bit characterization logic value. As an example, the logic value corresponding to the first source signal can change from 1 to 0, and A1 can correspondingly change from 1 to 0. Thus, the simulation input corresponding to the first source signal can change from 1@0 to 0@0. Simultaneously, LARE can change from 0 to 1, triggering the analog lamp reset signal. After the first source signal undergoes a state change from the first logic value to the second logic value, the logic value extraction module 701 can extract the logic value corresponding to the first source signal, and the logic NOT module 702 can perform a logic NOT operation on the logic value extracted by the logic value extraction module 701. The logic value obtained by the logic NOT operation is opposite to the current logic value of the first source signal, thereby forming a second input signal with the opposite direction of the logic change corresponding to A1. The logic value extraction module 701 and the logic NOT module 702 can respectively correspond to the logic value extraction function and the logic NOT processing function in the aforementioned second signal chain 203. The quality bit extraction module 703 can extract the quality bit corresponding to the first source signal and transmit it to the logic value judgment module 704. The logic value judgment module 704 can determine whether the logic value obtained by the logic NOT module 702 is valid based on the quality bit. If the quality bit indicates a valid logic value, the logic value judgment module 704 can transmit the corresponding second input signal to the processor 705; if the quality bit indicates an invalid logic value, the corresponding signal can be excluded from subsequent judgments as a valid second input signal. Therefore, Figure 7 The quality bit extraction module 703 and the logic value judgment module 704 can be used to implement the aforementioned quality bit extraction and logic value validity judgment.

[0166] As an example, when the first logic value is 1 and the second logic value is 0, the first input signal can exhibit a falling edge change, and the second input signal, after being processed by the logic NOT module 702, can exhibit a rising edge change. The processor 705 can receive the first input signal and the second input signal determined to be valid by the logic value judgment module 704, and further determine whether the transmission periods corresponding to the first and second input signals are both within the target time window of the same operating cycle. This operating cycle can correspond to the alarm algorithm operating cycle defined by the aforementioned parameter dt. When the transmission periods of the first and second input signals are both within the target time window of the same operating cycle, the processor 705 can output a first prompt message, which can be used to indicate that the fault corresponding to the first source signal has been processed. Therefore, this stage can simultaneously verify whether the logic value extraction, logic NOT processing, quality bit judgment, and time condition judgment within the same operating cycle meet expectations.

[0167] In the fourth debugging phase, the software configuration tool can observe the AA output status and corresponding quality status corresponding to the first prompt message output by the processor 705. If the aforementioned simulation inputs change in a predetermined order and the corresponding quality bit remains valid, the AA can switch between Boolean true and Boolean false values ​​according to different alarm processing stages, and the quality status corresponding to the AA can remain "Good". The software configuration tool can determine the simulation debugging result based on whether the AA's status change conforms to the pre-configured alarm algorithm logic.

[0168] As an example, the software configuration tool can also observe the flashing frequency, continuous active status, or other output states of the alarm response (AA). Different alarm processing stages can correspond to different AA output states, and this application does not limit the specific output method.

[0169] Thus, before the alarm algorithm logic is installed, the software configuration tool can verify the processor 705's processing of the alarm trigger signal and the lamp confirmation signal by setting the logic value and quality bit of the simulation input, and verify the formation and validity judgment of the second input signal by the logic value extraction module 701, the logic NOT module 702, the quality bit extraction module 703, and the logic value judgment module 704. The processor 705 can also output a first prompt message when the two input signals meet the time conditions within the same operating cycle. The software configuration tool can judge whether the corresponding processing result meets expectations by observing the output changes of AA. Since the above simulation process covers multiple processing stages such as alarm triggering, lamp confirmation, fault recovery, and fault handling completion judgment, the software configuration tool can determine whether the input-output relationship of each processing stage meets expectations before the alarm algorithm logic is installed onto the MPU board, thereby reducing the possibility of alarm algorithm logic that does not meet expectations entering the actual operating environment.

[0170] Reference Figure 8 , Figure 8 A schematic diagram of the hardware structure of an alarm testing system according to an embodiment of this application is shown. This alarm testing system can be used to perform actual signal injection tests on the alarm algorithm logic executed by the processor and to verify whether the alarm output results meet expectations. The alarm testing system may include a signal processing system 800 and a notification terminal 830. The notification terminal 830 can be a test instrument, oscilloscope, or other test device capable of displaying the alarm output status.

[0171] The signal processing system 800 may include an I / O chassis 810 and a main control chassis 820. The I / O chassis 810 can accommodate a cascading style sheet (CSS) board 811, digital input (DI1) boards 812 and DI2 boards 813, and a digital output (DO) board 814. The main control chassis 820 can accommodate an SCU board 821 and an MPU board 822. The alarm algorithm logic software can run on the MPU board 822 to implement the logic processing corresponding to the alarm algorithm.

[0172] The I / O chassis 810 can accommodate CSS board 811, DI1 board 812, DI2 board 813, and DO board 814. The main control chassis 820 can accommodate SCU board 821 and MPU board 822. The specific number of these boards and their installation positions in the corresponding chassis can be configured according to the test system structure, and this application does not impose any limitations on this.

[0173] The DI1 board 812 can be used to receive the alarm trigger input corresponding to the first source signal and the input corresponding to the lamp reset signal LARE. In one possible implementation, the DI1 board 812 can be connected to the circuit breaker 1, and the state change of the circuit breaker 1 can be used to inject a corresponding test signal into the DI1 board 812. The alarm trigger input corresponding to the first source signal can trigger A1 to generate a corresponding logic value change, and when the circuit breaker 1 further undergoes a corresponding state change, the lamp reset signal LARE can also generate a corresponding trigger.

[0174] The DI2 board 813 can be used to receive test inputs corresponding to the LACK. In one possible implementation, the DI2 board 813 can be connected to the circuit breaker 2. The state change of the circuit breaker 2 can be used to inject a lamp confirmation test signal into the DI2 board 813, and the LACK generates a corresponding pulse change based on the lamp confirmation test signal.

[0175] The DO board 814 can be used to receive the alarm output result generated by the MPU board 822 after executing the alarm algorithm logic, and output the alarm output result to the prompt terminal 830. In one possible implementation, the alarm output result can correspond to the aforementioned AA. The prompt terminal 830 can be an oscilloscope, and the DO board 814 can transmit the alarm output signal corresponding to AA to the oscilloscope so that the waveform changes of the alarm output signal can be observed through the oscilloscope.

[0176] The CSS board 811 can be used to transmit alarm input signals and alarm output signals between the I / O chassis 810 and the main control chassis 820. The SCU board 821 can be used to realize communication between the main control chassis 820 and the I / O chassis 810, and can also interact with the MPU board 822. Thus, the test input received by the I / O chassis 810 can be transmitted to the MPU board 822 via the CSS board 811 and the SCU board 821, and the processing results generated by the MPU board 822 can also be transmitted to the DO board 814 in the I / O chassis 810 via the corresponding communication path.

[0177] MPU board 822 can be used to execute alarm algorithm logic. Based on the first source signal, lamp confirmation signal, and other relevant inputs from the I / O chassis 810, MPU board 822 can perform alarm status judgment and generate corresponding alarm or prompt information. The alarm output generated by MPU board 822 can be output to the prompt terminal 830 via DO board 814.

[0178] Based on the aforementioned hardware structure, the alarm testing system can be used to implement the actual testing process of alarm testing methods. This testing process can include setting up the test environment, injecting test signals, and observing test results.

[0179] During the test environment setup phase, the alarm test system may include an I / O chassis 110 equipped with DI1 board 812, DI2 board 813, and DO board 814, and a main control chassis 820 equipped with MPU board 822 and SCU board 821. CSS board 811 can be connected to SCU board 821 via a communication link. As an example, CSS board 811 and SCU board 821 can be connected via a network cable to enable communication between the I / O chassis 810 and the main control chassis 120. DI1 board 812 can be connected to circuit breaker 1, DI2 board 813 can be connected to circuit breaker 2, and DO board 814 can be connected to a notification terminal 830. The notification terminal 830 can be an oscilloscope for observing the alarm output waveform.

[0180] In one possible implementation, after the prompting terminal 830 completes the alarm algorithm logic configuration and generates a download file, the download file can be transmitted to the MPU board 822. Upon receiving the download file, the MPU board 822 can complete its own configuration based on the configuration information in the download file, and configure the corresponding information of other boards to the SCU board 821 and the corresponding boards in the I / O chassis 810. To make the download configuration effective, the main control chassis 820 and the I / O chassis 810 can be powered off and restarted. After both chassis restart and operate normally, the alarm test system can begin injecting actual test signals.

[0181] During the test signal injection phase, circuit breaker 1 can first be changed from an open state to a closed state. After this change, DI1 board 812 can provide a test input corresponding to the first source signal to the alarm algorithm logic of MPU board 822. A1 changes from 0 to 1 based on this test input and generates a rising edge trigger signal. When the processor executes the alarm algorithm logic, it can output the first alarm information based on this state change to indicate that an alarm state has occurred but has not yet been manually confirmed.

[0182] Subsequently, circuit breaker 2 can change from an open state to a closed state, and then back to an open state. After the circuit breaker 2 undergoes these changes, DI2 board 813 can provide a test input corresponding to LACK to the alarm algorithm logic of MPU board 822. LACK changes from 0 to 1 and then from 1 to 0 based on this test input, generating a series of pulse trigger signals containing rising edges. After receiving LACK, the processor can output a second alarm message to indicate that the corresponding fault is being processed.

[0183] Next, circuit breaker 1 can change from a closed state to an open state. After this change, the test input corresponding to the first source signal can be restored from an active state to an inactive state, and A1 changes from 1 to 0 according to this test input. Simultaneously, the lamp reset signal LARE can be triggered. At this time, the first sub-signal in the first source signal can be transmitted to the processor through the first signal chain, and the first input signal received by the processor can indicate that the logic value changes from the first logic value to the second logic value. The second sub-signal in the first source signal can be extracted and subjected to logical NOT operations through the second signal chain, and the second input signal received by the processor can indicate that the logic value changes from the second logic value to the first logic value. The processor can further determine whether the time periods for the transmission of the first and second input signals to the processor are both within the target time window of the same operating cycle. When both the first and second input signals meet this time condition, the processor can output a first prompt message, which can be used to indicate that the fault corresponding to the first source signal has been processed.

[0184] During the test result observation phase, the prompt terminal 830 can display the alarm output signal from the DO board 814 for observation. As an example, if the prompt terminal 830 is an oscilloscope, the oscilloscope can display the waveform output by the DO board 814. When the first input signal and the second input signal satisfy the aforementioned logical and timing relationships, the alarm output signal from the DO board 814 can be represented as a flashing pulse output at a second frequency. For example, the second frequency can be 0.5Hz. When the prompt terminal 830 displays a 0.5Hz flashing pulse signal, it indicates that the alarm algorithm logic has output the corresponding first prompt information based on the recovery of the state of the first source signal and the condition that the two mutually inverse input signals meet the target time window within the same operating cycle.

[0185] In this way, the alarm test system can verify the running results of the alarm algorithm logic under actual board communication link and signal input and output conditions, and can judge whether the fault handling completion prompt meets expectations based on the output waveform displayed by the prompt terminal 830, thereby further verifying the execution results of the alarm algorithm logic in the actual hardware environment.

[0186] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application. Any equivalent substitutions, modifications, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A signal processing method, characterized in that, The method is applied to a signal processing system, which includes an interface circuit and a processor. The interface circuit and the processor are connected via multiple signal chains, including a first signal chain and a second signal chain. The method includes: The interface circuit acquires a first source signal, which is used to indicate that the logic value changes from a first logic value to a second logic value. The first logic value and the second logic value are different values ​​in binary logic. The logic value indicated by the first source signal is used to characterize whether the device has a fault. The processor receives a first input signal, which is a sub-signal of the first source signal transmitted to the processor through the first signal chain. The first input signal is used to indicate that the logic value changes from the first logic value to the second logic value. The processor receives a second input signal, which is a sub-signal of the first source signal that has undergone logical value extraction and logical NOT operation on the second signal chain and is transmitted to the processor. The second input signal is used to indicate that the logical value changes from the second logical value to the first logical value. The second signal chain includes a value-taking circuit and a logical NOT circuit. The value-taking circuit is used to determine the logical value according to the first source signal, and the logical NOT circuit is used to perform a logical NOT operation on the logical value determined by the value-taking circuit. When the time periods during which the first input signal and the second input signal are transmitted to the processor are both within the target time window of the same operating cycle, the processor outputs a first prompt message, which indicates that the fault corresponding to the first source signal has been processed.

2. The method according to claim 1, characterized in that, The second signal chain further includes a logic value judgment circuit, which is used to determine whether the logic value indicated by the second input signal is valid, and the second input signal received by the processor is a second input signal with a valid logic value.

3. The method according to claim 2, characterized in that, The logic value determination circuit is used to determine the quality bit corresponding to the first source signal, and the quality bit is used to characterize whether the logic value of the first source signal is valid. If the quality bit indicates that the logic value is valid, the second input signal is output.

4. The method according to claim 1, characterized in that, The start time of the first input signal and the completion time of the second input signal arriving at the processor are both within the target time window.

5. The method according to claim 1, characterized in that, The method also includes a third signal chain and a fourth signal chain, and further includes: The interface circuit acquires a second source signal, which is used to indicate that the logic value changes from the first logic value to the second logic value. The logic value indicated by the second source signal is used to characterize whether the device has a fault. The processor receives a third input signal, which is a sub-signal of the second source signal transmitted to the processor through the third signal chain. The third input signal is used to indicate that the logic value changes from the first logic value to the second logic value. The processor receives a fourth input signal, which is a sub-signal of the second source signal that has undergone logical value extraction and logical NOT operation on the fourth signal chain and then transmitted to the processor. The fourth input signal is used to indicate that the logical value changes from the second logical value to the first logical value. The fourth signal chain includes a value-taking circuit and a logical NOT circuit. The value-taking circuit in the fourth signal chain is used to determine the logical value according to the second source signal, and the logical NOT circuit in the fourth signal chain is used to perform a logical NOT operation on the logical value determined by the value-taking circuit in the fourth signal chain. While the processor is outputting the first prompt information, and if the time periods during which the third input signal and the fourth input signal are transmitted to the processor are both within the target time window of the same operating cycle, the processor also performs the operation of outputting the second prompt information in parallel. The second prompt information is used to indicate that the fault corresponding to the second source signal has been processed.

6. The method according to claim 5, characterized in that, The signal processing system also includes a terminal; The method further includes: When the transmission periods of the first input signal, the second input signal, the third input signal, and the fourth input signal are all within the same operating cycle, the terminal displays a fault record in the terminal's interactive interface, and the fault record includes the faults that have occurred in the device.

7. The method according to claim 1, characterized in that, The signal processing system also includes a lamp confirmation circuit, which includes a lamp confirmation switch. Before the processor receives the first input signal, the method further includes: When the logic value of the first source signal changes from the second logic value to the first logic value, the processor outputs a first alarm message, which is used to indicate that the alarm status corresponding to the first source signal has not been manually confirmed. When the lamp confirmation switch is manually triggered, the lamp confirmation circuit generates a lamp confirmation signal, which is used to indicate that the alarm status corresponding to the first source signal has been manually confirmed. When the processor receives the light confirmation signal, the processor outputs a second alarm message, which indicates that the fault corresponding to the first source signal is being processed.

8. The method according to any one of claims 1 to 7, characterized in that, The signal processing system is a microprocessor unit (MPU).

9. A signal processing system, characterized in that, The signal processing system includes an interface circuit and a processor. The interface circuit and the processor are connected through multiple signal chains, including a first signal chain and a second signal chain. The interface circuit is used to acquire a first source signal, which is used to indicate that a logic value changes from a first logic value to a second logic value. The first logic value and the second logic value are different values ​​in binary logic. The logic value indicated by the first source signal is used to characterize whether the device has a fault. The processor is configured to receive a first input signal and a second input signal. The first input signal is a sub-signal of the first source signal transmitted to the processor via the first signal chain. The first input signal is used to indicate that a logic value changes from a first logic value to a second logic value. The second input signal is a sub-signal of the first source signal that has undergone logic value extraction and logic NOT operation on the second signal chain and is transmitted to the processor. The second input signal is used to indicate that a logic value changes from the second logic value to the first logic value. The second signal chain includes a value-taking circuit and a logic NOT circuit. The value-taking circuit is used to determine a logic value based on the first source signal, and the logic NOT circuit is used to perform a logic NOT operation on the logic value determined by the value-taking circuit. The processor is further configured to output a first prompt message when the time periods during which the first input signal and the second input signal are transmitted to the processor are both within the same operating cycle target time window. The first prompt message is used to indicate that the fault corresponding to the first source signal has been processed.

10. The signal processing system according to claim 9, characterized in that, The start time of the first input signal and the completion time of the second input signal arriving at the processor are both within the target time window.

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