Method for transmitting data blocks using data pipes of programmable logic controllers

Abstract

A method for transferring a plurality of data messages from a first programmable logic controller to a second programmable logic controller using a data pipe. The method includes generating a pipe output header within the first programmable logic controller, determining whether a data block of the plurality of data messages has been modified, transferring the plurality of data messages over the data pipe, determining that the second programmable logic controller has successfully received the plurality of data messages using the header, and storing the data of the plurality of data messages in memory of the second programmable logic controller. The data pipe includes a plurality of data that transfers the plurality of data messages from the first programmable logic controller to the second programmable logic controller, and vice versa, both having a maximum available pipe space of 8,000 bytes, and each can have up to 20 data segments.

Description

Technical Field

[0001] This disclosure relates to a dynamically configurable bidirectional multi-segment data pipeline for a programmable logic controller. Background Technology

[0002] A data pipeline comprises a series of processes for transferring and modifying data from one programmable logic controller (PLC) to another. However, current data pipelines rely on fixed data structures for producer-consumer data connections, which limits flexibility by requiring software changes to add or remove data, and are limited by a 500-byte bandwidth constraint due to the use of the Ethernet industry protocol. These limitations have become a bottleneck for the amount of data that can be transferred and modified through a data pipeline over time, meaning that larger data loads to be transferred through a data pipeline may take a significant amount of time to complete.

[0003] Therefore, while current data pipelines achieve their intended purpose, a new and improved system and approach are still needed for transferring data between data pipelines without fixed data structures and 500-byte bandwidth limitations. Summary of the Invention

[0004] According to several aspects, a method is provided for transmitting multiple data messages via a data pipeline between a first programmable logic controller (PLC) and a second PLC having memory tags. The method may include establishing a data pipeline having a pipeline input array, a pipeline output array, multiple data segments, and a pipeline size, wherein the pipeline input array has a pipeline input header, and the pipeline output array has a pipeline output header. The method may further include generating multiple data messages having block headers and data blocks. The method may further include loading the block headers into the pipeline output headers of the pipeline output array. The method may further include comparing the data blocks of the multiple data messages with stored data blocks stored in the memory tag. The method may further include determining, based on the comparison between the data block and the stored data block, that the data block is different from the stored data block. The method may further include determining that the size of the data block is smaller than the available pipeline space of the pipeline output array of the data pipeline. The method may further include loading the data block into the pipeline output array when the data block is different from the stored data block and the size of the data block is smaller than the available pipeline space of the data pipeline. The method may further include copying the data block to the memory tag. The method may further include transmitting the block header from the pipe output head of the pipe output array to the pipe input head of the pipe input array via the data pipe through the plurality of data segments, and transmitting the data block from the pipe output array to the pipe input array via the data pipe through the plurality of data segments.

[0005] In an additional aspect of this disclosure, the method may further include transmitting the plurality of data messages between a first programmable logic controller having a memory tag operable within an automated guided vehicle and a second programmable logic controller operable within an automated workstation via the data pipeline.

[0006] In another aspect of this disclosure, the method may further include generating a block header containing a record ID that allows the data pipeline to track the data block.

[0007] In an additional aspect of this disclosure, the method may further include refreshing the pipe output head when the first programmable logic controller cannot find the record ID of the block head.

[0008] In another aspect of this disclosure, the method may further include removing a plurality of loaded heads from the pipe output head and loading the block head into the pipe output head.

[0009] In an additional aspect of this disclosure, the method may further include determining, based on a comparison of the data block with the stored data block, that the data block is similar to the stored data block, and either continuously or based on a state change of the data block, transferring the data block in the pipeline output array from the pipeline output array to the pipeline input array via the multiple data segments through the data pipeline.

[0010] In another aspect of this disclosure, the method may further include determining the available pipeline space as the space in the pipeline output array that is not occupied by the block header or the data block.

[0011] In an additional aspect of this disclosure, the method may also include determining that the maximum available pipeline space is 400 times the number of data segments in the plurality of data segments, and can be up to 8,000 bytes.

[0012] In another aspect of this disclosure, the method may further include setting the queue bit of the record in the block header to true when the size of the data block is greater than the available pipeline space, thereby preventing the data block from being loaded into the pipeline output array.

[0013] In an additional aspect of this disclosure, the method may further include setting the queue bit of the record in the block header to false when the size of the data block is less than or equal to the available pipeline space, thereby allowing the data block to be loaded into the pipeline output array.

[0014] In another aspect of this disclosure, the method may further include copying the data block to a memory tag when the data block is configured to be transferred across a data pipeline based on a change in the state of the data block.

[0015] In another aspect of this disclosure, the method may further include: transmitting a block header and a data block via a plurality of data segments having up to 20 data segments.

[0016] According to several aspects, a method is provided for storing a header and a data block, transmitted across a data pipeline by a first programmable logic controller (PLC), into a second PLC having a plurality of target tags. The method may include establishing a data pipeline having a pipeline input array, a pipeline output array, and a plurality of data segments, wherein the pipeline input array has a pipeline input header and the pipeline output array has a pipeline output header. The method may further include receiving the header from the pipeline output header of the pipeline output array to the pipeline input header of the pipeline input array across the data pipeline via the plurality of data segments, and receiving the data block from the pipeline output array to the pipeline input array. The method may further include determining that the pipeline input array has successfully received the header and the data block. The method may further include storing the data block into one of the plurality of target tags.

[0017] In another aspect of this disclosure, the method may further include: determining that block headers and data blocks have been synchronized within the multiple data segments by determining that the transaction IDs of each of the multiple data segments are similar to each other.

[0018] In another aspect of this disclosure, the method may also include locating a record ID of the block head in the pipe input head.

[0019] In another aspect of this disclosure, the method may further include: determining that the pipe input array has not successfully received a block header by a record ID of a block header that fails to be located in the pipe input header, and clearing the data blocks in multiple target labels.

[0020] In another aspect of this disclosure, the method may further include determining that the space occupied by the data blocks and block headers within the pipeline input array is similar to the space occupied by a plurality of temporary data within a temporary data array of a second programmable logic controller.

[0021] In another aspect of this disclosure, the method may further include determining that the value of the record locator or record length of the data block is not zero.

[0022] According to several aspects, a method is provided for transferring multiple data messages having block headers and data blocks across a data pipeline between a first programmable logic controller having memory tags and a second programmable logic controller having multiple target tags, and storing the block headers and data blocks into the multiple target tags. The method may include establishing a data pipeline having a pipeline input array, a pipeline output array, multiple data segments having up to 20 data segments, and a pipeline size, wherein the pipeline input array has a pipeline input header and the pipeline output array has a pipeline output header. The method may further include generating multiple data messages having block headers and data blocks. The method may further include loading the block header into the pipeline output header of the pipeline output array. The method may further include comparing the data blocks of the multiple data messages with stored data blocks stored in the memory tags. The method may further include determining, based on the comparison between the data block and the stored data block, that the data block is different from the stored data block. The method may further include determining that the size of the data block is smaller than the available pipeline space of the pipeline output array of the data pipeline. The method may further include loading the data block into the pipe output array when the data block is different from the stored data block and the size of the data block is smaller than the available pipe space of the data pipe. The method may further include copying the data block to the memory tag. The method may further include: when it is determined that the block header and data block have been synchronized within multiple data segments by determining that the transaction IDs of each data segment in the multiple data segments are similar, transmitting the block header from the pipe output head of the pipe output array to the pipe input head of the pipe input array across the multiple data segments of the data pipe, and transmitting the data block from the pipe output array to the pipe input array across the multiple data segments of the data pipe. The method may further include: receiving the block header from the pipe output head of the pipe output array to the pipe input head of the pipe input array across the multiple data segments of the data pipe, and receiving the data block from the pipe output array to the pipe input array. The method may further include: determining that the pipe input array has successfully received the block header and data block by locating the record ID of the block header in the pipe input header, determining that the space occupied by the data block and block header in the pipe input array is similar to the space occupied by multiple temporary data in the temporary data array of the second programmable logic controller, and determining that the value of the record locator or record length of the data block is not zero. The method may also include storing the data block in one of a plurality of target tags.

[0023] In an additional aspect of this disclosure, the method may further include transmitting, via the data pipeline, the plurality of data messages having the header and the data block between a first programmable logic controller having a memory tag operable in an automated guided vehicle and a second programmable logic controller having a plurality of target tags operable in an automated workstation, and storing the header and the data block in the plurality of target tags.

[0024] Other applicable areas will become apparent from the description provided herein. It should be understood that this description and specific examples are for illustrative purposes only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0025] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure in any way.

[0026] Figure 1 This is a schematic diagram of a system according to an exemplary embodiment, the system including a central programmable logic controller that establishes multiple data pipelines with multiple satellite programmable logic controllers; Figure 2 This is a schematic diagram of a central programmable logic controller (PLC), one of the plurality of satellite programmable logic controllers (SPLCs), and one of the plurality of data pipelines between the central PLC and the SPLC. Figure 3 This is a schematic diagram of a data block being transmitted through the data pipeline according to an exemplary embodiment; Figure 4 This is a schematic diagram of a write command queue for the data pipeline according to an exemplary embodiment; Figure 5 This is a flowchart illustrating a method, according to an exemplary embodiment, for transferring a data block from the central programmable logic controller (PLC) to one of the plurality of satellite PLCs via the data pipeline when associated with a write instruction; and Figure 6 This is a flowchart illustrating a method for executing a read instruction on a data block received from a central programmable logic controller via a data pipeline within at least one of a plurality of satellite programmable logic controllers, according to an exemplary embodiment. Detailed Implementation

[0027] The following description is merely exemplary in nature and is not intended to limit this disclosure, application, or use.

[0028] Reference Figure 1The diagram of the system, including a central programmable logic controller 10, is generally indicated by reference numeral 16. This central programmable logic controller establishes multiple data pipelines 12 with multiple satellite programmable logic controllers 14. The central programmable logic controller 10 is an industrial digital computer configured for the automation and control of various processes, including but not limited to process control, energy management, manufacturing and assembly lines, mining, automotive, food and beverage, and wastewater treatment. The central programmable logic controller 10 oversees the system 16, coordinates, and transmits instruction and data flows between itself and the multiple satellite programmable logic controllers 14. In the non-limiting list of examples, the central programmable logic controller 10 may operate within a server network, personal computer, smartphone, tablet, vehicle, automated guided vehicle, or automated workstation.

[0029] The plurality of satellite programmable logic controllers 14 are at least one programmable logic controller that receives instructions and data from the central programmable logic controller 10. Each of the plurality of satellite programmable logic controllers 14 can manage a specific aspect of the system 16 and can transmit instructions and data to the central programmable logic controller 10. In a non-limiting list of examples, the central programmable logic controller 10 may be located within a server network, a personal computer, a smartphone, a tablet, a vehicle, an automated guided vehicle, or an automated workstation.

[0030] Reference Figure 2 The diagram illustrates the central programmable logic controller (PLC) 10, one of the multiple satellite PLCs 14, and a data pipeline 18, which is one of multiple data pipelines 12 between the central PLC 10 and one of the multiple satellite PLCs 14. The central PLC 10 includes a central processing unit (CPU) 20, multiple central instruction sets (CIS) 22, and a central memory 24.

[0031] The central processing unit 20 may be a custom or commercially available processor, a central processing unit (CPU), a graphics processing unit (GPU), an auxiliary processor among a plurality of processors associated with the central programmable logic controller 10, a semiconductor-based microprocessor (in the form of a microchip or chipset), or generally a device for executing instructions.

[0032] For example, the central processing unit 20 can use Rockwell 5000 series software to facilitate the automation and control of these various processes. The Rockwell 5000 series software enables the central programmable logic controller 10 to organize control logic into programs and routines and create custom additional instructions (AOIs). The Rockwell 5000 series software also supports the EtherNet / IP communication protocol for exchanging data between the central programmable logic controller 10 and other devices, such as the plurality of satellite programmable logic controllers 14, and for monitoring diagnostic data for troubleshooting and optimization. It should be understood that the use of Rockwell 5000 series software by the central processing unit 20 is exemplary, and in the non-limiting list of examples, the central processing unit 20 may also use other software with similar features and applications, such as Siemens TIA Portal, Schneider Electric EcoStruxure Control Expert, Mitsubishi GX Works, Omron CX-One, Beckhoff TwinCAT, and AutomationDirect Productivity Suite, and the use of AOIs in the Rockwell 5000 series software is similar to the function blocks in the aforementioned software with similar features and applications.

[0033] Multiple central commands 22 are commands that can be added to or removed from the data pipeline 18, specifying how multiple data messages 40 within each of the multiple central commands 22 should be processed, moved, or transformed. In an exemplary embodiment using Rockwell 5000 series software, the multiple central commands 22 allow the use of custom AOIs that utilize common logic to improve the versatility and efficiency of the use of the multiple central commands 22. In a non-limiting list of examples, the multiple central commands 22 may have read commands, write commands, comparison commands, diagnostic commands (including header decoding commands and data monitoring commands), and pipeline management commands. It should be understood that write commands from the multiple central commands 22 will be received as read commands by each of the multiple satellite programmable logic controllers 14 (referred to as a read / write pair).

[0034] Central memory 24 is used to store data, such as control logic, software applications, instructions, computer code, data, lookup tables, etc. Central memory 24 includes any type of media accessible to a computer, such as read-only memory (ROM), random access memory (RAM), hard disk drive, optical disc (CD), digital video disc (DVD), or any other type of memory. Central memory 24 includes a central memory label 26 and multiple central target labels 28.

[0035] Central memory tag 26 is a memory location where data is temporarily stored during write operations. Multiple central target tags 28 are memory locations where data is permanently stored after a read operation is successfully executed.

[0036] Each of the multiple satellite programmable logic controllers 14 includes a satellite processor 30, multiple satellite instructions 32, and satellite memory 34. The satellite processor 30 may be a custom or commercially available processor, a central processing unit (CPU), a graphics processing unit (GPU), an auxiliary processor among multiple processors associated with one of the satellite programmable logic controllers 14, a semiconductor-based microprocessor (in the form of a microchip or chipset), or generally a device for executing instructions. Each satellite processor 30 may run Rockwell 5000 series software, which has the same capabilities and functions as described with respect to the central processing unit 20, including the creation of the multiple satellite instructions 32. Each satellite processor 30 may also use a non-limiting list of other software with similar features and applications to the Rockwell 5000 series software as described with respect to the central processing unit 20.

[0037] Multiple satellite commands 32 are commands that can be added to or removed from the data pipeline 18, specifying how multiple data messages 40 within each satellite command of the multiple satellite commands 32 should be processed, moved, or transformed. In an exemplary embodiment where the central programmable logic controller 10 and the multiple satellite programmable logic controllers 14 use Rockwell 5000 series software, the multiple satellite commands 32 allow the use of custom AOIs that utilize common logic to improve the versatility and efficiency of the use of the multiple satellite commands 32. In a non-limiting list of examples, the multiple satellite commands 32 may have read commands, write commands, comparison commands, diagnostic commands (including header decoding commands and data monitoring commands), and pipeline management commands. It should be understood that write commands derived from the multiple satellite commands 32 will be received by the central programmable logic controller 10 as read commands (referred to as read / write pairs).

[0038] Satellite memory 34 has a similar form and function to central memory 24, except that satellite memory 34 is located within each of the multiple satellite programmable logic controllers 14. Satellite memory 34 also has satellite memory tags 36 and multiple satellite target tags 38, which have similar form and function to central memory tags 26 and multiple central target tags 28, respectively.

[0039] Reference Figure 1 and Figure 2Data pipeline 18, originating from multiple data pipelines 12, serves as a means of data communication between the central programmable logic controller 10 and multiple satellite programmable logic controllers 14. In the non-limiting list of examples, data pipeline 18 can be a physical data pipeline, such as one built using physical servers and storage systems or existing on a local area network, or an internet-based data pipeline, such as one created using cloud services (e.g., Google Cloud, AWS, Azure, etc.). It should be understood that data pipeline 18 can be a hybrid data pipeline created using elements from both physical and internet-based data pipelines.

[0040] return Figure 2 The data pipeline 18 includes at least one or more data messages 40, a central pipeline output array 42, multiple central data segments 44, a satellite pipeline input array 46, a satellite pipeline output array 48, multiple satellite data segments 50, and a central pipeline input array 52.

[0041] Multiple data messages 40 contain information that will be transmitted from the central programmable logic controller 10 to each of the multiple satellite programmable logic controllers 14 via data pipe 18, and vice versa. It should be understood that more than one multiple data message 40 can be transmitted simultaneously via data pipe 18.

[0042] The central pipeline output array 42 is a data structure within the central programmable logic controller 10, used to store multiple data messages 40 before information is transmitted from the central programmable logic controller 10 to one of the multiple satellite programmable logic controllers 14 via the data pipeline 18. The multiple data messages 40 are stored in multiple central output indices 54 within the central pipeline output array 42, each of which stores a double integer (DINT). This double integer can store data of various data types, including but not limited to integers (ints), floating-point numbers, double-precision numbers, characters (chars), strings, boolean values, and user-defined types (UDTs). The first index in the multiple central output indices 54 indicates the cumulative size of all data blocks within the current central pipeline output array 42. Subsequent indices in the multiple central output indices 54 include a central pipeline output header 56, which sequentially indicates the headers of all write instructions of the multiple central instructions 22 within the central pipeline output array 42, as described in more detail below. It should be understood that the number of indices constituting the central pipeline output head 56 varies based on the number of write instructions in the multiple central instructions 22, and therefore does not contain a fixed number of indices. The data of each individual multiple data messages 40 to be loaded in sequence occupies the indices of multiple central output indices 54 following the central pipeline output head 56 in the order in which the data blocks are added to the central pipeline output array 42, which will be described in more detail below.

[0043] Multiple central data segments 44 are at least one pipe within data pipe 18 through which multiple data messages 40 are transmitted from the central programmable logic controller 10 to at least one of the multiple satellite programmable logic controllers 14. The multiple data messages 40 transmitted through each individual central data segment are aligned with the corresponding indices of the multiple data messages 40 stored in the central pipe output array 42. It should be understood that there can be up to 20 central data segments within the multiple central data segments 44. It should also be understood that in the exemplary embodiment where the central programmable logic controller 10 and the multiple satellite programmable logic controllers use Rockwell 5000 series software, the multiple central data segments 44 are producer / consumer pipe segments, allowing the multiple central data segments 44 to act as producer segments to generate data and provide data to one of the multiple satellite programmable logic controllers 14, and as consumer segments to consume data received by the multiple satellite programmable logic controllers 14. It should also be understood that when the central programmable logic controller 10 needs to provide data to more than one of the multiple satellite programmable logic controllers 14, the communication between the central programmable logic controller 10 and each corresponding satellite programmable logic controller utilizes different data pipelines, each of which has a corresponding number of central data segments.

[0044] Each of the multiple central data segments 44 has a central producer transaction ID 58 within its producer segment and a central consumer transaction ID 60 within its consumer segment. The central producer transaction ID 58 and central consumer transaction ID 60 are integers used to track the number of scans of the data pipeline 18 that occur when multiple data messages 40 are transmitted from the central programmable logic controller 10 to one of the multiple satellite programmable logic controllers 14, as described in more detail below. The central producer transaction ID 58 and central consumer transaction ID 60 are initialized to the value "one" and can be incremented up to the value "one hundred". When the value of the central producer transaction ID 58 is incremented to "one hundred", it is reset to "one". When the value of the central consumer transaction ID 60 is incremented to "one hundred", it is reset to "one".

[0045] The satellite pipeline input array 46 is a data structure within each of the multiple satellite programmable logic controllers 14. It is used to receive and store multiple data messages 40 after they have been transmitted from the central programmable logic controller 10 to at least one of the multiple satellite programmable logic controllers 14 via the data pipeline 18. The multiple data messages 40 are stored in multiple satellite input indices 62 within the satellite pipeline input array 46, and can store various data types. The first index in the multiple satellite input indices 62 indicates the cumulative size of all data blocks within the current satellite pipeline input array 46. Subsequent indices in the multiple satellite input indices 62 include a satellite pipeline input header 64, which sequentially indicates the headers of all read instructions of the multiple satellite instructions 32 within the satellite pipeline input array 46, as described in more detail below. It should be understood that the number of indices constituting the satellite pipeline input header 64 varies based on the number of read instructions in the multiple satellite instructions 32, and therefore does not contain a fixed number of indices. The data of each individual multiple data message 40 to be received in sequence occupies the index in multiple satellite input indices 62 after the satellite input head 64 in the order in which the data blocks are added to the satellite pipeline input array 46, which will be described in more detail below.

[0046] The satellite pipeline output array 48 is a data structure within each of the multiple satellite programmable logic controllers 14, used to store multiple data messages 40 before they are transmitted from one of the satellite programmable logic controllers 14 to the central programmable logic controller 10 via the data pipeline 18. The multiple data messages 40 are stored in multiple satellite output indices 66 within the satellite pipeline output array 48, where each of the multiple central output indices 54 stores a double integer (DINT), which can store data of various different data types, including but not limited to integers (int), floating-point numbers, double-precision floating-point numbers, characters (char), strings, booleans, and user-defined types (UDTs). The first index in the multiple satellite output indices 66 indicates the cumulative size of all data blocks within the current satellite pipeline output array 48. Subsequent indices in the multiple satellite output indices 66 include a satellite pipeline output header 68, which sequentially indicates the headers of all write instructions of the multiple satellite instructions 32 within the satellite pipeline output array 48, as described in more detail below. It should be understood that the number of indices constituting the satellite pipeline output head 68 varies based on the number of write instructions in the multiple satellite instructions 32, and therefore does not contain a fixed number of indices. The data of each individual multiple data messages 40 to be loaded sequentially occupies indices in multiple satellite output indices 66 following the satellite pipeline output head 68 in the order in which the data blocks are added to the satellite pipeline output array 48.

[0047] Multiple satellite data segments 50 are at least one conduit within data conduit 18 through which multiple data messages 40 are transmitted from one of the multiple satellite programmable logic controllers 14 to the central programmable logic controller 10. The multiple data messages 40 transmitted via each individual satellite data segment are aligned with the corresponding indices of the satellite conduit output array 48 storing those multiple data messages 40. It should be understood that there can be up to 20 satellite data segments within the multiple satellite data segments 50. It should also be understood that in an exemplary embodiment where the central programmable logic controller 10 and the multiple satellite programmable logic controllers use Rockwell 5000 series software, the multiple satellite data segments 50 are producer / consumer conduit segments, enabling the multiple satellite data segments 50 to generate data as producer segments and provide data to the central programmable logic controller 10, and to consume data received by the central programmable logic controller 10 as consumer segments.

[0048] Each of the multiple satellite data segments 50 has a satellite producer transaction ID 70 within its producer segment and a satellite consumer transaction ID 72 within its consumer segment. The satellite producer transaction ID 70 and satellite consumer transaction ID 72 are integers used to track the number of scans that have occurred in the data pipeline 18 when multiple data messages 40 are transmitted from one of the multiple satellite programmable logic controllers 14 to the central programmable logic controller 10, as described in more detail below. The satellite producer transaction ID 70 and satellite consumer transaction ID 72 are initialized to the value "one" and can be incremented up to the value "one hundred". When the value of satellite producer transaction ID 70 increments to "one hundred", it is reset to "one". When the value of satellite consumer transaction ID 72 increments to "one hundred", it is reset to "one".

[0049] The central pipeline input array 52 is a data structure within the central programmable logic controller 10, used to receive and store multiple data messages 40 after they are transmitted from one of the multiple satellite programmable logic controllers 14 to the central programmable logic controller 10 via the data pipeline 18. The multiple data messages 40 are stored in multiple central input indices 74 within the central pipeline input array 52, and can hold various different data types. The first index among the multiple central input indices 74 indicates the cumulative size of all data blocks currently within the central pipeline output array 42. Subsequent indices among the multiple central input indices 74 constitute the central pipeline input header 76, which sequentially indicates the headers of all write instructions of the multiple central instructions 22 within the central pipeline output array 42, as described in more detail below. It should be understood that the number of indices constituting the central pipeline input header 76 varies based on the number of read instructions in the multiple central instructions 22, and therefore does not contain a fixed number of indices. Each individual data message 40 that will be received in sequence will occupy an index in multiple central input indices 74 after the central input head 76, in the order in which the data blocks are added to the central pipe output array 42, as will be described in more detail below.

[0050] It should be understood that the size of multiple data messages 40 that can be loaded into the central pipeline output array 42 or the satellite pipeline output array 48, transmitted through multiple central data segments 44 or multiple satellite data segments 50, and received by the central pipeline input array 52 or the satellite pipeline input array 46 depends on the number of central data segments 44 or the number of satellite data segments 50 utilized. Each of the central data segments 44 and each of the satellite data segments 50 can transmit up to 400 bytes of data. When using 20 central data segments or 20 satellite data segments, each of the central data segments 44 and the satellite data segments 50 can transmit up to 8,000 bytes of data. The size of data that can be transmitted through the multiple central data segments 44 or the multiple satellite data segments 50, relative to the number of central data segments or satellite data segments utilized, is referred to as the maximum available pipeline space of any of the central pipeline output array 42, the satellite pipeline output array 48, the multiple central data segments 44, the multiple satellite data segments 50, the central pipeline input array 52, or the satellite pipeline input array 46. It should also be understood that the size of multiple data messages 40 that can be transmitted through each individual data segment in multiple central data segments 44 or multiple satellite data segments 50 can be up to 400 bytes (also known as the maximum single available segment space).

[0051] Furthermore, it should be understood that when the size of multiple data messages 40 is greater than the maximum single available segment space and less than the maximum available pipeline space, some or all of the data messages 40 can be transmitted on the data pipeline 18 through one or more of the multiple central data segments 44 or multiple satellite data segments 50. It should also be understood that when the size of multiple data messages 40 is less than the maximum single available segment space of one of the multiple central data segments 44 or multiple satellite data segments 50 that are transmitting the multiple data messages 40, some or all of the information from different data blocks can be transmitted simultaneously through the same data segment of the multiple central data segments 44 or multiple satellite data segments 50.

[0052] It should be understood that the act of transmitting multiple data messages 40 through data pipe 18 via any of the multiple central data segments 44 or multiple satellite data segments 50 is referred to as scanning data pipe 18. Scanning data pipe 18 is a function of pipe management commands. The scanning frequency of data pipe 18 is based on the Request Packet Interval (RPI) of the multiple central data segments 44 and the multiple satellite data segments 50, which defines the frequency at which multiple data messages 40 communicate through data pipe 18.

[0053] In a non-limiting exemplary embodiment, multiple data messages 40 are transmitted from a central programmable logic controller 10 to one of a plurality of satellite programmable logic controllers 14 via a data pipeline 18. A scan of the data pipeline 18 is initiated by transmitting multiple data messages 40 from each producer segment of a plurality of central data segments 44 to each consumer segment of the plurality of central data segments 44, including setting the value of a central consumer transaction ID 60 to the value of a central producer transaction ID 58. When the values ​​of each central consumer transaction ID 60 in each of the plurality of central data segments 44 are identical, multiple data messages 40 are copied to the satellite pipeline input array 46, and each central consumer transaction ID 60 is copied to its corresponding satellite producer transaction ID 70. When the values ​​of each central consumer transaction ID 60 in each of the plurality of central data segments 44 are identical, all data messages 40 have been successfully received by the consumer segments of the plurality of central data segments 44 (referred to as synchronization of multiple data messages 40). Then, the value of each central producer transaction ID 58 is incremented by one. It should be understood that when the value of each central producer transaction ID 58 is "one hundred", the value of each central producer transaction ID 58 will be reset to "one" when each central producer transaction ID 58 is incremented.

[0054] In a non-limiting exemplary embodiment where multiple data messages 40 are transmitted from one of the multiple satellite programmable logic controllers 14 to the central programmable logic controller 10 via data pipeline 18, a scan of data pipeline 18 is initiated by transmitting multiple data messages 40 from each producer segment of multiple satellite data segments 50 to each consumer segment of multiple satellite data segments 50, including setting the value of satellite consumer transaction ID 72 to the value of satellite producer transaction ID 70. When the value of each satellite consumer transaction ID 72 in each satellite data segment of multiple satellite data segments 50 is the same, multiple data messages 40 are copied to the central pipeline input array 52, and each satellite consumer transaction ID 72 is copied to its corresponding central producer transaction ID 58. When the value of each satellite consumer transaction ID 72 in each satellite data segment of multiple satellite data segments 50 is the same, all data messages of multiple data messages 40 have been successfully received by the consumer segments of multiple satellite data segments 50 (referred to as synchronization of multiple data messages 40). Then, the value of each satellite producer transaction ID 70 is incremented by one. It should be understood that when the value of each satellite producer transaction ID 70 is "one hundred", the value of each satellite producer transaction ID 70 will be reset to "one" when each satellite producer transaction ID 70 is incremented.

[0055] Reference Figure 3The diagram illustrates multiple data messages 40 located within multiple central commands 22 or multiple satellite commands 32, to be transmitted via data pipeline 18. The multiple data messages 40 include a header 78 and data blocks 80.

[0056] The block header 78 stores metadata related to the corresponding multiple data entries 40. Whenever a write instruction is added to or removed from the data pipeline 18 via pipeline management instructions, the block header 78 is automatically added to or removed from the central pipeline output array 42 without interrupting data communication through the data pipeline 18. The block header is loaded into the central pipeline output head 56 or the satellite pipeline output head 68.

[0057] It should be understood that when at least one of the multiple satellite programmable logic controllers 14 transmits a write instruction to the central programmable logic controller 10 via data pipe 18, the block header 78 is automatically generated by the output array 48 of each satellite pipe of at least one of the multiple satellite programmable logic controllers 14. In a non-limiting list of examples, the metadata within the block header 78 may include record ID 82, record instance 84, record locator 86, record queue position 88, and record type 90.

[0058] Record ID 82 is a unique integer that identifies multiple data messages 40 among the central programmable logic controller 10 and each of the multiple satellite programmable logic controllers 14. It should be understood that, in a non-limiting exemplary embodiment, when the multiple data messages 40 are processed by write instructions, read instructions, or diagnostic instructions, Record ID 82 has a size of 15 bits.

[0059] Record instance 84 is a four-bit integer that uniquely identifies a specific read or write instruction associated with a particular record ID. This allows multiple different data blocks associated with a specific write instruction having the same record ID to be transferred through data pipe 18, provided that each of the multiple different data blocks has a different record instance.

[0060] The record locator 86 is an integer that identifies the starting position of the data block 80 in the central pipeline output array 42, the central pipeline input array 52, the satellite pipeline output array 48, or the satellite pipeline input array 46. It should be understood that in exemplary embodiments where multiple data messages 40 are associated with write instructions, read instructions, or diagnostic instructions, the record locator 86 has an 11-bit size.

[0061] Record queue bit 88 is a single bit that indicates whether multiple data entries 40 are in the write command queue (described below) and have not yet been transmitted through data pipe 18. When data block 80 is to be added to the write command queue, a specific write instruction associated with block header 78 sets record queue bit 88 to true. When record queue bit 88 is set to true, a read instruction associated with block header 78 will maintain the information within data block 80 in either satellite pipe input array 46 or central pipe input array 52. ​​When record queue bit 88 is set to false, a read instruction associated with block header 78 will update the information within data block 80.

[0062] Record type 90 indicates whether record ID 82 is a task number or a footprint number.

[0063] Data block 80 contains data stored within multiple data messages 40, which are to be transmitted via data pipe 18 through multiple central data segments 44 and multiple satellite data segments 50. Data block 80 is loaded into the central pipe output array 42 after the central pipe output head 56. Data block 80 includes a record length 92. The record length 92 indicates the size of data block 80. The record length 92 is loaded into the first central output index among the multiple central output indices 54 following the central pipe output head 56. The remaining information of data block 80 is loaded into the remaining indices among the multiple central output indices 54, occupying the number of indices in the multiple central output indices 54 required to accommodate the entire data block 80. It should be understood that in an exemplary embodiment in which multiple data messages 40 are transmitted from one of the multiple satellite programmable logic controllers 14 to the central programmable logic controller 10 via a data pipeline 18, the data block 80 is loaded into the satellite pipeline output array 48 after the satellite pipeline output head 68, the record length 92 is loaded into the first satellite output index among the multiple satellite output indices 66 after the satellite pipeline output head 68, and the remaining information of the data block 80 is loaded into the remaining indices among the multiple satellite output indices 66.

[0064] It should be understood that for each read / write pair, the data structure of data block 80 within multiple data messages 40 must be similar between the read and write instructions. It should also be understood that once a specific write instruction is loaded into the central programmable logic controller 10, the block header 78 associated with that specific write instruction is permanently loaded into the central pipeline output array 42 or the satellite pipeline output array 48 until that specific write instruction is removed from the logic of the central programmable logic controller 10 or one of the multiple satellite programmable logic controllers 14. This allows the associated read instruction of a specific write instruction within one of the multiple satellite programmable logic controllers 14 to find the block header 78 of that specific write instruction and be able to determine how to process data block 80 (as described below). Figure 6 (as described).

[0065] It should be understood that the combination of record type 90, record instance 84 and record ID 82 is called a unique data identifier, which helps the data pipeline 18 to track specific multiple data messages 40 associated with the unique data identifier when multiple data messages 40 are transmitted via the data pipeline 18.

[0066] Reference Figure 4 The diagram illustrates the write command queue 94 of data pipe 18. Write command queue 94 references multiple data blocks that may have queued positions set to true for corresponding records when the occupied space of the central pipe output array 42 or satellite pipe output array 48 exceeds the available pipe space and therefore cannot be loaded into the central pipe output array 42 or satellite pipe output array 48. It should be understood that write command queue 94 is not a location in central memory 24 or satellite memory 34. It should also be understood that the occupied space of the central pipe output array 42 is the byte space in the central pipe output array 42 occupied by information not in data block 80. It should also be understood that the occupied space of the satellite pipe output array 48 is the byte space in the satellite pipe output array 48 occupied by information not in data block 80. It should also be understood that the available pipe space of the central pipe output array 42 is the maximum available pipe space of the central pipe output array 42 minus the occupied space of the central pipe output array 42. It should also be understood that the available pipe space of satellite pipe output array 48 is the maximum available pipe space of satellite pipe output array 48 minus the space occupied by satellite pipe output array 48.

[0067] Multiple write instructions for multiple data blocks 96 determine whether each data block in the multiple data blocks 96 is transferable via data pipe 18 by traversing the multiple data blocks 96 and sequentially adding each data block in the multiple data blocks 96 to the central pipe output array 42. Iteration continues until the byte size of the next sequential data block causes the occupied space of the central pipe output array 42 or satellite pipe output array 48 to exceed the available pipe space of the central pipe output array 42 or satellite pipe output array 48 in the first scan 98. When the occupied space exceeds the available pipe space, the write instruction associated with the sequential data block sets the record queue bit 88 of the block header 78 to true. When it is determined that the sequential data block fits the central pipe output array 42, the sequential data block is added to the central pipe output array 42, and the record queue bit 88 in the block header 78 is set to false. It should be understood that the first scan 98 is the first instance of a scan of data pipe 18.

[0068] In an exemplary embodiment where multiple data messages 40 are transmitted from the central programmable logic controller 10 to multiple satellite programmable logic controllers 14, the size of the loaded data block that can be accommodated in the first scan 98 is compared with the occupied space of the central pipeline output array 42. In an exemplary embodiment where multiple data messages 40 are transmitted from any one of the multiple satellite programmable logic controllers 14 to the central programmable logic controller 10, the size of the loaded data block that can be accommodated in the first scan 98 is compared with the occupied space of the satellite pipeline output array 48. Then, multiple write instructions continue to traverse the multiple data blocks 96 until it is determined that each data block can be accommodated in the first scan 98, or that the size of each data block is too large to be accommodated in the first scan 98, at which point the queue bit of the record in the block header associated with each data block is set to true.

[0069] Then, the write command queue 94 repeats the iteration, adding individual data blocks from multiple data blocks 96 to multiple subsequent scans 100 of the data pipeline 18 until the record queue bit 88 of all block headers associated with each data block is set to false.

[0070] Reference Figure 5 This diagram illustrates a flowchart of a method 200 in which multiple data messages 40 are transmitted from a central programmable logic controller (PLC) 10 to one of a plurality of satellite programmable logic controllers (SPCs) 14 via a data pipeline 18 when associated with a write instruction. It should be understood that although in this exemplary embodiment, the PLC 10 is transmitting multiple data messages 40 to one of the SPCs 14, the PLC 10 can simultaneously transmit more than one data block of information to all of the SPCs 14, wherein communication between the PLC 10 and each of the SPCs 14 utilizes a corresponding data pipeline. It should also be understood that, when associated with a write instruction, each of the SPCs 14 can transmit multiple data messages 40 to the PLC 10. Furthermore, it should be understood that, although in this exemplary embodiment, the PLC 10 contains only write instructions and one of the SPCs 14 contains only read instructions, both types of programmable logic controllers can contain both read and write instructions. Method 200 begins at step 202, in which the central processing unit 20 searches for record ID 82 of multiple data messages 40 in the central pipeline output head 56. If record ID 82 is not found, method 200 proceeds to step 204.

[0071] In step 204, the head refresh request flag is set to true, and multiple headers within the central pipe output header 56 are removed. The head refresh request flag indicates that the unique data identifier within block header 78 is incomplete, and block header 78 must be rebuilt. In a non-limiting list of examples, the head refresh request flag can be a Boolean variable that can be set to true or false, or it can be a bit that can be set to 0 or 1. Then, method 200 proceeds to step 206.

[0072] In step 206, the head refresh request flag is set to false, and the head refresh in progress flag is set to true. The head refresh in progress flag indicates that the central pipe output head 56 is being rebuilt. In the list of non-limiting examples, the head refresh in progress flag can be a Boolean variable that can be set to true or false, or it can be a bit that can be set to 0 or 1. Then, method 200 proceeds to step 208.

[0073] In step 208, each instance of the multiple data messages 40 indicated by record instance 84 loads the block header 78 of the multiple data messages 40 into the central pipe output head 56. It should be understood that although the write instruction associated with the multiple data messages 40 adds the block header 78 to the central pipe output head 56, pipe management instructions are executed to oversee the complete central pipe output head 56 refresh process. Method 200 then proceeds to step 210.

[0074] In step 210, the head refresh in progress flag is set to false, and a comparison instruction is executed to determine whether the current data block 80 in the multiple data messages 40 has been modified by determining whether the value of the current data block 80 in the multiple data messages 40 is similar to the value of the multiple copy block data stored in the central memory tag 26. When the value of the current data block 80 in the multiple data messages 40 is not similar to the value of the multiple copy block data stored in the central memory tag 26, method 200 proceeds to step 212.

[0075] In step 212, the data refresh flag is set to true, and the byte size of data block 80 is compared with the available pipe space of the central pipe output array 42.

[0076] It should be understood that, in this exemplary embodiment, although the size of data block 80 and the size of the loaded data block are compared in bytes, they can also be compared in smaller data sizes, such as nibbles, quadbytes, and bits. When the size of data block 80 is greater than the available pipeline space of the central pipeline output array 42, method 200 proceeds to step 214.

[0077] In step 214, data block 80 is added to write command queue 94 by setting record queue bit 88 to true. Then, method 200 proceeds to step 212.

[0078] Returning to step 212, when the size of data block 80 is less than or equal to the available pipe space of the central pipe output array 42, method 200 proceeds to step 216.

[0079] In step 216, a write instruction associated with multiple data messages 40 loads data block 80 into the central pipeline output array 42. A data refresh flag indicates that data block 80 is being loaded into the central pipeline output array 42. In a non-limiting list of examples, the data refresh flag can be a Boolean variable that can be set to true or false, or it can be a bit that can be set to 0 or 1. It should also be understood that when data block 80 has previously been added to the write command queue 94, the record queue bit 88 is set to false. Method 200 then proceeds to step 218.

[0080] In step 218, multiple data messages 40 are transmitted from the central pipeline output array 42 to the satellite pipeline input array 46 of at least one of the multiple satellite programmable logic controllers 14 via multiple central data segments 44 and data pipeline 18. The multiple data messages 40 are transmitted via data pipeline 18 either continuously or based on state changes of data blocks 80 of at least one of the multiple satellite programmable logic controllers 14, depending on the configuration of the write instructions associated with the multiple data messages 40. Then, method 200 proceeds to step 220.

[0081] In step 220, data blocks 80 of the multiple data messages 40 are copied to central memory tag 26. It should be understood that step 220 is optional and is executed only when write instructions associated with the multiple data messages 40 are configured to transfer data blocks 80 via data pipe 18 based on state changes. Then, method 200 proceeds to step 202.

[0082] Returning to step 202, when multiple data information 40 record ID 82 is found, method 200 proceeds to step 210.

[0083] Returning to step 210, when the current data block 80 in multiple data information 40 is similar to the value of multiple replicated block data stored in the central memory tag 26, method 200 proceeds to step 222.

[0084] In step 222, multiple data messages 40 are transmitted through data pipe 18 in either a continuous manner or based on state changes of information within the multiple data messages 40 by at least one of the multiple satellite programmable logic controllers 14, depending on the configuration of the write instructions associated with the multiple data messages 40. Then, method 200 proceeds to step 224.

[0085] In step 224, data blocks 80 of the multiple data messages 40 are copied to central memory tag 26. It should be understood that step 220 is optional and is executed only when the write instruction associated with the multiple data messages 40 is configured to transfer data blocks 80 via data pipe 18 based on state changes. Then, method 200 proceeds to step 202.

[0086] It should be understood that, in the exemplary embodiment, when at least one of the multiple satellite programmable logic controllers 14 transmits multiple data messages 40 in association with a write instruction, method 200 will be executed in the same manner, wherein components of the programmable logic controllers are switched. This means that the central programmable logic controller 10, at least one of the multiple satellite programmable logic controllers 14, the central pipeline output array 42, the satellite pipeline input array 46, the multiple central data segments 44, the central memory tag 26, the central processor 20, and the central pipeline output head 56 will be replaced by one of the multiple satellite programmable logic controllers 14, the central programmable logic controller 10, the satellite pipeline output array 48, the central pipeline input array 52, the multiple satellite data segments 50, the satellite memory tag 36, the satellite processor 30, and the satellite pipeline output head 68, respectively. It should also be further understood that the head refresh request flag, the head refresh in progress flag, and the data refresh flag are located within the pipeline management instruction.

[0087] Reference Figure 6This document illustrates a flowchart of a method 300 for executing a read instruction on multiple data messages 40 received from a central programmable logic controller (PLC) 10 via a data pipeline 18 within at least one of a plurality of satellite PLCs 14. It should be understood that although only communication between the central PLC 10 and one of the multiple satellite PLCs 14 is shown in this exemplary embodiment, method 300 can be executed simultaneously between the central PLC 10 and up to all of the multiple satellite PLCs 14, wherein communication between the central PLC 10 and each of the multiple satellite PLCs 14 utilizes a corresponding data pipeline. It should also be understood that although in this exemplary embodiment one of the multiple satellite PLCs 14 receives multiple data messages 40 from the central PLC 10, in another exemplary embodiment, the central PLC 10 may receive multiple data messages 40 from one of the multiple satellite PLCs 14. Method 300 begins at step 302, determining that the respective satellite consumer transaction IDs are similar to each other. When the respective satellite consumer transaction IDs are not similar to each other, method 300 repeats step 302. When the individual satellite consumer transaction IDs are similar to each other, method 300 then proceeds to step 304.

[0088] In step 304, the satellite pipeline input array 46 receives multiple data messages 40 transmitted by the central programmable logic controller in step 218 or step 222 of method 200. Then, method 300 proceeds to step 306.

[0089] In step 306, the satellite processor 30 searches for record ID 82 within the block header 78 of the data transmitted to the satellite pipeline input head 64. When record ID 82 is found, method 300 then proceeds to step 308.

[0090] In step 308, the satellite processor 30 determines whether the space occupied by the data block 80 within the plurality of satellite input indices 62 and the space occupied by the block header 78 within the satellite pipeline input head 64 are similar to the space occupied by data in the temporary data array of one of the plurality of satellite programmable logic controllers 14 that does not belong to the plurality of data information 40. When the space occupied by the data block 80 and the block header 78 within the plurality of satellite input indices 62 is similar to the space occupied by data in the temporary data array that does not belong to the plurality of data information 40, method 300 then proceeds to step 310.

[0091] In step 310, the satellite processor 30 determines whether the record locator 86 or the record length 92 of the data block 80 has a zero value. If neither the record locator 86 nor the record length 92 has a zero value, method 300 then proceeds to step 312.

[0092] In step 312, a read instruction associated with the data block 80 created by the satellite processor 30 sets the data ready flag to true. The data ready flag indicates that multiple data messages 40 have been successfully transmitted through the data pipeline 18 and can be copied to multiple satellite target tags 38. In a non-limiting list of examples, the data ready flag can be a Boolean variable that can be set to true or false, or it can be a bit that can be set to 0 or 1. Then, method 300 proceeds to step 314.

[0093] In step 314, data block 80 is copied to one of the multiple satellite target tags 38. Then, method 300 proceeds to step 302.

[0094] Returning to step 306, if record ID 82 is not found, method 300 then proceeds to step 316.

[0095] In step 316, the satellite processor 30 sets the data invalidation flag to true and clears the data blocks 80 in the plurality of satellite target tags 38. It should be understood that only the data blocks 80 in the plurality of satellite target tags 38 are cleared, and the other data blocks are retained. The data invalidation flag indicates that an error exists within data block 80 or that data block 80 is incomplete. In a non-limiting list of examples, the data invalidation flag can be a Boolean variable that can be set to true or false, or it can be a bit that can be set to 0 or 1. Method 300 then proceeds to step 318.

[0096] In step 318, a temporary data array is used to copy data block 80 to one of the multiple satellite target tags 38. Then, method 300 proceeds to step 302.

[0097] Returning to step 308, when the space occupied by data blocks 80 and block headers 78 within multiple satellite input index 62 is not similar to the space occupied by data in the temporary data array that does not belong to multiple data information 40, method 300 then proceeds to step 320.

[0098] In step 320, the satellite processor 30 sets the data invalidation flag to true and clears the data blocks 80 in the plurality of satellite target tags 38. It should be understood that only the data blocks 80 in the plurality of satellite target tags 38 are cleared, and the other data blocks are retained. Then, method 300 proceeds to step 322.

[0099] In step 322, data block 80 is copied to one of the multiple satellite target tags 38 using a temporary data array. Then, method 300 proceeds to step 302.

[0100] Returning to step 310, when the value of record locator 86 or record length 92 is zero, method 300 then proceeds to step 324.

[0101] In step 324, the satellite processor 30 sets the data ready flag to false, indicating that the data block 80 will not be copied to the multiple satellite target tags 38, and the previous data within the multiple satellite target tags 38 will be preserved. Then, method 300 proceeds to step 302.

[0102] It should be understood that, in the exemplary embodiment, when at least one of the multiple satellite programmable logic controllers 14 transmits multiple data messages 40 in association with a write instruction, method 300 will be executed in the same manner, wherein components of the programmable logic controllers are switched. This means that the central programmable logic controller 10, at least one of the multiple satellite programmable logic controllers 14, the satellite pipeline input array 46, the multiple central data segments 44, the multiple satellite target tags 38, the satellite processor 30, the satellite consumer transaction ID, and the satellite pipeline input header 64 will respectively be changed to one of the multiple satellite programmable logic controllers 14, the central programmable logic controller 10, the central pipeline input array 52, the multiple satellite data segments 50, the multiple central target tags 28, the central processor 20, the central consumer transaction ID, and the central pipeline input header 76. It should also be understood that the data ready flag and the data invalid flag are within the pipeline management instruction.

[0103] The data pipeline 18 of this disclosure provides several advantages. These advantages include having up to 20 segments across multiple central data segments 44 and multiple satellite data segments 50, being able to transmit up to 8,000 bytes on each of the multiple central data segments 44 and multiple satellite data segments 50, and being able to dynamically add and remove write and read commands from the data pipeline 18. Furthermore, the data pipeline 18 of this disclosure allows for automatic flushing of the central pipeline output header 56 when a write command is added to or removed from the data pipeline 18, and implements a write command queue 94 that assists in transmitting multiple data messages 40 across the data pipeline 18 when the block size of the multiple data blocks 96 to be transmitted exceeds the maximum available pipeline space of the central pipeline output array 42 and the maximum available pipeline space of the satellite pipeline output array 48. The data pipeline 18 of this disclosure ensures that the multiple data messages 40 are synchronized by using transaction IDs, ensuring that the multiple data messages 40 are up-to-date with each corresponding scan of the data pipeline 18. Furthermore, system 16 implements flexibility and modularity in the configuration of programmable logic controllers. In a non-limiting list of examples, the central programmable logic controller 10 transmits multiple data messages 40 to only one satellite programmable logic controller via data pipe 18, communicates with each of the multiple satellite programmable logic controllers 14 using corresponding data pipes, or the central programmable logic controller 10 transmits multiple data messages 40 to only one satellite programmable logic controller via data pipe 18, which then further transmits the multiple data messages 40 to another satellite programmable logic controller via a separate data pipe.

[0104] The description in this disclosure is exemplary in nature only, and variations thereof without departing from the purpose of this disclosure are intended to be within its scope. Such variations should not be considered as departing from the spirit and scope of this disclosure.

Claims

1. A method for transmitting multiple data messages between a first programmable logic controller (PLC) and a second PLC having memory tags via a data pipeline, the method comprising: Establish a data pipeline with a pipeline input array, a pipeline output array, multiple data segments, and a pipeline size, wherein the pipeline input array has a pipeline input head, and the pipeline output array has a pipeline output head; Generate multiple data entries with block headers and data blocks; Load the block header into the pipe output header of the pipe output array; The data block containing the multiple data information is compared with the data block stored in the memory tag; Based on the comparison between the data block and the stored data block, it is determined that the data block and the stored data block are different; Determine that the size of the data block is smaller than the available pipe space of the pipe output array of the data pipe; When the data block is different from the stored data block and the size of the data block is smaller than the available pipeline space of the data pipeline, the data block is loaded into the pipeline output array; Copy the data block to the memory tag; as well as The block header is transmitted from the pipe output head of the pipe output array to the pipe input head of the pipe input array via the multiple data segments through the data pipeline, and the data block is transmitted from the pipe output array to the pipe input array via the multiple data segments through the data pipeline.

2. The method of claim 1, further comprising transmitting the plurality of data messages between a first programmable logic controller having a memory tag operable within an automated guided vehicle and a second programmable logic controller operable within an automated workstation via the data pipeline.

3. The method according to claim 1, wherein, Generating the multiple data entries also includes generating the block header containing a record ID, which allows the data pipeline to track the data block.

4. The method according to claim 3, further comprising refreshing the pipe output head when the first programmable logic controller cannot find the record ID of the block head.

5. The method according to claim 4, wherein, Refreshing the pipe output head also includes removing multiple loaded heads from the pipe output head and loading the block head into the pipe output head.

6. The method of claim 1, further comprising determining that the data block is similar to the stored data block based on the comparison between the data block and the stored data block, and continuously or based on state changes of the data block from the pipeline output array to the pipeline input array via the data pipeline through the plurality of data segments.

7. The method according to claim 1, wherein, Determining whether the size of the data block is less than the available pipeline space of the pipeline output array of the data pipeline also includes determining the available pipeline space as the space in the pipeline output array that is not occupied by the block header or the data block.

8. The method according to claim 7, wherein, Determining whether the size of the data block is less than the available pipeline space of the pipeline output array of the data pipeline also includes determining that the maximum available pipeline space is 400 times the number of the data segments among the plurality of data segments, in bytes, and a maximum of 8,000 bytes.

9. The method of claim 1, further comprising setting the queue bit of the record of the block header to true when the size of the data block is greater than the available pipeline space, thereby preventing the data block from being loaded into the pipeline output array.

10. The method of claim 9, further comprising setting the queue position of the record in the block header to false when the size of the data block is less than or equal to the available pipeline space, thereby allowing the data block to be loaded into the pipeline output array.

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