Voltage regulator and method of operating a voltage regulator

Abstract

A voltage regulator and a method of operating a voltage regulator are provided. The voltage regulator can include an error amplifier including a first input terminal to receive a reference voltage, a second input terminal connected to a feedback node, and a first output terminal configured to output a pass gate voltage. A pass transistor connected between an input voltage and an output node. The pass transistor is configured to operate in response to the pass gate voltage. The voltage regulator further includes a first resistor connected between the output node and the feedback node, a second resistor connected between the feedback node and a ground voltage, and a recovery enhancement circuit configured to control a magnitude of one or more drive currents for the error amplifier based on an output voltage of the output node.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0049629, filed on April 16, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Some example embodiments of this disclosure relate to a voltage regulator and a method of operating the voltage regulator. Background Technology

[0003] Different types of voltage regulators are used to supply power to loads with specific voltage levels. However, when the load size (or value) changes suddenly, the output voltage of the voltage regulator can vary depending on how the voltage regulator's circuitry is implemented or designed. This variation in the voltage regulator's output voltage can lead to errors in the operation of electronic devices that rely on the voltage regulator's output voltage. Summary of the Invention

[0004] Some example embodiments of this disclosure relate to a voltage regulator and its operation method for reducing and / or minimizing unexpected variations in the output voltage of the voltage regulator.

[0005] According to some example embodiments, a voltage regulator may include: an error amplifier including a first input terminal receiving a reference voltage, a second input terminal connected to a feedback node, and a first output terminal configured to output a gate voltage; and a transistor connected between the input voltage and the output node. The transistor is configured to operate in response to the gate voltage. The voltage regulator further includes: a first resistor connected between the output node and the feedback node; a second resistor connected between the feedback node and ground; and recovery enhancement circuitry configured to control the magnitude of one or more drive currents for the error amplifier based on the output voltage of the output node.

[0006] According to some example embodiments, a method of operating a voltage regulator includes setting a drive current of an error amplifier to a first current. The voltage regulator includes an error amplifier configured to generate a through-gate voltage. The method further includes increasing the drive current to a second current higher than the first current in response to a differential voltage between the output voltage of the voltage regulator and the through-gate voltage being greater than a first supplementary threshold voltage; and decreasing the drive current to the first current in response to a differential voltage being less than the second supplementary threshold voltage.

[0007] According to some example embodiments, a voltage regulator may include: an error amplifier configured to generate a gate voltage; a transistor connected to an output node and configured to operate in response to the gate voltage; and a recovery enhancement circuit configured to increase one or more drive currents of the error amplifier in response to an overshoot in the voltage level of the output node. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an implementation of a voltage regulator according to some example embodiments.

[0009] Figure 2 A graph showing the relationship between load current, through-gate voltage, and output voltage according to a comparative example is shown.

[0010] Figure 3 yes Figure 1 Block diagram of the error amplifier.

[0011] Figure 4 Based on some example embodiments Figure 3 The circuit diagram of the error amplifier.

[0012] Figure 5 Based on some example embodiments Figure 3 The circuit diagram of the error amplifier.

[0013] Figure 6 This is a circuit diagram of a drive current source according to some example embodiments.

[0014] Figure 7 It is an instruction Figure 1 The curve shows how the recovery enhancement circuit controls the drive current source.

[0015] Figure 8 A graph is shown illustrating the relationship between load current, through-gate voltage, output voltage, and drive current according to some example embodiments of the present disclosure.

[0016] Figure 9 Based on some example embodiments Figure 1 The circuit diagram of the recovery enhancement circuit.

[0017] Figure 10 This is a flowchart of a method for operating a voltage regulator according to some example embodiments of the present disclosure.

[0018] Figure 11 This is a block diagram of a voltage regulator according to some example embodiments.

[0019] Figure 12 Based on some example embodiments Figure 11 The circuit diagram of the recovery enhancement circuit.

[0020] Figure 13 This is a block diagram of a memory system according to some example embodiments.

[0021] Figure 14 This is a block diagram of a Universal Flash Storage (UFS) system according to some example embodiments of the present disclosure. Detailed Implementation

[0022] Various embodiments will be described in detail and clearly below to enable those skilled in the art to readily implement this disclosure. Specific details, such as detailed components and structures, are provided only to aid in a comprehensive understanding of the various embodiments. Therefore, those skilled in the art will understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures have been omitted. In the following drawings or specific embodiments, the configuration may be connected to any components other than those shown in the drawings or described in the specific embodiments. The terminology described below is defined in consideration of the functionality of this disclosure and is not limited to any particular function. The definitions of the terms should be determined based on the entirety of this specification.

[0023] In specific implementations, the components described by reference to terms such as "driver" and "block" will be implemented using software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0024] Figure 1 This is a block diagram of a voltage regulator according to some example embodiments. (Refer to...) Figure 1 The voltage regulator 100 may include an error amplifier 110 and a recovery enhancement circuit 120.

[0025] For ease of explanation, voltage regulator 100 is described as an LDO (low dropout) voltage regulator. However, the exemplary embodiments of this disclosure are not limited to any particular type of voltage regulator 100. For example, voltage regulator 100 may be implemented as one of various voltage regulators, such as linear regulators, buck converters, boost converters, shunt regulators, etc.

[0026] The voltage regulator 100 may also include a transistor TRPS, a first resistor Ra, and a second resistor Rb.

[0027] The transistor TRPS can be connected between the input node NIN and the output node NOUT. The voltage level of the input node NIN can be the input voltage VIN, and the voltage level of the output node NOUT can be the output voltage VOUT.

[0028] The gate terminal of the transistor TRPS can be connected to the through-gate node NPG. The transistor TRPS can be operated based on the through-gate voltage VPG, which is the voltage level of the through-gate node NPG. For example, the transistor TRPS can control the amount of charge supplied between the input node NIN and the output node NOUT in response to the through-gate voltage VPG.

[0029] For ease of explanation, Figure 1 An example of implementing an NMOS (n-channel metal-oxide-semiconductor) transistor via a transistor TRPS is shown, but the example embodiment is not limited thereto. For example, a p-channel metal-oxide-semiconductor PMOS transistor can be implemented via a transistor TRPS.

[0030] The first resistor Ra and the second resistor Rb can be connected in series between the output node NOUT and the ground node. For example, the first resistor Ra can be connected between the output node NOUT and the feedback node NFB, and the second resistor Rb can be connected between the feedback node NFB and the ground node. The voltage level of the feedback node NFB can be called the feedback voltage VFB.

[0031] Error amplifier 110 can receive a reference voltage VREF and a feedback voltage VFB. Error amplifier 110 can generate a through-gate voltage VPG based on the difference between the reference voltage VREF and the feedback voltage VFB. Error amplifier 110 can provide the through-gate voltage VPG to the through-gate node NPG.

[0032] In some example embodiments, the reference voltage VREF may be provided from a constant voltage source. However, the example embodiments of this disclosure are not limited thereto.

[0033] In some example embodiments, the error amplifier 110 may be implemented as an operational amplifier that receives a reference voltage VREF through a non-inverting input terminal and a feedback voltage VFB through an inverting input terminal. However, the example embodiments of this disclosure are not limited thereto. For example, the implementation of the error amplifier 110 may vary depending on the type of transistor TRPS.

[0034] The feedback voltage VFB can be determined based on the resistance ratio of the first resistor Ra and the second resistor Rb, and the output voltage VOUT. The gate voltage VPG can be generated based on the feedback voltage VFB. The output voltage VOUT can be adjusted based on the gate voltage VPG. Thus, the output voltage VOUT can be adjusted to a value corresponding to the resistance ratio of the first resistor Ra and the second resistor Rb, and the level of the reference voltage VREF.

[0035] A load LD can be connected between the output node NOUT and the ground node. A load LD can correspond to one of various electronic devices (such as memory devices, storage devices, processing devices, sensor devices, motor devices, etc.). However, the exemplary embodiments of this disclosure are not limited to a specific type of load LD.

[0036] The current supplied to the load LD is called the load current ILD. The load current ILD can vary dynamically depending on the operation of the load LD (for example, if the load LD is implemented through a memory device or is implemented as a memory device, the load current ILD can vary depending on whether the load LD is performing a read operation or a write operation).

[0037] The output capacitor Cout can be connected between the output node NOUT and the ground node. The output capacitor Cout maintains the output voltage VOUT at a relatively constant value. For example, when there is no load current ILD or when the load current ILD changes, the output capacitor Cout can maintain the output voltage VOUT at a relatively constant value.

[0038] However, if the value of the load current ILD (e.g., its magnitude) (or the value of the power required by the load LD) (e.g., suddenly) changes, the voltage level of the output node NOUT may change (e.g., unexpectedly or unintentionally). This change may cause errors in the operation of a load LD that operates based on the voltage level of the output node NOUT.

[0039] For example, when the value of the load current ILD decreases (e.g., at a relatively rapid rate or suddenly), an overshoot may occur in the voltage level of the output node NOUT. In this case, an overshoot may also occur in the voltage level of the feedback voltage VFB, and the error amplifier 110 may reduce the gate voltage VPG based on the feedback voltage VFB to a level that keeps the transistor TRPS in the off state. Then, the magnitude of the load current ILD may increase (e.g., relatively rapidly). However, due to the reduced gate voltage VPG, the transistor TRPS remains off. In this case, charge transfer between the input node NIN and the output node NOUT is limited, reduced, or decreased until the gate voltage VPG recovers to a relatively higher value to turn on the transistor TRPS, resulting in a relatively larger undershoot in the voltage level of the output voltage VOUT due to the load current ILD.

[0040] On the other hand, according to some exemplary embodiments of this disclosure, the recovery enhancement circuit 120 may enhance or improve the recovery through the gate voltage VPG based on the output voltage VOUT. For example, the recovery enhancement circuit 120 may increase the rate at which the gate voltage VPG increases to a relatively higher voltage level to turn on the transistor TRPS.

[0041] For example, in response to an overshoot in the output voltage VOUT, the recovery enhancement circuit 120 can enhance or improve the recovery through the gate voltage VPG. In this case, even if the load current ILD increases (e.g., at a relatively fast rate or suddenly), the gate voltage VPG can recover to a high voltage level that allows the transistor TRPS to conduct more quickly. Therefore, according to some example embodiments of this disclosure, the undershoot of the output voltage VOUT caused by the increase in the load current ILD while the transistor TRPS is turned off can be minimized or reduced.

[0042] In the following description, for ease of explanation, an example embodiment is described in which the recovery enhancement circuit 120 determines whether an overshoot has occurred in the output voltage VOUT based on the difference between the output voltage VOUT and the gate voltage VPG. However, the example embodiments of this disclosure are not limited to any particular method by which the recovery enhancement circuit 120 determines whether an overshoot has occurred in the output voltage VOUT.

[0043] The recovery enhancement circuit 120 may include a differential detection circuit 121 and a drive current control circuit 122.

[0044] The differential detection circuit 121 can detect the difference between the gate voltage VPG and the output voltage VOUT. For example, the differential detection circuit 121 can detect the differential voltage (hereinafter referred to as "VDIFF") by subtracting the gate voltage VPG from the output voltage VOUT.

[0045] The differential detection circuit 121 can determine whether an overshoot occurs in the output voltage VOUT based on the differential voltage VDIFF. The differential detection circuit 121 can control the drive current control circuit 122 based on the differential voltage VDIFF. For example, the differential detection circuit 121 can generate a supplementary current control voltage (hereinafter referred to as "VSCC") based on the differential voltage VDIFF.

[0046] The drive current control circuit 122 can control the drive current source CS_DRV included in the error amplifier 110 according to the control of the differential detection circuit 121. For example, the drive current control circuit 122 can generate a drive current supplement signal SS_IDRV based on the supplementary current control voltage VSCC.

[0047] Error amplifier 110 may include a drive current source CS_DRV. The drive current source CS_DRV may change the value of the drive current IDRV in response to a drive current supplement signal SS_IDRV. For example, the drive current source CS_DRV may increase the value of the drive current IDRV in response to the drive current supplement signal SS_IDRV.

[0048] In some example embodiments, the drive current IDRV may be the current used for the operation of the error amplifier 110. See below for further details. Figures 3 to 5 Discuss the drive current IDRV.

[0049] As the drive current IDRV increases, the rate at which the error amplifier 110 supplies current through the gate node NPG (e.g., the rate at which effective charge is supplied through the gate node NPG) can be increased. The length of the transient response through the gate voltage VPG can be shortened according to the change in the feedback voltage VFB. Therefore, the rate at which the error amplifier 110 controls the gate voltage VPG based on the reference voltage VREF and the feedback voltage VFB can be increased. The time required for the gate voltage VPG to recover to a level high enough to turn on the transistor TRPS can be minimized, reduced, or decreased. Therefore, according to some example embodiments of this disclosure, the undershoot of the output voltage VOUT can be minimized, reduced, or decreased.

[0050] Figure 2 A graph showing the relationship between load current, through-gate voltage, and output voltage according to a comparative example is shown. Referring below... Figure 1 and Figure 2 It describes the load current ILD, the gate voltage VPG, and the output voltage VOUT when the recovery enhancement circuit 120 does not perform the recovery enhancement operation (e.g., the drive current supplement signal SS_IDRV is not provided to the error amplifier 110). Figure 2 The horizontal axis of each graph shown represents time, while Figure 2 The vertical axis of each of the graphs shown can represent voltage (e.g., through the gate voltage VPG and the output voltage VOUT) or current (e.g., the load current ILD).

[0051] Before the first time point t1, the output voltage VOUT can be the target voltage VTG. In the following, it is assumed that the load current ILD has a constant value before the first time point t1. However, the exemplary embodiments of this disclosure are not limited thereto.

[0052] Between the first time point t1 and the second time point t2, the magnitude of the load current ILD can decrease (e.g., rapidly). However, since the gate voltage VPG is determined by the error amplifier 110 based on the operation of the feedback voltage VFB, the gate voltage VPG can decrease relatively slowly compared to the rate of decrease of the load current ILD. In this case, even if the value of the load current ILD decreases (e.g., suddenly), the transistor TRPS can still provide the input voltage VIN to the output node NOUT in response to the gate voltage VPG. Therefore, between the first time point t1 and the second time point t2, the output voltage VOUT can rise (e.g., overshoot) to a voltage level higher than the target voltage VTG.

[0053] After the second time point t2, the load current ILD may remain at a lower value compared to the first time point t1. For ease of explanation, it is assumed below that after the second time point t2, the value of the load current ILD is '0' (e.g., in a no-load state). However, the exemplary embodiments of this disclosure are not limited thereto.

[0054] At the second time point t2, the output voltage VOUT may be higher than the target voltage VTG. In this case, the error amplifier 110 can reduce the gate voltage VPG to reduce the output voltage VOUT. Therefore, after the second time point t2, the gate voltage VPG can be further reduced. In this case, charge transfer between the input node NIN and the output node NOUT can be prevented or reduced, and the output voltage VOUT is maintained by the output capacitor Cout, so even after the second time point t2, the output voltage VOUT can remain in an overshoot state.

[0055] Thus, if the no-load (or low-load) state is maintained after the second time point t2, the gate voltage VPG can be maintained at a low voltage that turns off the transistor TRPS before the third time point t3 when the load current ILD increases again, and the output voltage VOUT can be maintained in an overshoot state.

[0056] Between the third time point t3 and the fourth time point t4, the magnitude of the load current ILD can increase (e.g., rapidly). However, since the through-gate voltage VPG at the third time point t3 is a low voltage that turns off the through-transistor TRPS, the load LD can receive current from the output capacitor Cout instead of the input node NIN. In this case, the output voltage VOUT can continuously decrease due to the discharge of the output capacitor Cout before the through-gate voltage VPG increases high enough to turn on the voltage through the transistor TRPS. Therefore, a temporary undershoot can occur in the output voltage VOUT between the third time point t3 and the fourth time point t4.

[0057] Simultaneously, as the output voltage VOUT decreases, the feedback voltage VFB also decreases. In this case, the error amplifier 110 can increase the gate voltage VPG in response to the feedback voltage VFB. For example, the error amplifier 110 can provide charge to the gate node NPG in response to the decrease in output voltage VOUT (e.g., in response to the decrease in feedback voltage VFB). In this case, the transistor TRPS can increase the voltage level of the output node NOUT based on the input voltage VIN in response to the gate voltage VPG. Therefore, at the fourth time point t4, the output voltage VOUT can recover to the target voltage VTG.

[0058] In other words, the value of the undershoot of the output voltage VOUT (e.g., the difference between the target voltage VTG and the lowest level of the output voltage VOUT between the third time point t3 and the fourth time point t4) and the duration of the undershoot (e.g., the duration of time after the third time point t3 for the output voltage VOUT to recover to the target voltage VTG) can be determined based on the rate at which the gate voltage VPG increases in response to a decrease in the output voltage VOUT. The rate at which the gate voltage VPG increases in response to a decrease in the output voltage VOUT can be determined by the rate at which the error amplifier 110 provides charge to the gate node NPG (e.g., the amount of effective charge provided per unit time). The rate at which the error amplifier 110 provides charge to the gate node NPG can be determined based on the current value of the drive current source CS_DRV included in the error amplifier 110. In summary, the value of the undershoot of the output voltage VOUT and the duration of the undershoot can be determined based on the current value of the drive current source CS_DRV included in the error amplifier 110. However, as the drive current source CS_DRV generates a higher drive current IDRV, the power consumption of the voltage regulator 100 can increase.

[0059] According to some example embodiments of this disclosure, the recovery enhancement circuit 120 can adaptively adjust the value of the drive current IDRV. In this case, the power consumption of the voltage regulator 100 during normal operation can be minimized or reduced, and the undershoot of the output voltage VOUT can be minimized or reduced even if the load current ILD changes at a relatively high rate. Referring below... Figures 7 to 9 Describe the operating mechanism of the recovery enhancement circuit 120.

[0060] Figure 3 yes Figure 1 The block diagram of the error amplifier. (Refer to...) Figure 3 Continue to refer to Figure 1 and Figure 2 The error amplifier 110 may include a differential input circuit 111 and an amplifier circuit 112.

[0061] The differential input circuit 111 can receive a reference voltage VREF and a feedback voltage VFB. The differential input circuit 111 can control the amplifier circuit 112 based on the reference voltage VREF and the feedback voltage VFB.

[0062] Amplifier circuit 112 can generate an output voltage (e.g., via gate voltage VPG) in response to control of differential input circuit 111, which is the result of the difference between amplified reference voltage VREF and feedback voltage VFB.

[0063] Error amplifier 110 may include one or more drive current sources CS_DRV. For example, at least one of differential input circuit 111 and amplifier circuit 112 may include one or more drive current sources CS_DRV. For ease of explanation, Figure 3 Some example embodiments are shown where the differential input circuit 111 includes a drive current source CS_DRVa and the amplifier circuit 112 includes a drive current source CS_DRVb, but the example embodiments of this disclosure are not limited to the number of drive current sources CS_DRV included in each of the differential input circuit 111 and the amplifier circuit 112.

[0064] The differential input circuit 111 can operate based on the drive current source CS_DRVa. For example, the differential input circuit 111 can control the amplifier circuit 112 based on the drive current IDRVa generated by the drive current source CS_DRVa.

[0065] Amplifier circuit 112 can operate based on drive current source CS_DRVb. For example, amplifier circuit 112 can generate gate voltage VPG based on drive current IDRVb generated by drive current source CS_DRVb.

[0066] The drive current control circuit 122 can provide a drive current supplement signal SS_IDRV to one or more drive current sources CS_DRV included in the error amplifier 110. For example, the drive current control circuit 122 can provide a drive current supplement signal SS_IDRVa to a drive current source CS_DRVa, and can provide a drive current supplement signal SS_IDRVb to a drive current source CS_DRVb.

[0067] The drive current source CS_DRVa can increase the drive current IDRVa in response to the drive current supplement signal SS_IDRVa. The drive current source CS_DRVb can increase the drive current IDRVb in response to the drive current supplement signal SS_IDRVb. In this case, the rate at which the level of the gate voltage VPG changes in response to changes in the reference voltage VREF and the feedback voltage VFB can be increased.

[0068] The scope of this disclosure is not limited to any particular implementation of the differential input circuit 111 and the amplifier circuit 112. For ease of explanation, reference will be made to... Figure 4 and Figure 5 Describe the structure or configuration of the differential input circuit 111 and the amplifier circuit 112.

[0069] Figure 4 Based on some example embodiments Figure 3 The circuit diagram of the error amplifier. (Refer to...) Figure 4 Continue to refer to Figures 1 to 3 The differential input circuit 111 can be implemented as differential input circuit 111_1, and the amplifier circuit 112 can be implemented as amplifier circuit 112_1. The differential input circuit 111_1 may include a drive current source CS_DRVa, and the amplifier circuit 112_1 may not include a drive current source CS_DRVb.

[0070] The differential input circuit 111_1 may include a first differential input transistor TRDI1, a second differential input transistor TRDI2, and a drive current source CS_DRVa.

[0071] The drive current source CS_DRVa can be connected between the power supply voltage VDD and the first node N1. The drive current source CS_DRVa can provide the drive current IDRVa to the first node N1. The drive current source CS_DRVa can adjust the value of the drive current IDRVa in response to the drive current supplement signal SS_IDRVa.

[0072] The first differential input transistor TRDI1 can be connected between the first node N1 and the second node N2. The gate terminal of the first differential input transistor TRDI1 can receive the reference voltage VREF. The second differential input transistor TRDI2 can be connected between the first node N1 and the third node N3. The gate terminal of the second differential input transistor TRDI2 can receive the feedback voltage VFB.

[0073] In some example embodiments, the ratio of the drive current IDRVa distributed to each of the second node N2 and the third node N3 can be determined based on the relative magnitudes of the feedback voltage VFB and the reference voltage VREF. That is, the current flowing through the first differential input transistor TRDI1 and the current flowing through the second differential input transistor TRDI2 can be determined based on the feedback voltage VFB and the reference voltage VREF.

[0074] The amplifier circuit 112_1 may include a first amplifying transistor TRA1 and a second amplifying transistor TRA2.

[0075] The first amplifying transistor TRA1 can be connected between the second node N2 and ground. The gate terminal of the first amplifying transistor TRA1 can be connected to the second node N2. The second amplifying transistor TRA2 can be connected between the third node N3 and ground. The gate terminal of the second amplifying transistor TRA2 can be connected to the second node N2.

[0076] The third node N3 can be connected to the output terminal of the error amplifier 110. For example, the third node N3 can be connected through the gate node NPG.

[0077] As the value of the drive current IDRVa increases, the amount of charge flowing through the first differential input transistor TRDI1 and the second differential input transistor TRDI2 can increase. The gate voltage VPG can recover at a higher rate between the third time point t3 and the fourth time point t4, thus minimizing or reducing the undershoot of the output voltage VOUT.

[0078] In some example embodiments, the first differential input transistor TRDI1 and the second differential input transistor TRDI2 may be implemented as PMOS transistors, and the first amplifying transistor TRA1 and the second amplifying transistor TRA2 may be implemented as NMOS transistors. However, the example embodiments of this disclosure are not limited to any particular type of transistor included in the error amplifier 110.

[0079] For ease of explanation, in Figure 4 The present disclosure typically describes some example embodiments of the differential input circuit 111_1 including a single drive current source CS_DRVa, but these examples are not limited thereto. For instance, the differential input circuit 111_1 may not include a drive current source CS_DRVa or may include two or more drive current sources CS_DRVa. In some example embodiments, when the differential input circuit 111_1 includes two or more drive current sources CS_DRVa, the drive current control circuit 122 may provide a drive current supplement signal SS_IDRVa to some or all of the drive current sources CS_DRVa included in the differential input circuit 111_1.

[0080] Figure 5 Based on some example embodiments Figure 3 The circuit diagram of the error amplifier. (Refer to...) Figure 5 Continue to refer to Figures 1 to 4 The differential input circuit 111 can be implemented as a differential input circuit 111_2, and the amplifier circuit 112 can be implemented as an amplifier circuit 112_2. The differential input circuit 111_2 may include a drive current source CS_DRVa, and the amplifier circuit 112_2 may include a first drive current source CS_DRVb1 and a second drive current source CS_DRVb2.

[0081] The differential input circuit 111_2 may include a third differential input transistor TRDI3, a fourth differential input transistor TRDI4, and a drive current source CS_DRVa. The drive current source CS_DRVa can adjust the value of the drive current IDRVa in response to the drive current compensation signal SS_IDRVa.

[0082] The drive current source CS_DRVa can be connected between the power supply voltage VDD and the eleventh node N11. The third differential input transistor TRDI3 can be connected between the eleventh node N11 and the twelfth node N12. The gate terminal of the third differential input transistor TRDI3 can receive the reference voltage VREF. The fourth differential input transistor TRDI4 can be connected between the eleventh node N11 and the thirteenth node N13. The gate terminal of the fourth differential input transistor TRDI4 can receive the feedback voltage VFB. The functions and operations of the components included in the differential input circuit 111_2 are similar to those of the components included in the differential input circuit 111_1, therefore detailed descriptions are omitted.

[0083] The amplifier circuit 112_2 may include a third amplifier transistor TRA3 to an eighth amplifier transistor TRA8, a first drive current source CS_DRVb1, and a second drive current source CS_DRVb2.

[0084] The third amplifying transistor TRA3 can be connected between the twelfth node N12 and ground. The fourth amplifying transistor TRA4 can be connected between the thirteenth node N13 and ground. The gate terminals of the third amplifying transistor TRA3 and the fourth amplifying transistor TRA4 can be connected to the fourteenth node N14.

[0085] The fifth amplifying transistor TRA5 can be connected between the twelfth node N12 and the fourteenth node N14. The sixth amplifying transistor TRA6 can be connected between the thirteenth node N13 and the fifteenth node N15. The gate terminals of the fifth amplifying transistor TRA5 and the sixth amplifying transistor TRA6 can be connected to each other.

[0086] The seventh amplifying transistor TRA7 can be connected between the fourteenth node N14 and the sixteenth node N16. The eighth amplifying transistor TRA8 can be connected between the fifteenth node N15 and the seventeenth node N17. The gate terminals of the seventh amplifying transistor TRA7 and the eighth amplifying transistor TRA8 can be connected to each other. The fifteenth node N15 can be connected to the output terminal of the error amplifier 110. For example, the fifteenth node N15 can be connected through the gate node NPG.

[0087] The first drive current source CS_DRVb1 can be connected between the power supply voltage VDD and the sixteenth node N16. The first drive current source CS_DRVb1 can provide the first drive current IDRVb1 to the sixteenth node N16. The first drive current source CS_DRVb1 can adjust the value of the first drive current IDRVb1 in response to the drive current supplement signal SS_IDRVb.

[0088] The second drive current source CS_DRVb2 can be connected between the power supply voltage VDD and the seventeenth node N17. The second drive current source CS_DRVb2 can provide the second drive current IDRVb2 to the seventeenth node N17. The second drive current source CS_DRVb2 can adjust the value of the second drive current IDRVb2 in response to the drive current supplement signal SS_IDRVb.

[0089] In some example embodiments, the magnitudes of the first drive current IDRVb1 and the second drive current IDRVb2 may be the same. In this case, the drive current control circuit 122 can uniformly control the first drive current IDRVb1 and the second drive current IDRVb2 based on the drive current supplement signal SS_IDRVb. However, the example embodiments of this disclosure are not limited thereto. For the sake of simplicity, in Figure 5 The example embodiment described is a first drive current source CS_DRVb1 and the second drive current source CS_DRVb2 sharing a drive current supplement signal SS_IDRVb. However, the drive current control circuit 122 may control only some (not all) of the two or more drive current sources CS_DRVb included in the amplifier circuit 112_2 (e.g., only control the second drive current source CS_DRVb2), or it may independently control the two or more drive current sources CS_DRVb included in the amplifier circuit 112_2.

[0090] When one or more of the drive current IDRVa, the first drive current IDRVb1, and the second drive current IDRVb2 increase, the amount of charge moving between the nodes included in the error amplifier 110 can increase according to the change in the feedback voltage VFB. In this case, the gate voltage VPG can change at a faster rate according to the change in the feedback voltage VFB. Therefore, according to the exemplary embodiment of this disclosure, the gate voltage VPG can recover at a relatively faster rate between the aforementioned third time point t3 and the fourth time point t4, thus minimizing or reducing the undershoot of the output voltage VOUT.

[0091] In some example embodiments, the third differential input transistor TRDI3 and the fourth differential input transistor TRDI4, as well as the seventh amplifying transistor TRA7 and the eighth amplifying transistor TRA8, may be implemented as PMOS transistors; and the third amplifying transistor TRA3 through the sixth amplifying transistor TRA6 may be implemented as NMOS transistors. However, the example embodiments of this disclosure are not limited to any particular type of transistor included in the error amplifier 110.

[0092] Figure 6 This is a circuit diagram of a drive current source according to some example embodiments. In the following, reference is made to... Figures 1 to 6 , described Figures 3 to 5 Example configuration of one of the drive current sources CS_DRV.

[0093] The drive current source CS_DRV can be connected between the first node Na and the second node Nb. In some example embodiments, the first node Na can be supplied with a power supply voltage VDD, and the second node Nb can be connected to one of the nodes included in the error amplifier 110.

[0094] The driving current source CS_DRV may include a driving constant current source CS_cst and a driving variable current source CS_var. The driving constant current source CS_cst and the driving variable current source CS_var may be connected in parallel between the first node Na and the second node Nb.

[0095] A constant current source CS_cst can generate a constant current IDRV_cst. The constant current IDRV_cst can be a constant (or relatively constant) current that can be maintained between the first node Na and the second node Nb.

[0096] The variable current source CS_var generates a supplementary drive current IDRV_supp. The value of the supplementary drive current IDRV_supp can be determined based on the drive current supplement signal SS_IDRV. For example, the variable current source CS_var can temporarily increase the value of the supplementary drive current IDRV_supp in response to the drive current supplement signal SS_IDRV. See below. Figure 7 and Figure 8 Discuss how to determine the value of the supplementary drive current IDRV_supp.

[0097] The drive current IDRV can be implemented as the sum of the supplementary drive current IDRV_supp and the drive constant current IDRV_cst.

[0098] In some example embodiments, the drive current source CS_DRV may further include an operating mode current source connected in parallel with the drive constant current source CS_cst and the drive variable current source CS_var between the first node Na and the second node Nb. The operating mode current source may generate an operating mode current value according to the operating mode of the voltage regulator 100 (e.g., high-performance mode, low-power mode, etc.) in response to an operating mode signal. The drive current IDRV may be determined as the sum of the supplementary drive current IDRV_supp, the drive constant current IDRV_cst, and the operating mode current. However, other implementations are possible, and the example embodiments of this disclosure are not limited to any particular implementation of the drive current source CS_DRV.

[0099] Figure 7 It is an instruction Figure 1 The curve showing how the recovery enhancement circuit controls the drive current source is shown below. For ease of explanation, please refer to... Figures 1 to 7 An example embodiment of the recovery enhancement circuit 120 is discussed, which controls a drive current source CS_DRV included in the error amplifier 110 based on the difference between the output voltage VOUT and the gate voltage VPG. Figure 7 The horizontal axis can represent the differential voltage VDIFF corresponding to the value obtained by subtracting the gate voltage VPG from the output voltage VOUT, and the vertical axis can represent the value of the drive current IDRV.

[0100] When the differential voltage VDIFF is less than the supplementary threshold voltage VTHSP, the recovery enhancement circuit 120 can determine the value of the drive current IDRV as the first current I1. For example, the recovery enhancement circuit 120 can determine the value of the supplementary drive current IDRV_supp as '0' based on the drive current supplementary signal SS_IDRV. In this case, the value of the drive current IDRV can be determined as the first current I1 corresponding to the value of the drive constant current IDRV_cst.

[0101] When the differential voltage VDIFF is greater than the supplementary threshold voltage VTHSP, the recovery enhancement circuit 120 can determine the value of the drive current IDRV as the second current I2. For example, the recovery enhancement circuit 120 can determine the value of the supplementary drive current IDRV_supp as greater than '0' based on the drive current supplementary signal SS_IDRV. In this case, the value of the drive current IDRV can be greater than the value of the drive constant current IDRV_cst.

[0102] For ease of explanation, Figure 7The illustration shows the recovery enhancement circuit 120 determining the value of the drive current IDRV as one of a first current I1 and a second current I2 based on the supplementary threshold voltage VTHSP; however, the exemplary embodiments of this disclosure are not limited thereto. For example, as the differential voltage VDIFF becomes greater than the supplementary threshold voltage VTHSP, the recovery enhancement circuit 120 may increase the value of the drive current IDRV. In other words, the recovery enhancement circuit 120 may gradually (e.g., linearly or logarithmically) increase the value of the supplementary drive current IDRV_supp according to the value of the differential voltage VDIFF.

[0103] In addition, for ease of explanation, Figure 7 A scheme in which the recovery enhancement circuit 120 controls a drive current source CS_DRV has been described representatively, but the exemplary embodiments of this disclosure are not limited thereto. For example, the recovery enhancement circuit 120 may be configured in accordance with the above-described reference. Figures 3 to 5 The error amplifier 110 includes two or more drive current sources CS_DRV in a similar manner. In this case, the recovery enhancement circuit 120 can control each of the two or more drive current sources CS_DRV included in the error amplifier 110 to generate drive currents IDRV of different values ​​(e.g., magnitudes).

[0104] Figure 8 A graph illustrating the relationship between load current, through-gate voltage, output voltage, and drive current according to some example embodiments of the present disclosure is shown. Hereinafter, reference is made to... Figures 1 to 8 Assume that the recovery enhancement circuit 120 controls the drive current IDRV of a drive current source CS_DRV. Figure 8 In the graphs shown, the horizontal axis represents time, and the vertical axis represents voltage or current.

[0105] The dashed curve corresponds to the case where the recovery enhancement circuit 120 does not perform the recovery enhancement operation, while the solid curve corresponds to the case where the recovery enhancement circuit 120 performs the recovery enhancement operation.

[0106] The magnitude of the load current ILD can decrease between a first time point t1 and a second time point t2 (e.g., at a relatively higher rate or suddenly). In this case, as referenced... Figure 2 As previously described, the output voltage VOUT can be increased to a voltage level higher than the target voltage VTG (e.g., overshoot) until the magnitude of the load current ILD increases again, and the gate voltage VPG can be reduced to a low voltage that turns off the transistor TRPS.

[0107] When the recovery enhancement circuit 120 performs a recovery enhancement operation, the differential detection circuit 121 can identify the differential voltage VDIFF. At the fifth time point t5 when the differential voltage VDIFF becomes greater than the supplementary threshold voltage VTHSP, the differential detection circuit 121 can control the drive current source CS_DRV through the drive current control circuit 122 to increase the drive current IDRV from the first current I1 to the second current I2. In this way, the recovery enhancement circuit 120 can increase the drive current IDRV in response to the value of the load LD decreasing at a relatively higher rate or suddenly. On the other hand, when the recovery enhancement circuit 120 does not perform a recovery enhancement operation, the drive current IDRV can be maintained at (or approximately maintained at) the first current I1.

[0108] For ease of explanation, Figure 8 The fifth time point t5 is shown to be a time point between the first time point t1 and the second time point t2, but the exemplary embodiments of this disclosure are not limited thereto. For example, the fifth time point t5 could be a time point between the second time point t2 and the third time point t3.

[0109] Between the third time point t3 and the fourth time point t4, the magnitude of the load current ILD can increase. In this case, it is similar to the reference above. Figure 2 As described, the output voltage VOUT can continue to decrease until the gate voltage VPG increases high enough to turn on the voltage across transistor TRPS. As a result, an undershoot can occur in the output voltage VOUT.

[0110] Referring to both the dashed and solid graphs, when the recovery enhancement circuit 120 performs the recovery enhancement operation, the gate voltage VPG can rise relatively quickly to a sufficiently high level to conduct the voltage through the transistor TRPS, compared to when the recovery enhancement circuit 120 does not perform the recovery enhancement operation.

[0111] Therefore, compared to when the recovery enhancement circuit 120 does not perform the recovery enhancement operation, when the recovery enhancement circuit 120 performs the recovery enhancement operation, the value and duration of the undershoot of the output voltage VOUT occurring between the third time point t3 and the fourth time point t4 can be reduced. Since the output voltage VOUT can be maintained similarly to the target voltage VTG, the possibility of errors occurring in the operation of the electronic device corresponding to the load LD can be reduced.

[0112] When the recovery enhancement circuit 120 performs the recovery enhancement operation, at the sixth time point t6 when the differential voltage VDIFF becomes less than the supplementary threshold voltage VTHSP, the differential detection circuit 121 can control the drive current source CS_DRV via the drive current control circuit 122 to reduce the drive current IDRV to a first current I1. In this way, the recovery enhancement circuit 120 can recover (e.g., reduce) the drive current IDRV in response to an increase in the value of the load LD. In this case, while the electronic device corresponding to the load LD operates normally, the power consumption of the voltage regulator 100 can be minimized, reduced, or decreased.

[0113] For ease of explanation, Figure 8 and Figure 9 An example embodiment is shown where the recovery enhancement circuit 120 increases the drive current IDRV when the differential voltage VDIFF becomes greater than the supplementary threshold voltage VTHSP and decreases the drive current IDRV when the differential voltage VDIFF becomes less than the supplementary threshold voltage VTHSP. However, the example embodiments of this disclosure are not limited thereto. For example, the recovery enhancement circuit 120 may be implemented to increase the drive current IDRV when the differential voltage VDIFF becomes greater than a first supplementary threshold voltage, and may be implemented to decrease the drive current IDRV when the differential voltage VDIFF becomes less than a second supplementary threshold voltage different from the first supplementary threshold voltage. The example embodiments of this disclosure are not limited to any particular operating condition (e.g., trigger condition) of the recovery enhancement circuit 120.

[0114] Figure 9 Based on some example embodiments Figure 1 The circuit diagram of the recovery enhancement circuit is shown below. (Refer to...) Figures 1 to 9 The recovery enhancement circuit 120 may include a differential detection circuit 121 and a drive current control circuit 122.

[0115] The differential detection circuit 121 may include a comparator amplifier CAMP and an offset voltage source VS_OS. The non-inverting input terminal of the comparator amplifier CAMP can be connected to the output node NOUT. The comparator amplifier CAMP can receive the output voltage VOUT through its non-inverting input terminal. The inverting input terminal of the comparator amplifier CAMP can be connected to the gate node NPG through the offset voltage source VS_OS. The comparator amplifier CAMP can receive a voltage with an offset voltage VOS higher than the gate voltage VPG through its inverting input terminal.

[0116] In some example embodiments, the offset voltage VOS may correspond to the supplementary threshold voltage VTHSP.

[0117] The comparator amplifier (CAMP) outputs a supplementary current control voltage (VSCC) via its output terminal. A relatively high VSCC is generated when the value obtained by subtracting the gate voltage (VPG) from the output voltage (VOUT) is higher than the offset voltage (VOS); conversely, a relatively low VSCC is generated when the value obtained by subtracting the gate voltage (VPG) from the output voltage (VOUT) is less than the offset voltage (VOS). Thus, the comparator amplifier (CAMP) generates the supplementary current control voltage (VSCC) based on whether the differential voltage (VDIFF) is greater than the supplementary threshold voltage (VTHSP) (or the offset voltage (VOS)).

[0118] For ease of explanation, Figure 9 An example embodiment of the comparator amplifier CAMP is shown, which receives the output voltage VOUT through a non-inverting input terminal and a voltage VOS that is higher than the gate voltage VPG through an inverting input terminal. However, the example embodiments of this disclosure are not limited to the specific implementation of the differential detection circuit 121. For example, the comparator amplifier CAMP may be implemented to receive a voltage VOS that is lower than the output voltage VOUT through a non-inverting input terminal and to receive the gate voltage VPG through an inverting input terminal.

[0119] The drive current control circuit 122 may include a first current source transistor TRCS1 and first mirror transistors TRMR1 to third mirror transistors TRMR3.

[0120] The first current source transistor TRCS1 can be connected between the power supply voltage VDD and the twenty-first node N21. The first current source transistor TRCS1 can supply current to the twenty-first node N21 in response to the supplementary current control voltage VSCC. For example, when the supplementary current control voltage VSCC has a higher voltage, the first current source transistor TRCS1 can supply a relatively larger current to the twenty-first node N21; and when the supplementary current control voltage VSCC has a lower voltage, the first current source transistor TRCS1 can supply a relatively smaller current to the twenty-first node N21.

[0121] The first mirror transistor TRMR1 can be connected between the 21st node N21 and ground. The second mirror transistor TRMR2 can be connected between the 22nd node N22 and ground. The gate terminals of the first mirror transistor TRMR1 and the second mirror transistor TRMR2 can be connected to the 21st node N21. A current with the same (or similar) value as the current generated by the first current source transistor TRCS1 can be mirrored as the current flowing through the second mirror transistor TRMR2.

[0122] The third mirror transistor TRMR3 can be connected between the 22nd node N22 and the power supply voltage VDD. The gate terminal of the third mirror transistor TRMR3 can be connected to the 22nd node N22.

[0123] The driving variable current source CS_var may include a fourth mirror transistor TRMR4. The source terminal of the fourth mirror transistor TRMR4 may be connected to the power supply voltage VDD. The gate terminal of the fourth mirror transistor TRMR4 may be connected to the twenty-second node N22. The drive current control circuit 122 may provide a drive current supplement signal SS_IDRV to the drive current source CS_DRV in the form of the voltage level of the twenty-second node N22. The current flowing through the second mirror transistor TRMR2 may be mirrored by the third mirror transistor TRMR3 into a supplementary drive current IDRV_supp flowing through the fourth mirror transistor TRMR4. In other words, the drive current control circuit 122 may generate a supplementary drive current IDRV_supp (e.g., the current flowing through the second mirror transistor TRMR2), and the driving variable current source CS_var may mirror the supplementary drive current IDRV_supp into a current flowing through the fourth mirror transistor TRMR4. Thus, the recovery enhancement circuit 120 may control the value of one or more drive currents IDRV.

[0124] In some example embodiments, the first current source transistor TRCS1 and the first mirror transistor TRMR1 and the second mirror transistor TRMR2 may be implemented as NMOS transistors. The third mirror transistor TRMR3 and the fourth mirror transistor TRMR4 may be implemented as PMOS transistors. However, the example embodiments of this disclosure are not limited to the specific types of transistors included in the recovery enhancement circuit 120.

[0125] In some example embodiments, a 'current-limiting transistor' may also be connected between the drain terminal of the second mirror transistor TRMR2 and the twenty-second node N22. The gate terminal of the 'current-limiting transistor' may be connected to a bias voltage. In this case, the value of the supplementary drive current IDRV_supp can be limited to a specific (or desired or given) value by the current-limiting transistor. In this case, the phenomenon that the supplementary drive current IDRV_supp increases excessively as the differential voltage VDIFF increases can be reduced or prevented. However, the example embodiments of this disclosure are not limited thereto.

[0126] For ease of explanation, Figure 9This is a representative example of the recovery enhancement circuit 120 controlling the value of the supplementary drive current IDRV_supp based on the comparator amplifier CAMP and the current mirror, but the exemplary embodiments of this disclosure are not limited to the specific implementation of the recovery enhancement circuit 120. For example, the recovery enhancement circuit 120 may be implemented as switching one or more current sources included in the variable current source CS_var based on the supplementary current control voltage VSCC.

[0127] Figure 10 This is a flowchart of a method for operating a voltage regulator according to some example embodiments of this disclosure. It should be understood that... Figure 10 Additional operations are provided before, during, and after the operations described herein, and for additional embodiments of the method, some of the operations described below may be replaced or cancelled. The order of operations / processes may be changed, or two or more operations may be performed simultaneously. See reference. Figure 10 Continue to refer to Figures 1 to 9 In operation S110, the voltage regulator 100 can set the drive current IDRV with a first current I1. For example, the recovery enhancement circuit 120 can set the drive current IDRV generated by a drive current source CS_DRV included in the error amplifier 110 with a first current I1.

[0128] In operation S120, the voltage regulator 100 determines whether the differential voltage VDIFF is greater than the supplementary threshold voltage VTHSP. If the differential voltage VDIFF is greater than the supplementary threshold voltage VTHSP, operation S130 can be executed. If the differential voltage VDIFF is less than the supplementary threshold voltage VTHSP, operation S120 can be repeated. In this way, the voltage regulator 100 can maintain the drive current IDRV at the first current I1 until the differential voltage VDIFF becomes greater than the supplementary threshold voltage VTHSP.

[0129] In operation S130, voltage regulator 100 can increase the drive current IDRV from the first current I1. For example, recovery enhancement circuit 120 can increase the drive current IDRV generated by a drive current source CS_DRV included in error amplifier 110 to a second current I2 higher than the first current I1.

[0130] In some example embodiments, operation S130 can be performed in response to a decrease in the magnitude of the load current ILD. For example, operation S130 can be performed in response to an increase in the output voltage VOUT and a decrease in the gate voltage VPG as the magnitude of the load current ILD decreases.

[0131] In operation S140, voltage regulator 100 determines whether the differential voltage VDIFF is less than the supplementary threshold voltage VTHSP. If the differential voltage VDIFF is less than the supplementary threshold voltage VTHSP, operation S150 is performed. If the differential voltage VDIFF is greater than the supplementary threshold voltage VTHSP, operation S140 is repeated. In this way, voltage regulator 100 can maintain the magnitude of the drive current IDRV above the first current I1 (e.g., maintain it at the second current I2) until the differential voltage VDIFF becomes less than the supplementary threshold voltage VTHSP. In this case, even if the load current ILD changes (e.g., rapidly), the gate voltage VPG can be recovered at a relatively high rate, thereby minimizing or reducing the change in the output voltage VOUT of voltage regulator 100.

[0132] In operation S150, voltage regulator 100 can reduce the drive current IDRV to a first current I1. For example, recovery enhancement circuit 120 can restore the drive current IDRV generated by a drive current source CS_DRV included in error amplifier 110 to the value previously set in operation S110. Therefore, the method can reduce the power consumption of voltage regulator 100.

[0133] In some example embodiments, operation S150 may be performed in response to an increase in the magnitude of the load current ILD. For example, operation S150 may be performed in response to a decrease in the output voltage VOUT as the magnitude of the load current ILD increases.

[0134] Figure 11 This is a block diagram of a voltage regulator according to some example embodiments. (Refer to...) Figure 11 And continue to refer to Figures 1 to 10 The voltage regulator 200 may include an error amplifier 210, a recovery enhancement circuit 220, a buffer circuit 230, a transistor TRPS, a first resistor Ra, a second resistor Rb, and an output capacitor Cout. The configuration and operation of the error amplifier 210, the transistor TRPS, the first resistor Ra, the second resistor Rb, and the output capacitor Cout are similar to those described above. Figures 1 to 11 The descriptions are omitted for the sake of brevity.

[0135] Buffer circuit 230 may be connected between the output terminal of error amplifier 210 (hereinafter referred to as error amplifier output node NEAO) and the through-gate node NPG. For example, buffer circuit 230 may provide the through-gate voltage VPG generated by buffering the error amplifier output voltage VEAO provided from error amplifier output node NEAO to through-gate node NPG.

[0136] The recovery enhancement circuit 220 may include an error clamping circuit ECC and a drive current control circuit 222. The error clamping circuit ECC may include a differential detection circuit 221.

[0137] The error clamping circuit ECC can control the error amplifier output voltage VEAO based on the gate voltage VPG and the output voltage VOUT. For example, the error clamping circuit ECC can detect the difference between the gate voltage VPG and the output voltage VOUT based on the differential detection circuit 221. The error clamping circuit ECC can provide current to the error amplifier output node NEAO based on the differential voltage VDIFF.

[0138] The drive current control circuit 222 can provide a supplementary drive current IDRV_supp, corresponding to the current provided to the error amplifier output node NEAO, to the error amplifier 210.

[0139] Figure 12 Based on some example embodiments Figure 11 The circuit diagram of the recovery enhancement circuit is shown below. (Refer to...) Figure 12 Continue to refer to Figures 1 to 11 The recovery enhancement circuit 220 may include an error clamping circuit ECC and a drive current control circuit 222.

[0140] The error clamping circuit (ECC) may include a differential detection circuit 221, a clamping transistor TR_CLMP, a clamping resistor R_CLMP, and a clamping capacitor C_CLMP.

[0141] The output terminal of the differential detection circuit 221 can be connected to the clamping node NCLMP. The voltage level of the clamping node NCLMP can be referred to as the supplementary current control voltage VSCC. The configuration and operation of the differential detection circuit 221 are similar to those described above. Figure 9 The configuration and operation of the differential detection circuit 121 are described, thus omitting a detailed description.

[0142] The clamping resistor R_CLMP and the clamping capacitor C_CLMP may be connected between the supply voltage VDD and the clamping node NCLMP. In some example embodiments, the clamping resistor R_CLMP and the clamping capacitor C_CLMP may be separate or discrete components connected between the supply voltage VDD and the clamping node NCLMP. However, the example embodiments of this disclosure are not limited thereto; the clamping resistor R_CLMP may be a parasitic resistance, and the clamping capacitor C_CLMP may be a parasitic capacitance.

[0143] The clamping transistor TR_CLMP can be connected between the supply voltage VDD and the error amplifier output node NEAO. The clamping transistor TR_CLMP can supply current to the error amplifier output node NEAO in response to the supplementary current control voltage VSCC. For example, the clamping transistor TR_CLMP can adjust the error amplifier output voltage VEAO by supplying current to the error amplifier output node NEAO in response to the supplementary current control voltage VSCC.

[0144] The drive current control circuit 222 can generate a supplementary drive current IDRV_supp based on the supplementary current control voltage VSCC. For example, the drive current control circuit 222 may include a first current source transistor TRCS1 and first mirror transistors TRMR1 through third mirror transistors TRMR3.

[0145] The gate terminal of the first current source transistor TRCS1 can be connected to the clamping node NCLMP. The value of the current generated by the first current source transistor TRCS1 can correspond to the value of the current generated by the clamping transistor TR_CLMP.

[0146] The driving variable current source CS_var may include a fourth mirror transistor TRMR4. The supplementary driving current IDRV_supp generated by the driving current source CS_DRV can be determined based on the current generated by the first current source transistor TRCS1. The specific configuration and operating principle of the driving current control circuit 222 are similar in some respects to those described above. Figure 9 The configuration and operation of the drive current control circuit 222 described are the same or similar, so a detailed description is omitted.

[0147] according to Figure 11 and Figure 12 In one embodiment, the recovery enhancement circuit 220 can be implemented based on components of the error clamping circuit ECC. Since components of the error clamping circuit ECC can also be used for recovery enhancement operation, the production efficiency of the voltage regulator 200 can be improved.

[0148] Figure 13 This is a block diagram of a memory system according to some example embodiments. (Refer to...) Figure 13 Continue to refer to Figures 1 to 12 The memory system MS may include a host device 1100, a memory device 1200, and a PMIC (power management integrated circuit) 1300.

[0149] The host device 1100 can control the memory device 1200 by issuing the command CMD and the address ADDR. For example, the host device 1100 can read data DATA from the memory device 1200 or store data DATA in the memory device 1200 by issuing the command CMD and the address ADDR.

[0150] In some example embodiments, host device 1100 may be implemented as one of a variety of electronic devices such as a processor, application processor (AP), system-on-a-chip (SoC), etc.

[0151] In some example embodiments, memory device 1200 may be implemented as a non-volatile memory device such as flash memory. However, the example embodiments of this disclosure are not limited thereto, and memory device 1200 may be implemented as a volatile memory device such as DRAM (Dynamic Random Access Memory) device, SRAM (Static Random Access Memory) device, etc.

[0152] The PMIC 1300 may include one or more voltage regulators REG. The PMIC 1300 can generate a host drive voltage VHD and a memory drive voltage VMD based on the one or more voltage regulators REG. The host drive voltage VHD and the memory drive voltage VMD may correspond to the voltages referred to above. Figures 1 to 12 The voltage regulator 100 or voltage regulator 200 generates an output voltage VOUT. PMIC 1300 can provide a host drive voltage VHD to host device 1100 and a memory drive voltage VMD to memory device 1200. However, the exemplary embodiments of this disclosure are not limited thereto, and PMIC 1300 can provide drive voltages to only one of host device 1100 and memory device 1200.

[0153] In some example embodiments, each of one or more voltage regulators REG may be implemented as described above. Figures 1 to 12 The voltage regulator 100 or voltage regulator 200 are mentioned above. For example, the PMIC 1300 can generate the host drive voltage VHD based on the voltage regulator 100. In this case, refer to the above. Figures 1 to 12 The described load LD may correspond to host device 1100. Alternatively, PMIC 1300 may generate memory drive voltage VMD based on voltage regulator 100. In this case, refer to the above. Figures 1 to 12 The described load LD may correspond to memory device 1200.

[0154] In some example embodiments, when based on the above reference Figures 1 to 12When the voltage regulator 100 or voltage regulator 200 generates the host drive voltage VHD and memory drive voltage VMD, even if the value of the load LD changes (e.g., rapidly), the voltage levels of the host drive voltage VHD and memory drive voltage VMD can remain relatively constant according to the operation of the host device 1100 or memory device 1200. According to some example embodiments of this disclosure, the undershoot of the host drive voltage VHD and memory drive voltage VMD can be minimized or reduced. Operational errors of the host device 1100 due to unexpected or unforeseen fluctuations in the host drive voltage VHD can be minimized or reduced, and operational errors of the memory device 1200 due to unexpected or unforeseen fluctuations in the memory drive voltage VMD can be minimized or reduced.

[0155] Figure 14 This is a block diagram of a Universal Flash Storage (UFS) system according to some example embodiments of the present disclosure. (Refer to...) Figure 14 Continue to refer to Figures 1 to 13 The UFS system 2000 can be a system based on the UFS standard provided by the Joint Electronic Equipment Committee (JEDEC). The UFS system 2000 may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300.

[0156] UFS host 2100 and UFS device 2200 can be interconnected via UFS interface 2300. UFS host 2100 can be implemented as... Figure 13 The host device 1100. The UFS device 2200 can be implemented as Figure 13 The memory device 1200. The UFS system 2000 can correspond to the above reference. Figure 13 The memory system MS is described.

[0157] UFS host 2100 may include UFS host controller 2110, application 2120, UFS driver 2130, host memory 2140, and UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, non-volatile memory 2220, storage interface (I / F) 2230, device memory 2240, UIC layer 2250, and regulator 2260.

[0158] The non-volatile memory 2220 may include a plurality of memory cells 2221. The plurality of memory cells 2221 may include V-NAND flash memory having a 2D structure or a 3D structure. However, the exemplary embodiments of this disclosure are not limited thereto, and the plurality of memory cells 2221 may include other types of non-volatile memory, such as phase-change random access memory (PRAM) and / or resistive random access memory (RRAM).

[0159] The UFS device controller 2210 and non-volatile memory 2220 can be connected to each other via storage interface 2230. Storage interface 2230 may conform to (or be based on) standard specifications such as Trigger or Open NAND Flash Interface (ONFI).

[0160] Application 2120 may refer to a program that communicates with UFS device 2200 to utilize the functionality of UFS device 2200. Application 2120 may transmit input / output requests for UFS device 2200 to UFS drive 2130. Input / output requests may refer to data read requests, data storage requests, or data discard requests, but the exemplary embodiments of this disclosure are not limited thereto.

[0161] UFS drive 2130 can manage UFS host controller 2110 via UFS-HCI (UFS-Host Controller Interface). UFS drive 2130 can translate input / output requests generated by application 2120 into UFS commands defined by the UFS standard, and can send the translated UFS commands to UFS host controller 2110. A single I / O request can be translated into multiple UFS commands. UFS commands can be commands defined by the Small Computer System Interface (SCSI) standard, but the exemplary embodiments of this disclosure are not limited thereto, and UFS commands can be special commands used with the UFS standard.

[0162] The UFS host controller 2110 can send UFS commands translated by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 of the UFS host controller 2110 can be configured as a command queue.

[0163] The UIC layer 2150 located on the UFS host 2100 side may include MIPI M-PHY 2151 and MIPI UniPro 2152. The UIC layer 2250 located on the UFS device 2200 side may include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0164] The UFS interface 2300 may include a line for transmitting a reference clock REF_CLK, a line for transmitting a hardware reset signal RESET_n for the UFS device 2200, a pair of lines for transmitting differential input signal pairs DIN_T and DIN_C, and a pair of lines for transmitting a pair of differential output signals DOUT_T and DOUT_C.

[0165] The frequency of the reference clock REF_CLK provided from the UFS host 2100 to the UFS device 2200 can be one of the following four values: 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz. However, the exemplary embodiments of this disclosure are not limited thereto.

[0166] Even when performing data transmission or reception operations with the UFS device 2200, the UFS host 2100 can change the frequency value of the reference clock REF_CLK. The UFS device 2200 can generate clocks of various frequencies based on the reference clock REF_CLK provided by the UFS host 2100 using electronic circuitry such as a PLL (Phase-Locked Loop). Furthermore, the UFS host 2100 can also set the data rate between the UFS host 2100 and the UFS device 2200 based on the frequency value of the reference clock REF_CLK. The data rate value can be determined according to the frequency value of the reference clock REF_CLK.

[0167] The UFS interface 2300 can support multiple channels, and each channel can be implemented as a differential line pair. For example, the UFS interface 2300 may include one or more receive channels and one or more transmit channels. Figure 14 In this configuration, a pair of lines transmitting differential input signals DIN_T and DIN_C corresponds to the receiving channel of the UFS device 2200; and a pair of lines transmitting differential output signals DOUT_T and DOUT_C ​​corresponds to the transmitting channel of the UFS device 2200. For ease of explanation, in... Figure 14 The illustration shows a transmit channel and a receive channel, but the exemplary embodiments of this disclosure are not limited to any particular number of transmit channels and receive channels.

[0168] The receive channel and the transmit channel can transmit data in a serial communication manner. Since the receive channel and the transmit channel are independent of each other, the UFS host 2100 and the UFS device 2200 can communicate with each other in full-duplex mode. For example, the UFS device 2200 can receive data from the UFS host 2100 through the receive channel while simultaneously transmitting data to the UFS host 2100 through the transmit channel.

[0169] Control data, such as commands provided from the UFS host 2100 to the UFS device 2200, can be transmitted through the same channel as user data sent via the UFS interface 2300 when the UFS host 2100 performs input / output operations for the UFS device 2200. Therefore, data transmission between the UFS host 2100 and the UFS device 2200 does not require additional channels besides a pair of receive channels and a pair of transmit channels.

[0170] UFS device controller 2210 controls the overall operation of UFS device 2200. UFS device controller 2210 can manage non-volatile memory 2220 based on LU (Logic Unit).

[0171] In some example embodiments, the number of LUs managed by the UFS device controller 2210 may be 8. However, the example embodiments of this disclosure are not limited thereto.

[0172] UFS device controller 2210 may include a flash translation layer (FTL). UFS device controller 2210 may translate logical addresses (e.g., logical block addresses (LBAs)) sent from UFS host 2100 into physical addresses (e.g., physical block addresses (PBAs)) by utilizing address mapping information from the FTL.

[0173] In some example embodiments, the size (or capacity) of the logical block used to store user data in the UFS system 2000 can be within a specific, desired, or given range. For example, the minimum size (or capacity) of the logical block can be 4KB.

[0174] When the command issued by the UFS host 2100 is provided to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 can perform the corresponding operation and then send the completion response to the UFS host 2100.

[0175] For example, when UFS host 2100 stores user data in UFS device 2200, UFS host 2100 can send a data storage command to UFS device 2200. UFS device 2200 can provide a response instructing UFS device 2200 to be ready to receive user data (e.g., ready to transmit response) to UFS host 2100. UFS host 2100 can then transmit the user data to UFS device 2200. UFS device controller 2210 can temporarily store the user data in device memory 2240; and can temporarily store the user data in device memory 2240 within non-volatile memory 2220 based on FTL address mapping information.

[0176] In another example, when UFS host 2100 reads user data from UFS device 2200, UFS host 2100 may send a data read command to UFS device 2200. UFS device controller 2210 may read user data from non-volatile memory 2220 in response to the data read command, and may temporarily store the read user data in device memory 2240, and may then send the user data in device memory 2240 to UFS host 2100.

[0177] UFS host 2100 may store commands to be sent to UFS device 2200 in a command queue (e.g., UFS host register 2111) and may sequentially serve the commands to UFS device 2200. Even if a previously sent command is still being processed in UFS device 2200 (e.g., before receiving a completion response for the previously sent command from UFS device 2200), UFS host 2100 may also send another command queued in the command queue to UFS device 2200. In this case, UFS device 2200 may be configured to receive another command while processing the previously sent command.

[0178] In some example embodiments, the maximum number of commands that can be stored in the command queue (e.g., queue depth) may be 32. However, the example embodiments of this disclosure are not limited thereto.

[0179] In some example embodiments, the command queue may be implemented as a circular queue type that stores commands based on head and tail pointers. However, the example embodiments of this disclosure are not limited thereto.

[0180] UFS device 2200 can receive various types of power voltages such as “VCC”, “VCCQ”, “VCCQ2”, etc. “VCC” can be the main power voltage of UFS device 2200 and can have a level of 2.4 V (or about 2.4 V) to 3.6 V (or about 3.6 V). “VCCQ” can be a low operating voltage for UFS device 2200 (e.g., the voltage to be supplied to UFS device controller 2210) and can have a level of 1.14 V (or about 1.14 V) to 1.26 V (or about 1.26 V). “VCCQ2” can be an operating voltage between “VCC” and “VCCQ” (e.g., the voltage to be supplied to an input / output interface such as MIPI M-PHY 2251) and can have a level of 1.7 V (or about 1.7 V) to 1.95 V (or about 1.95 V). These electrical voltages can be supplied to the various components of the UFS device 2200 via regulator 2260.

[0181] In some example embodiments, reference can be made to the above. Figures 1 to 12The voltage regulator 100 or voltage regulator 200 described provides one or more of various power supply voltages such as "VCC", "VCCQ", "VCCQ2", etc. For example, "VCC" can be generated from the voltage regulator 100. Even if the UFS device 2200 changes from a state requiring high load current ILD (such as a read operation or write operation) to a state requiring low load current ILD (such as an idle state or sleep mode) and then changes back to a state requiring high load current ILD, the undershoot of the voltage level of "VCC" can be minimized or reduced. In other words, when "VCC" is provided from the voltage regulator 100, "VCC" can maintain a constant voltage level even if the load current ILD required by the UFS device 2200 changes suddenly. The voltages supplied to the components of the UFS device 2200 can remain relatively consistent, thus improving the operational stability of the UFS device 2200.

[0182] According to some example embodiments, a memory system includes: a power management integrated circuit (PMIC) including a first voltage regulator configured to generate a host drive voltage and a second voltage regulator configured to generate a memory drive voltage; a host device connected to the PMIC and configured to receive the host drive voltage; and a memory device connected to the PMIC and configured to receive the memory drive voltage. Each of the first and second voltage regulators includes: an error amplifier including a first input terminal configured to receive a reference voltage, a second input terminal connected to a feedback node, and a first output terminal configured to output a gate voltage; a transistor connected between the input voltage and the output node, wherein the transistor is configured to operate in response to the gate voltage; a first resistor connected between the output node and the feedback node; a second resistor connected between the feedback node and ground; and a recovery enhancement circuit configured to provide one or more drive currents to the error amplifier and configured to control the magnitude of the one or more drive currents based on the output voltage of the output node, wherein the output voltage corresponds to one of the host drive voltage and the memory drive voltage. According to some example embodiments, the error amplifier includes: a differential input circuit configured to receive a reference voltage and a feedback voltage corresponding to a feedback node; and an amplification circuit configured to generate a through-gate voltage based on control of the differential input circuit. At least one of the differential input circuit and the amplification circuit includes a first drive current source configured to generate a first drive current, and one or more drive currents including the first drive current. According to some example embodiments, the first drive current source is a variable current source configured to operate in response to control of a recovery enhancement circuit. According to some example embodiments, the recovery enhancement circuit includes: a differential detection circuit configured to generate a supplementary current control voltage based on a differential voltage between the output voltage and the through-gate voltage; and a drive current control circuit configured to control the value of the first drive current based on the supplementary current control voltage. According to some example embodiments, the drive current control circuit is configured to generate a supplementary drive current based on the supplementary current control voltage and to provide the supplementary drive current to the first drive current source.

[0183] As described herein, any device, system, module, part, unit, controller, circuit and / or some part thereof, and / or any part thereof according to any example embodiment (including (but not limited to) error amplifier 110, recovery enhancement circuit 120, differential detection circuit 121, drive current control circuit 122, differential input circuit 111, amplifier circuit 112, differential input circuit 111_1, amplifier circuit 112_1, differential input circuit 111_2, amplifier circuit 112_2, error clamping circuit ECC, drive current control circuit 222) Differential detection circuit 221, PMIC (Power Management Integrated Circuit) 1300, UFS host 2100, UFS device 2200, UFS interface 2300, host device 1100, UFS host controller 2110, application 2120, UFS driver 2130, host memory 2140, UFS interconnect (UIC) layer 2150, UFS device controller 2210, non-volatile memory 2220, storage interface 2230, device memory 2240, UIC layer 2250, regulator 2260, MIPI The M-PHY 2151, MIPI UniPro 2152, MIPI M-PHY 2251, MIPI UniPro 2252, UFS host register 2111, and any part thereof may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry; hardware / software combinations such as processors executing software; or combinations thereof. For example, the processing circuitry may more specifically include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transient computer-readable storage device (e.g., memory) such as a solid-state drive (SSD) for storing a program of instructions, and a processor (e.g., CPU) configured to execute instructions to implement functions and / or methods performed by any device, system, module, section, unit, controller, circuit, and / or some portions thereof according to any example embodiment.

[0184] Any of the elements and / or functional blocks disclosed above may include or be implemented in processing circuitry, such as hardware including logic circuitry; hardware / software combinations such as processors executing software; or combinations thereof. For example, processing circuitry may more specifically include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processing circuitry may include electronic components such as at least one of transistors, resistors, capacitors, etc. Processing circuitry may include electronic components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0185] The example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

[0186] While several embodiments have been provided in this disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of this disclosure. These examples are to be considered illustrative rather than restrictive and are not intended to be limited to the details given herein. For example, various elements or components may be combined or integrated into another system, or certain features may be omitted or not implemented.

Claims

1. A voltage regulator, comprising: An error amplifier includes a first input terminal configured to receive a reference voltage, a second input terminal connected to a feedback node, and a first output terminal configured to output a voltage through a gate voltage. A transistor is connected between the input voltage and the output node, wherein the transistor is configured to operate in response to the gate voltage; A first resistor is connected between the output node and the feedback node; A second resistor is connected between the feedback node and ground voltage; and A recovery enhancement circuit is configured to control the magnitude of one or more drive currents for the error amplifier based on the output voltage of the output node.

2. The voltage regulator according to claim 1, wherein, The error amplifier includes: A differential input circuit, configured to receive the reference voltage and a feedback voltage corresponding to the feedback node; and An amplifier circuit is configured to generate the gate voltage based on control from the differential input circuit. At least one of the differential input circuit and the amplifier circuit includes a first drive current source, which is configured to generate a first drive current, and the one or more drive currents include the first drive current.

3. The voltage regulator according to claim 2, wherein: The first drive current source is a variable current source configured to operate in response to control from the recovery enhancement circuit.

4. The voltage regulator according to claim 3, wherein, The recovery enhancement circuit includes: A differential detection circuit is configured to generate a supplementary current control voltage based on the differential voltage between the output voltage and the through-gate voltage; and A drive current control circuit is configured to control the value of the first drive current based on the supplementary current control voltage.

5. The voltage regulator according to claim 4, wherein, The drive current control circuit is further configured to: A supplementary drive current is generated based on the supplementary current control voltage; and The supplementary drive current is provided to the first drive current source.

6. The voltage regulator according to claim 5, wherein the first drive current source comprises: A constant current source is driven, which is configured to generate a constant driving current. as well as A variable current source is driven, which is connected in parallel with the constant current source and configured to mirror the supplementary drive current.

7. The voltage regulator according to claim 4, wherein, The differential detection circuit includes a comparator amplifier. The comparator amplifier includes: A third input terminal is configured to receive the output voltage; A fourth input terminal is configured to receive a voltage that is offset by a voltage higher than the through-gate voltage; and The second output terminal is configured to output the supplementary current control voltage.

8. The voltage regulator according to claim 2, in, The differential input circuit includes: A first differential input transistor is connected between a first node and a second node, wherein the first differential input transistor includes a first gate terminal configured to receive the reference voltage; A second differential input transistor is connected between the first node and the third node, wherein the second differential input transistor includes a second gate terminal configured to receive the feedback voltage; and The first drive current source is configured to provide the first drive current to the first node.

9. The voltage regulator according to claim 8, wherein, The amplifier circuit includes: A first amplifying transistor is connected between the second node and the ground node, wherein the first amplifying transistor includes a third gate terminal connected to the second node; and A second amplifying transistor is connected between the third node and the ground node, wherein the second amplifying transistor includes a fourth gate terminal connected to the second node. The third node is connected to the output node.

10. The voltage regulator according to claim 8, wherein, The amplifier circuit includes: A third amplifying transistor is connected between the second node and the ground node, wherein the third amplifying transistor includes a fifth gate terminal connected to the fourth node; A fourth amplifying transistor is connected between the third node and the ground node, wherein the fourth amplifying transistor includes a sixth gate terminal connected to the fourth node; The fifth amplifying transistor is connected between the second node and the fourth node; The sixth amplifying transistor is connected between the third and fifth nodes; The seventh amplifying transistor is connected between the fourth and sixth nodes; The eighth amplifying transistor is connected between the fifth and seventh nodes; A second drive current source, configured to provide a second drive current to the sixth node, wherein the one or more drive currents include the second drive current; and A third drive current source is configured to provide a third drive current to the seventh node, wherein the one or more drive currents include the third drive current. The gate terminals of the fifth and sixth amplifying transistors are connected to each other, the gate terminals of the seventh and eighth amplifying transistors are connected to each other, and the fifth node is connected to the output node.

11. A method of operating a voltage regulator, the method comprising: The drive current of the error amplifier is set to a first current, and the voltage regulator includes the error amplifier, which is configured to generate a gate voltage. In response to the voltage difference between the output voltage of the voltage regulator and the voltage through the gate being greater than a first supplementary threshold voltage, the drive current is increased to a second current higher than the first current; as well as In response to the differential voltage being less than the second supplementary threshold voltage, the drive current is reduced to the first current.

12. The method according to claim 11, wherein: The differential voltage corresponds to the value obtained by subtracting the voltage level through the gate voltage from the voltage level of the output voltage.

13. The method according to claim 11, wherein, The voltage regulator also includes a pass transistor connected between an input node configured to receive an input voltage and an output node configured to provide the output voltage. The transistor is configured to operate in response to the gate voltage, and The error amplifier is configured to generate the gate voltage based on a feedback voltage generated according to the output voltage.

14. The method according to claim 11, wherein, The step of increasing the drive current is performed in response to a decrease in the load connected to the voltage regulator.

15. The method according to claim 11, wherein, The step of reducing the drive current is performed in response to an increase in the load connected to the voltage regulator.

16. A voltage regulator, comprising: An error amplifier configured to generate a voltage through the gate; It is connected to the output node via a transistor and is configured to operate in response to the gate voltage; as well as A recovery enhancement circuit is configured to increase one or more drive currents of the error amplifier in response to an overshoot in the voltage level of the output node.

17. The voltage regulator according to claim 16, wherein, The recovery enhancement circuit includes: A differential detection circuit is configured to determine the occurrence of the overshoot based on the difference between the output voltage of the output node and the through-gate voltage; and A drive current control circuit is configured to control the one or more drive currents based on the occurrence of the overshoot determined by the differential detection circuit.

18. The voltage regulator according to claim 17, wherein, The differential detection circuit includes a comparator amplifier. The comparator amplifier includes, A first input terminal is configured to receive the output voltage; A second input terminal is configured to receive a voltage that is offset by a voltage higher than the through-gate voltage; and A first output terminal is configured to output a supplementary current control voltage, which is configured to control the drive current control circuit.

19. The voltage regulator according to claim 16, further comprising: A first resistor connected between the output node and the feedback node, and a second resistor connected between the feedback node and ground voltage, wherein: The error amplifier includes a third input terminal configured to receive a reference voltage, a fourth input terminal connected to the feedback node, and a second output terminal configured to output the voltage through the gate; and The transistor is connected between the input voltage and the output node.

20. The voltage regulator according to claim 19, wherein, The error amplifier includes: A differential input circuit, configured to receive the reference voltage and a feedback voltage corresponding to the feedback node; and An amplifier circuit is configured to generate the gate voltage in response to control from the differential input circuit. At least one of the differential input circuit and the amplifier circuit includes a drive current source configured to generate one of the one or more drive currents in response to control from the recovery enhancement circuit.

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