Low-dropout linear voltage regulator with pole-zero compensation and method of operation thereof

Abstract

A low dropout linear regulator including a compensation capacitor, a first compensation resistor, a second compensation resistor, and a switching element is provided. The switching element is used to bypass / short the first compensation resistor. When the switching element is not turned on, the compensation capacitor, the first compensation resistor, and the second compensation resistor are used to determine a first zero. When the switching element is turned on, the compensation capacitor and the second compensation resistor are used to determine a second zero. The frequency of the second zero is higher than the frequency of the first zero.

Description

Technical Field

[0001] This invention relates to a low-dropout linear regulator, specifically, to a low-dropout linear regulator and its operating method that enables the zero point of the low-dropout linear regulator to shift to a higher frequency when the tap current exceeds a preset value, so that the zero point can compensate for the output poles and achieve circuit stability of the low-dropout linear regulator. Background Technology

[0002] Please refer to Figure 1 This is a schematic diagram of the transfer function of a known low-dropout linear regulator. Traditional low-dropout linear regulators typically have two poles, P1 and P2, and one zero, Z1. The zero, Z1, is not very responsive to the pump current of the low-dropout linear regulator. This can lead to multiple pole transitions at high frequencies, resulting in instability of the low-dropout linear regulator.

[0003] Furthermore, when the pump current is too large, the output pole P2 will shift to a higher frequency, causing the zero point Z1 to fail to compensate for the output pole P2, which may lead to insufficient stability, especially when the gain bandwidth (BGW) is large.

[0004] The information disclosed in the background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the relevant information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides a low-dropout linear regulator and its operation method, which moves the zero point to a higher frequency when the tap current of the low-dropout linear regulator exceeds a preset current value in a preset tap current range, so that the zero point can compensate for the output pole and achieve circuit stability of the low-dropout linear regulator.

[0006] The present invention also provides a low-dropout linear regulator and its operation method that changes the zero point position by detecting the pump current to turn on the control switch.

[0007] This invention provides a low-dropout linear regulator comprising an error amplifier, a first transistor, a compensation capacitor, and compensation resistors. The error amplifier has an inverting input terminal, a non-inverting input terminal, and an output terminal. The first transistor is coupled between an input voltage source and a first node, and the gate of the first transistor is coupled to the output terminal of the error amplifier. Two compensation resistors and the compensation capacitor are connected in series between the output terminal of the error amplifier and the first node, wherein the compensation resistors are used to switch between at least two resistance values.

[0008] This invention also provides a low-dropout linear regulator comprising a compensation capacitor, a first compensation resistor, a second compensation resistor, and a switching element. The second compensation resistor is connected in series with the first compensation resistor and the compensation capacitor. The switching element is used to bypass the first compensation resistor. The compensation capacitor, the first compensation resistor, and the second compensation resistor determine a first zero point, and the compensation capacitor and the second compensation resistor determine a second zero point. When the pump current of the low-dropout linear regulator is greater than a preset current value, the switching element bypasses the first compensation resistor.

[0009] The present invention also provides a method for operating a low-dropout linear regulator. The low-dropout linear regulator includes a zero-point control circuit, a current detection circuit, and a buffer connected between the zero-point control circuit and the current detection circuit. The operating method includes: detecting the pumped current of the low-dropout linear regulator using the current detection circuit; when the pumped current is greater than a preset current value, outputting a control signal through the buffer; and after receiving the control signal, the zero-point control circuit shifts the frequency position of the zero point towards a higher frequency.

[0010] To make the above and other objects, features and advantages of the present invention more apparent, they will be described in detail below with reference to the accompanying drawings. Furthermore, in this invention, the same components are denoted by the same symbols, which are hereby explained first. Attached Figure Description

[0011] Figure 1 A schematic diagram of the transfer function of a known low-dropout linear regulator; Figure 2 This is a circuit diagram of a low-dropout linear regulator according to an embodiment of the present invention.

[0012] Figure 3 This is a schematic diagram of the transfer function of the low-dropout linear regulator after the switching element is turned on, according to an embodiment of the present invention. Figure 4 The circuit diagram for generating the current source of the low-dropout linear regulator is shown in an embodiment of the present invention. Figure 5 A flowchart illustrating the operation method of a low-dropout linear regulator according to an embodiment of the present invention; and Figure 6 This is a circuit diagram of a low-dropout linear regulator according to another embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures 200 Low Dropout Linear Regulator 21 Error Amplifier 23 Buffer 25 Zero-point control circuit 27 Current Detection Circuit 29 voltage divider circuit V DD Input voltage V out Output voltage Detailed Implementation One object of the present invention is to provide a low-dropout linear regulator and its operation method that can shift the frequency position of the zero point towards a higher frequency direction under heavy load to compensate for the output pole. The present invention utilizes a current detection circuit to detect the pumped current of the low-dropout linear regulator, and when the pumped current is greater than a preset current value, uses a digital signal output by a buffer to control the zero-point control circuit to change the frequency position of the zero point.

[0014] In one embodiment, the low-dropout linear regulator of this invention has a preset pumped-out current range, which is determined based on the downstream connected load. When the current pumped-out current is greater than a preset current value within the preset pumped-out current range, the frequency position of the zero point is moved toward the frequency position of the output pole to compensate for the output pole and stabilize the low-dropout linear regulator circuit.

[0015] Please refer to Figure 2 The diagram shown is a circuit diagram of a low-dropout linear regulator (LDO) 200 according to an embodiment of the present invention. The low-dropout linear regulator 200 includes an error amplifier 21, a buffer 23, a zero-point control circuit 25, a current detection circuit 27, a voltage divider circuit 29, an output capacitor Cload, and a pass transistor (or first transistor) M1.

[0016] In one embodiment, buffer 23 may be composed of two inverters connected in series, but the invention is not limited thereto. Buffer 23 may be other circuits that output digital signals ("1" or "0") based on input voltage or current values ​​to control the switching elements. Figure 2 In this circuit, buffer 23 is connected between zero-point control circuit 25 and current detection circuit 27 to receive input voltage Vth.

[0017] Error amplifier 21 has an inverting input (displayed as "-"), a non-inverting input (displayed as "+"), and an output. The inverting input is coupled to a reference voltage Vref.

[0018] The pass transistor M1 is coupled between the input voltage source VDD and the first node N1. The gate of the pass transistor M1 is coupled to the output of the error amplifier 21.

[0019] The output capacitor Cload is connected between the first node N1 and ground. The output capacitor Cload and the equivalent output resistance Rout of the low-dropout linear regulator 200 determine the output pole P2, for example, referring to... Figure 3 For example, the frequency of the output pole P2 is fp2≈1 / (2π×Rout×Cload). The method for calculating the equivalent output resistance Rout is known and is not the main purpose of this invention, so it will not be described in detail here.

[0020] The zero-point control circuit 25 includes a compensation capacitor Cc, a first compensation resistor Rc1, and a second compensation resistor Rc2 connected in series between the output of the error amplifier 21 and the first node N1. The resistance values ​​of the first compensation resistor Rc1 and the second compensation resistor Rc2 can be determined, for example, using the formula R=(Cload+Cc) / (gm1×Cc), where gm1 is the transconductance of the pass transistor M1.

[0021] In this invention, to shift the zero point Z1 towards the high-frequency direction, the second compensation resistor Rc2 is configured to be much smaller than the first compensation resistor Rc1, for example, less than 17 to 23 times, to increase the adjustment range of the zero point Z1. Please refer to... Figure 3 This is a schematic diagram of the transfer function of the low-dropout linear regulator 200 after the switching switch S1 is turned on, according to an embodiment of the present invention. In this invention, the compensation capacitor Cc, the first compensation resistor Rc1, and the second compensation resistor Rc2 determine the first zero point, for example, referring to... Figure 3 Z1 (e.g., the first frequency f of Z1) Z1 ≈1 / 2π×(Rc1+Rc2)×Cc); the compensation capacitor Cc and the second compensation resistor Rc2 determine the second zero point, for example, referring to Figure 3 Z2 (e.g., the second frequency f of Z2) Z2 ≈1 / 2π×Rc2×Cc). As mentioned above, the second compensation resistor Rc2 is preferably much smaller than the first compensation resistor Rc1, so Rc1+Rc2 is very close to Rc1. Therefore, compared to the frequency position f of the zero point formed only by the first compensation resistor Rc1 and the compensation capacitor Cc, the frequency position f is much smaller. Z ≈1 / 2π×Rc1×Cc, adding the second compensation resistor Rc2 will not significantly change f. Z That is, f Z ≈f Z1 .from Figure 3 It can be seen that the second frequency position of the second zero point Z2 is higher than the first frequency position of the first zero point Z1.

[0022] The zero-point control circuit 25 also includes a switching element S1 connected in parallel with a first compensation resistor Rc1, but is not limited thereto; the specific configuration depends on the form of the switching element S1. In this invention, the switching element S1 is used to bypass the first compensation resistor Rc1 according to the control signal Sc, i.e., the first compensation resistor Rc1 is short-circuited by the switching element S1. In one embodiment, the buffer 23 is used to output the control signal Sc, such as the digital value "1", but is not limited thereto. In this invention, the resistance value of the second compensation resistor Rc2 is selected such that when the control signal Sc controls the switching element S1 to conduct, the first compensation resistor Rc1 is bypassed, and the second frequency position of the second zero point Z2 is equal to the frequency position of the output pole P2, thereby compensating for the output pole P2 to achieve circuit stability of the low-dropout linear regulator. Preferably, all corners of the low-dropout linear regulator 200 allow the LDO phase to be greater than 60 degrees.

[0023] The current detection circuit 27 includes a second transistor M2 and a current source Ith. The second transistor M2 is coupled between the input voltage source VDD and the first node N1. The gate of the second transistor M2 is coupled to the gate of the pass transistor M1. In one embodiment, the size of the second transistor M2 is more than 100 times smaller than the size of the pass transistor M1. For example, when the size of M1 is 1, the size of M2 is greater than or equal to 100.

[0024] The current source Ith is connected between the drain of the second transistor M2 and ground. The buffer 23 is connected between the switching element S1 and the drain of the second transistor M2. Figure 4 The circuit diagram shown illustrates the generation of the current source Ith for a low-dropout linear regulator 200 according to an embodiment of the present invention. It includes a current mirror that generates a voltage Vbias using a reference current Iref, and the current source Ith is formed by configuring the ratio of transistors Mref and Mth. It must be noted that... Figure 4 This invention is only used to illustrate one embodiment of forming a current source Ith. The current source Ith can be generated by other known circuits and is not limited to the one proposed in this invention.

[0025] In this invention, when a load is connected downstream of the low-dropout linear regulator 200, the adjusted DC output voltage Vout is provided to the load and can generate a pumped current I. RL Preferably, the low-dropout linear regulator 200 has a preset pump-out current range, for example, 0 to 10 mA, but not limited thereto. When the current pump-out current I of the low-dropout linear regulator 200... RL When the current value exceeds the preset current value in the preset current range, for example, 5 to 7 mA, the buffer 23 outputs a control signal Sc to short-circuit the first compensation resistor Rc1 to move the zero point Z1 toward the high frequency direction as compensation.

[0026] Assuming the current pumping current I RL When the current is less than the preset current value, the positions of zero point Z1 and output pole P2 are as follows: Figure 1 As shown. When the current pump current I RL As the voltage increases gradually, the gate voltage Vgate of the primary transistor M1 and the secondary transistor M2 gradually decreases, causing the current I of the secondary transistor M2 to decrease. M2 Increase. When current I M2 When the current is greater than Ith, the input voltage Vth of buffer 23 increases with the current pumped current I. RL The voltage increases with the increase of the buffer voltage Vth. When the voltage Vth exceeds the critical voltage of buffer 23 (i.e., the current pump-out current I), the voltage increases. RL When the current exceeds the preset value, buffer 23 outputs a control signal Sc to turn on the switching element S1 and bypass the first compensation resistor Rc1. At this time, the second zero point Z2 is determined by the compensation capacitor Cc and the second compensation resistor Rc2, referring to... Figure 3 .

[0027] It must be stated that, Figure 3 The two zero points Z1 and Z2 shown represent the zero points of the low-dropout linear regulator 200 before and after the switching element S1 is turned on, respectively. They do not represent two simultaneous zero points of the low-dropout linear regulator 200. That is, after the switching element S1 is turned on, the zero point shifts from Z1 to Z2.

[0028] Voltage divider circuit 29 includes a first voltage divider resistor R1 and a second voltage divider resistor R2. The first voltage divider resistor R1 is connected between the first node N1 and the second node N2. The second voltage divider resistor R2 is connected between the second node N2 and ground. The second node N2 is coupled to the non-inverting input terminal of the error amplifier 21. The function of voltage divider circuit 29 in the low dropout linear regulator is known and is not the main objective of this invention, so it will not be described in detail here.

[0029] Please refer to Figure 5 The diagram shown is a flowchart of the operation method of the low-dropout linear regulator 200 according to an embodiment of the present invention, which includes the following steps: Step S51: Detect the pump current I of the low-dropout linear regulator 200 using the current detection circuit 27. RL As mentioned above, when the pump current I... RL When increased, the input voltage Vth of buffer 23 is at I M2 >Ith increases.

[0030] Step S53: When the pumping current I RL When the current exceeds the preset value (i.e., the input voltage Vth is greater than the critical voltage of the buffer 23), the buffer 23 can output a control signal Sc, such as a digital value "1" or "0", depending on the type of buffer 23 and switching element S1.

[0031] Step S55: After receiving the control signal Sc, the zero-point control circuit 25 moves the frequency position of the zero point towards the higher frequency direction, referring to... Figure 3 As mentioned earlier, the control signal Sc output by buffer 23 is used to turn on switching element S1 to bypass the first compensation resistor Rc1, causing the zero point Z1 to shift towards the high-frequency direction. Preferably, by appropriately configuring the second compensation resistor Rc2, the frequency position of the zero point Z1 can be equal to the frequency position of the output pole P2, for example... Figure 3 This shows that Z2 and P2 are located in roughly the same position.

[0032] In this invention, the path transistor M1 and the second transistor M2 are illustrated using a PMOS transistor as an example.

[0033] It must be noted that the numerical values ​​in this invention description, such as preset load current range, preset current value and transistor size ratio, are for illustrative purposes only and are not intended to limit the invention.

[0034] It must be noted that although the above embodiment uses the zero-point control circuit 25 containing two compensation resistors Rc1 and Rc2 as an example, the present invention is not limited thereto. In other embodiments, the zero-point control circuit 25 may contain two or more compensation resistors controlled by different switching elements, for example, using multiple buffers with different threshold voltages to control the multiple switching elements, the purpose of which is to move the zero point toward the high-frequency direction. In yet another embodiment, the compensation resistors Rc1 and Rc2 can be replaced by variable resistors, when the pump current I... RL When the resistance is increased, the variable resistance value decreases, the purpose of which is to shift the zero point toward the high-frequency direction. The variable resistance value has at least two selectable resistance values, for example, one is Rc1+Rc2 and the other is Rc2, but the invention is not limited thereto.

[0035] In another embodiment, Rc1 is a variable resistor with multiple variable resistance values ​​or a stepless variable resistance value, the switching element S1 is a multi-segment switch or a stepless switch, and the buffer 23 can provide multiple digital signals or a stepless digital signal (i.e., Sc) to change the equivalent resistance value of the zero-point control circuit 25, for example, referring to... Figure 6 Among them, the switching element S 11 S 12 and S 13 The conduction is determined by the control signal Sc from the buffer 23. This is achieved by switching element S... 11 S 12 and S 13Different combinations can change the equivalent resistance to Ra, Rb, Rc, Ra+Rb, Rb+Rc, Ra+Rc, and Ra+Rb+Rc, thereby relatively changing the position of the zero point Z1 and shifting it towards higher frequencies. For example, refer to... Figure 3 The control signal Sc can have multiple bits to control the switching element S. 11 S 12 and S 13 .

[0036] In summary, the zero point of known low-dropout linear regulators is unlikely to change with the pump current, which could lead to multiple pole transitions in the high-frequency region and cause instability in the low-dropout linear regulator circuit. Therefore, this invention provides another low-dropout linear regulator (see, for example, reference...). Figure 2 ) and its operating methods (e.g., refer to Figure 5 When the pumped current exceeds the preset current value within the preset pumped current range, the zero point is moved towards the high frequency direction so that the zero point can compensate for the output pole and stabilize the low dropout linear regulator.

[0037] While the present invention has been disclosed through the above examples, it is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make various modifications and alterations without departing from the spirit and scope of the description. Therefore, the scope of protection of this invention shall be determined by the appended claims.

Claims

1. A low-dropout linear regulator, the low-dropout linear regulator comprising: An error amplifier having an inverting input, a non-inverting input, and an output; A first transistor is coupled between an input voltage source and a first node, and the gate of the first transistor is coupled to the output of the error amplifier; Compensation capacitor; as well as A compensation resistor, wherein the compensation resistor and the compensation capacitor are connected in series between the output terminal of the error amplifier and the first node, wherein the compensation resistor is used to switch to at least two resistance values.

2. The low-dropout linear regulator according to claim 1, wherein, The compensation resistor comprises a first compensation resistor and a second compensation resistor connected in series. The second compensation resistor is smaller than the first compensation resistor, and The low-dropout linear regulator further includes a switching element for bypassing the first compensation resistor according to a control signal.

3. The low-dropout linear regulator according to claim 2, wherein, The compensation capacitor, the first compensation resistor, and the second compensation resistor determine the first zero point. The compensation capacitor and the second compensation resistor determine the second zero point, and The second frequency of the second zero point is higher than the first frequency of the first zero point.

4. The low-dropout linear regulator according to claim 2 further comprises a second transistor coupled between the input voltage source and the first node. in, The gate of the second transistor is coupled to the gate of the first transistor, and The size of the second transistor is more than 100 times smaller than the size of the first transistor.

5. The low-dropout linear regulator according to claim 4, further comprising: A current source, coupled between the drain of the second transistor and ground; and A buffer is coupled between the drain of the second transistor and the switching element.

6. The low-dropout linear regulator according to claim 5, further comprising: An output capacitor is coupled between the first node and the ground.

7. The low-dropout linear regulator according to claim 6, wherein, The compensation capacitor and the second compensation resistor determine the second zero point. The output capacitor and the equivalent output resistance of the low-dropout linear regulator determine the output poles, and The second frequency of the second zero is equal to the frequency of the output pole.

8. The low-dropout linear regulator according to claim 7, wherein, The low-dropout linear regulator has a preset pump-out current range, and When the pump current of the low-dropout linear regulator is greater than the preset current value in the preset pump current range, the buffer outputs the control signal.

9. The low-dropout linear regulator according to claim 1, further comprising: The first voltage divider resistor is connected between the first node and the second node; and The second voltage divider resistor is connected between the second node and ground.

10. The low-dropout linear regulator according to claim 9, wherein, The second node is coupled to the non-inverting input of the error amplifier, and The inverting input of the error amplifier is coupled to a reference voltage.

11. A low-dropout linear regulator, the low-dropout linear regulator comprising: Compensation capacitor; First compensation resistor; A second compensation resistor, wherein the second compensation resistor is connected in series with the first compensation resistor and the compensation capacitor; and A switching element, which is used to bypass the first compensation resistor, The compensation capacitor, the first compensation resistor, and the second compensation resistor determine the first zero point. The compensation capacitor and the second compensation resistor determine the second zero point, and When the pump current of the low-dropout linear regulator is greater than the preset current value, the switching element bypasses the first compensation resistor.

12. The low-dropout linear regulator according to claim 11, wherein, The second compensation resistor is smaller than the first compensation resistor.

13. The low-dropout linear regulator according to claim 11, further comprising: Error amplifier, where, The first compensation resistor, the second compensation resistor, and the compensation capacitor are connected between the output terminal of the error amplifier and the first node; and An output capacitor is coupled between the first node and ground. The output poles are determined by the output capacitor and the equivalent output resistance of the low-dropout linear regulator.

14. The low-dropout linear regulator according to claim 13, wherein, The resistance value of the second compensation resistor is selected such that when the first compensation resistor is bypassed, the second frequency of the second zero point is equal to the frequency of the output pole.

15. The low-dropout linear regulator according to claim 11, further comprising: transistor; A current source, which is connected to the drain of the transistor; and A buffer is connected between the switching element and the drain of the transistor.

16. A method for operating a low-dropout linear regulator, the low-dropout linear regulator comprising a zero-point control circuit, a current detection circuit, and a buffer connected between the zero-point control circuit and the current detection circuit, the method comprising: The current detection circuit detects the pump current of the low-dropout linear regulator. When the pumped current exceeds a preset current value, the buffer outputs a control signal; and After receiving the control signal, the zero-point control circuit shifts the frequency of the zero point toward a higher frequency.

17. The operating method according to claim 16, wherein, The zero-point control circuit includes a compensation capacitor, a first compensation resistor, and a second compensation resistor connected in series. The compensation capacitor, the first compensation resistor, and the second compensation resistor determine the first zero point. The compensation capacitor and the second compensation resistor determine the second zero point, and The second frequency of the second zero point is higher than the first frequency of the first zero point.

18. The operating method according to claim 16, wherein, The low-dropout linear regulator has a preset pump-out current range, and The preset current value is within the preset pump-out current range.

19. The operating method according to claim 16, wherein, The current detection circuit includes: transistor; and A current source, which is connected to the drain of the transistor. The buffer is connected to the drain of the transistor.

20. The operating method according to claim 16, wherein, The buffer consists of two inverters connected in series.

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