Direct current elimination circuit for capacitive sensor, control chip and electronic device

Abstract

The present application relates to a kind of direct current elimination circuit for capacitive sensor, a control chip of capacitive sensor and a kind of electronic equipment.The direct current elimination circuit includes multiple current mirror branches, each current mirror branch includes first PMOS tube, second PMOS tube, first NMOS tube and second NMOS tube connected in turn, wherein the connection point of second PMOS tube and second NMOS tube is used to couple a parasitic capacitance in capacitive sensor, when charging corresponding parasitic capacitance, first PMOS tube and second PMOS tube are turned on, and second NMOS tube is turned off, when discharging parasitic capacitance, first NMOS tube and second NMOS tube are turned on, and second PMOS tube is turned off, while eliminating direct current component in capacitive sensor signal, compared with the current source of source negative feedback form, the direct current elimination circuit can improve current efficiency and direct current elimination rate, reduce circuit area.The control chip and the electronic equipment include above-mentioned direct current elimination circuit.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a DC cancellation circuit for a capacitive sensor, a control chip for a capacitive sensor, and an electronic device. Background Technology

[0002] Products employing capacitance-based sensors (hereinafter referred to as capacitive sensors) are widely used in consumer and industrial electronic products, such as touch displays and fingerprint recognition products. When a capacitive sensor is working, the sensed signal is transmitted, amplified, and filtered by a signal chain circuit, and then quantized by an analog-to-digital converter circuit. However, the sensed signal often contains a certain DC component, which causes the parasitic capacitance within the sensor to also have a charge. Excessive DC component can affect the linearity of signal transmission and even cause complete distortion.

[0003] To mitigate DC interference, a current source is typically used to charge and discharge parasitic capacitors at regular intervals to eliminate the DC component. Currently used current sources employ source-to-negative feedback, resulting in low current efficiency. This leads to a low operating frequency and low DC elimination rate for the entire module. Furthermore, the current source, coupled to the display module via parasitic capacitance, can negatively impact display quality. Additionally, current current sources suffer from a large circuit area. Summary of the Invention

[0004] To eliminate the DC component in a capacitive sensor signal, and to improve current efficiency and DC cancellation rate while reducing circuit area compared to a source-based negative feedback current source, this invention provides a DC cancellation circuit for a capacitive sensor. This invention also provides a control chip for the capacitive sensor and an electronic device.

[0005] On one hand, the present invention provides a DC cancellation circuit for a capacitive sensor. The DC cancellation circuit includes multiple current mirror branches. Each current mirror branch includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source terminal of the first PMOS transistor is coupled to the positive terminal of the power supply voltage. The drain terminal of the first PMOS transistor is coupled to the source terminal of the second PMOS transistor. The drain terminal of the second PMOS transistor is coupled to the drain terminal of the second NMOS transistor. The source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor. The source terminal of the first NMOS transistor is coupled to the negative terminal of the power supply voltage.

[0006] The connection point between the second PMOS transistor and the second NMOS transistor is used to couple a parasitic capacitor in the capacitive sensor. When the corresponding parasitic capacitor is charged, the first PMOS transistor and the second PMOS transistor are turned on, and the second NMOS transistor is turned off. When the parasitic capacitor is discharged, the first NMOS transistor and the second NMOS transistor are turned on, and the second PMOS transistor is turned off.

[0007] Optionally, the capacitive sensor includes a plurality of parasitic capacitors generated by the transmitting electrode channel or the receiving electrode channel, and the capacitance values ​​of each parasitic capacitor are equal.

[0008] Optionally, the plurality of current mirror branches include multiple groups corresponding to each of the parasitic capacitances, and each group of current mirror branches includes k current mirror branches for selective connection with the corresponding parasitic capacitance, where k is an integer greater than 1.

[0009] Optionally, the DC cancellation circuit further includes:

[0010] The programming circuit module is used to adjust the gate potentials of the first PMOS transistor and the first NMOS transistor to adjust the current flowing through the first PMOS transistor and the second PMOS transistor when charging the corresponding parasitic capacitor, and to adjust the current flowing through the first NMOS transistor and the second NMOS transistor when discharging the corresponding parasitic capacitor.

[0011] Optionally, the programming circuit module includes:

[0012] The clamping module includes a sensing unit, a third PMOS transistor, and a third NMOS transistor. The source terminal of the third PMOS transistor is coupled to the positive terminal of the power supply voltage, and the drain terminal is coupled to the drain terminal of the third NMOS transistor. The source terminal of the third NMOS transistor is connected to ground. The input terminal of the sensing unit is connected to the connection point of the third PMOS transistor and the third NMOS transistor. The first output terminal of the sensing unit is coupled to the gate of the third PMOS transistor PM3, and the second output terminal is coupled to the gate of the third NMOS transistor. The clamping module is used to clamp the voltage at the connection point of the third PMOS transistor and the third NMOS transistor.

[0013] The first capacitor has its upper plate coupled to the connection point of the third PMOS transistor and the third NMOS transistor; and

[0014] The lower plate input module is coupled to the lower plate of the first capacitor. The lower plate input module is used to adjust the charge state of the lower plate of the first capacitor so as to adjust the gate potential of the first PMOS transistor or the first NMOS transistor accordingly by forming a corresponding current at the connection point of the third PMOS transistor and the third NMOS transistor.

[0015] Optionally, the sensing unit employs a first operational amplifier, one input terminal of which is coupled to a clamping voltage, and the other input terminal is coupled to the connection point of the third PMOS transistor and the third NMOS transistor. The gates of the third PMOS transistor and the first PMOS transistor are coupled to the first output terminal of the first operational amplifier, and the gates of the third NMOS transistor and the first NMOS transistor are coupled to the second output terminal of the first operational amplifier.

[0016] Optionally, the lower plate input module provides positive charge to the lower plate of the first capacitor when the parasitic capacitor is discharging, and provides negative charge to the lower plate of the first capacitor when the parasitic capacitor is charging.

[0017] Optionally, the lower plate input module includes a first resistor and a waveform output unit. One end of the first resistor is coupled to the lower plate of the first capacitor, and the output end of the waveform output unit is coupled to the other end of the first resistor. The waveform generation unit is used to generate a voltage rise waveform when the parasitic capacitor discharges and to generate a voltage fall waveform when the parasitic capacitor is charged.

[0018] Optionally, the voltage rise waveform is a step rise shape; and / or, the voltage fall waveform is a step fall shape.

[0019] On the other hand, the present invention provides a control chip for a capacitive sensor, the control chip including the above-mentioned DC cancellation circuit.

[0020] Optionally, the control chip further includes a signal processing module, which includes a second operational amplifier, a switching element, and a second capacitor; one input terminal of the second operational amplifier is coupled to a reference voltage, and the other input terminal is coupled to one end of the parasitic capacitor coupled to the DC cancellation circuit through the switching element.

[0021] In another aspect, the present invention provides an electronic device, the electronic device including the above-described DC cancellation circuit and a capacitive sensor using the DC cancellation circuit.

[0022] Optionally, the capacitive sensor is a capacitive touch display module or a capacitive fingerprint recognition module.

[0023] The DC cancellation circuit provided by this invention can charge and discharge the parasitic capacitance in a capacitive sensor, eliminating the DC component in the sensor signal and avoiding problems such as poor transmission linearity or even complete distortion caused by excessive DC component. Furthermore, the current mirror branch used for charging and discharging injects charge into the corresponding parasitic capacitance through first and second PMOS transistors, and extracts the charge stored on the parasitic capacitance through first and second NMOS transistors. The source terminal of the first PMOS transistor is coupled to the positive terminal of the power supply voltage (without a resistor between them), and the source terminal of the first NMOS transistor is coupled to the negative terminal of the power supply voltage (without a resistor between them). The current mirror branch adopts a common-source configuration instead of a source-negative feedback configuration. For the first PMOS transistor and the first NMOS transistor, the overdrive voltage is larger, the current drive capability is stronger, and the current efficiency is higher in the common-source configuration, which can improve the operating speed and DC cancellation rate. Moreover, since no resistor is used to form source-negative feedback, it helps to reduce the circuit area.

[0024] The control chip for the capacitive sensor provided by this invention includes the aforementioned DC cancellation circuit, which can eliminate the DC component in the sensor signal while controlling the operation of the capacitive sensor. Compared with a source-based negative feedback current source, it improves current efficiency and DC cancellation rate, which helps to improve the overall performance of the capacitive sensor. Furthermore, since the aforementioned DC cancellation circuit can reduce the circuit area, it helps to miniaturize the control chip.

[0025] The electronic device provided by the present invention includes the above-described DC cancellation circuit and a capacitive sensor using the DC cancellation circuit. The DC component in the signal of the capacitive sensor can be eliminated by the DC cancellation circuit, and it has high current efficiency and small circuit area, which helps to improve the performance of the electronic device. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a DC cancellation circuit according to an embodiment of the present invention, and of charging and discharging parasitic capacitors using the DC cancellation circuit.

[0027] Figure 2 It is to utilize Figure 1 The diagram shows the gate control signals of each MOS transistor in the current mirror branch when the DC cancellation circuit is charging and discharging.

[0028] Figure 3 This is a schematic diagram of a DC cancellation circuit with a programming circuit module according to an embodiment of the present invention.

[0029] Figure 4 This is a circuit diagram of the clamping module in one embodiment of the present invention.

[0030] Figure 5 When discharging parasitic capacitance Figure 3The waveform characteristics of the VTRG node, VBP node, and VBN node of the programming circuit module shown are illustrated.

[0031] Figure 6 This is a partial circuit diagram of a capacitive sensor and its control chip in one embodiment of the present invention. Detailed Implementation

[0032] The DC cancellation circuit, control chip, and electronic device for a capacitive sensor of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0033] Capacitive sensors typically use capacitor arrays to transmit signals, such as in capacitive touch display modules or fingerprint recognition modules. The capacitor array may include multiple transmitting electrode channels (Tx) forming the capacitor structure and multiple receiving electrode channels (Rx) isolated from the transmitting electrodes. Tx and Rx have parasitic capacitance and parasitic resistance. Taking a capacitive touch display module as an example, since the sensed signal often contains a certain DC component, after each coding and display module drive according to a preset timing sequence, the parasitic capacitance is also charged and stores charge. To avoid affecting signal transmission, the charge on the parasitic capacitance needs to be canceled, i.e., DC voltage cancellation. Otherwise, the charge on the parasitic capacitance will overwhelm the effective signal charge, causing the effective signal to distort during transmission due to circuit saturation.

[0034] The DC cancellation circuit for capacitive sensors described in the following embodiments of the present invention can charge and discharge the parasitic capacitance in the capacitive sensor, eliminate the DC component in the sensor signal, avoid the problem of poor transmission linearity or even complete distortion caused by excessive DC component, and has higher current driving capability and current efficiency than the current source of source negative feedback, with a larger operating speed and DC cancellation rate. In addition, it does not require a resistor for source negative feedback, which helps to reduce the circuit area.

[0035] For clarity, the DC cancellation circuit, control chip, and electronic device for a capacitive sensor of the present invention will be described in detail below with reference to the accompanying drawings and several embodiments. It should be understood that the various embodiments are merely exemplary specific implementations of manufacturing and application examples and do not constitute a limitation on the scope of the invention. Furthermore, the separate description of multiple embodiments is only to more clearly illustrate the connotation of the invention, but the technical features of each embodiment are not unique to that embodiment, and all features of each embodiment can also be considered as features of a general embodiment. In some implementations, the technical features of the following multiple embodiments can also be related to or inspired by each other to constitute new embodiments.

[0036] Example 1

[0037] This embodiment relates to a DC cancellation circuit for a capacitive sensor. (Refer to...) Figure 1 The DC cancellation circuit 100 includes multiple current mirror branches 110. Each current mirror branch 110 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a second NMOS transistor NM1, and a first NMOS transistor NM2. The source terminal of the first PMOS transistor PM1 is coupled to the positive terminal of the power supply voltage VDD. The drain terminal of the first PMOS transistor PM1 is coupled to the source terminal of the second PMOS transistor PM2. The drain terminal of the second PMOS transistor PM2 is coupled to the drain terminal of the second NMOS transistor NM2. The source terminal of the second NMOS transistor NM2 is coupled to the drain terminal of the first NMOS transistor NM1. The source terminal of the first NMOS transistor NM1 is coupled to the negative terminal of the power supply voltage VSS.

[0038] The DC cancellation circuit 100 employs a current mirror structure formed by CMOS circuitry, which utilizes the current of the MOSFET when it operates in the saturation region and the MOSFET dimensions (including such as...) Figure 1 The width-to-length ratio (W / L)p of the first PMOS transistor PM1 and the width-to-length ratio (W / L)n of the first NMOS transistor NM1 are related to the gate-source voltage (Vgs). By designing the corresponding MOS transistors in each current mirror branch to have the same size and ensuring proper matching, when all corresponding MOS transistors use the same Vgs, the current in each current mirror branch will be the same. The current amplification ratio (K value) of the current mirror structure can be set through programming.

[0039] like Figure 1 As shown, the connection point of the second PMOS transistor and the second NMOS transistor is used to couple a parasitic capacitance Cpar in the capacitive sensor 200. One plate of the parasitic capacitance Cpar is coupled to the connection point, and the other plate is coupled to one end of the parasitic resistor Rpar. The other end of the parasitic resistor Rpar is connected to the common ground terminal (ELVSS) of the circuit.

[0040] like Figure 1As shown, the gate control signals of the first PMOS transistor PM1, the second PMOS transistor PM2, the second NMOS transistor NM2, and the first NMOS transistor NM1 are represented as VBP, DC_CKB, DC_CK, and VBN, respectively. Figure 2 It shows the use of Figure 1 The waveform characteristics of the gate control signals of each MOS transistor during the charging and discharging of parasitic capacitance in the DC cancellation circuit shown are illustrated. (Refer to...) Figure 2 When the current mirror branch 110 charges the corresponding parasitic capacitance Cpar (i.e., the parasitic capacitance Cpar coupled to the current mirror branch 110) (i.e., the charging process in DC cancellation), DC_CKB is pulled low, VBP remains low, and DC_CK remains low, while VBN remains high, for example. This turns on the first PMOS transistor and the second PMOS transistor, and turns off the second NMOS transistor, ensuring that the current generated by the first PMOS transistor PM1 and the second PMOS transistor PM1 can only flow to the parasitic capacitance Cpar outside the DC cancellation circuit 100. The current flows, thereby pulling up the voltage of the parasitic capacitor Cpar, thus achieving charging. When the aforementioned current mirror branch 110 discharges the corresponding parasitic capacitor Cpar (i.e., the discharge process in DC elimination), DC_CKB remains at a high level, VBP remains at a low level, while DC_CK is pulled to a high level and VBN remains at a high level. Then, the second PMOS transistor PM2 is turned off, and the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on. The current generated by the conduction can only be provided by the parasitic capacitor Cpar, thereby pulling down the voltage of the parasitic capacitor Cpar, thus achieving discharge.

[0041] In this embodiment, during the charging and discharging processes described above, the gate control signal VBP of the first PMOS transistor PM1 and the gate control signal VBN of the first NMOS transistor NM2 remain at constant operating voltages, and the current flowing through them is determined by the source-drain voltage difference. However, the present invention is not limited thereto. Figure 2 The waveform characteristics shown are merely examples. In another embodiment, VBP or VBN may also change during charging or discharging. For example, VBN may be low during charging and switch to high during discharging, and / or VBP may be low during charging and switch to high during discharging. Furthermore, Embodiment 2 describes an example where VBN and VBP change.

[0042] In the current mirror branch 110 of the aforementioned DC cancellation circuit 100, no resistors for forming source negative feedback are provided between the source terminal of the first PMOS transistor PM1 and the positive power supply voltage VDD, or between the source terminal of the first NMOS transistor NM1 and the negative power supply voltage VSS. That is, the current mirror uses a common-source configuration instead of a source negative feedback configuration. This allows the first PMOS transistor PM1 and the first NMOS transistor NM1 to have larger overdrive voltages. Taking the first NMOS transistor NM1 as an example, if a source negative feedback structure is used, the current flowing through the resistor between the first NMOS transistor NM1 and the negative power supply voltage VSS will cause the source voltage (VS) to increase, which in turn will cause the gate-source voltage (VGS) to decrease, resulting in a smaller overdrive voltage. However, with the common-source configuration, the source voltage (VS) is smaller, resulting in a larger gate-source voltage (VGS), and thus a larger overdrive voltage. Similarly, it can be understood that the overdrive voltage of the first PMOS transistor PM1 is larger in the common-source configuration. Since the overdrive voltages of the first PMOS transistor PM1 and the first NMOS transistor NM1 are larger, their current driving capability is stronger and their current efficiency is higher. This can improve the operating speed and DC elimination rate of the DC elimination circuit 100, which helps to improve the refresh rate of the capacitive sensor product. Furthermore, since no resistor is set to form source negative feedback, it helps to reduce the circuit area.

[0043] The capacitive sensor 200 may include multiple parasitic capacitances generated by the transmitting electrode channel (Tx) or the receiving electrode channel (Rx), wherein the capacitance values ​​of each parasitic capacitance are, for example, equal. (See reference...) Figure 1 As an example, the multiple current mirror branches 110 in the DC cancellation circuit 100 may include multiple groups corresponding to each parasitic capacitance Cpar, each group including k current mirror branches 110 for selective connection to a corresponding parasitic capacitance Cpar, where k is an integer greater than 1. Figure 1 The depth plane on one side of the DC cancellation circuit 100 shows k current mirror branches 110 corresponding to the same parasitic capacitance Cpar, where the first one is the first current mirror branch (1st) and the last one is the kth current mirror branch (kth). By selectively connecting the same parasitic capacitance Cpar to the k current mirror branches, and by adjusting the actual number of current mirror branches 110 selected for each parasitic capacitance Cpar (the actual number of selected current mirror branches 110 is less than or equal to k), it helps to improve the mismatch between the channels that generate the parasitic capacitance 110 (such as each emitter electrode channel (Tx) or each receiver electrode channel (Rx)), improve the matching, and ensure that each channel can fully eliminate the DC voltage on the parasitic capacitance Cpar.

[0044] Example 2

[0045] This embodiment relates to a DC cancellation circuit 100 for a capacitive sensor 200. The main difference between this DC cancellation circuit 100 and the DC cancellation circuit 100 described in Embodiment 1 is that, in this embodiment, during the charging and discharging of the parasitic capacitance Cpar, the gate control signal VBP of the first PMOS transistor PM1 and the gate control signal VBN of the first NMOS transistor NM1 are not kept at constant operating voltages, but are programmed to have a certain changing trend. This allows adjustment of the current on the first PMOS transistor PM1 and the first NMOS transistor NM1, facilitating controllable DC cancellation rate. The following mainly describes the above differences. For other features of the DC cancellation circuit 100 in this embodiment, please refer to the description of the DC cancellation circuit 100 in Embodiment 1.

[0046] According to the capacitor discharge formula Qpar = Idischarge * t (where Qpar represents the charge on the parasitic capacitor Cpar, Idischarge represents the discharge current, and t represents the discharge time), when Qpar is constant, the discharge time can be controlled by adjusting the discharge current, thereby controlling the rate of DC voltage elimination. Alternatively, when Qpar changes, the discharge time can be kept essentially constant by adjusting the discharge current. The relationship for capacitor charging is similar; by adjusting the charging current, the charging time can be controlled or kept essentially constant. In this embodiment, the DC elimination circuit 100, in addition to the current mirror branch 110 described in Embodiment 1 above, also includes a programming circuit module 30. The programming circuit module 30 is used to adjust the gate potentials of the first PMOS transistor PM1 and the first NMOS transistor NM1 to adjust the current flowing through the first PMOS transistor PM1 and the second PMOS transistor PM2 when charging the corresponding parasitic capacitor Cpar, and to adjust the current flowing through the first NMOS transistor NM1 and the second NMOS transistor NM2 when discharging the corresponding parasitic capacitor Cpar. As can be seen, the charging and discharging times of the DC elimination circuit 100 can be adjusted or stabilized as needed using the programming circuit module 30.

[0047] Figure 3 The programming circuit module 30 in the DC cancellation circuit 100 is shown. (Refer to...) Figure 3 As an example, the programming circuit module 30 includes a lower plate input module 310, a clamping module 320, and a first capacitor CL.

[0048] The clamping module 320 includes a sensing unit 321, a third PMOS transistor PM3, and a third NMOS transistor NM3. The source terminal of the third PMOS transistor PM3 is coupled to the positive terminal of the power supply voltage VDD, and its drain terminal is coupled to the drain terminal of the third NMOS transistor NM3. The source terminal of the third NMOS transistor NM3 is connected to ground. The input terminal of the sensing unit 321 is connected to the connection point of the third PMOS transistor PM3 and the third NMOS transistor NM3. One output terminal is coupled to the gate of the third PMOS transistor PM3 and the gate of the first PMOS transistor PM1, and the other output terminal is coupled to the gate of the third NMOS transistor NM3 and the gate of the first NMOS transistor NM1. The clamping module 320 is used to clamp the voltage at the connection point of the third PMOS transistor PM3 and the third NMOS transistor NM3.

[0049] Figure 4 The circuitry of the clamping module 320 in one embodiment is shown. (Refer to...) Figure 3 and Figure 4 As an example, the sensing unit 321 employs an operational amplifier (OPA), denoted as the first operational amplifier OPA. One input terminal of the first operational amplifier OPA is coupled to a clamping voltage V0, and the other input terminal is coupled to the connection point of the third PMOS transistor PM3 and the third NMOS transistor NM3. The gates of the third PMOS transistor PM3 and the aforementioned first PMOS transistor PM1 are coupled to the first output terminal of the first operational amplifier OPA, and the gates of the third NMOS transistor NM3 and the aforementioned first NMOS transistor NM1 are coupled to the second output terminal of the first operational amplifier OPA. The clamping module 320 is used to couple the connection point voltage of the third PMOS transistor PM3 and the third NMOS transistor NM3 to the clamping voltage V0. In other embodiments, the sensing unit 321 may also employ other circuit structures.

[0050] In the programming circuit module 30, the connection point between the upper plate of the first capacitor CL and the third PMOS transistor PM3 and the third NMOS transistor NM3 is clamped at the clamping voltage V0. The lower plate of the first capacitor CL is coupled to the lower plate input module 310. The lower plate input module 310 is used to adjust the charge state of the lower plate of the first capacitor CL so as to adjust the gate potential of the first PMOS transistor PM1 or the first NMOS transistor NM1 accordingly by forming a corresponding current at the connection point of the third PMOS transistor PM3 and the third NMOS transistor NM3. As an example, in order to improve the DC elimination rate, the lower plate input module 310 provides positive charge to the lower plate of the first capacitor CL when the parasitic capacitor Cpar is discharging, and provides negative charge to the lower plate of the first capacitor CL when the parasitic capacitor Cpar is charging. Further explanation is as follows.

[0051] Reference Figure 3The lower plate input module 310 includes, for example, a first resistor RL and a waveform output unit. One end of the first resistor RL is coupled to the lower plate of the first capacitor CL, and the output end of the waveform output unit is coupled to the other end of the first resistor RL. The waveform generation unit is used to generate a voltage rise waveform when the parasitic capacitor Cpar is discharged, and also to generate a voltage drop waveform when the parasitic capacitor Cpar is charged.

[0052] The waveform output unit is, for example, a waveform generator 311, with its output directly coupled to a first resistor RL. However, this invention is not limited to this; the waveform output unit can also employ other structures. For instance, in some embodiments, the waveform output unit may include a waveform generator and a waveform modulation circuit connecting the waveform generator and the first resistor RL respectively. The output waveform of the waveform output unit is formed by the waveform modulation circuit modulating the output of the waveform generator as needed. The following description uses a waveform generator 311 as an example of the waveform generation unit.

[0053] The waveform generator 311 is used to generate a voltage rise waveform when the DC cancellation circuit 100 discharges the parasitic capacitance Cpar, so as to adjust the potential of the output terminal of the sensing unit 321 connected to the gates of the third NMOS transistor NM3 and the first NMOS transistor NM1 (such as the second output terminal of the first operational amplifier OPA), thereby adjusting the gate potentials of the third NMOS transistor NM3 and the first NMOS transistor NM1. It is also used to generate a voltage drop waveform when the parasitic capacitance Cpar is charged, so as to adjust the potential of the output terminal of the sensing unit 321 connected to the gates of the third PMOS transistor PM3 and the first PMOS transistor PM1 (such as the first output terminal of the first operational amplifier OPA), thereby adjusting the gate potentials of the third PMOS transistor PM3 and the first PMOS transistor PM1.

[0054] The rates of change of the voltage rise waveform and the voltage fall waveform are set by programming. The voltage rise waveform is, for example, a step rise shape; and / or, the voltage fall waveform is, for example, a step fall shape.

[0055] In the clamping module 320 described above, the first operational amplifier OPA, the third PMOS transistor PM3, and the third NMOS transistor NM3 form a closed-loop circuit. This closed-loop circuit can clamp the voltage on the upper plate of the first capacitor CL. Thus, when the waveform generator 311 generates a waveform, because the voltage on the upper plate of the first capacitor CL is clamped at the clamping voltage V0, charge accumulates on the first capacitor CL. This charge is provided by the third PMOS transistor PM3 or the third NMOS transistor NM3. If the VTRG node is a rising waveform, the lower plate of the first capacitor CL is positively charged (i.e., positive charge is provided to the lower plate), and the upper plate of the first capacitor CL needs to be negatively charged (i.e., negative charge is provided to the upper plate), requiring the third MOS transistor NM3 to extract the charge.

[0056] Figure 5 This shows the discharge of the parasitic capacitance Cpar. Figure 3 and Figure 4 The waveform characteristics of the VTRG node, VBP node, and VBN node in the programming circuit module 30 are described below. The discharge process is used as an example. Figures 3 to 5 The function of programming circuit module 30 is explained.

[0057] Figure 5 The waveform A shown depicts a step from a voltage (denoted as the first voltage V1, which can be 0V) to a higher voltage (denoted as the second voltage V2), and the rise rate can be adjusted as needed. The waveform B depicts a step from a voltage to a higher voltage, maintaining this position for a period before stepping to an even higher voltage. Waveform B can be considered a superposition of waveforms A, where the rise rate through each step of waveform A is adjustable. It should be noted that the waveforms generated by waveform generator 311 are not limited to... Figure 5 The waveforms A and B shown can also be used to generate other waveform styles as needed.

[0058] When waveform generator 311 generates such Figure 5 As shown in waveform A (voltage rise waveform), the lower plate of the first capacitor CL is positively charged. Through the induction of the first capacitor CL, since the upper plate of the first capacitor CL is clamped, the upper plate of the first capacitor CL needs to be negatively charged. Therefore, the third NMOS transistor NM3 needs to pump charge, forming a current, which pulls the VBN node voltage high, generating waveform A' at the VBN node. The VBP node voltage remains unchanged (e.g., remains low, see reference). Figure 2 Since the VBN node provides the gate signal VBN of the first NMOS transistor NM1 in each of the aforementioned current mirror branches 110, the gate signal VBN of the first NMOS transistor NM1 forms a voltage rise waveform as shown in waveform A' during discharge. When waveform generator 311 generates... Figure 5 When the B waveform is shown, due to the induction of the first capacitor CL, the upper plate of the first capacitor CL is clamped, and the third NMOS transistor NM3 needs to draw charge to form a discharge current, which pulls up the voltage of the VBN node. This can generate the B' waveform at the VBN node, while the voltage of the VBP node remains unchanged. As a result, the gate signal VBN of the first NMOS transistor NM1 in each of the above current mirror branches forms a voltage rise waveform as shown by the B' waveform when discharging.

[0059] The slope formula for the rising edge of waveform A is I / CL, where I represents the charging current to the lower plate of the first capacitor CL. Different rising edges of waveform A indicate different magnitudes of the charging current to the first capacitor CL. A smaller slope indicates a smaller current, and correspondingly, a smaller stable value of the gate signal VBN of the third MOSFET NM3, and a slower rise rate of the VBN node voltage. Therefore, if... Figure 5 As shown, if the VTRG node is waveform A, then the VBN node needs to be pulled high. Different pull rates of the VBN node result in different heights and durations, as shown by waveform A'. Table 1 lists the voltage changes and rise times corresponding to three waveforms of different rise times (denoted as A1 (corresponding to the black line), A2 (corresponding to the red line), and A3 (corresponding to the green line), as well as the voltage changes and high-level durations corresponding to the A' waveforms (A1 corresponds to A1', A2 corresponds to A2', and A3 corresponds to A3') formed at the VBN node due to these three waveforms, and illustrates the relationships between them.

[0060] Table 1

[0061] Signal voltage change A waveform rise time A' High level duration A1 V1 → V2 Δt1 / A1’ V1'——>V2' / t1 A2 V1 → V2 Δt2 / A2’ V1'——>V3' / t2 A3 V1 → V2 Δt3 / A3’ V1'——>V4' / t3 relation V4' <V3’<V2’ Δt1<Δt2<Δt3 t1 <t2<t3

[0062] Referring to Table 1, in Figure 5 Of the three A waveforms shown, for the A1 waveform, when the voltage of the VTRG node rises from V1 (which can be 0V) to V2 within a time Δt1, the high-level duration t1 of the A1' waveform corresponding to the VBN node is the shortest, and the voltage value V3' of the VBN node is the largest. Furthermore, since the positive charge charged on the lower plate of the first capacitor CL (i.e., the product of the capacitance value of the first capacitor CL and the voltage difference, which can be expressed as CL*(V2-V1)) is fixed, the faster the rise rate of the A waveform, the shorter the charge transfer can be completed in a shorter time. Correspondingly, the discharge current provided by the third NMOS transistor NM3 is also larger. Reflected in the closed-loop circuit of the clamping module 320, this makes the high level of the VBN node higher and the duration shorter. Since the high-level voltage of the VBN node also acts on the gate of the first NMOS transistor NM1 of each current mirror branch 110, the A1 waveform will make the discharge current flowing through the first NMOS transistor NM1 the largest, that is, the DC elimination rate is the fastest.

[0063] Similarly, if the voltage signal at the VTRG node is waveform B, since waveform B is composed of the superposition of at least two waveforms A, waveform B' is also a superposition of at least two waveforms A'. For example... Figure 5The three B waveforms shown (represented as B1 (corresponding to the black line), B2 (corresponding to the red line), and B3 (corresponding to the green line)) illustrate this. Waveform B3 indicates that the voltage at the VTRG node rises from V1 to V2 after a certain period, and then rises to V3 after another period. A voltage rise occurs at the VBN node at each step, making the B' waveform at the VBN node periodic. The square wave period of the B' waveform is t3. The voltage of this B3' waveform acts on the gate of the first NMOS transistor NM1 in each current mirror branch 110, resulting in a longer discharge time and a more thorough DC cancellation effect. It is evident that by controlling the step-by-step voltage rise time of the B waveform, the overall rate of DC cancellation can also be controlled.

[0064] As can be seen, during the discharge process of the current mirror branch 110, the programming circuit module 30 can generate a voltage rise waveform at the VTRG node to cause a corresponding voltage change at the VBN node. By adjusting the voltage rise waveform, the discharge current and discharge time flowing through the first NMOS transistor NM1 during the discharge process can be controlled, thereby achieving control of the DC elimination rate. During this discharge process, such as... Figure 5 As shown, the voltage of the VBP node remains unchanged, so the gate signal VBP of the first PMOS transistor remains unchanged (e.g., low level).

[0065] Using the above principle, the programming circuit module 30 can also control the charging current and charging time during the charging process of the current mirror branch 110. As an example, if the voltage waveform at the VTRG node is the inverse of waveform A or waveform B, then the lower plate of the first capacitor CL is discharged (i.e., negative charge is provided). Since the upper plate of the first capacitor CL is clamped, the upper plate needs to be positively charged (i.e., positive charge is provided). The charging current is formed by the third PMOS transistor PM3, the voltage at the VBP node is pulled down, and the voltage at the VBN node remains unchanged (e.g., remains high, see reference). Figure 2 The voltage of the VBP node can be, for example, presented as the above-mentioned A' waveform (when the voltage of the VTRG node is the inverse of the above-mentioned A waveform) or B' waveform (when the voltage of the VTRG node is the inverse of the above-mentioned B waveform), thereby allowing control over the current and duration of the charging process.

[0066] In this embodiment, by adjusting the waveform of the waveform generator 311 (e.g., by raising it from V1 to different voltages such as V2 or V3 with different durations), the voltage of the VBN node (i.e., the gate voltage of the first NMOS transistor NM1) and the voltage of the VBP node (i.e., the gate voltage of the first PMOS transistor PM1) can be adjusted. This allows for adjustment of the discharge current and / or charging current of the current mirror branch 110, making the DC cancellation rate controllable. Taking a capacitive touch display as an example, by adjusting the DC cancellation efficiency, the impact of the DC cancellation process on the display effect when coupled to the display module through parasitic capacitance can be reduced.

[0067] Example 3

[0068] This embodiment relates to a control chip for a capacitive sensor, the control chip including the DC cancellation circuit 100 described in Embodiment 1 or Embodiment 2 above.

[0069] Reference Figures 1 to 5 The control chip can be used to drive the capacitive sensor 200 to work, and the control chip can eliminate the DC voltage of the signal of the capacitive sensor 200 using the DC cancellation circuit 100. Figure 6 A partial circuit of the control chip 10 of a capacitance sensor 200 and parasitic circuitry in the capacitance sensor 200 are shown. (Refer to...) Figure 6 In addition to the DC cancellation circuit 100 described above, the control chip 10 may also include a signal processing module 120, which processes the sensor signal and generates a corresponding output voltage. As an example, the signal processing module 120 includes a second operational amplifier 121, a switching element SW, and a second capacitor Cf; one input terminal of the second operational amplifier 121 is coupled to a reference voltage Vref, and the other input terminal is coupled through the switching element SW to one end of the parasitic capacitor Cpar that is coupled to the DC cancellation circuit 100.

[0070] Taking the capacitive sensor 200 as an example of a capacitive touch display module, when the control chip 10 operates according to a preset timing sequence, in each cycle, the first stage is the driving display module stage, that is, coding the capacitive touch display module. In this stage, signal charge and parasitic charge will be generated on the parasitic capacitor Cpar. The second stage is the DC cancellation stage, that is, DC cancellation is performed by the DC cancellation circuit 100 to eliminate the parasitic charge. This stage is also the reset stage of the second operational amplifier 121. The third stage is the charge transfer stage, which is also the stage when the second operational amplifier 121 is in the amplification phase. In this third stage, the remaining signal charge on the parasitic capacitor Cpar will be transferred to the second capacitor Cf, which is reflected as the output voltage Vout.

[0071] Since the control chip 10 of this embodiment adopts the DC elimination circuit 100 described above, it can eliminate the DC component in the sensing signal while controlling the operation of the capacitive sensor 200. At the same time, compared with the current source of negative feedback, it can improve the current efficiency and DC elimination rate, reduce the circuit area, and help improve the overall performance of the capacitive sensor 200.

[0072] Example 4

[0073] This embodiment relates to an electronic device, which includes the DC cancellation circuit 100 described in Embodiment 1 or Embodiment 2 above, and also includes a capacitive sensor 200 using the DC cancellation circuit 100. The capacitive sensor 200 is, for example, a capacitive touch display module or a capacitive fingerprint recognition module. However, it is not limited to these; the capacitive sensor 200 can also be other sensors that utilize capacitive sensing signals.

[0074] In the electronic device, the DC component in the sensing signal of the capacitive sensor 200 can be eliminated by the DC cancellation circuit 100, which has high current efficiency and small circuit area, thus helping to improve the overall performance of the electronic device.

[0075] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and relevant parts can be understood by referring to them.

[0076] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A DC cancellation circuit for a capacitive sensor, characterized in that, It includes multiple current mirror branches, each of which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source terminal of the first PMOS transistor is coupled to the positive terminal of the power supply voltage, the drain terminal of the first PMOS transistor is coupled to the source terminal of the second PMOS transistor, the drain terminal of the second PMOS transistor is coupled to the drain terminal of the second NMOS transistor, the source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor, and the source terminal of the first NMOS transistor is coupled to the negative terminal of the power supply voltage. The connection point between the second PMOS transistor and the second NMOS transistor is used to couple a parasitic capacitor in the capacitive sensor. When the corresponding parasitic capacitor is charged, the first PMOS transistor and the second PMOS transistor are turned on, and the second NMOS transistor is turned off. When the parasitic capacitor is discharged, the first NMOS transistor and the second NMOS transistor are turned on, and the second PMOS transistor is turned off.

2. The DC cancellation circuit as described in claim 1, characterized in that, The capacitive sensor includes multiple parasitic capacitors generated by the transmitting electrode channel or the receiving electrode channel, and the capacitance values ​​of each parasitic capacitor are equal.

3. The DC cancellation circuit as described in claim 2, characterized in that, The plurality of current mirror branches include multiple groups corresponding to each of the parasitic capacitances. Each group of current mirror branches includes k current mirror branches for selective connection to the corresponding parasitic capacitance, where k is an integer greater than 1.

4. The DC cancellation circuit as described in claim 1, characterized in that, Also includes: The programming circuit module is used to adjust the gate potentials of the first PMOS transistor and the first NMOS transistor to adjust the current flowing through the first PMOS transistor and the second PMOS transistor when charging the corresponding parasitic capacitor, and to adjust the current flowing through the first NMOS transistor and the second NMOS transistor when discharging the corresponding parasitic capacitor.

5. The DC cancellation circuit as described in claim 4, characterized in that, The programming circuit module includes: A clamping module includes a sensing unit, a third PMOS transistor, and a third NMOS transistor. The source terminal of the third PMOS transistor is coupled to the positive terminal of the power supply voltage, and the drain terminal is coupled to the drain terminal of the third NMOS transistor. The source terminal of the third NMOS transistor is connected to ground. The input terminal of the sensing unit is connected to the connection point of the third PMOS transistor and the third NMOS transistor. One output terminal of the sensing unit is coupled to the gate of the third PMOS transistor and the first PMOS transistor, and the other output terminal is coupled to the gate of the third NMOS transistor and the first NMOS transistor. The clamping module is used to clamp the voltage at the connection point of the third PMOS transistor and the third NMOS transistor. The first capacitor has its upper plate coupled to the connection point of the third PMOS transistor and the third NMOS transistor; and The lower plate input module is coupled to the lower plate of the first capacitor. The lower plate input module is used to adjust the charge state of the lower plate of the first capacitor so as to adjust the gate potential of the first PMOS transistor or the first NMOS transistor accordingly by forming a corresponding current at the connection point of the third PMOS transistor and the third NMOS transistor.

6. The DC cancellation circuit as described in claim 5, characterized in that, The sensing unit employs a first operational amplifier. One input terminal of the first operational amplifier is coupled to a clamping voltage, and the other input terminal is coupled to the connection point of the third PMOS transistor and the third NMOS transistor. The gates of the third PMOS transistor and the first PMOS transistor are coupled to the first output terminal of the first operational amplifier, and the gates of the third NMOS transistor and the first NMOS transistor are coupled to the second output terminal of the first operational amplifier.

7. The DC cancellation circuit as described in claim 5, characterized in that, The lower plate input module provides positive charge to the lower plate of the first capacitor when the parasitic capacitor discharges, and provides negative charge to the lower plate of the first capacitor when the parasitic capacitor is charging.

8. The DC cancellation circuit as described in claim 7, characterized in that, The lower electrode plate input module includes: The first resistor has one end coupled to the lower plate of the first capacitor; and The waveform output unit has its output terminal coupled to the other end of the first resistor. The waveform generation unit is used to generate a voltage rise waveform when the parasitic capacitor discharges and to generate a voltage drop waveform when the parasitic capacitor is charged.

9. The DC cancellation circuit as described in claim 8, characterized in that, The voltage rise waveform is a step rise shape; and / or, the voltage fall waveform is a step fall shape.

10. A control chip for a capacitive sensor, characterized in that, The control chip includes a DC cancellation circuit as described in any one of claims 1 to 9.

11. The control chip as described in claim 10, characterized in that, It also includes a signal processing module, which includes a second operational amplifier, a switching element, and a second capacitor; one input terminal of the second operational amplifier is coupled to a reference voltage, and the other input terminal is coupled to one end of the parasitic capacitor that is coupled to the DC cancellation circuit through the switching element.

12. An electronic device, characterized in that, Includes a DC cancellation circuit as described in any one of claims 1 to 9 and a capacitive sensor using the DC cancellation circuit.

13. The electronic device as claimed in claim 12, characterized in that, The capacitive sensor is either a capacitive touch display module or a capacitive fingerprint recognition module.

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