Touch substrate and touch display panel

Abstract

The present disclosure provides a touch substrate and a touch display panel. The touch substrate comprises a display area and a frame area. The display area comprises: a source-drain electrode layer comprising a plurality of data lines extending along a first direction; a touch trace layer comprising a plurality of effective touch traces and a plurality of virtual touch traces extending along the first direction, the effective touch traces and the virtual touch traces being arranged along a second direction, and a projection of the effective touch traces and the virtual touch traces on a substrate substrate at least partially overlapping with a projection of the data lines on the substrate; a first insulating layer; and a common electrode layer comprising a plurality of electrode blocks arranged in an array, wherein: the effective touch traces and the electrode blocks correspond to each other one by one, any effective touch trace is connected to a corresponding electrode block through a first via, the plurality of effective touch traces are connected to a plurality of first signal pins of a driving chip one by one, and the virtual touch traces are connected to a second signal pin of the driving chip or are connected to adjacent effective touch traces.

Description

Technical Field

[0001] This disclosure relates to the field of touch display technology. More specifically, it relates to a touch substrate and a touch display panel. Background Technology

[0002] As display products evolve towards higher resolution and higher screen-to-body ratios, the number of fan-out traces in the bottom bezel area of ​​the display panel increases significantly with the increase in pixels. Given that trace width is limited by manufacturing capabilities, the increased wiring space required in the fan-out area restricts further reduction of the bottom bezel. To address this issue, some products add a separate metal layer to fabricate the touch traces. These touch traces are stacked with the data lines in the source / drain electrode layers within the display area, freeing up the light-shielding space occupied by the touch traces in the traditional structure, thereby improving pixel aperture ratio and screen transmittance.

[0003] However, in actual image quality testing, display products using the above structure were found to exhibit issues such as… Figure 1 The evenly spaced vertical stripes (blocks) shown affect image quality. Summary of the Invention

[0004] The purpose of this disclosure is to provide a touch substrate and a touch display panel to solve at least one of the above-mentioned technical problems.

[0005] To achieve the above objectives, the present disclosure adopts the following technical solution: This disclosure provides a touch substrate, including a substrate, a display area disposed on the substrate, and a border area surrounding the display area, wherein the display area includes: A source / drain electrode layer is disposed on one side of the substrate, and the source / drain electrode layer includes multiple data lines extending along a first direction; A touch trace layer is disposed on the side of the source / drain electrode layer away from the substrate. The touch trace layer includes multiple effective touch traces and multiple virtual touch traces extending along a first direction. The effective touch traces and the virtual touch traces are arranged in a second direction. The orthographic projections of the effective touch traces and the virtual touch traces on the substrate at least partially overlap with the orthographic projections of the data lines on the substrate. A first insulating layer is disposed on the side of the touch trace layer away from the substrate. A common electrode layer is disposed on the side of the first insulating layer away from the substrate. The common electrode layer includes a plurality of electrode blocks arranged in an array, wherein: Each effective touch trace corresponds to one of the electrode blocks. Each effective touch trace is connected to the corresponding electrode block through a first via penetrating the first insulating layer. The multiple effective touch traces are connected to multiple first signal pins of the driver chip. The virtual touch trace is connected to the second signal pin of the driver chip or to an adjacent effective touch trace.

[0006] Optionally, the effective touch traces and the virtual touch traces are arranged periodically in the second direction in a manner that a first number of effective touch traces and a second number of virtual touch traces are grouped together, where the first number and the second number are both positive integers.

[0007] Optionally, the bezel area includes a binding area and an opposite area located on opposite sides of the display area in the first direction. The binding area is provided with multiple first fan-out lines and the driver chip. The multiple first fan-out lines correspond one-to-one with the multiple effective touch traces. The end of any effective touch trace near the binding area extends to the binding area and is connected to a first signal pin of the driver chip through the corresponding first fan-out line.

[0008] Optionally, each group includes one active touch trace and one virtual touch trace. In the second direction, the active touch trace and the virtual touch trace are alternately distributed. For any group, the virtual touch trace in that group is connected to the active touch trace.

[0009] Optionally, for any group, the end of the virtual touch trace within the group that is close to the binding area extends into the binding area and connects to the first fan-out line corresponding to the valid touch trace within the group.

[0010] Optionally, for any group, the end of the virtual touch trace in the group near the opposite side area is connected to the effective touch trace in the group, and the virtual touch trace is connected to the target electrode block through a second via penetrating the first insulating layer. The target electrode block is the electrode block connected to the effective touch trace in the group.

[0011] Optionally, both the first quantity and the second quantity are positive integers greater than 1. For any group, the first number of valid touch traces in the group are distributed at intervals along the second direction to form a valid trace group, and the second number of virtual touch traces are distributed at intervals along the second direction to form a virtual trace group. In the second direction, the valid trace group and the virtual trace group are distributed alternately in sequence, and the virtual touch traces in the virtual trace group are connected to at least one second signal pin of the driver chip.

[0012] Optionally, the bonding area is further provided with multiple second fan-out lines, each of which corresponds one-to-one with the multiple virtual touch traces. The end of any virtual touch trace near the bonding area extends to the bonding area and is connected to a second signal pin of the driver chip through the corresponding second fan-out line.

[0013] Optionally, the bound area is also provided with multiple second fan-out lines. Each of the virtual wiring groups corresponds to multiple second fan-out lines, and one second fan-out line is connected to at least two adjacent virtual touch wiring lines in the corresponding virtual wiring group.

[0014] Optionally, the touch substrate further includes a common signal line, which is disposed in the frame area and has a ring structure surrounding the display area, and the driver chip is connected to the common signal line.

[0015] Optionally, the display area further includes a gate layer, a gate insulating layer, an active layer, a pixel electrode layer, and a second insulating layer, wherein the gate layer, the gate insulating layer, the active layer, the pixel electrode layer, the source / drain electrode layer, the second insulating layer, the touch wiring layer, the first insulating layer, and the common electrode layer are stacked sequentially in a direction away from the substrate.

[0016] Based on the same inventive concept, a second aspect of this disclosure provides a touch display panel, including a touch substrate, a liquid crystal layer and an opposing substrate as described above, wherein the liquid crystal layer is disposed between the touch substrate and the opposing substrate.

[0017] Beneficial effects In this embodiment, the touch substrate connects the virtual touch traces to the second signal pin of the driver chip or to adjacent effective touch traces. This allows the virtual touch traces to no longer be all connected to the same Vcom bus, but instead obtain the same or basically equivalent driving capability as the effective touch traces. When the voltage jump on the data line pulls the Vcom voltage through the coupling capacitor, the Vcom of the effective touch traces and the virtual touch traces are pulled and their amplitude and speed tend to be consistent. This makes the common electrode voltage of the corresponding areas of the two types of traces uniform, avoiding uneven brightness caused by the difference in the common voltage of the area, and effectively improving the vertical stripe defect. Attached Figure Description

[0018] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0019] Figure 1 This is a schematic diagram illustrating the appearance of vertical stripes when a display panel shows a heavily loaded image in related technologies. Figure 2 This is a schematic diagram of the film layer distribution in the display panel of the 6Mask and 7Mask solutions in related technologies; Figure 3 This is a schematic diagram of the signal access method for touch traces in the 7Mask solution; Figure 4 The voltage waveforms of the effective touch traces and virtual touch traces under heavy load conditions; Figure 5 This is a schematic diagram of the touch trace distribution of an embodiment of the touch substrate provided in this disclosure; Figure 6 This is a schematic diagram of the film layer stacking structure of the touch substrate provided in this disclosure; Figure 7 This is a schematic diagram of the touch trace distribution of another embodiment of the touch substrate provided in this disclosure; Figure 8 This is a schematic diagram of the touch trace distribution of another embodiment of the touch substrate provided in this disclosure; Figure 9 This is a schematic diagram of the touch trace distribution of another embodiment of the touch substrate provided in this disclosure. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0021] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0022] In related technologies, display panels are typically manufactured using a 6-mask process. The film structure, starting from the substrate, sequentially includes: a gate layer, a gate insulating layer (GI), an active layer, and a first transparent conductive layer. st ITO (as pixel electrode layer PXL), source / drain electrode layer (SD), passivation layer (PVX), and second transparent conductive layer 2 nd ITO (as a common electrode layer COM), specifically as follows Figure 2 As shown in Figure (a), the common electrode layer is patterned into multiple touch electrode blocks, which also serve as touch sensing electrodes. The touch traces are separated from the data lines (Source lines) of the source and drain electrode layers within the display area. However, with the increase in product resolution and the growing demand for narrow bezels, the high resistivity of the ITO material used in the common electrode layer prevents further reduction in the linewidth of the touch traces to ensure the quality of touch signal transmission. This results in a large wiring area being occupied within the display area, limiting the improvement of the pixel aperture ratio. Simultaneously, in the fan-out area, the lower border bezel is difficult to further compress due to the limited space of the double-layer wiring.

[0023] To address the aforementioned issues, a 7-mask process solution has been proposed in related technologies. This solution adds a third metal layer, Metal3, to the 6-mask film structure. The touch traces are fabricated using the third metal layer, Metal3, and its film structure is as follows. Figure 2 As shown in Figure (b), in the 7MASK solution, touch traces and data lines are stacked within the display area. This frees up the light-shielding space occupied by touch traces in the traditional structure, effectively improving the pixel aperture ratio. Simultaneously, in the fan-out area, the fan-out traces are changed from traditional double-layer wiring to triple-layer metal stacked wiring, saving approximately one-third of the fan-out wiring space and providing a basis for compressing the bottom bezel. However, in actual image quality testing, the aforementioned display products using the 7MASK process exhibited issues under heavy loads. Figure 1 The image shows 17 equally spaced vertical stripes.

[0024] The inventors discovered through research that the cause of the vertical stripe defect is that in the 7MASK product, the touch traces include active touch traces (Tx traces) and dummy touch traces. Active touch traces are used to send and receive touch signals, while dummy touch traces are inactive traces that do not participate in the sending and receiving of touch signals. Furthermore, active touch traces and dummy touch traces use different signal access methods.

[0025] Specifically, in the display panel, along the horizontal direction X, the touch traces are distributed at intervals in the following manner: M effective touch traces L1 → N virtual touch traces L2 → M effective touch traces L1 → N virtual touch traces L2... A total of 306 virtual touch traces are distributed in 17 areas with N=18. It can be understood that this arrangement is for the sake of simplicity in the accompanying diagram. Figure 3 The diagram only schematically illustrates the arrangement of 5 active touch traces L1 to 4 virtual touch traces L2 to 5 active touch traces L1 to 4 virtual touch traces L2... and a 5×5 electrode block array. This does not represent the actual number of traces or electrode blocks. In the actual product, the traces are arranged as 32 active touch traces L1 to 18 virtual touch traces L2, and the 17 areas with virtual touch traces correspond exactly to the 17 vertical stripes under heavy load. Each active touch trace L1 is connected to the driver chip IC through an independent pin, and the driver chip IC directly provides the Vcom signal. All virtual touch traces are connected to a common signal line (Vcom bus) led out from the ET Pad, meaning that one Vcom bus carries all the virtual touch traces L2. The two types of touch trace signal access methods are different, resulting in differences in the driving capabilities of the effective touch trace L1 and the virtual touch trace L2. Furthermore, due to the overlapping wiring, there is a coupling capacitor between the touch trace and the data line. Under heavy screen load, the voltage jump on the data line pulls the Vcom voltage of the touch trace through the coupling capacitor.

[0026] The inventors selected heavy-load test screens with different load levels and used an oscilloscope to collect the common voltage of the effective touch traces and virtual touch traces within the panel in real time. Figure 4 The waveform comparison diagram shown illustrates the testing process, which selected heavy-load screens at 127 grayscale and 255 grayscale as operating conditions. Simultaneously, Vcom signals from the two types of touch traces were acquired to form four sets of comparison waveforms. Figure 4 It can be seen that under the same load, the effective touch trace can quickly recover to the initial voltage after being pulled, while the virtual touch trace recovers slowly after being pulled. The difference in voltage recovery speed and degree between the two leads to the Vcom voltage in the area where the virtual touch trace is located being inconsistent with the Vcom voltage in the area where the effective touch trace is located. This manifests macroscopically as a difference in brightness, i.e., vertical stripe defects.

[0027] Based on the above findings, this application provides a touch substrate, please refer to... Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the planar structure of the touch panel provided in this application. Figure 6 for Figure 5 A schematic diagram of the film layer distribution in the thickness direction of the display panel, as shown below. Figure 5 and Figure 6 As shown, the touch substrate includes a substrate 10, a display area AA disposed on the substrate, and a border area BB surrounding the display area AA. The display area AA includes: A source / drain electrode layer 11 is disposed on one side of the substrate 10, and the source / drain electrode layer 11 includes a plurality of data lines extending along a first direction D1; A touch trace layer 12 is disposed on the side of the source / drain electrode layer 11 away from the substrate 10. The touch trace layer 12 includes multiple effective touch traces 121 and multiple virtual touch traces 122 extending along a first direction D1. The effective touch traces 121 and the virtual touch traces 122 are arranged in a second direction D2. The orthographic projections of the effective touch traces 121 and the virtual touch traces 122 on the substrate at least partially overlap with the orthographic projections of the data lines on the substrate. The first insulating layer 13 is disposed on the side of the touch wiring layer 12 away from the substrate 10; A common electrode layer 14 is disposed on the side of the first insulating layer 13 away from the substrate 10. The common electrode layer 14 includes a plurality of electrode blocks 141 arranged in an array, wherein: The effective touch traces 121 correspond one-to-one with the electrode blocks 141. Each effective touch trace 121 is connected to the corresponding electrode block 141 through a first via H1 penetrating the first insulating layer 13. The multiple effective touch traces 121 are connected one-to-one with the multiple first signal pins of the driver chip 20. The virtual touch traces 122 are connected to the second signal pins of the driver chip 20 or to adjacent effective touch traces 121.

[0028] In this embodiment, within the plane of the substrate 10, the first direction D1 and the second direction D2 are perpendicular to each other. The first direction D1 is the length extension direction of the data lines and touch traces, and the second direction D2 is the side-by-side arrangement direction of the data lines and touch traces. The direction perpendicular to the plane of the substrate is the film layer stacking direction, that is, the thickness direction of each layer structure. For example, this embodiment describes the first direction D1 as the vertical direction Y and the second direction D2 as the horizontal direction X.

[0029] It is understood that insulating layers and other film layer structures for pixel driving may also be disposed between the various metal film layers. Optionally, the display area AA further includes a gate layer 15, a gate insulating layer 16, an active layer 17, a pixel electrode layer 18, and a second insulating layer 19. In the direction away from the substrate 10, the gate layer 15, gate insulating layer 16, active layer 17, pixel electrode layer 18, source / drain electrode layer 11, second insulating layer 19, touch wiring layer 12, first insulating layer 13, and common electrode layer 14 are stacked sequentially. The touch substrate of this embodiment is an improved design based on the 7Mask solution, which includes three metal layers, namely the gate layer 15, the source / drain electrode layer 11, and the touch wiring layer 12.

[0030] Specifically, the source / drain electrode layer 11 includes source / drain electrodes and multiple data lines extending along a first direction D1. These data lines are spaced apart along a second direction D2 and used to transmit pixel-driving data signals. The touch trace layer 12 is disposed on the side of the source / drain electrode layer 11 away from the substrate 10. It includes multiple effective touch traces 121 and multiple virtual touch traces 122 extending along the first direction D1. Both types of touch traces are arranged side-by-side along the second direction D2. In the stacking direction perpendicular to the substrate 10, the orthographic projections of the effective touch traces 121 and virtual touch traces 122 onto the substrate at least partially overlap with the orthographic projections of the data lines below. This indicates that the touch traces and data lines are spatially arranged in an overlapping configuration, separated by a second insulating layer 19, forming a parasitic capacitance. The transition data signals transmitted by the data lines are coupled to the upper touch traces through this parasitic capacitance, causing potential fluctuations in the touch traces.

[0031] The common electrode layer 14 includes multiple independent electrode blocks 141 arranged in an array. These electrode blocks 141 serve both as common electrodes to input a common voltage during the display phase and as touch electrodes to transmit touch signals during the touch phase. For example, in... Figure 5 In the illustrated embodiment, 5×5 electrode blocks 141 are schematically arranged along the horizontal direction X and the vertical direction Y. It can be understood that... Figure 5 For the sake of simplified illustration and understanding of the structure, in actual touch substrate products, the number of electrode blocks 141 needs to be matched with the panel resolution and the total number of touch channels, and the actual number is much larger than that. Figure 5 As shown, this application does not impose specific limitations on this.

[0032] Specifically, the common electrode layer 14 is divided into multiple electrode blocks 141, forming a self-capacitance touch structure. During the display phase, the electrode blocks 141 serve as common electrodes receiving a common voltage signal, and during the touch phase, they are reused as touch electrodes. Each electrode block 141 is connected to a corresponding effective touch trace 121 through a first via H1 penetrating the first insulating layer 13. The effective touch trace 121 extends to the bonding area DP and is connected one-to-one with the first signal pin of the driver chip 20 through a first fan-out line 31, allowing the driver chip 20 to independently access each electrode block 141. Based on this structure, this embodiment uses a self-capacitance detection principle to identify the touch position: the electrode block 141 has an inherent parasitic capacitance with ground. When a finger touches the location of an electrode block 141, a coupling capacitance is formed between the finger and the electrode block 141. This coupling capacitance is connected in parallel with the inherent parasitic capacitance of the electrode block 141, increasing the total capacitance of the electrode block 141 to ground. The driver chip 20 scans each electrode block 141 row by row and column by column, detecting the capacitance changes of each electrode block 141 sequentially. The capacitance increases significantly at the touch point, while the capacitance remains unchanged at non-touch points. Based on this, the driver chip 20 determines the horizontal and vertical coordinates and combines them to form the planar coordinates of the touch point. Since each electrode block 141 is connected to a first signal pin of the driver chip 20 through an independent first fan-out line 31 and an effective touch trace 121, the driver chip 20 can distinguish the capacitance changes of different electrode blocks 141 and accurately determine the touch position.

[0033] In this embodiment, the effective touch traces 121 and electrode blocks 141 are arranged in a one-to-one correspondence. This can be understood as follows: the number of effective touch traces 121 matches the number of electrode blocks 141. Each effective touch trace 121 corresponds to an independent electrode block 141 and is electrically connected to that electrode block 141 through a first via H1 at a corresponding position. Multiple effective touch traces 121 extend to the frame area BB and are connected one-to-one to multiple first signal pins of the driver chip 20. Each effective touch trace 121 serves as an independent touch channel, with the driver chip 20 independently outputting touch driving signals or acquiring touch sensing signals. For any given effective touch trace 121, multiple spaced first vias H1 can be provided along its length to connect to the corresponding electrode block 141.

[0034] To improve the vertical stripe defect, this application improves the connection method and arrangement of the virtual touch traces 122, which can be divided into two types of structures: The first type of structure: The virtual touch trace 122 extends to the bezel area BB and connects to the second signal pin of the driver chip 20. The driver chip 20 inputs a Vcom signal to the virtual touch trace 122 that is synchronized with and at the same potential as the active touch trace 121, replacing the traditional method of connecting all virtual touch traces 122 to a single Vcom bus. It should be noted that the first signal pin and the second signal pin are both general-purpose signal transmission pins of the driver chip 20 itself, and there is no essential difference between them in terms of hardware structure and signal transmission capability. The names "first" and "second" are used here only to identify the different traces connected to the pins, that is, the first signal pin corresponds to the active touch trace 121, and the second signal pin corresponds to the virtual touch trace 122, and does not limit the function of the pins.

[0035] In this structure, the virtual touch traces are directly connected to the independent second signal pin of the driver chip. The driver chip directly provides the Vcom signal, and the second signal pin of the driver chip independently drives one or a small number of virtual touch traces 122 connected to it. This prevents the driving capability of each virtual touch trace 122 from being spread out by a large number of traces, so that each virtual touch trace can obtain sufficient driving current. When the data line is pulled by coupling, the driver chip can provide sufficient charge compensation to the virtual touch trace 122 through the independent second signal pin, so that the Vcom voltage of the virtual touch trace can quickly recover to its initial value after being pulled. Its recovery speed and amplitude are consistent with those of the effective touch trace 121, so that the common electrode voltage in the area where the two are located is basically the same, the display brightness is uniform, and thus the vertical stripe defects are suppressed.

[0036] The second type of structure: the virtual touch trace 122 is directly electrically connected to the adjacent valid touch trace 121, so that the two are at the same potential, instead of the traditional solution that connects all virtual touch traces 122 to a single Vcom bus.

[0037] In this structure, the virtual touch trace 122 is directly electrically connected to the adjacent active touch trace 121, forming the same node electrically. The active touch trace 121 is independently driven by the driver chip 20 and has strong driving capability. The virtual touch trace 122 borrows the driving channel of the active touch trace 121 through this electrical connection and obtains a driving capability that is basically the same as that of the active touch trace 121. Since the active touch trace 121 and the virtual touch trace 122 are directly short-circuited electrically, their Vcom voltages remain consistent. When the data line is pulled by coupling, the driver chip 20 provides charge compensation to both the active touch trace 121 and the virtual touch trace 122 through the independent pin of the active touch trace 121. The two recover to the initial voltage together, and the recovery speed and amplitude are basically the same, which can effectively suppress vertical stripe defects caused by Vcom differences.

[0038] Compared with related technologies, the embodiments of this disclosure connect the virtual touch traces to the second signal pin of the driver chip, or to adjacent effective touch traces. This allows the virtual touch traces to no longer be all connected to the same Vcom bus, but to obtain the same or basically equivalent driving capability as the effective touch traces. When the voltage jump on the data line pulls the Vcom voltage through the coupling capacitor, the Vcom of the effective touch traces and the virtual touch traces are pulled and their amplitude and speed tend to be consistent. This makes the common electrode voltage of the corresponding areas of the two types of traces uniform, avoiding uneven brightness caused by the difference in the common voltage of the area, and effectively improving the vertical stripe defects.

[0039] Optionally, the effective touch traces 121 and the virtual touch traces 122 are periodically arranged in the second direction D2 in a manner that a first number N1 of effective touch traces 121 and a second number N2 of virtual touch traces 122 are grouped together, where the first number N1 and the second number N2 are both positive integers.

[0040] In some embodiments, N1=N2=1, in which case each group includes one active touch trace 121 and one virtual touch trace 122. In the second direction D2, the active touch trace 121 and the virtual touch trace 122 are alternately distributed, i.e., the overall arrangement is a periodic pattern of 121—122—121—122—121—122..., as detailed below. Figure 5 , Figure 7 As shown, an adjacent active touch trace 121 and a virtual touch trace 122 constitute a layout cycle, which can also be represented as a group.

[0041] In other embodiments, the first quantity N1 and the second quantity N2 are both positive integers greater than 1. The first quantity N1 and the second quantity N2 can be the same or different. In this case, on the second direction D2, the touch traces present a periodic arrangement of: (121,121,121...)—(122,122,122...)—(121,121,121...)—(122,122,122...)......, where each bracket includes N1 effective touch traces 121 or N2 virtual touch traces 122, as specifically... Figure 8 As shown, N1 adjacent active touch traces 121 and N2 virtual touch traces 122 constitute a layout cycle, which can also be represented as a group.

[0042] Optionally, the bezel area BB includes a bonding area DP and an opposite side area DPO located on opposite sides of the display area AA in the first direction. The bonding area DP is provided with multiple first fan-out lines 31 and the driver chip 20. The multiple first fan-out lines correspond one-to-one with the multiple effective touch traces 121. The end of any effective touch trace 121 near the bonding area DP extends to the bonding area DP and is connected to a first signal pin of the driver chip 20 through the corresponding first fan-out line 31.

[0043] Specifically, the border area BB includes the top border area located above the display area AA, the bottom border area located below the display area AA, the left border area located to the left of the display area AA, and the right border area located to the right of the display area AA. Figure 5 In the specific example shown, the first direction D1 is the vertical direction Y, the binding area DP is located in the lower border area, that is, the binding area DP is located below the display area AA, and the opposite side area DPO is located above the display area AA, that is, the upper border area.

[0044] The bonding area DP contains a driver chip 20 and multiple first fanout lines 31. Within the display panel, the fanout lines are conductive lines connecting the signal pins of the driver chip 20 to the signal traces within the display area AA. Specifically, the fanout lines act as spacing conversion and signal transfer between the driver chip 20 and the display area AA. One end of the fanout line is connected to the signal pin of the driver chip 20 with a smaller spacing, while the other end is connected to the signal traces within the display area AA with a larger spacing, thereby leading the signals from the driver chip 20 to the traces within the display area AA. In this embodiment, the first fanout lines 31 are used to connect the first signal pins of the driver chip 20 to the effective touch traces 121 within the display area AA.

[0045] Optionally, each group includes an active touch trace 121 and a virtual touch trace 122. In the second direction, the active touch trace 121 and the virtual touch trace 122 are alternately distributed. For any group, the virtual touch trace 122 in the group is connected to the active touch trace 121.

[0046] In this embodiment, along the horizontal direction X, the effective touch trace 121 and the virtual touch trace 122 are alternately arranged in a periodic pattern of 121-122-121-122-121-122..., that is, in two adjacent traces, one is the effective touch trace 121 and the other is the virtual touch trace 122, as detailed below. Figure 5 and Figure 7 As shown.

[0047] For any group, the virtual touch traces 122 in that group are directly connected to the active touch traces 121 in the same group, instead of connecting all virtual touch traces 122 to a single Vcom bus. This belongs to the second type of structure described above. Since the active touch traces 121 and virtual touch traces 122 are electrically short-circuited, their Vcom voltages are basically the same. When the data lines are coupled and pulled, they can both recover to the initial voltage. The recovery speed and amplitude are basically the same, which can effectively suppress vertical stripe defects caused by Vcom differences.

[0048] In some embodiments, for any group, the end of the virtual touch trace 122 in the group near the binding area DP extends to the binding area DP and is connected to the first fan-out line 31 corresponding to the effective touch trace 121 in the group.

[0049] For example, please refer to Figure 7 ,exist Figure 7 In the example shown, multiple first signal pins of the driver chip 20 are connected one-to-one with multiple first fan-out lines 31, each extending from the area where the driver chip 20 is located toward the display area AA. The end of the first fan-out line 31 near the display area AA is connected to an effective touch trace 121. In this embodiment, the effective touch trace 121 and the virtual touch trace 122 are arranged in a periodic alternation in the first direction (horizontal direction X), and each effective touch trace 121 and a virtual touch trace 122 are paired to form a group.

[0050] For any group, the virtual touch trace 122 within that group extends from the end near the binding area DP to the binding area DP and connects to the first fan-out line 31 corresponding to the valid touch trace 121 within that group. That is, the virtual touch trace 122 is not connected to an independent fan-out line, but is directly connected to the first fan-out line 31 of the valid touch trace 121 within the same group, thus achieving direct connection within the group. Specifically, as shown... Figure 7 As shown in position Q2. Each first signal pin independently outputs a Vcom signal, which is transmitted to the corresponding active touch trace 121 via the first fan-out line 31, and simultaneously transmitted to the virtual touch trace 122 in the same group via the connection point (e.g., via adapter structure) on the first fan-out line 31, so that the virtual touch trace 122 obtains the same Vcom potential as the active touch trace 121.

[0051] The wiring structure and signal access method provided in this embodiment can ensure that the Vcom signal on the virtual touch trace 122 is consistent with the Vcom signal on the effective touch trace 121, avoiding vertical stripes caused by inconsistent coupling. Furthermore, the virtual touch trace 122 does not need to be independently fanned out to the Vcom bus or connected one-to-one with multiple second signal pins of the driver chip 20, which helps to optimize the size of the driver chip and design a narrow bezel for the panel.

[0052] In some embodiments, for any group, the end of the virtual touch trace 122 in the group near the opposite side region DPO is connected to the effective touch trace 121 in the group. The virtual touch trace 122 is connected to the target electrode block through the second via H2 through the first insulating layer 13. The target electrode block is the electrode block 141 connected to the effective touch trace 121 in the group.

[0053] For example, such as Figure 5 As shown, in this embodiment, the active touch traces 121 and virtual touch traces 122 are arranged periodically and alternately in the second direction (horizontal direction X), with one active touch trace 121 paired with one virtual touch trace 122. Each active touch trace 121 and its adjacent virtual touch trace 122 form a group. For any group, the virtual touch traces 122 within that group are no longer connected to the Vcom bus, but are electrically connected to the active touch traces 121 within that group at the end near the opposite side area DPO within the display area AA, specifically as follows: Figure 5 As shown in position Q1. Specifically, the effective touch trace 121 and the virtual touch trace 122 are both located on the same touch trace layer. Their ends in the display area AA are directly shorted by the same layer of metal traces, without needing to extend to the DPO bezel area on the opposite side. This avoids the additional wiring space requirements caused by the traces crossing layers or going around.

[0054] Simultaneously, the virtual touch trace 122 is connected to the target electrode block through the second via H2 penetrating the first insulating layer 13. This target electrode block is the same electrode block 141 connected to the effective touch trace 121 within the same group. That is, the effective touch trace 121 is connected to the electrode block 141 through the first via H1, and the virtual touch trace 122 is connected to the same electrode block 141 through the second via H2. The two share the same electrode block through their respective independent vias.

[0055] It should be noted that in the traditional solution, the original function of the virtual touch trace 122 was to match the coupling capacitance between the effective touch trace 121 and other metal layers, so that the coupling capacitance load of the area where the effective touch trace 121 is located is consistent with that of the area where the virtual touch trace 122 is located. In this embodiment, after the virtual touch trace 122 is transformed into an actual effective driving trace through shorting and via connection, its physical structure remains unchanged, and it still maintains the overlapping relationship with the data line, that is, it still plays the physical role of matching the coupling capacitance. At the same time, since its driving method changes to share the same driving channel with the effective touch trace 121, its Vcom recovery speed and amplitude after being pulled by coupling tend to be consistent with those of the effective touch trace 121, thereby eliminating the vertical stripe defects caused by the difference in driving capability.

[0056] The wiring structure and signal access method provided in this embodiment do not require the use of additional pins of the driver chip 20. The virtual touch trace 122 and the effective touch trace 121 are shorted on the same layer in the display area AA, and do not need to extend to the opposite side area border, which is beneficial for narrow bezel design. At the same time, the virtual touch trace 122 and the effective touch trace 121 are connected to the same electrode block through the second via H2, which can effectively improve the vertical stripe defect.

[0057] Optionally, both the first quantity and the second quantity are positive integers greater than 1. For any group, the first number of effective touch traces 121 in the group are distributed at intervals along the second direction to form an effective trace group G1, and the second number of virtual touch traces 122 are distributed at intervals along the second direction to form a virtual trace group G2. In the second direction, the effective trace group G1 and the virtual trace group G2 are distributed alternately in sequence, and the virtual touch traces in the virtual trace group G2 are connected to at least one second signal pin of the driver chip 20.

[0058] like Figure 8 As shown, in this embodiment, the touch traces in the second direction D2 are arranged in a periodic pattern of G1—G2—G1—G2......, where G1 includes N1 effective touch traces 121, G2 includes N2 virtual touch traces 122, and adjacent G1 and G2 can be represented as a group.

[0059] For example, for a display panel with a resolution of 900×2000, N1=32, N2=18, and a total of 17 virtual trace groups G2 are included. For each virtual trace group G2, multiple virtual touch traces 122 contained in the virtual trace group G2 are connected to at least one second signal pin of the driver chip 20. It belongs to the first type of structure. In this structure, the virtual touch traces are directly connected to the independent second signal pin of the driver chip. The driver chip directly provides the Vcom signal. The second signal pin of the driver chip independently drives one or a small number of virtual touch traces 122 connected to it, so that the driving capability of each virtual touch trace 122 is no longer spread by a large number of traces, which can effectively suppress vertical stripe defects.

[0060] In some embodiments, the bonding area DP is further provided with a plurality of second fan-out lines 32, the plurality of second fan-out lines 32 corresponding one-to-one with the plurality of virtual touch traces 122, and any virtual touch trace 122 extending to the bonding area DP from the end near the bonding area DP and connected to a second signal pin of the driver chip 20 through the corresponding second fan-out line 32.

[0061] For example, please refer to Figure 9 In this embodiment, multiple second fan-out lines 32 are also provided within the bonding area DP, and each of the multiple second fan-out lines 32 corresponds one-to-one with a multiple virtual touch traces 122. The end of any virtual touch trace 122 closest to the bonding area DP extends into the bonding area DP and is connected to a second signal pin of the driver chip 20 via the corresponding second fan-out line 32. That is, each virtual touch trace 122 is provided with a Vcom signal independently by the driver chip 20, rather than all virtual touch traces 122 merging into a single common Vcom bus.

[0062] Specifically, the first signal pin and the second signal pin of the driver chip 20 independently output Vcom signals. The first signal pin provides a Vcom signal to the effective touch trace 121 via the first fan-out line 31, and the second signal pin provides a Vcom signal to the virtual touch trace 122 via the second fan-out line 32. Thus, the Vcom signal of the virtual touch trace 122 and the Vcom signal of the effective touch trace 121 have the same source, both being directly output by the driver chip 20, with consistent thrust and phase synchronization. There is no signal deviation introduced by the Vcom bus cross-layer routing or ET Pad. Each virtual touch trace 122 can obtain the same Vcom driving capability as the effective touch trace 121, except that the virtual touch trace 122 is not connected to the electrode block 141 within the display area AA and does not participate in touch detection.

[0063] The wiring structure and signal access method of this disclosure embodiment make the signal quality and thrust of the virtual touch trace the same as those of the effective touch trace, which can avoid vertical stripe defects from the source. At the same time, it does not need to rely on the ET Pad to introduce the common Vcom signal, reducing the wiring complexity and design difficulty of the panel bezel.

[0064] Optionally, the bound area DP is also provided with multiple second fan-out lines 32. Each of the virtual wiring groups G2 corresponds to multiple second fan-out lines 32. One second fan-out line 32 is connected to at least two adjacent virtual touch wiring lines 122 in the corresponding virtual wiring group.

[0065] In this embodiment, multiple second fan-out lines 32 are provided within the binding area DP. Each virtual routing group G2 corresponds to multiple second fan-out lines 32. Each second fan-out line 32 is connected to at least two adjacent virtual touch routing lines 122 within the corresponding virtual routing group G2. This can be understood as follows: the number of second fan-out lines 32 is greater than the number of virtual routing groups G2, but less than the total number of virtual routing lines 122. For example, if the total number of virtual touch routing lines is 306 and the total number of virtual routing groups G2 is 17, then the number of second fan-out lines 32 is greater than 17 and less than 306. In specific implementation, the virtual touch routing lines 122 within the same virtual routing group G2 are not individually led out one-to-one, but rather in batches, with multiple second fan-out lines 32 each carrying at least two adjacent virtual touch routing lines 122. For example, a second signal pin is connected to two or three virtual touch routing lines 122 through one second fan-out line 32.

[0066] For example, in Figure 8 In the illustrated embodiment, each virtual trace group G2 corresponds to two second-fan outgoing lines 32, and each second-fan outgoing line 32 is connected to three adjacent virtual touch traces 122. It is understood that in this embodiment... Figure 8 This is for illustrative purposes only and does not represent the actual number of effective touch traces 121, virtual touch traces 122, and second fan-out traces 32 in the actual product.

[0067] This configuration has several advantages. First, compared to the traditional method of consolidating all virtual touch traces into a single Vcom bus, the number of virtual touch traces carried by each second fan-out line 32 in this embodiment is limited, far less than the total number of virtual touch traces. This effectively reduces the load capacitance and resistance of a single second fan-out line, reduces the thrust and phase difference of the Vcom signal, and improves the signal consistency between virtual touch traces and active touch traces. Second, the number of second fan-out lines 32 is far less than the total number of virtual touch traces 122, effectively saving trace space in the bonding area and reducing the trace density in the fan-out area. This is beneficial for optimizing the size of the driver chip and designing a narrow bezel for the panel, and is especially suitable for scenarios with stringent requirements for bezel width and display uniformity in large-size, high-resolution touch products.

[0068] Optional, such as Figures 5 to 9 As shown, the touch substrate also includes a common signal line 40, which is disposed in the border area BB and is a ring structure surrounding the display area AA. The driver chip 20 is connected to the common signal line 40.

[0069] Specifically, the common signal line 40 surrounds the display area AA within the bezel area BB, and the common signal line 40 is connected to the driver chip 20, which provides the Vcom signal. The common signal line 40 is also the Vcom bus in the traditional solution.

[0070] In this embodiment, the common signal line 40 is no longer connected to the virtual touch trace 122, but it still needs to be retained as a ring-shaped shielding layer to form a stable shield between the GOA circuit in the border area and the display area AA, so as to isolate the coupling pull interference of the GOA circuit to the signal traces in the display area AA.

[0071] It should be noted that the number of effective touch traces 121 and virtual touch traces 122 shown in the accompanying drawings is merely a schematic representation of the embodiments of this application. Its purpose is to clearly demonstrate the arrangement, pairing method, and connection structure of the traces, and does not constitute any limitation on the actual number of traces. Those skilled in the art should understand that in actual products, the specific number of effective touch traces 121 and virtual touch traces 122 can be flexibly adjusted according to the resolution of the display panel, the number of touch channels, the bezel size, and process requirements. For example, 32 effective touch traces can be paired with 18 virtual touch traces, 36 effective touch traces can be paired with 20 virtual touch traces, or any other appropriate combination, as long as the periodic arrangement and signal connection relationship defined in this application are satisfied.

[0072] Based on the same inventive concept, this disclosure also provides a touch display panel, including a touch substrate, a liquid crystal layer and an opposing substrate as described above, wherein the liquid crystal layer is disposed between the touch substrate and the opposing substrate.

[0073] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A touch substrate, characterized in that, The display area includes a substrate, a display area disposed on the substrate, and a border area surrounding the display area. The display area includes: A source / drain electrode layer is disposed on one side of the substrate, and the source / drain electrode layer includes a plurality of data lines extending along a first direction; A touch trace layer is disposed on the side of the source / drain electrode layer away from the substrate. The touch trace layer includes multiple effective touch traces and multiple virtual touch traces extending along a first direction. The effective touch traces and the virtual touch traces are arranged in a second direction. The orthographic projections of the effective touch traces and the virtual touch traces on the substrate at least partially overlap with the orthographic projections of the data lines on the substrate. A first insulating layer is disposed on the side of the touch trace layer away from the substrate. A common electrode layer is disposed on the side of the first insulating layer away from the substrate. The common electrode layer includes a plurality of electrode blocks arranged in an array, wherein: Each effective touch trace corresponds to one of the electrode blocks. Each effective touch trace is connected to the corresponding electrode block through a first via penetrating the first insulating layer. The multiple effective touch traces are connected to multiple first signal pins of the driver chip. The virtual touch trace is connected to the second signal pin of the driver chip or to an adjacent effective touch trace.

2. The touch substrate according to claim 1, characterized in that, The effective touch traces and the virtual touch traces are arranged periodically in the second direction in a manner that a first number of effective touch traces and a second number of virtual touch traces are grouped together, where the first number and the second number are both positive integers.

3. The touch substrate according to claim 2, characterized in that, The frame area includes a binding area and an opposite area located on opposite sides of the display area in a first direction. The binding area is provided with multiple first fan-out lines and the driver chip. The multiple first fan-out lines correspond one-to-one with the multiple effective touch traces. The end of any effective touch trace near the binding area extends to the binding area and is connected to a first signal pin of the driver chip through the corresponding first fan-out line.

4. The touch substrate according to claim 3, characterized in that, Each group includes one active touch trace and one virtual touch trace. In the second direction, the active touch trace and the virtual touch trace are distributed alternately in sequence. For any group, the virtual touch trace in the group is connected to the active touch trace.

5. The touch substrate according to claim 4, characterized in that, For any group, the end of the virtual touch trace in the group that is close to the binding area extends into the binding area and connects to the first fan-out line corresponding to the valid touch trace in the group.

6. The touch substrate according to claim 5, characterized in that, For any group, the end of the virtual touch trace in the group that is close to the opposite side area is connected to the effective touch trace in the group. The virtual touch trace is connected to the target electrode block through a second via that penetrates the first insulating layer. The target electrode block is the electrode block that is connected to the effective touch trace in the group.

7. The touch substrate according to claim 2, characterized in that, Both the first quantity and the second quantity are positive integers greater than 1. For any group, the first quantity of effective touch traces in the group are distributed at intervals along the second direction to form an effective trace group, and the second quantity of virtual touch traces are distributed at intervals along the second direction to form a virtual trace group. In the second direction, the effective trace group and the virtual trace group are distributed alternately in sequence, and the virtual touch traces in the virtual trace group are connected to at least one second signal pin of the driver chip.

8. The touch substrate according to claim 7, characterized in that, The bonding area is also provided with multiple second fan-out lines, each of which corresponds one-to-one with the multiple virtual touch traces. The end of any virtual touch trace near the bonding area extends to the bonding area and is connected to a second signal pin of the driver chip through the corresponding second fan-out line.

9. The touch substrate according to claim 7, characterized in that, The bound area is also provided with multiple second fan-out lines. Each of the virtual wiring groups corresponds to multiple second fan-out lines. One second fan-out line is connected to at least two adjacent virtual touch wiring lines in the corresponding virtual wiring group.

10. The touch substrate according to claim 1, characterized in that, The touch substrate also includes a common signal line, which is disposed in the frame area and has a ring structure surrounding the display area. The driver chip is connected to the common signal line.

11. The touch substrate according to claim 1, characterized in that, The display area further includes a gate layer, a gate insulating layer, an active layer, a pixel electrode layer, and a second insulating layer. In the direction away from the substrate, the gate layer, gate insulating layer, active layer, pixel electrode layer, source / drain electrode layer, second insulating layer, touch wiring layer, first insulating layer, and common electrode layer are stacked sequentially.

12. A touch display panel, characterized in that, It includes a touch substrate, a liquid crystal layer, and an opposing substrate as described in any one of claims 1 to 11, wherein the liquid crystal layer is disposed between the touch substrate and the opposing substrate.

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