An embedded memory chip data storage method

Abstract

The application relates to the technical field of data storage, and discloses an embedded storage chip data storage method, which comprises the following steps: S1, performing data hierarchical management, performing multi-dimensional hierarchical storage on data according to the access frequency, access mode, life cycle and importance of the data; S2, performing intelligent wear leveling, dispersing read-write load through multi-level wear distribution, dynamic balancing and an adaptive prediction model; S3, performing adaptive compression and deduplication, selecting a compression mode according to data characteristics and removing duplicate data. Through intelligent hierarchical management, dynamic wear leveling, adaptive compression and deduplication, real-time data protection and low-power consumption management, the application improves the storage efficiency, data reliability and system energy efficiency of the embedded storage chip, prolongs the service life of the chip, optimizes the storage resource utilization rate, and ensures the data safety in the case of voltage abnormality or power failure.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, specifically to a data storage method for embedded memory chips. Background Technology

[0002] Currently, data storage methods using embedded memory chips are widely used in IoT devices, smart devices, and industrial automation. These methods primarily optimize data storage efficiency and stability through data tiering management, storage balancing, compression and deduplication, data protection, and low-power management.

[0003] Current memory chip data storage methods generally improve storage efficiency through static tiered management and fixed wear leveling strategies. Specifically, common storage methods include tiered storage based on data access frequency, distributing read / write loads using basic wear leveling algorithms, compressing data using simple compression algorithms, ensuring data security through periodic full backups, and reducing system power consumption under low load. These technologies can improve data access speed and storage resource utilization to a certain extent, while reducing chip wear and extending its lifespan.

[0004] However, existing storage methods still have shortcomings. First, traditional static hierarchical management and fixed wear leveling strategies are difficult to adapt to the frequent changes in data read and write operations in embedded systems, resulting in low storage efficiency, uneven wear distribution, and impact on chip lifespan. Second, existing compression and backup methods waste storage space and cannot guarantee data reliability when data is frequently updated. In addition, power management strategies fail to integrate with real-time loads, resulting in inefficient power management in high-energy-consuming scenarios and limiting system endurance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a data storage method for embedded memory chips, which solves the problems of low storage efficiency, uneven wear distribution, insufficient data reliability, and inflexible power management in existing technologies.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a data storage method for an embedded memory chip, comprising the following steps:

[0007] S1. Implement data hierarchical management, and store data in a multi-dimensional hierarchical manner based on data access frequency, access pattern, life cycle and importance;

[0008] S2. Perform intelligent wear leveling, which distributes read and write loads through multi-level wear allocation, dynamic balancing and adaptive prediction models;

[0009] S3. Perform adaptive compression and deduplication, selecting the compression method and removing duplicate data based on data characteristics;

[0010] S4. Implement dynamic data protection and self-recovery, and ensure data integrity through anomaly detection, multi-layer backup and snapshot management;

[0011] S5. Implement low-power hierarchical management, and optimize power consumption based on power prediction and adaptive adjustment.

[0012] Preferably, S1 includes:

[0013] Based on access frequency, the data is divided into three layers: high frequency, low frequency, and ultra-low frequency, and stored in high-speed, normal-speed, and low-speed areas respectively.

[0014] Based on access patterns, data is divided into three categories: write-heavy, read-heavy, and read-write balanced. Storage regions with matching characteristics are selected for different access patterns.

[0015] Based on the data lifecycle, data is divided into three categories: short lifecycle, medium lifecycle, and long lifecycle, and storage resources are allocated according to the lifecycle.

[0016] Based on the importance of the data, the data is divided into three categories: critical data, ordinary data, and alternative data. Critical data is preferentially stored in storage areas with high reliability and durability.

[0017] Preferably, S1 further includes:

[0018] Data is dynamically migrated, with high-frequency and critical data being prioritized for migration to high-speed areas;

[0019] Regularly clean up short-lived and alternative data to free up storage space and ensure the sustainability of data storage.

[0020] Preferably, S2 includes:

[0021] Set a local wear threshold, perform real-time read and write counts for each storage area, and start local balancing when the number of read and write operations in a certain area approaches the threshold, migrating hot data to low-frequency areas.

[0022] Periodically perform global load balancing, analyze the overall wear status of each region, and balance the read and write load of each storage unit;

[0023] In a multi-chip storage architecture, cross-chip migration is performed to distribute the storage load of a single chip and extend the overall lifespan of the chip.

[0024] Preferably, S2 further includes:

[0025] A deep learning prediction model is built based on historical read and write data to predict future hot spots and allocate wear leveling resources in advance.

[0026] Incremental backup is used to record only the changed parts of frequently updated data, thereby reducing the overall migration volume and avoiding excessive wear and tear.

[0027] Preferably, S3 includes:

[0028] Establish a compression algorithm library and select appropriate compression algorithms according to data type and characteristics. Text data uses Huffman coding, numerical data uses RLE coding, and image data uses LZW coding.

[0029] For large data blocks, a combined compression algorithm is used to perform multi-step compression in order to improve the compression ratio;

[0030] Data duplication is detected by hash matching, and duplicate data is stored as pointers to reduce storage space waste.

[0031] Preferably, S3 further includes:

[0032] The compression and deduplication frequencies are adjusted in real time according to the system load, increasing the frequency of compression and deduplication operations under low load and decreasing the frequency of operations under high load.

[0033] Incremental compression is used to record each data change in order to reduce repeated compression and optimize data storage.

[0034] Preferably, S4 includes:

[0035] The voltage is monitored in real time, and when an abnormal voltage is detected, data protection is immediately triggered, and the data being written is transferred to the cache.

[0036] Set up redundant backups for critical data, and ensure data recovery in the event of failure of any backup through dual backups;

[0037] Each time the system restarts, it performs a data integrity check using CRC or ECC, and restores the data from the backup if data corruption is detected.

[0038] Preferably, S4 further includes:

[0039] Regularly generate snapshots of frequently accessed data and save them in the snapshot area to ensure rapid recovery in case of data corruption;

[0040] Perform incremental backups of critical data, recording only the differences to reduce storage space usage.

[0041] Preferably, S5 includes:

[0042] Establish a power consumption prediction model, predict power consumption based on historical data access frequency and data characteristics, and dynamically adjust the power supply status of each partition.

[0043] The voltage of the memory chip is adaptively adjusted according to the load status. The voltage is reduced to save energy under low load and restored to normal voltage under high load.

[0044] For data areas that have not been accessed for a long time, a deep sleep mode is entered, and a wake-up period is set through a timer to ensure that access response is quickly restored when needed.

[0045] This invention provides a data storage method for embedded memory chips. It has the following beneficial effects:

[0046] 1. This invention provides multi-layered protection for data protection and recovery through real-time voltage monitoring, redundant backup, incremental backup, and snapshot mechanisms. It ensures safe recovery capabilities in the event of abnormal voltage, power outage, or data corruption, improves the reliability of data storage, and is suitable for applications with high data security requirements.

[0047] 2. This invention improves the storage efficiency and durability of embedded storage chips through multi-dimensional hierarchical management, intelligent wear leveling, adaptive compression and deduplication strategies. While ensuring data access speed, it extends the service life of storage chips and is suitable for embedded system scenarios with frequent data access, thereby improving the overall system performance.

[0048] 3. This invention combines a low-power hierarchical management strategy with a power prediction model, adaptive voltage regulation, and a deep sleep mechanism to reduce system power consumption and extend battery life, thereby achieving a dynamic balance between performance and energy consumption. It is particularly suitable for power-sensitive embedded devices and improves the system's energy efficiency ratio. Attached Figure Description

[0049] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0050] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Please see the appendix Figure 1 This invention provides a data storage method for an embedded memory chip, comprising the following steps:

[0052] S1. Implement data tiered management. Based on data access frequency, access pattern, lifecycle, and importance, data is stored in multi-dimensional tiers. This multi-dimensional tiered management strategy fully utilizes the characteristics of embedded storage chips, enabling fast reading of frequently accessed data and improving system response speed. Simultaneously, tiering by lifecycle effectively reduces storage space occupied by invalid data, improving storage resource utilization. Tiered storage based on data importance ensures the security and durability of critical data.

[0053] S2. Intelligent wear leveling is implemented. Through multi-level wear distribution, dynamic balancing and adaptive prediction models, the read and write load is distributed. Intelligent wear leveling effectively avoids the problem of excessive wear in local areas and ensures the service life of the memory chip. Through the synergistic effect of local and global balancing and deep learning prediction models, the long-term durability of the memory chip is achieved, thereby reducing the cost of maintaining and replacing the memory chip.

[0054] S3. Perform adaptive compression and deduplication. Select the compression method according to the data characteristics and remove duplicate data. Through the adaptive compression and deduplication mechanism, the utilization efficiency of storage space can be improved, the occupation of duplicate and invalid data can be reduced, and the storage density and data transmission speed of embedded storage can be improved. At the same time, the compression strategy ensures that the best compression effect is achieved under resource constraints, while the pointer reference mechanism reduces storage space waste and further optimizes the storage efficiency of the system.

[0055] S4. Implement dynamic data protection and self-recovery. Through anomaly detection, multi-layer backup, and snapshot management, data integrity is ensured. This multi-layer data protection and self-recovery mechanism ensures the data integrity and recovery capability of the system under power fluctuations, power outages, or other abnormal conditions, thereby improving data reliability. At the same time, through the combined application of redundant backup, snapshots, and incremental backup, this method improves the system's fault recovery capability without increasing storage space, ensuring stable system operation and reducing the risk of data loss.

[0056] S5. Implement low-power hierarchical management, optimize power consumption based on power prediction and adaptive adjustment. Low-power hierarchical management dynamically reduces system power consumption and extends device battery life through power prediction and partition adjustment. At the same time, partition management and deep sleep strategy reduce power consumption in idle storage areas. It is suitable for battery-powered embedded application scenarios such as IoT and sensors. Through adaptive adjustment of voltage and frequency, this method achieves low-power operation while ensuring data storage stability and also improves the system's energy efficiency ratio.

[0057] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S1 includes:

[0058] Based on access frequency, data is divided into three layers: high frequency, low frequency, and ultra-low frequency, and stored in high-speed, normal-speed, and low-speed areas respectively. Layered storage based on access frequency improves the system's response speed to high-frequency data, reduces the occupation of overall storage resources by high-frequency access, and effectively balances the system's storage speed and storage resource utilization.

[0059] Based on access patterns, data is divided into three categories: write-heavy, read-heavy, and read-write balanced. Storage regions with matching characteristics are selected for different access patterns. Tiered storage based on access patterns can avoid performance degradation caused by read-write conflicts. By matching the characteristics of different storage regions with data access patterns, the efficiency of data read and write and the durability of storage are effectively improved.

[0060] Based on the data lifecycle, data is divided into three categories: short lifecycle, medium lifecycle, and long lifecycle. Storage resources are allocated according to the lifecycle. The hierarchical strategy based on the data lifecycle enables efficient data management. By dynamically adjusting the storage location of data with different lifecycles, storage space waste is reduced. Short lifecycle data can be quickly cleared or updated after storage, freeing up storage space, while long lifecycle data is protected in the durability area, improving the resource utilization efficiency and data persistence of the storage system.

[0061] Based on data importance, data is divided into three categories: critical data, ordinary data, and alternative data. Critical data is preferentially stored in storage areas with high reliability and durability. This hierarchical approach based on data importance provides critical data with higher priority storage protection, preventing the loss of important data in the event of unexpected power outages or storage failures. Meanwhile, alternative data can be quickly cleaned up when storage space is insufficient, reducing the waste of storage resources and improving the system's ability to protect critical data.

[0062] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S1 further includes:

[0063] Data is dynamically migrated, prioritizing the migration of high-frequency and critical data to high-speed areas. This dynamic migration mechanism ensures that high-frequency and critical data can be accessed at the fastest speed, improving system response speed and data access efficiency. In addition, this mechanism effectively reduces the impact of uneven load distribution in storage areas, ensuring data security and stability.

[0064] Regularly cleaning up short-lifecycle and alternative data frees up storage space and ensures the sustainability of data storage. The regular cleaning mechanism effectively frees up storage space and avoids the waste of storage resources caused by short-lifecycle and alternative data occupying space for a long time, thereby ensuring the continuous and effective use of storage resources.

[0065] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S2 includes:

[0066] A local wear threshold is set, and read / write counts are performed in real time for each storage area. When the number of read / write operations in a certain area approaches the threshold, local balancing is initiated to migrate hot data to low-frequency areas. The local balancing mechanism can effectively prevent specific storage areas from being excessively worn due to frequent access, thus extending the lifespan of hot areas. By automatically monitoring the number of read / write operations and migrating data when the threshold is approached, wear and failure of local hot areas is avoided.

[0067] Global balancing is performed periodically to analyze the overall wear and tear of each region and balance the read and write load of each storage unit. During execution, the global balancing strategy uses a dynamic allocation algorithm based on the overall wear and tear of the storage chip to distribute some frequently accessed data to low-wear regions to balance the load of the storage units. This strategy combines the read and write performance of the storage chip with the data access frequency, ensuring both system response speed and slowing down the wear and tear of the entire chip.

[0068] In a multi-chip storage architecture, cross-chip migration is performed to distribute the storage load of a single chip and extend the overall lifespan of the chip. When performing cross-chip migration, the system will prioritize the migration of data blocks that have a smaller impact on the overall performance to ensure that the migration operation will not affect the normal operation of the system. At the same time, cross-chip migration will automatically adjust the storage allocation of each chip to make the system resources more rationally utilized and avoid performance bottlenecks or excessive wear of a single chip.

[0069] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S2 further includes:

[0070] Based on historical read and write data, a deep learning prediction model is built to predict future hot spots and allocate wear leveling resources in advance. First, the system monitors the read and write operations of the memory chip in real time, recording information such as the access frequency, data type, and read and write mode of each storage area to form a set of historical read and write datasets. Then, the dataset is used to train a deep learning model, such as a Long Short-Term Memory Network (LSTM) or a Convolutional Neural Network (CNN), to identify the time series patterns and spatial distribution characteristics of data access. This allows potential hot spots to be identified in advance and resource allocation to be adjusted in advance, avoiding the problem of accelerated local wear caused by concentrated access in hot spots.

[0071] Incremental backup is used to record only the changed parts of frequently updated data, thereby reducing the overall migration volume and avoiding excessive wear. Incremental backup reduces the number of writes to the storage area during the backup process, reducing storage wear on frequently updated data. At the same time, incremental backup only records the changed parts of the data, reducing the storage space required for backup and improving the system's backup efficiency. It is suitable for embedded system scenarios where data changes frequently.

[0072] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S3 includes:

[0073] A compression algorithm library is established to select the appropriate compression algorithm based on data type and characteristics. Huffman coding is used for text data, RLE coding for numerical data, and LZW coding for image data. The library includes various classic compression algorithms. For example, Huffman coding for text data uses character frequency to reduce storage space; RLE coding for numerical data compresses repeated values ​​into length markers, making it particularly suitable for compressing continuously repeating data; and LZW coding for image data replaces repetition patterns in the data stream with indices in a compression table, suitable for image data compression requirements. This allows the system to automatically select the most suitable compression algorithm based on data type. For instance, when text format is detected, the system will use Huffman coding from the library to compress the text data; if the data type is numeric and contains continuously repeating values, the system will use RLE for compression. Through this adaptive compression algorithm selection mechanism, different types of data can achieve optimal compression processing, effectively improving the data compression ratio.

[0074] For large data blocks, a combined compression algorithm is used for multi-step compression to improve the compression ratio. The implementation process of the combined compression algorithm is as follows: first, a primary compression algorithm is selected based on the characteristics of the data, and then other auxiliary compression algorithms are combined to perform multiple compressions on the data. For example, for a large data block containing text and numerical values, Huffman coding can be used to compress the text part first, and then RLE compression can be used for the numerical part. After the initial compression is completed, the system further applies the LZW algorithm for global compression to reduce repetitive patterns and residual redundant data, thereby improving the compression ratio of large data blocks and reducing the storage space occupied.

[0075] Based on hash matching to detect data duplication, duplicate data is stored in pointer mode to reduce storage space waste. The hash matching-based duplicate data detection and pointer storage mechanism effectively reduces the physical storage space of duplicate data, which is particularly suitable for data storage scenarios with high duplication rates. The pointer storage method not only saves storage space, but also reduces read and write operations of duplicate data, reduces wear and tear on storage units, effectively extends the lifespan of embedded storage chips, and improves the storage efficiency of the system.

[0076] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S3 further includes:

[0077] The system adjusts compression and deduplication frequencies in real time based on system load. It increases the frequency of compression and deduplication operations under low load and decreases them under high load. By monitoring real-time load information such as CPU utilization, memory usage, and data read / write frequency, the system establishes a load threshold. When the system load is below the threshold, it automatically increases the frequency of compression and deduplication operations, performing comprehensive compression and deduplication on new and redundant data to free up storage space. Conversely, when the system load is above the threshold, it reduces the frequency of compression and deduplication operations, preserving basic data storage functionality and prioritizing resources for critical tasks. By performing sufficient compression and deduplication operations under low load, the system maximizes storage space utilization; while reducing the frequency under high load ensures system real-time performance and responsiveness.

[0078] Incremental compression is used to record each data change, thereby reducing repeated compression and optimizing data storage. Incremental compression reduces storage space requirements, especially in frequently updated data blocks, avoiding duplicate storage and reducing the system's storage burden. By recording only the changed parts, incremental compression reduces storage space usage, lowers the frequency of storage and compression, and extends the lifespan of the storage chip.

[0079] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S4 includes:

[0080] This implementation integrates a voltage monitoring module into the embedded storage system to monitor the system voltage in real time. If the system detects a voltage drop below a safe threshold or abnormal fluctuations, it immediately triggers a data protection mechanism. In this case, the system prioritizes transferring the data being written from its current storage location to the cache to ensure data integrity and security. Data in the cache can continue to be written to the target storage area after the system voltage returns to normal, thus ensuring data continuity and consistency and improving the security and reliability of data storage.

[0081] Redundant backups are implemented for critical data, ensuring data recovery even if any backup fails. This dual-backup mechanism enables data recovery in the event of backup corruption or storage area failure, effectively improving the security of critical data. Through multi-layered data protection, this mechanism minimizes the risk of data corruption and loss, making it particularly suitable for important data requiring long-term storage. Dual backups provide robust protection for critical data, enhancing the reliability of embedded systems.

[0082] Each time the system restarts, the integrity of the data is checked by CRC or ECC. If data corruption is detected, the data is restored from the backup. The data integrity check and backup recovery mechanism provides complete detection and error correction functions for data storage. The automatic check and data restoration based on the check results each time the system restarts can prevent data loss or damage due to storage errors or external interference. This mechanism further improves the operational reliability of the embedded system and ensures the data security of the system in various environments.

[0083] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S4 further includes:

[0084] Regularly generate snapshots of frequently accessed data and save them in the snapshot area to ensure rapid recovery in case of data corruption. The snapshot mechanism can quickly restore the data to the latest valid state when the data is corrupted, reducing the time and resource consumption of data reconstruction, ensuring the continuous availability of high-frequency data, and effectively preventing the loss of high-frequency data due to sudden failures, thus providing a way to recover quickly.

[0085] Incremental backups of critical data record only the differences between the data to reduce storage space usage. By storing only the changed parts of the data, incremental backups reduce the storage space required for critical data backups and lower system resource consumption. Compared to traditional full backups, incremental backups reduce the number of storage writes, extend the lifespan of storage devices, ensure the reliability of critical data, and improve the backup efficiency of the system in environments with limited storage resources.

[0086] Please see the appendix Figure 1 In a preferred embodiment of the present invention, S5 includes:

[0087] A power consumption prediction model is established to predict power consumption based on historical data access frequency and data characteristics, and to dynamically adjust the power supply status of each partition. By identifying data access patterns in advance, the power consumption prediction model achieves more accurate power consumption management. This mechanism not only reduces the overall energy consumption of the system, but also improves the battery life of battery-powered devices.

[0088] The system adaptively adjusts the voltage of the memory chip based on the load status. It reduces the voltage to save energy under low load and restores the normal voltage under high load. By monitoring information such as CPU utilization, memory usage, and data read / write frequency in real time, the system determines the current load status. When the load is low, the system automatically reduces the voltage of the memory chip to reduce power consumption; when the system detects a high load, it restores the voltage to the normal level to ensure read / write speed and response efficiency. The voltage adjustment process is rapid and precise, ensuring that the system can adapt to voltage requirements in a timely manner when the load changes, maximizing power savings.

[0089] For data areas that have not been accessed for a long time, a deep sleep mode is entered. A wake-up period is set by a timer to ensure that the access response is quickly restored when needed. The deep sleep mechanism keeps the data areas that have not been accessed for a long time in a low power state, reducing the total power consumption and effectively extending the battery life of the embedded device. The introduction of the wake-up mechanism ensures that the data area can respond quickly when access is needed, avoiding data access delays caused by sleep.

[0090] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A data storage method for an embedded memory chip, characterized in that, Includes the following steps: S1. Implement data hierarchical management, and store data in a multi-dimensional hierarchical manner based on data access frequency, access pattern, life cycle and importance; S2. Perform intelligent wear leveling, which distributes read and write loads through multi-level wear allocation, dynamic balancing and adaptive prediction models; S3. Perform adaptive compression and deduplication, selecting the compression method and removing duplicate data based on data characteristics; S4. Implement dynamic data protection and self-recovery, and ensure data integrity through anomaly detection, multi-layer backup and snapshot management; S5. Implement low-power hierarchical management, and optimize power consumption based on power prediction and adaptive adjustment.

2. The embedded memory chip data storage method according to claim 1, characterized in that, S1 includes: Based on access frequency, the data is divided into three layers: high frequency, low frequency, and ultra-low frequency, and stored in high-speed, normal-speed, and low-speed areas respectively. Based on access patterns, data is divided into three categories: write-heavy, read-heavy, and read-write balanced. Storage regions with matching characteristics are selected for different access patterns. Based on the data lifecycle, data is divided into three categories: short lifecycle, medium lifecycle, and long lifecycle, and storage resources are allocated according to the lifecycle. Based on the importance of the data, the data is divided into three categories: critical data, ordinary data, and alternative data. Critical data is preferentially stored in storage areas with high reliability and durability.

3. The data storage method for an embedded memory chip according to claim 1, characterized in that, S1 further includes: Data is dynamically migrated, with high-frequency and critical data being prioritized for migration to high-speed areas; Regularly clean up short-lived and alternative data to free up storage space and ensure the sustainability of data storage.

4. The embedded memory chip data storage method according to claim 1, characterized in that, S2 includes: Set a local wear threshold, perform real-time read and write counts for each storage area, and start local balancing when the number of read and write operations in a certain area approaches the threshold, migrating hot data to low-frequency areas. Periodically perform global load balancing, analyze the overall wear status of each region, and balance the read and write load of each storage unit; In a multi-chip storage architecture, cross-chip migration is performed to distribute the storage load of a single chip and extend the overall lifespan of the chip.

5. The embedded memory chip data storage method according to claim 1, characterized in that, S2 further includes: A deep learning prediction model is built based on historical read and write data to predict future hot spots and allocate wear leveling resources in advance. Incremental backup is used to record only the changed parts of frequently updated data, thereby reducing the overall migration volume and avoiding excessive wear and tear.

6. The data storage method for an embedded memory chip according to claim 1, characterized in that, S3 includes: Establish a compression algorithm library and select appropriate compression algorithms according to data type and characteristics. Text data uses Huffman coding, numerical data uses RLE coding, and image data uses LZW coding. For large data blocks, a combined compression algorithm is used to perform multi-step compression in order to improve the compression ratio; Data duplication is detected by hash matching, and duplicate data is stored as pointers to reduce storage space waste.

7. The embedded memory chip data storage method according to claim 1, characterized in that, S3 further includes: The compression and deduplication frequencies are adjusted in real time according to the system load, increasing the frequency of compression and deduplication operations under low load and decreasing the frequency of operations under high load. Incremental compression is used to record each data change in order to reduce repeated compression and optimize data storage.

8. The embedded memory chip data storage method according to claim 1, characterized in that, S4 includes: The voltage is monitored in real time, and when an abnormal voltage is detected, data protection is immediately triggered, and the data being written is transferred to the cache. Set up redundant backups for critical data, and ensure data recovery in the event of failure of any backup through dual backups; Each time the system restarts, it performs a data integrity check using CRC or ECC, and restores the data from the backup if data corruption is detected.

9. The data storage method for an embedded memory chip according to claim 1, characterized in that, S4 further includes: Regularly generate snapshots of frequently accessed data and save them in the snapshot area to ensure rapid recovery in case of data corruption; Perform incremental backups of critical data, recording only the differences to reduce storage space usage.

10. The embedded memory chip data storage method according to claim 1, characterized in that, S5 includes: Establish a power consumption prediction model, predict power consumption based on historical data access frequency and data characteristics, and dynamically adjust the power supply status of each partition. The voltage of the memory chip is adaptively adjusted according to the load status. The voltage is reduced to save energy under low load and restored to normal voltage under high load. For data areas that have not been accessed for a long time, a deep sleep mode is entered, and a wake-up period is set through a timer to ensure that access response is quickly restored when needed.

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