Apparatus and operating method for protecting data in a pool memory system

Abstract

The disclosure relates to an apparatus and an operating method for protecting data in a pool memory system. The memory system can include a memory device configured to store data input with a data input / output (input / output) command or read stored data, and a controller configured to receive a data input / output command from at least one of a plurality of external devices and output a response corresponding to the data input / output command, store exchange data transmitted from a first external device among the plurality of external devices in the memory device, and block a write operation corresponding to a write command input from a second external device among the plurality of external devices with a same logical address as the exchange data.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2025-0049985, filed with the Korean Intellectual Property Office on April 17, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure described herein relate to a data storage device or memory system, and more specifically, to apparatus and methods of operation for protecting data in a shared or pooled memory system. Background Technology

[0004] Data processing systems, including memory systems or data storage devices, are constantly being developed to store more data in data storage devices, store data in data storage devices faster, and output data stored in data storage devices faster. These data processing systems may include multiple hosts and multiple data storage devices. Data storage devices may include non-volatile memory cells and / or volatile memory cells for storing data. Additionally, each memory cell may store multiple bits of data. Summary of the Invention

[0005] Embodiments of this disclosure may provide a memory device, a memory system including the memory device, a controller including the memory system, or a data processing apparatus including the memory system.

[0006] Embodiments of this disclosure can provide an apparatus and method for protecting exchanged data transmitted from a specific host to a memory system in an operating environment where multiple hosts can access the memory system.

[0007] A memory system according to embodiments of the present disclosure can provide an apparatus and method capable of receiving an identifier for exchange data from a host, inserting information for protecting the exchange data into mapping data of the exchange data stored in a memory device, and determining whether to execute the data input / output command based on the mapping data when receiving a data input / output command with the same logical address as the exchange data.

[0008] One embodiment of this disclosure may provide an apparatus and method capable of storing exchange data requested by a specific host in a memory device or memory system that can be shared and used by multiple hosts, and stopping, blocking, or preventing write operations when a host other than the respective host requests a corresponding write operation to change the exchange data.

[0009] In an embodiment, a memory system may include: a memory device configured to store data input along with data input and output (input / output) commands or to read stored data; and a controller configured to: receive data input / output commands from at least one of a plurality of external devices and output a response corresponding to the data input / output commands, store exchanged data transmitted from a first external device among the plurality of external devices in the memory device, and prevent write operations corresponding to write commands input from a second external device among the plurality of external devices along with the same logical address as the exchanged data.

[0010] The controller can be configured to receive a write command with a swap identifier from a first external device, which stores swap data in a memory device.

[0011] The controller can be configured to generate logical addresses and mapping data entries for physical or virtual addresses of exchanged data; and to add protection identifiers to the mapping data entries, the protection identifiers indicating that the data associated with the mapping data entries belongs to a protected area in the memory device.

[0012] The controller can be configured to: perform garbage collection or read recycling operations on the memory device; and maintain the protection identifier in the mapping data entry after performing garbage collection or read recycling operations on data belonging to the protected area and updating the mapping data entry associated with the data.

[0013] The controller can be configured to include an error code in the response corresponding to a write command entered from a first external device along with the same logical address; and to transmit the response to the first external device.

[0014] The controller can be configured to transfer exchange data to the first external device when a read command transmitted from the first external device is input along with the same logical address.

[0015] The controller can be configured to include a restriction code in the response corresponding to a read command entered from a second external device along with the same logical address; and to transmit the response to the second external device.

[0016] The controller can be configured to delete the mapped data entries of the swapped data based on a swap release command input from a first external device along with the same logical address.

[0017] The controller can be configured to include an error code in a response corresponding to an exchange release command entered from a second external device along with the same logical address; and to transmit the response to the second external device.

[0018] The memory device may include: a data storage area configured to store write data transferred from multiple external devices; and a switching area configured to store switch data different from the write data. The controller may be configured to: divide the data storage area and the switching area into different logical areas; and generate different mapping data for the data storage area and the switching area.

[0019] The memory device may include a plurality of volatile memory cells or a plurality of non-volatile memory cells, which are configured to store exchanged data.

[0020] In another embodiment, a data processing system may include: at least one host, including at least one application and a file system, configured to determine the storage location of write data generated by the at least one application based on the file system; and at least one memory system configured to receive exchange data from the at least one host, generate mapping data entries for the exchange data, and determine whether to access the exchange data based on the mapping data entries.

[0021] Mapped data entries may include the logical address for exchanging data and a protection identifier indicating access permissions to the logical address.

[0022] The protection identifier may include at least one of the following: an identifier indicating whether the relevant data is exchanged data; and unique information assigned to at least one host with access rights.

[0023] At least one host can be configured to restart when the logical address range used by at least one host changes. At least one memory system can be configured to: receive the changed range of logical addresses used by at least one host after the restart of at least one host; and apply the changed range to mapping data, which includes mapping data entries.

[0024] At least one host can be configured to transmit a write command, including a swap identifier, to at least one memory system, the write command being configured to store swap data in at least one memory system.

[0025] At least one memory system may include: a memory device configured to store or read data corresponding to data input and output (input / output) commands input from at least one host; and a controller configured to receive data input / output commands and output responses to the data input / output commands.

[0026] The controller can be configured to store exchanged data transferred from a first host among at least one host in a memory device; and to prevent write operations corresponding to a write command when a write command is input from a second host among at least one host along with the same logical address as the exchanged data.

[0027] The controller can be configured to include an error code in the response to a write command entered from the first host along with the same logical address; and to transmit that response to the first host.

[0028] The controller can be configured to transfer exchange data to the first host based on a read command transmitted from the first host along with the same logical address.

[0029] The controller can be configured to include a restriction code in the response corresponding to a read command entered from the second host along with the same logical address; and to transmit the response to the second host.

[0030] The controller can be configured to delete the mapped data entries of the swapped data based on a swap release command entered from the first host along with the same logical address.

[0031] The controller can be configured to include an error code in the response corresponding to an exchange release command entered from the second host along with the same logical address; and to transmit the response to the second host.

[0032] In another embodiment, a data processing system may include: at least one host comprising a plurality of virtual machines, each virtual machine configured to communicate with input and output (I / O) devices via different address ranges in a unified logical addressing scheme; and at least one memory system, serving as an I / O device, configured to store exchanged data transmitted from the at least one host. The at least one host may be configured to set the logical address of the exchanged data to be unavailable to the plurality of virtual machines in the unified logical addressing scheme.

[0033] In a data processing system, at least one of multiple virtual machines can run at least one application, and at least one application is configured to generate exchange data or specify write data as exchange data.

[0034] At least one memory system may include a remote storage space connected to at least one host via a network.

[0035] At least one host can be configured to: add an identifier indicating the exchange of data to the write command; and transmit the write command to at least one memory system. Attached Figure Description

[0036] This document is described with reference to the accompanying drawings, in which the same reference numerals denote the same parts throughout the drawings.

[0037] Figure 1 A data processing system according to an embodiment of the present disclosure is shown.

[0038] Figure 2 The configuration of a host and memory system according to an embodiment of the present disclosure is shown.

[0039] Figure 3 A swap operation according to an embodiment of this disclosure is illustrated.

[0040] Figure 4 The exchange operation of a data processing system according to an embodiment of this disclosure is illustrated.

[0041] Figure 5 A method for protecting exchanged data according to an embodiment of this disclosure is shown.

[0042] Figure 6 A method of operating a data processing system according to an embodiment of the present disclosure is shown.

[0043] Figure 7 This illustrates a data processing system where the exchange of data is unprotected.

[0044] Figure 8 A method of operating a data processing system according to an embodiment of the present disclosure is shown.

[0045] Figure 9 A method of operating a memory system according to an embodiment of the present disclosure is shown.

[0046] Figure 10 A write command according to an embodiment of this disclosure is shown.

[0047] Figure 11 Mapping data of a memory system according to an embodiment of this disclosure is shown.

[0048] Figure 12 A first operation of a shared memory device according to an embodiment of the present disclosure is shown.

[0049] Figure 13 A second operation of a shared memory device according to an embodiment of this disclosure is illustrated.

[0050] Figure 14 A data processing system according to an embodiment of the present disclosure is shown.

[0051] Figure 15 A memory system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0052] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The elements and features of the present disclosure may be configured or arranged in different ways to form other embodiments, which may be variations of any disclosed embodiment.

[0053] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiment.

[0054] In this disclosure, the terms “comprising,” “including,” “having,” and “containing” are open-ended. As used in the appended claims, these terms specify the presence of the said element but do not exclude the presence or addition of one or more other elements. Furthermore, the terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0055] In this disclosure, various units, circuits, or other components may be described or claimed to be "configured" to perform one or more tasks. In such a context, "configured" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when a block / unit / circuit / component is not currently running, e.g., not turned on or activated, it can be said that the specified block / unit / circuit / component is configured to perform a task. Blocks / units / circuits / components used with the language "configured" include hardware, such as circuits, memory storing program instructions operable to perform operations, etc. Additionally, "configured" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to operate in a manner capable of performing the relevant tasks. "Configured" may also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) suitable for performing or implementing one or more tasks.

[0056] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a purely hardware circuit implementation (e.g., an implementation of analog and / or digital circuitry only); and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) a processor / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit, such as a microprocessor or a portion thereof, that requires software or firmware to function, even if the software or firmware is not physically present. The definition of “circuit” or “logic” applies to all uses of the term in this application (including any claim). As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations of only one or more processors or a portion thereof and their accompanying software and / or firmware. The terms “circuit” or “logic” also cover integrated circuits, for example, for storage devices, if applicable to a particular claim element.

[0057] As used herein, the terms “first,” “second,” “third,” etc., used as labels preceding nouns do not indicate any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second. Furthermore, while these terms can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0058] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on these factors, or at least partially on them. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0059] In this document, a data entry, data item, or data term can be a bit sequence. For example, a data entry may include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to an embodiment, a data entry may include discrete objects. According to another embodiment, a data entry may include units of information processed or disposed of for data input / output operations. According to yet another embodiment, a data entry may include units of information within a data packet transmitted between two different components.

[0060] The embodiments described herein can provide an apparatus and method for improving data input / output operations of a memory system or data processing system. The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals indicate like elements.

[0061] Figure 1 A data processing system according to an embodiment of the present disclosure is shown.

[0062] Reference Figure 1 The data processing system may include multiple hosts (e.g., hosts 1 to 3) 300A, 300B, 300C and multiple memory systems (e.g., MS1 to MS2) 210A, 210B. The multiple hosts 300A, 300B, 300C and the multiple memory systems 210A, 210B can communicate data according to a preset method. According to an embodiment, the multiple hosts 300A, 300B, 300C and the multiple memory systems 210A, 210B can support not only 1:1 data communication but also 1:N data communication (where N is a natural number greater than or equal to 2). The following will refer to... Figure 2 Describe the internal configuration of multiple host systems 300A, 300B, 300C and multiple memory systems 210A, 210B.

[0063] According to an embodiment, multiple memory systems 210A and 210B can constitute a data infrastructure. Here, data infrastructure refers to a digital infrastructure that facilitates data sharing and consumption. Like other infrastructures, data infrastructure can include the structures, services, and facilities required for data sharing and consumption. For example, data infrastructure can include various components, including hardware, software, networks, services, policies, etc., to enable data consumption, storage, and sharing. Data infrastructure can provide or support the foundation for data generation, management, use, and protection.

[0064] For example, data infrastructure can be divided into physical infrastructure, information infrastructure, and business infrastructure. Physical infrastructure can include data storage devices, data processing devices, input / output networks, data sensor facilities, etc. Information infrastructure can include cloud resources and services, such as business applications, data repositories (e.g., databases and data warehouses), virtualization systems, and virtual services. Business infrastructure can include business intelligence (BI) systems and analytics tools, such as big data, artificial intelligence (AI), and machine learning (ML).

[0065] According to an embodiment, multiple hosts 300A, 300B, 300C and multiple memory systems 210A, 210B can communicate data via an interface based on Compute Fast Link (CXL) or a CXL-based protocol supporting memory pooling and memory sharing. A memory pool allows multiple hosts 300A, 300B, 300C in a heterogeneous topology to access a common memory address range. Each host can allocate a non-overlapping address range from the memory resource pool. Through the memory pool, data infrastructure or data processing devices can dynamically allocate memory within the pool, thereby reducing memory waste and improving memory utilization. CXL-based interfaces or protocols can provide effects such as efficient memory allocation, guaranteed memory access, memory isolation between multiple hosts or processors, and data or system security.

[0066] On the other hand, memory sharing allows multiple hosts 300A, 300B, and 300C in a heterogeneous topology to access a common memory address range, with each host and other hosts being allocated the same address range. Since multiple hosts 300A, 300B, and 300C can access the same data, data flow can be executed efficiently. However, the data infrastructure or data processing device must manage consistency between hosts to avoid or prevent data from being erroneously overwritten by other hosts. CXL-based interfaces or protocols can provide efficient data communication, low latency, and low power consumption between multiple hosts or processors.

[0067] Figure 2 The configuration of a host and memory system according to an embodiment of the present disclosure is shown.

[0068] Reference Figure 2 The host 300 can communicate with the storage system 210. Multiple virtual machines (VMs) 340 and 350 can operate on or within the host 300.

[0069] Host 300 may include at least one application 380. Application 380 may run on host operating system 320 or through multiple virtual machines 340 and 350. According to an embodiment, application 380 may include software programs used by a user to perform specific tasks. Application 380 may perform multiple tasks and generate data based on the tasks being performed. Data generated and requested by application 380 in relation to data storage may be transferred to and stored in memory system 210.

[0070] Host 300 may include host machine 310 and host operating system 320, and multiple virtual machines (VMs) 340 and 350 may operate on or within host operating system 320. Host machine 310 may include physical computing devices for running virtual machines. For example, host machine 310 may include multiple hardware-related components (e.g., processor, memory, storage devices, etc.). Host machine 310 may have the ability to run multiple virtual machines 340 and 350 simultaneously, and resources may be allocated to multiple virtual machines 340 and 350 through virtualization software (e.g., hypervisor 330).

[0071] The host operating system (OS) 320 may include an operating system running on the host machine 310. The host operating system 320 can interact directly with the host machine 310 (which is physical hardware) and can provide an installation environment for the hypervisor 330. The host operating system 320 can manage multiple virtual machines 340 and 350 and allocate the resources required by the multiple virtual machines 340 and 350.

[0072] The hypervisor 330 can serve as an interface between the host machine 310 (which is physical hardware) and multiple virtual machines 340, 350. According to embodiments of this disclosure, it can be implemented using two main types of hypervisors 330. Type 1 hypervisors (e.g., VMware ESXi, Microsoft Hyper-V) can run directly on the host machine 310 (which is physical hardware) and can manage multiple virtual machines 340, 350. On the other hand, Type 2 hypervisors (e.g., VMware Workstation, Oracle VirtualBox) can run on the host operating system 320 and can support multiple virtual machines 340, 350 on the host operating system 320.

[0073] Multiple virtual machines 340 and 350 can be associated with independent computer environments provided by the hardware of virtualization host machine 310. Each of the multiple virtual machines 340 and 350 can run its own operating system 342 and 352, and run applications on its own operating system 342 and 352. The multiple virtual machines 340 and 350 can share the resources of host machine 310, but operate independently of each other. Therefore, problems or failures occurring in the first virtual machine 340 may not affect the second virtual machine 350.

[0074] Each of the multiple virtual machines 340 and 350 may include an operating system 342 or 352, a kernel 344 or 354, and a file system 346 or 356. The operating systems 342 and 352 within the multiple virtual machines 340 and 350 may include software that enables the virtual machines (340, 350) to operate independently. The operating systems 342 and 352 can function to allow users to run applications, manage hardware resources, and handle interactions between users and the host system 300. The operating systems 342 and 352 within the multiple virtual machines 340 and 350 do not directly use the hardware of the host machine 310, but rather use virtualization resources through the hypervisor 330. Therefore, the operating systems 342 and 352 within the multiple virtual machines 340 and 350 can operate independently of the host operating system 320.

[0075] Cores 344 and 354 can manage or control the interaction between hardware and software. Cores 344 and 354 can perform basic system functions such as memory management, process management, and device management. According to embodiments, cores 344 and 354 can be considered components of operating systems 342 and 352. Cores 344 and 354 within multiple virtual machines 340 and 350 can manage virtualization hardware resources and allocate resources requested by the multiple virtual machines 340 and 350. Cores 344 and 354 may have a significant impact on the performance and stability of the multiple virtual machines 340 and 350.

[0076] File systems 346 and 356 may include software that defines how data is stored and managed. File systems 346 and 356 can support operations such as creating, deleting, reading, and writing files and directories. File systems 346 and 356 in multiple virtual machines 340 and 350 can be stored in a virtual disk image file, which can be located on a physical storage device (e.g., host memory) via the host machine 310. Multiple virtual machines 340 and 350 can manage data through file systems 346 and 356 and enable applications to access necessary files.

[0077] According to an embodiment, multiple virtual machines 340 and 350 can be configured as containers. These containers can perform the functions that the multiple virtual machines 340 and 350 can perform, but they differ structurally from the multiple virtual machines 340 and 350. The biggest difference between the multiple virtual machines 340 and 350 and containers lies in the presence or absence of kernels. The multiple virtual machines 340 and 350 may include independent kernels 344 and 354, different from the host machine 310 and the host operating system 320, while containers use the kernels included in the host operating system 320.

[0078] Cores 344 and 354 may include the lowest-level operating system software that interfaces with the computing device. Cores 344 and 354 can act as an intermediary between the host 300 (e.g., the computing device) and the operating systems 342 and 352, and the host machine 310. The host machine 310 can interact so that processes (called services and servers) can exchange information using inter-process communication (IPC). Cores 344 and 354 can handle disk I / O operations, network traffic, and storage. Because multiple virtual machines 340 and 350 may include separate cores 344 and 354, instead of using the cores of the host operating system 320, multiple virtual machines 340 and 350 can run operating systems 342 and 352 that are different from the host operating system 320. Furthermore, multiple virtual machines 340 and 350 may include their own virtual file systems 346 and 356, which are decoupled from the host machine 310 and the host operating system 320, while containers can use file systems that interface with the host machine 310 and the host operating system 320.

[0079] Reference Figure 2 The memory system 210 may include a storage device 250 with non-volatile memory cells, and the host 300 may include a file system for storing and managing data in the non-volatile memory device. For example, the host 300 may include a flash-friendly file system (F2FS), a file system specifically designed for flash memory-based storage devices. The design of F2FS can take into account the characteristics of flash memory. Unlike volatile memories such as static random access memory (SRAM) and dynamic random access memory (DRAM), write and erase operations on flash memory can be limited. F2FS can efficiently manage data programming and erasing by reflecting the characteristics of flash memory.

[0080] F2FS is a journaling file system (LFS) that improves write performance by continuously recording data and metadata. Specifically, F2FS maximizes performance by leveraging the page-based write method of flash memory. The journaling file system (LFS) is designed to record data in a journal so that all file changes are recorded sequentially in the journal. This approach minimizes random access to the storage system 210 and improves performance through continuous writes. Unlike other file systems, the journaling file system (LFS) can operate by adding data to new locations when storing data in the storage system 210. Therefore, considering the limitations of flash memory in terms of overwrite writes, the journaling file system (LFS) can support the storage system 210 to perform write operations quickly.

[0081] F2FS can be configured to periodically organize unused blocks through garbage collection, and through this operation, efficiently manage storage space, thereby helping to extend the lifespan of the flash memory included in the storage system 210. When unused blocks accumulate as data is recorded in the log, the Log-structured File System (LFS) can organize these unused blocks through garbage collection, ensuring space or regions are available for writing new or other data. For example, F2FS can support operations such as garbage collection or slack space recycling.

[0082] F2FS is a journaling file system (LFS) with a journaling structure. Even if the storage system 210 suddenly stops, it can be easily restored to the last recorded state through the stored journal. Therefore, the journaling file system (LFS) can improve data integrity. According to embodiments, journaling file systems (LFS) such as F2FS can be integrated into the Linux kernel and used on mobile platforms such as the Android operating system.

[0083] Journaling File System (LFS) offers several advantages over other file systems, primarily in environments with frequent write operations, and can be used in database systems or high-performance servers. Because LFS records file system data in a journaling format, operations can be performed to improve write performance and reduce disk fragmentation. For example, LFS can perform LFS cleaning, hole-plugging, and idle space reclamation to improve efficiency and optimize storage space.

[0084] Reference Figure 2 The memory system 210 may include a memory device 250. The host 300 may utilize the memory device 250, which includes non-volatile memory cells, in the memory system 210 to store and retrieve stored data. For example, the memory device 250 may include at least one of all types of non-volatile memory such as magnetic RAM (MRAM), NAND, NOR, and hard disk drive (HDD). In the following description, for simplicity and illustrative purposes, the memory device 250 is described as non-volatile memory (NVM).

[0085] On the other hand, host 300 may include host memory 370. According to an embodiment, host memory 370 may be one of the components or elements included in host 310. Application 380, host operating system 320, and virtual machines 340, 350 may generate necessary data and store the generated data in host memory 370 for later use. For example, host memory 370 may include main memory, operating memory, buffer memory, or cache memory included in host 300. Host memory 370 may include volatile memory, such as DRAM or SRAM.

[0086] The host memory 370 can be accessed by the host machine 310 through a memory access interface. For example, the host central processing unit (CPU) can directly access physical addresses through the memory controller in the host machine 310, and can quickly access physical addresses using instructions such as load / store (e.g., MOV, LDR, STR, etc.). Additionally, the host machine 310 can directly access the host memory 370 in bytes. According to embodiments, for virtual machines 340 and 350, virtual memory address translation can be performed through the memory management unit (MMU) to access the host memory 370.

[0087] Host memory 370 can be configured to respond quickly to requests from application 380, host operating system 320, and virtual machines 340 and 350. Furthermore, as the operations of application 380, host operating system 320, and virtual machines 340 and 350 become increasingly complex, the amount of data that application 380, host operating system 320, and virtual machines 340 and 350 need to store in host memory 370 will also increase. If host memory 370 is unable to store the data required by application 380, host operating system 320, and virtual machines 340 and 350, host 300 can perform a swapping operation and use memory system 210 as swap memory. Swapping memory can refer to the space created by using storage devices (e.g., memory system 210) to replace insufficient storage space when host memory 370 is full but more storage space is needed. The swapping operation will be described later. Figures 3 to 11 Describe it.

[0088] According to an embodiment, the host 300 may include an input / output (I / O) controller 360. The I / O controller 360 is a hardware device for handling communication between the CPU or processor included in the host 310 and various input / output (I / O) devices connected to or linked to the host 300, and for performing functions such as controlling and adjusting the timing of the input / output (I / O) devices and exchanging data with the host 310. The input / output (I / O) devices may include a memory system 210.

[0089] In some cases, due to the variety of input / output (I / O) devices and their different control methods, the I / O devices may not be able to be directly connected to the host machine 310 via the system bus within the host machine 300. Since the host machine 310 includes multiple circuits for controlling the I / O devices, which is inefficient, an input / output controller 360 may be used or included. Furthermore, since the operating speed of the host machine 310 differs from the operating speed of the I / O devices, the input / output controller 360 may perform a relay function. Additionally, since the size and length of the data exchanged during data communication between the host machine 310 and the I / O devices may differ, the input / output controller 360 may perform an interface function.

[0090] According to an embodiment, the input / output controller 360 can adjust the timing of control and communication with input / output (I / O) devices, perform communication with the host 310 and the input / output (I / O) devices, perform data buffering functions, or detect errors in transmitted data. Examples of the input / output controller 360 may include an I / O controller hub (ICH) for managing data communication between the central processing unit (CPU) and the motherboard, a Universal Serial Bus (USB) host controller for performing communication between a USB device and the host, a High-Speed ​​PCI (PCIe) host controller for performing communication between a PCIe device and the host, and a SATA host controller for performing communication between a Serial Advanced Technology Attached (SATA) device and the host.

[0091] Reference Figure 1 and Figure 2 The data processing apparatus may include multiple storage devices, such as memory system 210. For example, data processing apparatus 200 may include multiple memory systems 210 configured as a redundant array of independent disks (RAID), which together serve as a large-capacity storage device for host 300. Furthermore, according to embodiments, the data processing apparatus may include multiple computing devices, such as host 300. For example, the data processing apparatus may include memory system 210 configured as a shared memory device so that multiple computing devices (e.g., host 300) can use the memory system for data storage and retrieval.

[0092] The data processing apparatus may include a host 300 capable of storing and / or retrieving data in one or more storage devices (e.g., memory system 210). Figure 1As shown, host 300 can communicate with memory system 210 via host interface (I / F) 220. Host 300 may include various devices, including mobile electronic devices (e.g., automobiles), electronic devices (e.g., mobile phones or MP3 players), computer servers, network attached storage (NAS) devices, desktop computers, laptops, tablet computers, set-top boxes, telephones (e.g., "smartphones"), "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc.

[0093] The memory system 210 may include a controller 230, a memory device 250, and a host interface 220. The controller 230 may include a flash translation layer (FTL) 234. The FTL 234 can translate logical addresses into physical addresses to support data input / output operations. The FTL 234 can generate mapped data (e.g., L2P, P2L). Depending on the operating state, the FTL 234 can control or perform operations such as garbage collection, read retries, and wear leveling. The controller 230 and the FTL 234 may use at least one memory included in, coupled to, or linked to the controller 230. For example, at least one memory may include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0094] According to an embodiment, the memory system 210 may include Figure 2 Additional components are not shown for clarity. For example, memory system 210 may include a printed circuit board (PCB) including conductive lines, etc., to which components of memory system 210 are mechanically attached, and which electrically interconnect the components of memory system 210. In some examples, the physical dimensions and connector configuration of memory system 210 may conform to one or more standard form factors. For example, standard form factors may include, but are not limited to, 2.5-inch data storage devices (e.g., HDDs or solid-state drives (SSDs)), 1.8-inch data storage devices, peripheral component interconnects (PCI), PCI expansion (PCI-X), and high-speed PCI (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini cards, mini PCI, etc.). According to embodiments, memory system 210 may be directly connected (e.g., directly soldered) to the motherboard of host 300.

[0095] The host interface 220 of the memory system 210 may include one or both of a data bus for exchanging data with the host 300 and a control bus for exchanging commands with the host 300. The host interface 220 may operate according to any suitable protocol. For example, the host interface 220 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Universal Serial Bus (USB), Multimedia Card (MMC), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), PCI, PCIe, High-Speed ​​Non-Volatile Memory (NVMe), OpenCAPI, GenZ, Cache Coherence Interface Accelerator (CCIX), Compute Fast Link (CXL), Open Channel Solid State Drive (Open Channel SSD, OCSSD), or similar protocols. Electrical connections (e.g., a data bus, a control bus, or both) to the host interface 220 may be electrically connected to the controller 230 to provide an electrical connection between the host 300 and the controller 230, thereby enabling data exchange between the host 300 and the controller 230. According to an embodiment, the electrical connections to the host interface 220 may allow the memory system 210 to receive power from the host 300. For example, power-dependent devices of the memory system 210 may receive power from the host 300 via the host interface 220.

[0096] The memory system 210 may include a memory device 250, which includes multiple data storage areas. According to embodiments, the memory device 250 may be configured to store and / or retrieve data. For example, a memory die or memory chip included in the memory device 250 may receive data from a controller 230, as well as messages or commands instructing the memory device to store data. Similarly, a memory die or memory chip included in the memory device 250 may receive messages from the controller 230 instructing the memory device to retrieve data. According to embodiments, the memory die or memory chip included in the memory device 250 may be configured to store relatively large amounts of data (e.g., 128MB, 256MB, 412MB, 1GB, 2GB, 3GB, 8GB, 16GB, 22GB, 54GB, 128GB, 256GB, 412GB, 1TB, etc.).

[0097] According to embodiments, memory device 250 may include any type of non-volatile memory device, such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable ROM (EPROM), electrically erasable ROM (EEPROM), phase-change RAM (PRAM), magnetic RAM (MRAM), NAND or NOR flash memory, phase-change random access memory (PCRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), spin-transfer torque magnetic random access memory (STT-MRAM), holographic memory device, hard disk drive (HDD), and any other type of non-volatile memory device.

[0098] According to an embodiment, memory device 250 may include multiple flash memory devices. The flash memory devices may include NAND-based or NOR-based flash memory devices and may store data based on the amount of charge contained in the floating gate of the transistor in each flash memory cell. In a NAND flash memory device, the flash memory device may be divided into multiple blocks, and each block may be divided into multiple pages. Each block in a particular memory device may include multiple NAND cells. Rows of NAND cells may be electrically connected using word lines to create multiple pages. Each cell in each of the multiple pages may be electrically connected to a corresponding bit line. Additionally, the NAND flash memory device may be a 2D or 3D device. The flash memory device may include single-layer cell (SLC), multi-layer cell (MLC), three-layer cell (TLC), four-layer cell (QLC), or higher-layer cells. Controller 230 may write data to and read data from the NAND flash memory device at the page level and may erase data stored in the NAND flash memory device at the block level.

[0099] A portion of the memory device 250 can be formatted into logical blocks, partitions, or regions, thereby dividing the storage capacity of the memory device 250 into multiple streams. Each stream may include multiple physical blocks or multiple erase blocks of the memory device 250. Each physical block may be associated with multiple logical blocks. Each logical block may be associated with a unique Logical Block Address (LBA) or sector. The size of each stream can be adjusted according to the storage capacity of one or more physical blocks of the memory device 250. When the controller 230 receives a command from, for example, the host 300, the controller 230 can read data from and write data to the multiple logical blocks associated with the multiple physical blocks of the memory device 250.

[0100] The memory system 210 may include a power supply circuit configured to provide power to at least one component. When operating in a standard or normal mode, the power supply circuit can use power supplied by an external device (e.g., host 300) to power one or more components. For example, the power supply circuit can use power received from host 300 via host interface 220 to power one or more components. According to an embodiment, the power supply circuit may include one or more power auxiliary devices configured to supply power to one or more components when operating in a shutdown mode (e.g., when power input from an external device is interrupted). Examples of power auxiliary devices may include, but are not limited to, capacitors, supercapacitors, batteries, etc. According to an embodiment, the amount of electricity that one or more power storage components can store may correspond to the cost and / or size (e.g., area / volume) of one or more power storage components. As the amount of electricity stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0101] The memory system 210 may also include a volatile memory device that the controller 230 may use to temporarily store data or information. The volatile memory device may include one or more volatile memories. For example, the controller 230 may use the volatile memory as a cache. The controller 230 may store cached data or information in the volatile memory until the cached data or information is completely written to the memory device 250. Examples of volatile memory may include, but are not limited to, RAM, DRAM, SRAM, and SDRAM (e.g., Double Data Rate 1 (DDR1), DDR2, DDR3, Low Voltage Double Data Rate 3 (DDR3L), Low Power Double Data Rate 3 (LPDDR3), DDR4, LPDDR4, DDR5, LPDDR5, etc.).

[0102] Different types of volatile memory can be used based on different access characteristics. For example, DRAM can be arranged for longer burst accesses to allow for increased bandwidth on the same access bus. Alternatively, DRAM can be used for smaller accesses, resulting in better latency for random small accesses. Controller 230 may include additional optional SRAM and / or embedded MRAM. Embedded MRAM is another alternative memory that can be used in other embodiments. Similarly, while access to MRAM can be optimized for various design purposes, the amount of embedded MRAM in controller 230 may be cost-sensitive. Therefore, system trade-offs will influence the choice of how much data and which data is placed in advanced non-volatile memory and advanced volatile memory.

[0103] A controller 230 within the memory system 210 can manage one or more operations of the memory system 210. For example, the controller 230 may include multiple pipelines for parallel processing. The controller 230 may include at least one processor or core. Data input / output commands input from the host 300 or commands generated within the controller 230 can be divided into multiple stages or tasks for parallel processing, which can then be processed. Multiple pipelines can divide command processing into multiple stages or tasks so that at least one core can execute tasks of multiple threads simultaneously. According to an embodiment, the multiple pipelines can be configured to execute command processing using a superscalar technique with multiple cores capable of handling multiple pipelines.

[0104] Reference Figure 1 and Figure 2 The memory systems 210, 210A, and 210B can execute data input / output commands from multiple hosts 300, 300A, 300B, and 300C, and store data transmitted from these hosts. Exchanged data can be included within the data transmitted from the multiple hosts 300, 300A, 300B, and 300C.

[0105] The processor (e.g., central processing unit (CPU)) in host machine 310 can be configured to execute commands generated from application 380, host operating system 320, and virtual machines 340, 350, and can process data corresponding to commands or calculations. Host memory 370 can temporarily store the program currently being executed by the CPU and the corresponding data. Host memory 370 can have (e.g., configured with) a fast data input / output speed to quickly provide the data and commands required by the CPU. When the storage space of host memory 370 is insufficient, memory system 210 can operate as swap memory. Swapping operations can virtually expand the storage space of host memory 370 so that application 380, host operating system 320, or virtual machines 340, 350 can perform tasks that require a large amount of data storage space. However, since the operating speed of memory system 210 may be slower than that of host memory 370, memory system 210 can be configured to reduce the degradation of system performance through swapping operations.

[0106] By using swap memory, host 300 can execute more applications 380 simultaneously and avoid or prevent programs from being forcibly terminated when memory is insufficient. Additionally, the embodiment can prevent applications 380, host operating system 320, or virtual machines 340, 350 from crashing due to memory allocation failures, thereby improving the stability of the data processing system.

[0107] Additionally, according to the embodiment, the swap memory is primarily used for temporary storage of data that is not used for a long time or low-priority data. By moving data generated or used by the host machine 310 when executing low-priority processes to the swap area of ​​the memory system 210 instead of the host memory 370, the operational performance of the host 300 can be improved.

[0108] Additionally, when host 300 performs memory-intensive tasks, swap memory can be used. When performing tasks that consume a large amount of memory (e.g., large database processing, large file processing, or advanced graphics processing), the swap area of ​​memory system 210 can supplement host memory 370 so that host 300 can continue to perform tasks. Such swap memory can provide greater flexibility in memory management of the data processing system and helps optimize the use of host memory 370 included in host 300.

[0109] The size of the swap area in memory system 210 can be determined in response to a request from host 300. If the swap area is too large or too small, it can lead to performance problems or insufficient memory. According to an embodiment, the size of the swap area in memory system 210 can be determined based on the size of host memory 370. If the swap area is set too large compared to the required space, the amount of unused space in the swap area of ​​memory system 210 may increase, resulting in wasted storage space. On the other hand, if the swap area is set too small compared to the required space, both host memory 370 and the swap area in memory system 210 may be full, leading to insufficient memory, abnormal termination of application 380, host operating system 320, or virtual machines 340, 350, or stability issues with host 300. Furthermore, if the swap area is smaller than the required space, host 300 and memory system 210 may frequently perform swap-in and swap-out operations, which may lead to a decrease in the overall performance of the data processing system.

[0110] Figure 3 A swap operation according to an embodiment of this disclosure is illustrated.

[0111] Reference Figures 1 to 3A swap operation can be initiated by a swap request for specific data (e.g., a page). The specific data corresponding to the swap request can be stored in a temporary buffer or cache (e.g., a swap cache) used for the swap operation. According to an embodiment, the swap operation may include a three-stage configuration mechanism: a swap task in the swap cache, a swap task in the front end (e.g., a front swap), and a swap task in the back end (e.g., a swap area, a swap backing store). In this document, a swap task in the front end (e.g., front-end) may include operations that generate or prepare swap data in host 300, and a swap task in the back end (e.g., back-end) may include operations that store swap data in memory system 210.

[0112] A swap cache can refer to a situation where the contents of a swap area are temporarily stored in host memory 370 when specific data (e.g., pages) is swapped out or into the swap area. For example, due to insufficient memory, specific data (e.g., pages) used by processes executing in host application 380, host operating system 320, or virtual machines 340, 350 on host 300 can be stored in the swap area. During this process, the data can be retained in host memory 370.

[0113] According to an embodiment, the switching tasks in the front end can be executed by a high-speed computing device capable of synchronously storing the switched data (e.g., pages). For example, the switching tasks in the front end can be executed in virtual machines 340 and 350 within host 300. The transdomain memory (TMEM) within virtual machines 340 and 350 can be a function provided by kernels 344 and 354 of operating systems 342 and 352 (e.g., Linux), representing a type of unknown and dynamically variable memory. The transdomain memory can be addressed only indirectly by kernels 344 and 354, can be persistent or transient (e.g., briefly existing but possibly disappearing without warning), and can operate fast enough to enable synchronous access. The transdomain memory can be located in DRAM or persistent memory (PMEM) included in host memory 370.

[0114] While the "swap" function can be performed by the memory system 210 used by the operating systems 342 and 352 to store swapped data (e.g., pages), the "compressed swap (zswap)" function can support the functionality provided by the kernels 344 and 354 of the operating systems 342 and 352, which provides a compressed write-back cache for swapped data (e.g., pages) as a form of virtual memory compression. Unlike the "swap" function, which moves swapped data to the memory system 210 as a swapping device when swapped out, the "zswap" function can support the compression of swapped data and store the compressed and swapped data in a memory pool dynamically allocated to the host memory 370 after compression. Subsequently, write-back to the actual swapping device (e.g., memory system 210) can be postponed or even completely avoided, thereby significantly reducing input / output (I / O) between the host 300 and the memory system 210 that performs the swapping operation.

[0115] According to embodiments, compressed switching (i.e., zswap) can be performed using an encrypted compression mechanism (e.g., crypto compression) that combines data compression and encryption techniques. Examples of crypto compression algorithms include LZ4, LZO, Snappy, Zstandard, and TCOx (e.g., TCO50, TCO30, TCO10, etc.). The crypto compression mechanism can be designed to reduce data storage space or shorten data transmission or delivery time by identifying and removing duplicate data. Additionally, encryption can protect data from unauthorized parties (e.g., other unauthorized hosts). Simultaneous data compression and encryption can be more efficient than performing each process separately.

[0116] According to embodiments, compressed swapping (i.e., zswap) can be performed using a compressed pool (i.e., ZPOOL) or ZFS (i.e., Zettabyte File System) compression. Here, a pool is a logical group of devices used to describe the layout and physical characteristics of available storage. For example, disk space for a dataset can be allocated from a pool. ZFS compression is a feature that dynamically compresses data, improving storage efficiency and read performance. Examples of ZFS compression algorithms can include ZSMALLOC, ZBUD, Z3FLOLD, etc. For example, compressed swapping can be implemented from ZPOOL (stored in PMEM) as compressed memory storage based on algorithms such as ZSMALLOC, ZBUD, and Z3FLOLD.

[0117] Compacted swapping (i.e., zswap) can operate like compressed RAM cache and can operate alongside uncompressed swapping devices. Because compacted swapping (i.e., zswap) stores data in compressed form in host memory 370, it reduces the number of writes and reads, thereby improving the efficiency of swapping operations. Furthermore, compacted swapping (i.e., zswap) reduces the number of writes to and reads from non-volatile memory in memory system 210, thereby reducing wear and extending lifespan. Additionally, compacted swapping (i.e., zswap) can be an abstraction mechanism that can be integrated using front-end-provided interfaces (e.g., APIs) via kernels 344 and 354 on operating systems 342 and 352. Therefore, compacted swapping (i.e., zswap) can effectively provide additional storage space to host memory 370.

[0118] According to an embodiment, swapping operations performed in the backend can be performed through a swapping area of ​​the memory system 210. The host 300 can identify the swapping area in the memory system 210 used for storing swapped data (e.g., swap entries) as swap backing storage. The swapping area of ​​the memory system 210 can be logically or physically separated from the area in the memory device 250 within the memory system 210 where data is stored.

[0119] A swap region corresponding to a swap backup can be set up by specifying swap files (e.g., swap file 1, swap file 2) and swap disks (e.g., swap disk / partition). Alternatively, according to an embodiment, a swap region corresponding to a swap backup can be set up using a network file system (NFS) of a network-connected storage device (remote server) (e.g., via NFS swapping) (e.g., swap file 2 can be stored in the remote server partition / dev / hdc1). To set up a swap region or swap backup using swap files, swap disks (e.g., swap disk / partition), and a network file system (NFS), several tasks can be performed, such as partitioning the disk (e.g., / dev / sda1, / dev / sda2), setting up a swap region (e.g., / dev / zram0), and creating a swap file (e.g., / mnt / swap).

[0120] Reference Figures 1 to 3For data swapped out to memory system 210 via swap and zswap operations, host 300 cannot guarantee the integrity of data stored in the swap area of ​​memory system 210 until the data is swapped into host memory 370. If the swapped data is encrypted and securely protected, it can be decrypted and its integrity checked after it has been swapped out and then swapped in. However, if the swapped data is not encrypted and not securely protected, host 300 may have difficulty checking the integrity of the swapped-in data.

[0121] Figure 4 The exchange operation of a data processing system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 4 This describes the scenario where an overwrite write is performed on the swapped data that is the target of the swap operation.

[0122] Reference Figure 4 The host central processing unit (CPU) 302 can exchange portions of data stored in the host memory (e.g., main memory) 370. The exchange can be broadly categorized into two operations: "swap out" and "swap in". The "swap in" operation always follows the "swap out" operation (under normal operating conditions). If only the "swap in" operation is performed without the "swap out" operation, it may be considered a malfunction.

[0123] A "swap out" operation may include moving data from host memory 370 to memory system 210 and processing it. A "swap in" operation may include transferring data from memory system 210 to host memory 370 and processing it. The data exchanged may include, for example, Figure 3 The data compression or authentication signature and security key shown (e.g., Key / AG_ID, see...) Figure 11 The memory system 210 may include a swap area configured to store data to be exchanged and a file system area configured to store data unrelated to the exchange.

[0124] For example, during data movement within the host memory 370, the host central processing unit 302 can immediately detect whether the data has been corrupted via the memory management unit (MMU) when accessing the data, and ensure security by responding to unauthorized data access. However, the memory system (e.g., storage device) 210 is an external device that communicates via the input / output controller 360. Since external input / output devices are processed asynchronously, real-time monitoring may be limited. Even if data corruption occurs, the external input / output device can be detected during a later data inspection. Management may be more difficult, especially in the case of remote storage connected to a network in the switching area.

[0125] For example, some data stored in host memory 370 (e.g., swap data) can be stored in a swap area (i.e., Swap Area) in memory system 210 via a "swap-out" operation (①). Memory system 210 can maintain and manage the data stored in the swap area (i.e., Swap Area). The swap area (i.e., Swap Area) can be set as a remote area, such as a swap file (e.g., Swap File), a swap disk (e.g., SwapDisk / Partition), or a network file system (NFS). Memory system 210 can be connected to multiple hosts 300A, 300B, 300C, such as... Figure 1 As shown. If the swap area set in the memory system 210 is shared by multiple hosts 300A, 300B, and 300C, there is a possibility that data may be overwritten (②).

[0126] When the host central processing unit 302 requests data exchange, it can move data stored in the exchange area of ​​the memory system 210 to the host memory 370 through a "swap-in" operation (③). The host central processing unit 302 can check the exchange data stored in the host memory 370 and determine whether the exchange data is corrupted (e.g., contaminated) (④).

[0127] As described above, if any data in the swap area is changed or modified due to external or unforeseen factors after the swapped data is stored in the memory system 210 via a "swap-out" operation, the host central processing unit 302 may have difficulty immediately identifying whether the change or modification has occurred. If the host central processing unit 302 does not identify the change or modification, the corrupted data can be confirmed through subsequent operations after the "swap-in" operation. During this process, data corruption may lead to malfunctions and hacking attacks, thus potentially posing security risks to the data processing system.

[0128] Reference Figures 1 to 4The methods and timing for security monitoring and security risk identification of data stored in the host memory 370 and the swap area of ​​the memory system 210, which serves as an input / output (I / O) device, differ. Data monitoring of the host memory 370 is performed in real time, allowing the host 300 to detect access to the host memory 370. For example, the host 300 can detect immediate access to the host memory 370 through the access bits of page table entries (PTEs). A page table is a data structure used by the operating system to track the mapping between virtual addresses used by processes and corresponding physical addresses in system memory. A page table entry (PTE) is an entry in the page table that stores information about a specific memory page. Each page table entry (PTE) may include information such as the physical address of the page stored in the host memory 370, whether the page is in the host memory 370, whether the page is writable, or other access permissions for the page. Furthermore, the page table can be managed by the operating system and can be accessed and read by the memory management unit (MMU). The host 300 can immediately detect whether access permissions to pages in the host memory 370 have been violated through the memory management unit (MMU).

[0129] According to the embodiment, host 300 can track access to host memory 370 in real time using kernel monitoring tools (e.g., debugging mechanisms such as KProbes and uprobes). Additionally, host 300 can detect data tampering in host memory 370, immediately detect tampering attempts through write protection detection, track changes to host memory 370 using resource management techniques (e.g., copy-on-write (CoW)), or track changes to host memory 370 through an ECC module (566, see [link]). Figure 14 Immediately detect any abnormal changes (e.g., errors) occurring in the host memory 370.

[0130] On the other hand, data monitoring of the switching area in the memory system 210, which is an input / output (I / O) device, may differ from that of the host memory 370. The host 300 may have difficulty detecting real-time access to the switching area in the memory system 210. Since the host 300 can access the memory system 210 through the input / output controller 360, there is a delay in detecting access to the switching area. While changes to the switching area in the memory system 210 can be tracked using a block-level I / O tracing mechanism (e.g., blktrace) that provides detailed information about request queue operations up to the user queue, the overhead can be significant. Therefore, protective measures configured to prevent abnormal changes to the switching area in the memory system 210, as well as supplementary measures configured to handle data corruption, can be introduced into the data processing system.

[0131] Figure 5 A method for protecting exchanged data according to embodiments of the present disclosure is illustrated. Specifically, Figure 5 Describes methods for avoiding or preventing Figure 4 The mechanisms or operational methods of risk described in the document.

[0132] Reference Figure 5 Application 304 can store data in host memory 370 and swap a portion of the data in host memory 370 to the swap area of ​​memory system 210. The data processing system may include an apparatus and mechanism capable of protecting the data within memory system 210 to prevent or avoid contamination of the stored data through swapping operations. When host 300 notifies memory system 210 that the data being transferred or stored is swapped data, access by external devices to the swap area where the corresponding data stored in memory system 210 has been swapped out can be restricted to ensure data integrity. This document describes an operational method that ensures data integrity of swapped data in the data processing system even when host 300 does not monitor the swap area of ​​memory system 210.

[0133] First, when host 300 requests a page swap operation in host memory 370, the corresponding swap backup storage 372 can be notified or displayed that the data being transferred or stored is swap data (①) (e.g., based on an explicit alert or masking of the swap data for which a page swap request has been received). An identifier or similar identifier can be used to indicate an input / output request (e.g., I / O REQ) for the "swap out" operation of the swapped data (②). Memory system 210 can identify that the data transmitted along with the corresponding command CMD is swap data by the identifier or similar identifier included in the command CMD (③). According to the protocol of this disclosure embodiment, even if the command CMD and data are transmitted via a network-connected remote device or multi-level device and memory system 210, identifiers or similar identifiers can be transmitted so that the final target device storing the data can identify that the data is swap data. Reference will be made later. Figure 10 The protocol and command CMD according to embodiments of this disclosure are described.

[0134] To store swapped data in the swap area of ​​memory system 210, memory system 210 can check the command CMD. If the transmitted data is identified as swapped data by an identifier or the like, memory system 210 can perform write protection on that data (④). According to an embodiment, memory system 210 does not prevent overwriting of data other than swapped data stored in unprotected areas, but may prevent overwriting of swapped data stored in the swap area (④). If memory system 210 receives an abnormal request (e.g., overwrite, etc.) for swapped data in the swap area, memory system 210 can determine whether the request will compromise the data integrity of the swapped data and notify host 300 of this determination (④). Host 300 may have difficulty detecting the swap area in memory system 210 in real time. However, by notifying host 300 of errors or abnormal requests (e.g., overwrite, etc.) from memory system 210, the embodiment can provide host 300 with the ability to monitor the swap area within memory system 210. This can provide write protection at the memory system (e.g., endpoint) to ensure data integrity and notify errors. Thus, memory system 210 can achieve immediate detection capabilities even during non-monitoring periods.

[0135] Host 300 may request memory system 210 to swap in exchange data, and memory system 210 may transmit the requested data to host 300 (⑤). Host 300 may verify the swapped-in data through swap backup storage 372 and transmit the verified data (e.g., Data Verified) to host memory 370 (⑥).

[0136] The host 300 can instruct the memory system 210 to unmap or delete swapped-in data. Additionally, the host 300 can explicitly transmit additional measures (e.g., other protection) related to the corresponding data to the memory system 210 (⑦) (e.g., unmapping or deleting swapped-in data, or notifying that protection is complete). The memory system 210 can receive these additional measures from the host 300 and perform security measures such as write protection on the corresponding area (⑧).

[0137] Figure 6 An operation method of a data processing system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 6 This describes the exchange operations performed in the data processing system.

[0138] Reference Figure 6 The switching application 380 can decide to swap out the swap data and transfer the swap data to the host memory 370.

[0139] The host memory 370 can store swap data in a swap buffer and then transmit data input / output requests (e.g., block I / O requests) to the input / output controller 360.

[0140] The input / output controller 360 may transmit a write request (e.g., an I / O write request) to the memory system 210 in response to a request transmitted from the host memory 370. This write request is a data input / output command. The memory system 210 may store data in response to the write request (e.g., an I / O write request) and then notify the input / output controller 360 of the completion of the write request (e.g., a done interrupt).

[0141] The input / output controller 360 can modify page table entries in the swap area of ​​the host memory 370 based on the completion of the memory system 210 (e.g., a DoneInterrupt) (e.g., a Swap Area PTE Modification), which contains information about swap data. For example, the page table entry PTE for swap data can be changed to a swap entry (e.g., PTE: Change To Swap Entry). This process can correspond to the specific "Swap Out" operation during a swap operation.

[0142] The swap application 380 may request to read swap data (e.g., Swap AreaMemory Read). Since the host memory 370 has swapped the corresponding data out to the memory system 210, the corresponding data may not exist in the host memory 370 when the swapped data is not present (e.g., NOT DATA - Page Fault). (e.g., Data Evict). The host memory 370 can check and notify the swapped data (e.g., Hit Swap Entry). In response to a request from the application, the input / output controller 360 can transmit a read request (e.g., Block I / O Read Request), which is a data input / output command, to the memory system 210. The memory system 210 can transmit the stored data to the input / output controller 360 in response to the read request (e.g., Block I / O Read Request) (e.g., Done Interrupt). The input / output controller 360 can then transmit the corresponding data to the host memory 370 and modify the page table entry PTE of the corresponding data to a normal entry (PTE: Amend Normal). The host memory 370 can transfer the corresponding data to the switching application 380 (Swap Data In) based on the page table entry PTE to complete the "swap in" operation.

[0143] Figure 7 This illustrates a data processing system where the exchange of data is unprotected. Specifically, Figure 7 It describes a situation where data can still be corrupted even if it has been encrypted and swapped out.

[0144] Reference Figure 7 The Swap Application in host 300 can set at least one data (ORIG) stored in host memory 370 as a Swap Area Page Table entry (e.g., Swap Area PTE Setting).

[0145] If the data (ORIG) is set or specified as a swap area page table entry (e.g., Swap Area PTE Setting), the corresponding data can be protected in host memory 370 (e.g., Memory Swap Area Protection). Even if an application other than the swap application (e.g., Other Application) accesses the corresponding data in host memory 370 (e.g., MEM Access, MEMAcces), host memory 370 may detect the abnormal access. According to an embodiment, the corresponding data (ORIG) in host memory 370 can be encrypted (e.g., Crypto). The corresponding data (ORIG) in host memory 370 can be transferred to memory system 210 as swap data along with write I / O commands. Memory system 210 can store the corresponding data. However, memory system 210 can be shared by multiple external devices or multiple hosts (e.g., Pooled Memory).

[0146] When the memory system 210 is not a dedicated device for a specific host, it may be impossible to protect the exchanged data based on the logical address (e.g., LBA) used for data input / output (I / O) operations. This means that a write I / O request for the same logical address (e.g., the same LBA) can be delivered and executed by another external device (e.g., another agent) or another host connected to the memory system 210.

[0147] The memory system 210 may include a memory management unit (e.g., MMU) 232, but the MMU 232 may have difficulty determining or specifying which device the access to a corresponding logical address originates from. Therefore, the MMU 232 may be unable to stop or block write requests to the same logical address. In this case, the exchanged data in the memory system 210 may be corrupted. For a read request from the host 300 (e.g., Read I / O), the memory system 210 may transmit exchanged data corrupted by another external device (e.g., Another Agent) or another host. The corrupted exchanged data transmitted to the host memory 370 may differ from the data swapped out (ORIG) (e.g., !Original). The corrupted exchanged data stored in the host memory 370 may not be verified (e.g., Not Verified Data), and the corresponding data may be discarded (e.g., Discarded). In this case, even if the exchanged data is encrypted (e.g., Crypto), data protection may not be achieved (e.g., No Protection).

[0148] Figure 8 An operation method of a data processing system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 8 Describes the execution of processes between components of a data processing system. Figure 7 The events of the swap operation described in [the document].

[0149] Reference Figure 8 The switching application 380 can generate a request to exchange data (e.g., a data exchange request (SWAPDATA REQ)), determine the encryption of the exchange data to perform encryption (e.g., encrypt the exchange data (Crypto SWAP DATA)), and transmit a request to “swap out” the exchange data to the host memory 370 (e.g., swap data out (SWAP DATAOut)).

[0150] The host memory 370 can store swapped data in a swap cache (e.g., a swap cache) and then transmit data input / output requests (e.g., block I / O requests) to the input / output controller 360.

[0151] The input / output controller 360 can transmit data input / output commands, such as write requests (e.g., I / O write requests) to the memory system 210 in response to requests from the host memory 370.

[0152] The memory system 210 may store data in response to a write request (e.g., an I / O write request) and then notify the input / output controller 360 of the completion of the write request (e.g., an I / O write request) (e.g., a done interrupt).

[0153] The input / output controller 360 can modify the page table entry PTE (i.e., information about swapped data) in the host memory 370 in response to the completion of the memory system 210 (e.g., a DoneInterrupt). For example, the page table entry PTE for swapped data can be changed to a swap entry (e.g., Change To Swap Entry). This operation can correspond to the specific operation of the "swap out" operation during the swapping process.

[0154] The switching application 380 may request to read swapped data (e.g., a swap area memory read). Since the host memory 370 swaps the corresponding data out to the memory system 210, the corresponding data may not be present in the host memory 370 (e.g., a data eviction). The host memory 370 may check for the presence of swapped data (e.g., a hit swap entry) and may notify the input / output controller 360 that the corresponding swapped data is not present in the host memory 370 (e.g., a NOT DATA - page fault). In response, the input / output controller 360 may transmit a read request (i.e., a block I / O read request) to the memory system 210, which is a data I / O command.

[0155] Memory system 210 can transfer stored data to input / output controller 360 (e.g., a done interrupt) in response to a read request (i.e., a block I / O read request). Input / output controller 360 can transfer the data to host memory 370 and modify the page table entry PTE of the data to a normal entry (e.g., PTE: Amend Normal Entry). Host memory 370 can verify the data based on the page table entry PTE and decrypt the verified data (i.e., Data Verified) using a decryption algorithm or device.

[0156] The host memory 370 can transfer the decrypted data to the switching application 380 to complete the "swap in" operation. If the data is valid (e.g., if DATA Valid), the data can be swapped in and passed to the switching application 380 (e.g., Swap Data In). However, if the data is invalid (e.g., if Invalid), the data can be discarded (e.g., Discard if Invalid).

[0157] Figure 9 A method of operating a memory system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 9 A method for avoiding or preventing Figure 7 and Figure 8 The data contamination method described herein.

[0158] Reference Figure 9 A portion of the data stored in host memory 370, namely swap data, can be transferred and stored in memory system 210. In this document, memory system 210 can be shared by multiple external devices or multiple hosts (e.g., pooled memory).

[0159] If the data (ORIG) stored in host memory 370 is identified as swap data, host memory 370 can protect the data (ORIG) using a swap area (e.g., memory swap area protection). The swap data can be transferred to memory system 210 along with a write command (e.g., write I / O). The write command (e.g., write I / O) may include identifier 610 (see [link to documentation]). Figure 10The identifier 610 indicates that the data transmitted together is swap data.

[0160] The memory system 210 can identify swap data and store it in the memory device. At this time, the controller or flash translation layer (FTL) 540 within the memory system 210 (see...) Figure 14 This can generate mapping data that links logical addresses transferred from the host to physical addresses of the memory device (e.g., FTL mapping). The controller or flash translation layer (FTL) within the memory system 210 can access the mapping data 620B (see [link to documentation]). Figure 11 It records additional information about the exchanged data (SWAP DATA), such as identifiers, keys, and flags.

[0161] Multiple external devices or hosts that operate in conjunction with memory system 210 can transmit logical address LBAs along with data input / output commands. Memory system 210 can look up the physical address corresponding to the logical address LBA via the flash translation layer (FTL). During the process of looking up the physical address corresponding to the logical address LBA based on the mapping data, memory system 210 can check for the presence of additional information in the swap data, such as identifiers, keys, and flags. If additional information is present, memory system 210 can restrict, block, or not perform the corresponding operation. In this way, memory system 210 can prevent write operations to the same logical address LBA as the swap data (e.g., write protection). Even if a write request for the same logical address LBA as the swap data is transmitted from one of the multiple external devices or multiple hosts, memory system 210 may not perform the write operation corresponding to the corresponding write request. According to an embodiment, memory system 210 can include an error code in the response corresponding to the corresponding write request and transmit the response to one of the multiple external devices or multiple hosts. Data corruption on the storage disk can be identified in real time through the host memory 370.

[0162] Reference Figures 1 to 9The swap data does not need to be updated. Due to insufficient storage space in the host memory 370, the swap data is stored in the memory system 210. In many cases, the host 300 can perform a swap-in operation after the swap data is swapped out. On the other hand, another application in the host 300 may transmit a write command (e.g., write I / O) to the same logical address as the swap data. In this case, the memory system 210 can identify, based on the mapping data, that the corresponding write command (e.g., write I / O) is an error or unauthorized access. At this time, the memory system 210 can transmit a response including an error code (error response) to the host 300.

[0163] The memory system 210 can output swap data from a read command (e.g., Read I / O) transmitted by the host 300. Since the memory system 210 does not perform a write operation to the same logical address (LBA) as the swap data, the memory system 210 can transmit the original data (ORIG) identified as swap data based on the read command (e.g., Read I / O).

[0164] As described above, the memory system 210 can perform operations corresponding to read commands (e.g., Read I / O) or unmapping or deletion commands targeting the same logical address LBA as swap data stored in the memory device, but stopping or blocking write operations corresponding to write commands entered together with the same logical address LBA. Through this method of operation, the memory system 210 can maintain and supplement the data security of swap data requested by the host 300.

[0165] According to an embodiment, based on a data security policy, swap data stored in a memory device within memory system 210 can be shared by multiple external devices or multiple hosts. During the processing or execution of a read operation corresponding to a read command (e.g., Read I / O), memory system 210 can, based on mapping data, check whether the read command (e.g., Read I / O) was input from an external device or host, and whether it was input at the same logical address as swap data stored on another external device or host.

[0166] On the other hand, the memory system 210 can perform operations such as garbage collection (GC), read recycling (RRC), and wear leveling (WL) on the memory device. In this case, the location (i.e., physical address) of the swap data stored in the memory device may change. Even if the swap data is moved or migrated through operations such as garbage collection (GC), read recycling (RRC), and wear leveling (WL), the memory system 210 can still maintain additional information, such as identifiers, keys, and flags, in the mapping data of the logical addresses corresponding to the swap data. Therefore, even after performing operations such as garbage collection (GC), read recycling (RRC), and wear leveling (WL), the memory system 210 can provide the host 300 with uncontaminated swap data without any problems. Thus, the memory system 210 can more flexibly configure the swap area for storing swap data and improve the resource utilization efficiency within the memory device.

[0167] Figure 10 A write command according to an embodiment of this disclosure is shown. Figure 10 The format of a write command (e.g., the WRITE command) in SCSI commands has been used as an example. In essence, a similar format can be applied to other write commands defined in various protocols.

[0168] Reference Figure 10 The write command may include parameters such as operation code (e.g., OPERATION CODE, 2Ah), write protection (e.g., WRPROTECT), logical address (e.g., LOGICAL BLOCK ADDRESS), and transfer length (e.g., TRANSFER LENGTH).

[0169] Specifically, a write command can be used to request host 300 to transfer data stored in a specific or designated logical block (e.g., a logical block) in the data output buffer and store the corresponding data in memory system 210 (including the most significant bit (MSB) to the least significant bit (LSB)). Each transferred logical block may include user data. Protection information may be stored in response to parameters such as write protection (e.g., WRPROTECT) and data caching functions such as disabling page output (DPO), forced cell access (FUA), and obsolete. Each written logical block may include user data. If stored write protection (e.g., WRPROTECT) is activated, additional protection information can be added or included in the write command. The transfer length (e.g., TRANSFER LENGTH) can specify the number of consecutive logical data blocks to be transferred from the data output buffer and written to memory system 210, starting from the logical block specified by the starting logical address. For example, if the transfer length (e.g., TRANSFER LENGTH) is set to "0", then the transfer length (e.g., TRANSFER LENGTH) can represent that 256 logical blocks have been written. For other values ​​in the transfer length (e.g., TRANSFER LENGTH) that are not "0", the other values ​​can represent the number of logical blocks to be written in the memory system 210.

[0170] The write command includes a spare area (e.g., a reserved area), which is unused but designated as a reserved area. At least one bit 610 of the spare area (e.g., a reserved area) designated as a reserved area in the write command may include additional information such as an identifier, key, or flag for swap data. According to embodiments, the configuration of this additional information can vary depending on the available space in the write command.

[0171] Figure 11 Mapping data of a memory system according to an embodiment of this disclosure is shown. Specifically, Figure 11 The mapping data generated and managed by the memory system 210 is described.

[0172] Reference Figure 11The first mapping data 620A may include mapping information for logical addresses (e.g., from LBA0 to LBAn). When receiving exchanged data from host 300, memory system 210 may further record additional information such as identifiers, keys, flags, and agent numbers (Key / AG_ID) in the mapping information (e.g., from LBAc to LBAg) corresponding to the logical addresses (e.g., from LBAc to LBAg), which correspond to the exchanged data. Memory system 210 may determine, based on the second mapping data 620B, whether to perform a data input / output request (e.g., read, write, delete commands, etc.) on the logical addresses (from LBAc to LBAg) corresponding to the exchanged data.

[0173] According to an embodiment, the memory system 210 may use virtual addresses in response to logical addresses used and transmitted by external devices or hosts. In this case, mapping data can map or link logical addresses to virtual addresses. Additionally, according to an embodiment, the configuration of the mapping data used by the memory system 210 may vary based on the internal configuration of the memory device 250.

[0174] Figure 12 A first operation of a shared memory device according to an embodiment of the present disclosure is illustrated. Specifically, Figure 12 This describes an operation that increases the size of a storage area, one of many ways or methods to change the settings of a storage device in a virtualized environment.

[0175] Reference Figure 12 The applications (Apps) 680A and 680B on the host machine can recognize the logical address (LBA) used by the operating system 652A in the virtual machine. The operating system 652A can correspond to... Figure 2 The operating system 352 in the host. The available logical address range can be assigned to multiple hosts or multiple virtual machines within each host. For clarity, the operating system 652A of a virtual machine (one of multiple virtual machines on a host) (e.g., GS0, GS1) can use logical address LBAs "0" and "100". The same logical address range can be assigned to the operating system 652A of each virtual machine.

[0176] The hypervisor 630A included in the host can correspond to Figure 2 The hypervisor 330 described in the document. Figure 2The operating system 320 within the host 300 described herein can provide an input / output (I / O) virtualization configuration 662A. The I / O virtualization configuration 662A may include the ability to extend and set I / O ranges so that the operating systems 652A of multiple virtual machines within the host (as an external device) can simultaneously use multiple logical partitions (e.g., logical address ranges 656A) to share the storage device 610A. Through the I / O virtualization configuration 662A, the logical address range used by each virtual machine's operating system 652A (e.g., from "0" to "100") can be changed to different logical address ranges 642A (e.g., 0 to 100, 100 to 200, 200 to 300, 300 to 400), thereby avoiding overlap. In this document, the storage device 610A may correspond to... Figure 2 The memory system 210 described herein. The storage device 610A may have sufficient space (or sufficient storage area) to store data corresponding to the entire logical address range 642B from “0” to “400”.

[0177] The operating system 652A of a virtual machine (one of many virtual machines) can request the use of more logical addresses. For example, the operating system 652A of the virtual machine can request the logical address range 656B ("0" to "150") from the logical address range 656A ("0" to "100"). This change can imply or indicate that the operating system 652A of the virtual machine can generate and store more data than it has stored in the past.

[0178] If storage device 610A can accommodate it, the entire logical address range 642A (“0” to “400”) used for accessing storage device 610A via hypervisor 630A and input / output (I / O) virtualization configuration 662A can be changed and reset to the entire logical address range 642B (“0” to “450”). For example, the operation may include hypervisor (HV) identification and reset via reconfiguration and / or configuration. According to embodiments, additional operations such as rebooting may be required during this process to perform the change or reset.

[0179] Furthermore, according to the embodiments, although Figure 12 The description covers the case where the entire logical address range of the access memory device 610A increases, but the entire logical address range can be reduced in a similar manner.

[0180] Figure 13 A second operation of a shared memory device according to an embodiment of the present disclosure is illustrated. In such a way... Figure 12 After the entire logical address range of the access memory device 610A is increased, Figure 13 This illustrates the case where the entire logical address range decreases.

[0181] Reference Figure 12 and Figure 13 The virtual machine's operating system 652A requests the logical address range 656B ("0" to "150") from the logical address range 656A ("0" to "100"). The entire logical address range 642A ("0" to "400") can be changed and reset to the entire logical address range 642B ("0" to "450") via the hypervisor 630A and the I / O virtualization configuration 662A.

[0182] When the virtual machine's operating system 652A requests logical address 656A ("0" and "100") from logical addresses 656B ("0" and "150"), the logical address range can be reset via the hypervisor 630A and the I / O virtualization configuration 662A. The entire logical address range 642B ("0" to "450") used to access storage device 610A can be changed or reset back to the entire logical address range 642A ("0" to "400") via the hypervisor 630A and the I / O virtualization configuration 662A.

[0183] According to an embodiment, after changing the logical address range accessible to storage device 610A to "0" to "400", the hypervisor 630A may fail to reflect the logical address range used by the virtual machine's operating system 652A. In this case, the hypervisor 630A may determine that the virtual machine's operating system 652A can use a logical address range from 100 to 150. When the virtual machine's operating system 652A transmits a write command (e.g., IO Write) targeting logical address 120 (e.g., LBA 120), storage device 610A may experience incorrect or unauthorized access based on the reset logical address range 642A ("0" to "400"). Such incorrect or unauthorized access should be stopped or blocked to prevent or avoid failure.

[0184] on the other hand, Figure 13The operation of reducing the entire logical address range can be modified and used to write-protect specific areas of storage device 610A. For example, when the virtual machine's operating system 652A requests logical address range 656A ("0" to "100") from logical address range 656B ("0" to "150"), the hypervisor 630A can notify the virtual machine's operating system 652A that the settings have changed to use logical address range 656A ("0" to "100"), but can retain the entire logical address range 642B ("0" to "450"), which can be used to access storage device 610A through I / O virtualization configuration 662A. In this scenario, the logical address range ("100" to "150") used to access storage device 610A may not be used by the operating systems of the multiple virtual machines, and the operating systems of the multiple virtual machines may not generate any data input / output commands for the logical address range ("100" to "150") to access storage device 610A during normal operation.

[0185] By employing this roundabout method, the system's operating environment can be configured such that other applications cannot generate any data input / output commands for the logical address corresponding to the exchanged data requested or specified by any particular application in the host during an exchange operation. Even without recording additional information in separate mapped data within storage device 610A, data input / output commands transmitted from the host to the memory system can be restricted to the logical address corresponding to the exchanged data requesting the exchange operation. In this way, contamination of the exchanged data stored in storage device 610A can be prevented or avoided.

[0186] Reference Figure 12 and Figure 13 Even if the storage device 610A does not perform write protection operations based on mapped data, the hypervisor 630A, which is capable of recognizing exchanged data or related information, can restrict the generation of data input / output commands for logical addresses of exchanged data, thereby avoiding or preventing the exchanged data from being contaminated.

[0187] Figure 14 A data processing system 500 according to an embodiment of the present disclosure is shown.

[0188] Reference Figure 14 The data processing system 500 may include a host 502 that is coupled to or connected to the memory system 510. For example, the host 502 and the memory system 510 may be interconnected via a data bus, host cable, etc., for data communication. According to an embodiment, the memory system 510 included in the data processing system 500 may correspond to... Figure 2 The memory system 210 shown.

[0189] The memory system 510 may include a memory device 550 and a controller 530. The memory device 550 and controller 530 in the memory system 510 can be considered as physically separate components or elements. The memory device 550 and controller 530 can be connected via at least one data path. For example, the data path may include a channel and / or a way. According to an embodiment, the memory device 550 may include... Figure 2 The memory device 250 shown.

[0190] The memory device 550 may include multiple memory chips (i.e., flash memory chips) 552 connected to the controller 530 via multiple channels CH0, CH1, ..., CHn and paths W0, ..., W_k. The memory chips 552 may include multiple memory planes or multiple memory dies. According to an embodiment, a memory plane may be considered a logical or physical partition, including at least one memory block, drive circuitry capable of controlling an array comprising multiple non-volatile memory cells, and buffers capable of temporarily storing data input to or output from the non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode in which multiple data input / output operations are performed in parallel or simultaneously. According to an embodiment, the memory blocks included in each memory plane or each memory die of the memory device 550 may be grouped to input / output multiple data entries as a super block. Figure 14 The internal configuration of the illustrated memory device 550 can be changed based on the operating performance of the memory system 510. Embodiments of this disclosure are not limited to those described herein. Figure 14 The internal configuration described in [the document / document].

[0191] According to embodiments, the memory device 550 and the controller 530 can be functionally divided into components or elements. Furthermore, according to embodiments, the memory device 550 and the controller 530 can be implemented using a single chip or multiple chips.

[0192] The controller 530 can perform data input / output operations (e.g., read operations, programming operations, erase operations, etc.) in response to requests or commands input from an external device, such as the host 502. For example, when the controller 530 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 550 is transferred to the controller 530. Furthermore, the controller 530 can perform operations independently without requests or commands input from the host 502. Regarding the operating state of the memory device 550, the controller 530 can perform operations such as garbage collection (GC), wear leveling (WL), bad block management (BBM) for checking whether memory blocks are bad blocks and disposing of bad blocks.

[0193] Each memory chip 552 may include multiple memory blocks. A memory block can be understood as a set of non-volatile memory cells whose data is erased together in a single erase operation. Although not shown, a memory block may also include pages, which are a set of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages. The memory device 550 may include a voltage supply circuit capable of supplying at least one voltage to the memory block. The voltage supply circuit may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory block.

[0194] The host 502 or data processing system 500 (including the memory system 510 and the host 502) that interacts with the memory system 510 can be a mobile electronic device (e.g., a vehicle), a portable electronic device (e.g., a mobile phone, MP3 player, laptop, etc.), or a non-portable electronic device (e.g., a desktop computer, game console, television, projector, etc.). The host 502 can provide interaction between itself and a user using the data processing system 500 or the memory system 510 through at least one operating system (OS). The host 502 transmits multiple commands corresponding to user requests to the memory system 510, and the memory system 510 can perform data input / output operations (e.g., operations corresponding to user requests) corresponding to the multiple commands. According to an embodiment, the host 502 can correspond to... Figure 2 The host 300 shown.

[0195] Reference Figure 14The controller 530 in the memory system 510 can operate together with the host 502 and the memory device 550. As shown, the controller 530 may include a hierarchical structure, which includes a host interface layer (HIL) 520, a flash translation layer (FTL) 540, and a flash interface layer (FIL or memory interface layer) 560.

[0196] The Host Interface Layer (HIL) 520, Flash Translation Layer (FTL) 540, and Flash Interface Layer (FIL) 560 are illustrated as one embodiment. The HIL 520, FTL 540, and FIL 560 can be implemented in various forms depending on the operational performance of the memory system 510. According to an embodiment, the HIL 520, FTL 540, and FIL 560 can perform operations via multiple cores or processors with a pipelined architecture included in the controller 530.

[0197] Host 502 and memory system 510 can send and receive data between them using predetermined data communication rules or sets of procedures or preset interfaces. Examples of rules or sets of rules or interfaces for sending and receiving data supported by host 502 and memory system 510 include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to an embodiment, host 502 and memory system 510 can be interconnected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a highly scalable, hot-swappable, plug-and-play serial interface that ensures cost-effective and standardized connections with peripherals such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, and video conferencing cameras.

[0198] The memory system 510 may support High-Speed ​​Non-Volatile Memory (NVMe). NVMe is an interface based at least on High-Speed ​​Peripheral Component Interconnect (PCIe), designed to improve the performance and design flexibility of a host 502, server, computing device, etc., equipped with the NVMe memory system 510. PCIe can use slots or specific cables to connect computing devices (e.g., host 502) and peripheral devices (e.g., memory system 510). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of megabits per second. According to embodiments, PCIe schemes can achieve bandwidths of tens to hundreds of gigabits per second.

[0199] The buffer manager 580 included in the controller 530 can coordinate with the host interface layer (HIL) 520, flash translation layer (FTL) 540, and flash interface layer (FIL) 560 to control the input / output of data or operational information. To this end, the buffer manager 580 can set up or create various buffers, caches, or queues in memory, and control the data input / output of buffers, caches, or queues, or the data transfer between buffers, caches, or queues, in response to requests or commands generated by the host interface layer (HIL) 520, flash translation layer (FTL) 540, and flash interface layer (FIL) 560. For example, the controller 530 can temporarily store read data provided by the memory device 550 in response to a request from the host 502 before providing read data to the host 502. Furthermore, the controller 530 can temporarily store write data in memory before storing write data provided by the host 502 in the memory device 550. When operations such as read operations, programming operations, and erase operations are performed within the memory device 550, the read or write data transferred or generated between the controller 530 in the memory system 510 and the memory device 550 can be stored and managed in buffers, queues, etc., established in the memory by the buffer manager 580. In addition to read or write data, the buffer manager 580 can also store signals or information (e.g., mapped data, read commands, programming commands, etc., used to perform operations such as programming and read data between the host 502 and the memory device 550) in buffers, caches, queues, etc., established in the memory. The buffer manager 580 can set up or manage command queues, program memory, data memory, write buffers / caches, read buffers / caches, data buffers / caches, mapped buffers / caches, etc.

[0200] The Host Interface Layer (HIL) 520 can process commands, data, etc., sent from the host 502. By way of example and not limitation, the HIL 520 may include a command queue manager 522 and an event queue manager 524. The command queue manager 522 may store commands, data, etc., received from the host 502 in a command queue in sequence, and output them to the event queue manager 524, for example, in the order they are stored in the command queue manager 522. The event queue manager 524 may transmit events in sequence for processing commands, data, etc., received from the command queue. According to an embodiment, the event queue manager 524 may classify, manage, or adjust commands, data, etc., received from the command queue. Furthermore, according to an embodiment, the HIL 520 may include an Encryption Manager (EncryptionP) 526, which is configured to encrypt response or output data to be sent to the host 502, or to decrypt encrypted portions of commands or data sent from the host 502.

[0201] Host 502 can send multiple commands or data with the same characteristics, or it can mix or co-present multiple commands and data with different characteristics before sending them to memory system 510. For example, multiple commands for reading data (read commands) can be sent to memory system 510, or commands for reading data (read commands) and commands for programming / writing data (write commands) can be sent to memory system 510 alternately. The command queue manager 522 of host interface layer 520 can store the commands, data, etc., sent by host 502 in a command queue in sequence. Subsequently, host interface layer 520 can estimate or predict what type of internal operation controller 530 will perform based on the characteristics of the commands, data, etc., sent by host 502. Host interface layer 520 can determine the processing order and priority of commands, data, etc., based on their characteristics. According to the characteristics of the commands, data, etc., sent by host 502, event queue manager 524 in host interface layer 520 is configured to receive events from buffer manager 580 that should be processed or disposed of internally in memory system 510 or controller 530 according to the commands, data, etc., input by host 502. Then, the event queue manager 524 can send events, including commands, data, etc., to the flash translation layer (FTL) 540.

[0202] According to an embodiment, the Flash Translation Layer (FTL) 540 may include a Host Request Manager (HRM) 542, a Mapping Manager (MM) 544, a State Manager (GL / WL) 546, and a Block Manager (BM / BBM) 548. Furthermore, according to an embodiment, the Flash Translation Layer (FTL) 540 may implement a multi-threaded scheme to perform data input / output (I / O) operations. The multi-threaded FTL may be implemented using a multi-core processor with multi-threading included in the controller 530. For example, the Host Request Manager (HRM) 542 may manage events transferred from an event queue. The Mapping Manager (MM) 544 may dispose of or control mapped data. The State Manager 546 may perform operations such as garbage collection (GC) or wear leveling (WL) after checking the operational state of the memory device 550. The Block Manager 548 may run commands or instructions on blocks in the memory device 550.

[0203] The Host Request Manager (HRM) 542 can use the Mapping Manager (MM) 544 and the Block Manager 548 to handle or process requests based on read and program commands and events passed from the Host Interface Layer 520. The HRM 542 can send a query request to the Mapping Manager (MM) 544 to determine the physical address corresponding to a logical address entered along with an event. The HRM 542 can send a read request along with the physical address to the Flash Interface Layer 560 to handle the read request, i.e., handle the event. In one embodiment, the HRM 542 can send a program request (or write request) to the Block Manager 548 to program data into a specific empty page in the memory device 550 where no data is stored. A mapping update request corresponding to the programming request can then be transmitted to the Mapping Manager (MM) 544 to update the entries related to the programming data in the information mapping logical and physical addresses.

[0204] Block manager 548 can translate programming requests transmitted by host request manager (HRM) 542, mapping manager (MM) 544, and / or status manager 546 into flash programming requests for memory device 550 to manage flash blocks in memory device 550. To maximize or enhance the programming or writing performance of memory system 510, block manager 548 can collect programming requests and send multi-plane and single-programming operation flash programming requests to flash interface layer 560. In embodiments, block manager 548 can send multiple flash programming requests to flash interface layer 560 to enhance or maximize the parallel processing of multi-channel and multi-directional flash controllers.

[0205] In one embodiment, block manager 548 can manage blocks in memory device 550 based on the number of valid pages, selecting and erasing blocks without valid pages when free blocks are needed, and selecting blocks containing the fewest valid pages when it is determined that garbage collection should be performed. State manager 546 can perform garbage collection to move valid data stored in the selected blocks to empty blocks and erase data stored in the selected blocks, so that memory device 550 can have enough free blocks (i.e., empty blocks without data).

[0206] When block manager 548 provides information about the block to be erased to state manager 546, state manager 546 can examine all flash pages of the block to be erased to determine if each page of the block is valid. For example, to determine the validity of each page, state manager 546 can identify the logical address recorded in the out-of-band (OOB) area of ​​each page. To determine if each page is valid, state manager 546 can compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. State manager 546 can send a programming request to block manager 548 for each valid page. When the programming operation is complete, mapping manager 544 can update the mapping table.

[0207] Mapping manager 544 can manage mapping data, such as logical-physical mapping tables. Mapping manager 544 can handle various requests generated by host request manager (HRM) 542 or status manager 546, such as queries and updates. Mapping manager 544 can store the entire mapping table in memory device 550 (e.g., flash / non-volatile memory) and cache mapping entries according to the memory's storage capacity. When a mapping cache miss occurs while processing a query or update request, mapping manager 544 can send a read request to flash interface layer 560 to load the relevant mapping table stored in memory device 550. When the number of dirty cache blocks in mapping manager 544 exceeds a certain threshold, a programming request can be sent to block manager 546 to generate clean cache blocks and store the dirty mapping table in memory device 550.

[0208] During garbage collection, State Manager 546 copies valid pages to the free block, and Host Request Manager (HRM) 542 can program the latest version of the data for the same logical address of that page and simultaneously issue an update request. Mapping Manager 544 may not perform a mapping table update if State Manager 546 requests a mapping update while the copying of valid pages has not been completed correctly. This is because when State Manager 546 requests a mapping update and later completes the copying of valid pages, the issued mapping request contains old physical information. Mapping Manager 544 can only perform a mapping update operation to ensure accuracy if, or only if, the latest mapping table still points to the old physical address.

[0209] The Flash Interface Layer (FIL) 560 can exchange data, commands, status information, etc., with multiple memory chips 552 in the memory device 550 via data communication methods. According to an embodiment, the Flash Interface Layer 560 may include a Status Check Scheduler (SM / SC) 562 and a Data Path Manager (DPC) 564. The Status Check Scheduler 562 can check and determine the operating status of the multiple memory chips 552 connected to the controller 530, the operating status of multiple channels CH0, CH1, ..., CHn, and multiple paths W0, ..., W_k, etc. It can schedule the transmission and reception of data or commands in response to the operating status of the multiple memory chips 552 and the multiple channels CH0, CH1, ..., CHn. The Data Path Manager 564 can control the transmission and reception of data, commands, etc., through the multiple channels CH0, CH1, ..., CHn and the paths W0, ..., W_k based on the information transmitted by the Status Check Scheduler 562. According to an embodiment, the data path manager 564 may include multiple transceivers, each corresponding to each of the multiple channels CH0, CH1, ..., CHn. Furthermore, according to an embodiment, the status check scheduler 562 and data path manager 564 included in the flash interface layer 560 may be implemented as a memory control sequence generator or coupled to a memory control sequence generator.

[0210] According to an embodiment, the flash interface layer 560 may further include ECC (Error Correction Code) circuitry 566, configured to perform error checking and correction on data transmitted between the controller 530 and the memory device 550. The ECC circuitry 566 may be implemented as a separate module, circuit, or firmware within the controller 530, but according to an embodiment, it may also be implemented in each memory chip 552 included in the memory device 550. The ECC circuitry 566 may include programs, circuits, modules, systems, or devices for detecting and correcting error bits in the data processed by the memory device 550.

[0211] To locate and correct any errors in the data transmitted from memory device 550, ECC circuitry 566 may include an Error Correction Code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on the data to be programmed into memory device 550 to generate encoded data with parity bits added, and stores the encoded data in memory device 550. When controller 530 reads data stored in memory device 550, ECC decoder can detect and correct error bits contained in the data read from memory device 550. For example, after performing error correction decoding on data read from memory device 550, ECC circuitry 566 can determine whether the error correction decoding was successful and output an indication signal, such as a correction success signal or a correction failure signal, based on the result of the error correction decoding. ECC circuitry 566 can use the parity bits generated during the ECC encoding of data stored in memory device 550 to correct error bits in the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, ECC circuitry 566 may not correct the error bits but instead output a correction failure signal indicating that the correction of the error bits failed.

[0212] According to embodiments, the ECC circuit 566 can perform error correction operations based on coding modulation such as: low-density parity-check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 566 may include all circuits, modules, systems, and / or devices that perform error correction operations based on at least one of the above codes.

[0213] For example, the encoder in ECC circuit 566 can generate codewords as units of ECC application data. A codeword of length n bits can include k bits of user data and (nk) bits of parity check. The code rate can be calculated as (k / n). The higher the code rate, the more user data can be stored in a given codeword. When the codeword length is long and the code rate is low, the error correction capability of ECC circuit 566 can be improved. Furthermore, ECC circuit 566 uses information read from channels CH0, CH1, ..., CHn for decoding. The decoder in ECC circuit 566 can be divided into hard-decision decoders and soft-decision decoders based on the number of bits representing the information to be decoded. A hard-decision decoder uses memory cells represented by 1 bit for decoding; this 1 bit of information is called hard-decision information. A soft-decision decoder uses more accurate memory cells consisting of 5 bits or more; this information is called soft-decision information. ECC circuit 566 can use either hard-decision information or soft-decision information to correct errors included in the data.

[0214] According to an embodiment, to improve error correction capability, the ECC circuit 566 can use a concatenated code employing two or more codes. Alternatively, the ECC circuit 566 can use a product code, which divides a codeword into several rows and columns, and applies a different, relatively short ECC to each row and column.

[0215] According to an embodiment, the manager included in the host interface layer 520, flash translation layer (FTL) 540, and flash interface layer (FIL) 560 can be implemented using a general-purpose processor, accelerator, dedicated processor, coprocessor, multi-core processor, etc. According to an embodiment, the manager can be implemented using firmware that works in conjunction with the processor.

[0216] According to an embodiment, the memory device 550 is implemented as a non-volatile memory, such as a flash memory, or read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable ROM (EPROM), electrically erasable ROM (EEPROM), magnetic RAM (MRAM), NAND flash memory, NOR flash memory, etc. In another embodiment, the memory device 550 may be implemented by at least one of phase-change random access memory (PCRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), and spin-transfer torque magnetic random access memory (STT-MRAM).

[0217] According to an embodiment, the memory system 510 can support partitioning storage regions in the memory device 550 based on a preset standard, and dedicate each partitioned region to a specific range of logical block addresses (LBAs). When partitioned namespaces are supported, the memory system 510 can improve access efficiency and reduce access time by using a logical block address range dedicated to each region instead of using a specific logical block address range spanning multiple regions. For example, partitioned namespaces can improve write performance, which is very useful for workloads that require continuous writing of large amounts of data (e.g., video streaming or data backup).

[0218] Figure 15 A memory system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 15 A memory system comprising multiple cores or multiple processors is shown as an example of a data storage system. The memory system may support the Fast Non-Volatile Memory Protocol (NVMe).

[0219] NVMe is a transfer protocol designed specifically for solid-state storage, which can operate much faster than traditional hard drives. NVMe supports higher input / output operations per second (IOPS) and lower latency, thereby improving data transfer speeds and the overall performance of data storage systems. Unlike SATA, which is designed for hard drives, NVMe can leverage the parallelism of solid-state storage to use multiple queues and processors (e.g., CPUs) more efficiently. NVMe is designed to allow hosts to use multiple threads to achieve higher bandwidth. NVMe can fully utilize the parallelism offered by SSDs. However, due to the limited firmware scalability, limited computing power, and intense hardware competition within SSDs, the storage system may not be able to handle a large number of I / O requests in parallel.

[0220] Reference Figure 15 The host device, acting as an external device, can be connected to the memory system via multiple PCIe Gen 3.0 lanes, a PCIe physical (PHY) layer 412, and a PCIe core 414. The controller 400 may include three embedded processors 432A, 432B, and 432C, each using multiple cores 402A and 402B. In this document, the multiple cores 402A and 402B or the multiple embedded processors 432A, 432B, and 432C may have a pipelined architecture.

[0221] Multiple embedded processors 432A, 432B, and 432C can be interconnected to an internal DRAM controller (DDR controller) 434 via a processor interconnect. Controller 400 further includes a low-density parity-check (LDPC) sequencer 460, a direct memory access (DMA) engine (controller) 420, a temporary storage memory 450 for metadata management, and an NVMe controller 410. Components within controller 400 can be interconnected via a flash physical layer (NAND flash PHY) 440 to multiple channels connected to multiple memory packages (flash memory) 452. The multiple memory packages 452 can correspond to... Figure 14 The multiple memory chips 552 described in the document.

[0222] According to an embodiment, the NVMe controller 410 included in controller 400 is a storage controller designed for use with solid-state drives (SSDs) that use an NVMe interface. The NVMe controller 410 can manage data transfer between the SSD and the computer CPU, as well as other functions such as error correction, wear leveling, and power management. The NVMe controller 410 can support fast data transfer rates using a simplified, low-overhead protocol.

[0223] According to an embodiment, scratchpad memory 450 may be a storage area set up by NVMe controller 410 for temporary data storage. Scratchpad memory 450 may be used to store data awaiting writing to multiple memory packets 452. Scratchpad memory 450 may also typically utilize a small amount of dynamic random access memory (DRAM) or static random access memory (SRAM) as a buffer to accelerate the write process. When a write command is executed, data may first be written to scratchpad memory 450 and then transferred to multiple memory packets 452 in larger blocks. Scratchpad memory 450 may serve as a temporary memory buffer to help optimize the write performance of multiple memory packets 452. Scratchpad memory 450 may serve as intermediate storage for data before it is written to non-volatile memory cells.

[0224] The Direct Memory Access (DMA) engine (e.g., DMA controller) 420 included in controller 400 is a component that transfers data between the NVMe controller 410 in the host system and host memory without involving the processor in the host system. DMA engine 420 can enable the NVMe controller 410 to directly read data from or write data to host memory without intervention from the host processor. According to embodiments, DMA engine 420 can use DMA descriptors that include information related to data transfer (e.g., buffer address, transfer length, and other control information) to implement or support high-speed data transfer between the host and the NVMe device.

[0225] The LDPC sequencer 460 in controller 400 is a component that performs error correction on data stored in multiple (flash) memory packets 452. Herein, LDPC codes are a common error correction code used in NAND flash memory to reduce bit error rates. The LDPC sequencer 460 can be designed to process the encoding and decoding of LDPC codes immediately when reading data from and writing data to NAND flash memory (e.g., multiple (flash) memory packets 452). According to an embodiment, the LDPC sequencer 460 can divide data into multiple blocks, encode each block using LDPC codes, and store the encoded data in the multiple memory packets 452. Subsequently, when reading encoded data from the multiple memory packets 452, the LDPC sequencer 460 can decode the encoded data based on the LDPC codes and correct for errors that may have occurred during the write or read operations. The LDPC sequencer 460 can correspond to... Figure 14 The ECC circuit 566 described in the document.

[0226] As described above, in an environment where a memory device or memory system according to embodiments of the present disclosure performs data input / output operations together with multiple external devices, data security can be improved or enhanced by devices and methods capable of securely protecting data exchanged by a specific external device within the memory device or memory system.

[0227] Furthermore, in the data processing system according to embodiments of this disclosure, by implementing a mechanism that supports the protection of exchanged data by both the host and memory systems, data security in shared or pooled memory devices can be improved or enhanced.

[0228] The methods, processes, and / or operations described herein can be executed by code or instructions that run on a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the apparatus described herein, or an element other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0229] Furthermore, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the aforementioned code or instructions. The computer-readable medium may be a volatile or non-volatile memory or other storage device removably or permanently coupled to a computer, processor, controller, or other signal processing device to execute code or instructions for performing the operations of the method or apparatus embodiments described herein.

[0230] The controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features disclosed herein can be implemented, for example, as non-transient logic, which may include hardware, software, or both. When at least partially implemented as hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can be any of various integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0231] When implemented at least partially as software, controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0232] While this teaching has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims. Furthermore, embodiments may be combined to form other embodiments.

Claims

1. A memory system, comprising: A memory device for storing data input along with data input and output commands, i.e., data input / output commands, or for retrieving stored data; as well as Controller: Receive the data input / output command from at least one of a plurality of external devices and output a response corresponding to the data input / output command. The exchange data transmitted from the first of the plurality of external devices is stored in the memory device, and Prevent write operations corresponding to write commands, which are input from a second external device among the plurality of external devices along with the same logical address as the exchanged data.

2. The memory system according to claim 1, wherein, The controller receives a write command with a swap identifier from the first external device to store the swap data in the memory device.

3. The memory system according to claim 1, wherein, The controller: Generate logical address and physical address or virtual address mapping data entries for the exchanged data; and A protection identifier is added to the mapped data entry, the protection identifier indicating that the data associated with the mapped data entry belongs to a protected area in the memory device.

4. The memory system according to claim 3, wherein, The controller: Perform garbage collection or read / recycle operations on the memory device; and After performing the garbage collection or read-and-recycle operation on the exchanged data belonging to the protected area and updating the mapping data entry associated with the exchanged data, the protection identifier in the mapping data entry is maintained.

5. The memory system according to claim 1, wherein, The controller: The error code is included in the response corresponding to the write command input from the first external device along with the same logical address; and The response is transmitted to the first external device.

6. The memory system according to claim 1, wherein, When a read command transmitted from the first external device is input along with the same logical address, the controller transmits the exchanged data to the first external device.

7. The memory system according to claim 1, wherein, The controller: The restriction code will be included in the response corresponding to the read command entered from the second external device along with the same logical address; and The response is transmitted to the second external device.

8. The memory system according to claim 1, wherein, The controller deletes the mapping data entry of the swap data based on a swap release command input from the first external device along with the same logical address.

9. The memory system according to claim 1, wherein, The controller: The error code is included in the response corresponding to the exchange release command input from the second external device along with the same logical address; and The response is transmitted to the second external device.

10. The memory system according to claim 1, in, The memory device includes: A data storage area for storing write data transmitted from the plurality of external devices; and The exchange area stores exchanged data that is different from the data written, and Wherein, the controller: The data storage area and the exchange area are divided into different logical areas; and Different mapping data are generated for the data storage area and the exchange area.

11. The memory system according to claim 1, wherein, The memory device includes a plurality of volatile memory cells or a plurality of non-volatile memory cells for storing the exchanged data.

12. A data processing system, comprising: At least one host, including at least one application and a file system, determines the location of write data stored by the at least one application based on the file system; as well as At least one memory system receives exchanged data from the at least one host, generates a mapping data entry for the exchanged data, and determines whether to access the exchanged data based on the mapping data entry.

13. The data processing system according to claim 12, wherein, The mapping data entry includes the logical address of the exchanged data and a protection identifier indicating access rights to the logical address.

14. The data processing system according to claim 13, wherein, The protection identifier includes at least one of the following: An identifier that indicates whether the relevant data is the exchanged data; as well as Unique information is assigned to at least one host that has the aforementioned access rights.

15. The data processing system according to claim 12, in, When the range of logical addresses used by the at least one host changes, the at least one host restarts, and Wherein, the at least one memory system: The range of changes in the logical addresses used by the at least one host is received after the at least one host restarts; and The scope of the change is applied to the mapping data, which includes the mapping data entries.

16. The data processing system according to claim 12, wherein, The at least one host transmits a write command, including a swap identifier, to the at least one memory system, the write command being configured to store the swap data in the at least one memory system.

17. The data processing system according to claim 12, wherein, The at least one memory system includes: A memory device for storing or retrieving data corresponding to data input and output commands, i.e., data input / output commands, input from or from the at least one host; and The controller receives the data input / output commands and outputs a response to the data input / output commands.

18. The data processing system according to claim 17, wherein, The controller: The exchange data transmitted from the first host among the at least one host is stored in the memory device; and When a write command is input from a second host among the at least one hosts along with the same logical address as the exchanged data, the write operation corresponding to the write command is blocked.

19. The data processing system according to claim 18, wherein, The controller: The error code is included in the response to a write command entered from the first host along with the same logical address; and The response is transmitted to the first host.

20. The data processing system according to claim 18, wherein, The controller transmits the exchange data to the first host based on a read command transmitted from the first host along with the same logical address.

21. The data processing system according to claim 18, wherein, The controller: The restriction code will be included in the response corresponding to the read command entered from the second host along with the same logical address; and The response is transmitted to the second host.

22. The data processing system according to claim 18, wherein, The controller deletes the mapping data entry of the swap data based on a swap release command input from the first host along with the same logical address.

23. The data processing system according to claim 18, wherein, The controller: The error code is included in the response corresponding to the exchange release command entered from the second host along with the same logical address; and The response is transmitted to the second host.

24. A data processing system, comprising: At least one host includes multiple virtual machines, which communicate with input and output devices (i.e., input / output devices) through different address ranges in a unified logical address scheme. as well as At least one memory system, serving as the input / output device, stores exchanged data transmitted from the at least one host. In this scheme, at least one host sets the logical address of the exchanged data to be unavailable to the plurality of virtual machines.

25. The data processing system according to claim 24, wherein, At least one of the plurality of virtual machines runs at least one application, which generates the exchange data or specifies write data as the exchange data.

26. The data processing system according to claim 24, wherein, The at least one memory system includes a remote storage space connected to the at least one host via a network.

27. The data processing system according to claim 24, wherein, The at least one host: Add an identifier indicating the exchanged data to the write command; and The write command is transmitted to the at least one memory system.

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