Memory device including a memory controller and method of operating a memory controller

Abstract

A storage device includes a memory device including a plurality of memory blocks and a memory controller controlling a garbage collection operation mode of the memory device. The memory controller includes a host interface layer managing a plurality of logical pages based on a plurality of logical page numbers, the plurality of logical pages being respectively mapped to the plurality of memory blocks, a counter generating a count table including counts corresponding to indexes grouping the plurality of logical page numbers in units of data of a certain size, and increasing the count of the index corresponding to a write command when the write command is received from a host, and a locality garbage collection controller calculating a percentage value corresponding to the index based on the count, and determining the garbage collection operation mode to a mode performing a garbage collection operation considering locality based on the percentage value.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0051016, filed on April 18, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The various embodiments of this disclosure generally relate to a storage device, and more specifically, to a storage device including a memory controller and a method of operating the memory controller. Background Technology

[0003] A storage device is a means of storing data under the control of a host device such as a computer, smartphone, or tablet. A storage device may include a memory device for storing data and a memory controller for storing the data within the memory device. Memory devices can be classified as volatile memory devices or non-volatile memory devices.

[0004] The memory controller can perform garbage collection operations to reclaim unused memory blocks. In particular, the memory controller can perform localized garbage collection operations that take locality into account, controlling the memory device to keep in-use data close together.

[0005] However, for memory devices that only perform local garbage collection operations, unnecessary local garbage collection operations may be performed without considering the actual workload. Therefore, it is necessary to consider the workload of the memory device to determine whether to perform local garbage collection operations. Summary of the Invention

[0006] Various embodiments of this disclosure relate to a storage device that performs localized garbage collection operations based on the workload of the storage device, and a method for controlling the garbage collection operation mode of the storage device.

[0007] A storage device according to embodiments of the present disclosure may include a memory device and a memory controller. The memory device includes a plurality of memory blocks, and the memory controller is configured to control a garbage collection operation mode of the memory device. The memory controller may include: a host interface layer (HIL) configured to manage a plurality of logical pages based on a plurality of logical page numbers, the plurality of logical pages being mapped to a plurality of memory blocks respectively; a counter configured to generate a counter table including counts corresponding to indexes grouped in units of data of a specific size for the plurality of logical page numbers, and incrementing the count of the index corresponding to the write command when a write command is received from the host; and a locality garbage collection controller configured to calculate a percentage value corresponding to the index based on the count, and determine a garbage collection operation mode based on the percentage value to perform a mode that considers locality garbage collection operations.

[0008] In an embodiment, when the percentage value does not exceed a reference value, the local garbage collection controller can determine the garbage collection operation mode as a first mode, and when at least one of the percentage values ​​exceeds the reference value, it can determine the garbage collection operation mode as a second mode. The first mode can be a mode that performs garbage collection operations without considering locality, and the second mode can be a mode that performs garbage collection operations with consideration of locality.

[0009] In an embodiment, the second mode may be an operation mode that performs garbage collection by excluding the most recently invalidated logical storage block from the selection of the sacrificial block used for garbage collection operations.

[0010] In an embodiment, when HIL receives a write command from the host, HIL can convert the logical block address corresponding to the write command into a logical page number, and a counter can increment the count of the index corresponding to the logical page number obtained by converting the logical block address.

[0011] In an embodiment, the memory controller may further include a flash translation layer (FTL). When the FTL determines that the number of memory blocks managed by the FTL remains constant, the FTL may send a mode control request to the local garbage collection controller. After receiving the mode control request, the local garbage collection controller may periodically perform a mode determination operation to determine the garbage collection operation mode as one of a first mode and a second mode based on a percentage value.

[0012] In one embodiment, when the counter is updated, the local garbage collection controller can perform a pattern determination operation.

[0013] In one embodiment, the localized waste collection controller can determine its operation based on a periodic execution pattern during a first reference time period.

[0014] In an embodiment, when there is a second time period in which the memory device operates in a garbage collection operation mode different from the garbage collection operation mode of the first time period, the local garbage collection controller can compare the first throughput of the memory device during the first time period with the second throughput of the memory device during the second time period. When the first throughput is not greater than the second throughput, the garbage collection operation mode during the third time period after the second time period can be kept the same as the garbage collection operation mode of the second time period. The second time period can be after the first time period.

[0015] In an embodiment, when the first throughput is greater than the second throughput, the local garbage collection controller can switch the garbage collection operation mode of the third time period to be the same as the garbage collection operation mode of the first time period.

[0016] In an embodiment, the first throughput may be the Direct Memory Access (DMA) count of the memory device per unit time during a first time period, and the second throughput may be the DMA count of the memory device per unit time during a second time period.

[0017] In the embodiment, when the garbage collection operation mode during the third time period is the first mode, the local garbage collection controller can increase the reference value, and when the garbage collection operation mode during the third time period is the second mode, the local garbage collection controller can decrease the reference value.

[0018] In an embodiment, when a first time period and a second time period exist, the local garbage collection controller can periodically perform a mode switching operation to determine the garbage collection operation mode based on the first throughput and the second throughput.

[0019] In one embodiment, the localized waste collection controller may periodically perform mode switching operations based on a second reference time period.

[0020] According to embodiments of the present disclosure, a method for controlling a garbage collection operation mode of a memory device including a plurality of memory blocks can be provided. The method may include: generating a counter table including counts corresponding to indices grouped into multiple logical page numbers in units of data of a specific size; incrementing the count of the index corresponding to a write command when a write command is received from a host; calculating a percentage value corresponding to the index based on the count; and determining a garbage collection operation mode based on the percentage value to perform a locality-based garbage collection operation.

[0021] In an embodiment, calculating the percentage value may include calculating the percentage value when the number of memory blocks managed by the memory controller remains constant.

[0022] In an embodiment, determining the garbage collection operation mode as a mode that performs garbage collection operations considering locality based on a percentage value may include: comparing the percentage value with a reference value; determining the garbage collection operation mode as a first mode when the percentage value does not exceed the reference value; and determining the garbage collection operation mode as a second mode when at least one of the percentage values ​​exceeds the reference value, wherein the first mode may be a mode that performs garbage collection operations without considering locality, and the second mode may be a mode that performs garbage collection operations considering locality.

[0023] In an embodiment, the method may further include: when there is a second time period in which the memory device operates in a second garbage collection operation mode different from the first garbage collection operation mode of the first time period, comparing the first throughput of the memory device during the first time period with the second throughput of the memory device during the second time period; and when the first throughput is not greater than the second throughput, maintaining the garbage collection operation mode of a third time period after the second time period as the same as the garbage collection operation mode of the second time period, and the second time period may be after the first time period.

[0024] In an embodiment, the method may further include switching the garbage collection operation mode of the third time period to the same as the garbage collection operation mode of the first time period when the first throughput is greater than the second throughput.

[0025] In an embodiment, the method may further include increasing the reference value when the garbage collection operation mode during the third time period is the first mode.

[0026] In an embodiment, the method may further include reducing the reference value when the garbage collection operation mode during the third time period is the second mode. Attached Figure Description

[0027] Figure 1 This is a block diagram of an electronic system according to an embodiment of the present disclosure; Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 Detailed block diagram of the memory controller; Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 Detailed block diagram of the non-volatile memory device; Figure 4 This is a diagram illustrating the operation of the counter; Figure 5 This is a diagram illustrating the mode determination operation of a localized waste collection controller; Figure 6This is a block diagram illustrating the pattern determination operation of the local garbage collection module; Figure 7 This is a diagram illustrating the operation of a localized waste collection controller over time; Figure 8 This is a diagram illustrating the operation of a localized waste collection controller over time; Figure 9 This is a flowchart illustrating the mode determination operation of a localized waste collection controller; Figure 10 This is a flowchart illustrating the mode switching operation of a localized waste collection controller; Figure 11 This is a block diagram illustrating a memory card system employing a storage device according to an embodiment of the present disclosure; and Figure 12 This is a block diagram illustrating, by way of example, a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0028] Hereinafter, embodiments according to the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure may be described, and descriptions of other parts may be omitted so as not to obscure the subject matter of the disclosure. Furthermore, the present disclosure may be implemented in other forms and is not limited to the embodiments described herein. However, embodiments of the present disclosure have been described in detail so that those skilled in the art can readily implement the technical spirit of the present disclosure.

[0029] The terminology used herein is for describing particular embodiments and is not intended to limit this disclosure. Throughout the specification, where a section "includes" a component, that section may further include another component without excluding it, unless otherwise stated. "At least any one of X, Y, or Z" and "at least any one selected from the group including X, Y, or Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, and ZZ). Here, "and / or" includes all combinations of one or more corresponding configurations.

[0030] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Thus, "first component" may refer to "second component" without departing from the scope of this disclosure.

[0031] In this field, various embodiments are described and illustrated in the accompanying drawings based on functional blocks, units, components, and / or modules. Those skilled in the art will understand that these blocks, units, components, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, line connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, components, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software.

[0032] Furthermore, each block, unit, component, and / or module may be implemented by dedicated hardware, or by a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmable microprocessors and associated circuitry) performing other functions. Additionally, without departing from the scope of this disclosure, each block, unit, component, and / or module of some embodiments may be physically divided into two or more interacting and separate blocks, units, components, and / or modules. Furthermore, without departing from the scope of this disclosure, the blocks, units, components, and / or modules of some embodiments may be physically combined into more complex blocks, units, components, and / or modules.

[0033] Figure 1 This is a block diagram of an electronic system 10 according to an embodiment of the present disclosure.

[0034] Reference Figure 1 The electronic system 10 may be a computing system configured to process various types of information and / or store the processed information as data. In some embodiments, the electronic system 10 may be implemented as a personal computer (PC), a laptop, a portable computer, a server, a workstation, a tablet PC, a smartphone, a digital camera, a dashcam, etc.

[0035] Electronic system 10 may include host 11 and storage device 12. Host 11 can control various operations of electronic system 10. More specifically, host 11 can control the operation of other components constituting electronic system 10. Host 11 may be implemented as a general-purpose processor, special-purpose processor, central processing unit (CPU), or application processor (AP).

[0036] The host 11 can communicate with the storage device 12. For example, the host 11 can request the storage device 12 to perform programming operations, reading operations, erasing operations, etc. For programming operations on the storage device 12, the host 11 can send a host request, data, and a logical address to the storage device 12. For reading operations on the storage device 12, the host 11 can send a host request and a logical address to the storage device 12.

[0037] Storage device 12 can store data. For example, storage device 12 can store data under the control of host 11. In some embodiments, storage device 12 may include at least one of solid-state drive (SSD), embedded memory, or removable external memory.

[0038] When storage device 12 is an SSD, it may be a device compliant with the High Speed ​​Non-Volatile Memory (NVMe) standard. When storage device 12 is embedded memory or removable external memory, it may be a device compliant with the Universal Flash Memory (UFS) or Embedded Multimedia Card (eMMC) standard. Host 11 and storage device 12 may each generate data packets based on the adopted standard protocol and transmit the generated data packets to each other.

[0039] Storage device 12 may include memory controller 100 and memory device 200. Memory controller 100 can control the operation of storage device 12. For example, memory controller 100 can control the operation of storage device 12 according to internal policies or in response to requests from host 11. Memory controller 100 can store data in memory device 200 or read data stored in memory device 200 according to internal policies or in response to requests from host 11.

[0040] In response to a host request corresponding to a programming operation received from host 11, memory controller 100 can generate a programming command and provide the generated programming command to memory device 200. In response to a host request corresponding to a read operation received from host 11, memory controller 100 can generate a command and provide the generated command to memory device 200. Memory controller 100 can also transmit data read from memory device 200 to host 11.

[0041] The memory device 200 can store data under the control of the memory controller 100. The memory device 200 may include a plurality of memory blocks BLK1 to BLKn. Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of memory cells, which may form a plurality of strings or a plurality of pages. In some embodiments, a page may be a unit for storing data in the memory device 200 or for retrieving data stored in the memory device 200. A memory block may be a unit for erasing data stored in the memory device 200.

[0042] The memory device 200 can move or copy data within itself to perform various functions. For example, the memory device 200 can move or copy data stored in a first memory block to a second memory block to perform at least one of a garbage collection operation, a read-to-reclaim operation, a read-to-refresh operation, a wear-leveling operation, or an overprovisioning operation.

[0043] The memory device 200 can perform garbage collection operations or partial garbage collection operations.

[0044] Garbage collection operations may involve copying valid data contained in bad blocks within a storage block to free blocks within the storage block, and erasing invalid data contained in bad blocks.

[0045] A locality-based garbage collection operation can be a garbage collection operation that takes into account (e.g., performs the operation based on determination) locality. More specifically, a locality-based garbage collection operation can assume that logical blocks that have recently been invalidated (e.g., within a predetermined time span) are likely to be local, and can perform garbage collection by excluding these blocks from the selection of sacrifice blocks for the garbage collection operation. In the example, a locality-based garbage collection operation can exclude most recently invalidated blocks with predetermined exceptions for some recently invalidated blocks (i.e., garbage collection is still performed on these blocks even though they are local).

[0046] When the memory device 200 is determined (or programmed, instructed) to perform localized garbage collection operations during the manufacture of the conventional storage device 12, the memory device 200 may be unable to perform normal garbage collection operations that do not take locality into account.

[0047] Therefore, the memory device 200 performing local garbage collection operations may only perform local garbage collection operations, regardless of the actual workload. For example, when the memory device 200 is programmed to perform local garbage collection operations, it may still be necessary to perform local garbage collection operations even if the memory device 200 performs an operation to write data to a random address, making local garbage collection operations unnecessary. This unnecessary garbage collection may increase the write amplification factor (WAF).

[0048] Although the parameters of the local garbage collection operation (e.g., the number of logic blocks excluded from the sacrifice selection) can be adjusted to take into account the actual workload of the memory device 200, there may be limitations that prevent the local garbage collection operation from supporting all the various workloads.

[0049] In other words, the optimal efficiency of storage device 12 may need to be determined by considering the actual workload of storage device 200 to determine whether to perform local garbage collection operations.

[0050] The memory device 200 may be a NAND flash memory, but the scope of this disclosure is not limited thereto. The memory device 200 may be one of a variety of memory devices that can retain stored data even when the power is interrupted, such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM) devices.

[0051] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 Detailed block diagram of the memory controller 100.

[0052] Reference Figure 1 and Figure 2 The memory controller 100 can communicate with the host 11 and the non-volatile memory device 200. The memory controller 100 may include a local garbage collection (GC) module 110, a volatile memory device 120, a processor 130, a read-only memory (ROM) 140, an error correction code (ECC) engine 150, a host interface circuit 160, and a non-volatile memory interface circuit 170.

[0053] The local garbage collection module 110 may include a counter 111 and a local garbage collection (GC) controller 112. In some embodiments, the local garbage collection module 110 may be implemented as firmware. For example, the non-volatile memory device 200 may store instructions corresponding to the local garbage collection module 110. The processor 130 may load the instructions from the non-volatile memory device 200 into the volatile memory device 120. By executing the loaded instructions, the processor 130 may operate the local garbage collection module 110.

[0054] The local garbage collection module 110 can control the operating mode of the memory device 200 based on write commands received from the host 11. The operating mode may include a first mode and a second mode, wherein the first mode performs garbage collection operations without considering locality, and the second mode performs local garbage collection operations that do consider locality.

[0055] Whenever a write command is received from host 11, the host interface layer (HIL) 132 of processor 130 can convert the received write command into the corresponding logical page number.

[0056] Counter 111 can be implemented as hardware circuitry and can manage logical page numbers in units of specific data sizes. For example, counter 111 can generate a count table and store the count table in a memory area such as volatile memory device 120. The count table can group logical page numbers in 1 GB units. Index 0 of the count table can correspond to logical page numbers from 0 GB to 1 GB, and index 1 can correspond to logical page numbers from 1 GB to 2 GB. Counter 111 can increment the count of the index corresponding to the logical page number obtained through a write command.

[0057] The local garbage collection controller 112 can perform a mode determination operation and a mode switching operation. The mode determination operation can be an operation that determines the operating mode of the memory device 200 as one of a first mode and a second mode based on a counting table, and the mode switching operation can be an operation that keeps the operating mode of the memory device 200 in the previous operating mode or switches the operating mode to a different operating mode.

[0058] A more detailed description of counter 111 and local garbage collection controller 112 will be provided below. Figures 4 to 10 To describe.

[0059] The volatile memory device 120 can be used as the main memory, cache memory, or operational memory of the memory controller 100. For example, the volatile memory device 120 can be implemented as static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0060] Processor 130 can control various operations of memory controller 100. Processor 130 can run firmware to control the operation of memory controller 100. Processor 130 can execute (run) firmware loaded into volatile memory device 120 at startup to control various operations of memory controller 100 and perform logical operations.

[0061] Firmware is a program that runs within storage device 12 and may include various functional layers. For example, firmware may include one or more of the following: a flash translation layer (FTL) 131 for translating between the logical address requested by host 11 from storage device 12 and the physical address of memory device 200; a host interface layer (HIL) 132 for interpreting commands requested by host 11 from memory device 200 and passing the commands to FTL 131; and a flash interface layer (FIL) for passing commands indicated by FTL 131 to memory device 200.

[0062] ROM 140 can be used as a read-only memory to store information used in the operation of memory controller 100. ECC engine 150 can detect and correct errors in data read from non-volatile memory device 200. For example, ECC engine 150 can have a predetermined level of error correction capability. ECC engine 150 can treat data whose error level (e.g., the number of flip bits) exceeds the error correction capability as uncorrectable data.

[0063] The memory controller 100 can communicate with the host 11 via the host interface circuitry 160. In some embodiments, the host interface circuitry 160 can be implemented based on at least one of a variety of interfaces such as: Serial Advanced Technology Attachment (SATA) interface, High Speed ​​Peripheral Component Interconnect (PCIe) interface, Serial Attached Small Computer System Interface (SAS), Embedded Multimedia Card (eMMC) interface, Universal Flash Memory (UFS) interface, etc.

[0064] The memory controller 100 can communicate with the non-volatile memory device 200 via the non-volatile memory interface circuit 170. In some embodiments, the non-volatile memory interface circuit 170 can be implemented based on a NAND flash interface such as Toggle, Open NAND Flash Interface (ONFI), etc.

[0065] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 Detailed block diagram of the non-volatile memory device 200.

[0066] Reference Figure 3 The non-volatile memory device 200 may include a memory cell array 210, an address decoding circuit 220, a voltage generation circuit 230, a page buffer circuit 240, an input / output circuit 250, and a control logic circuit 260.

[0067] In some embodiments, the non-volatile memory device 200 may be a non-volatile memory device based on NAND flash memory. However, the scope of this disclosure is not limited thereto, and the non-volatile memory device 200 may be one of various types of memory devices, such as DRAM, SRAM, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0068] The memory cell array 210 may include multiple memory blocks. The multiple memory blocks may be referenced... Figure 1The description includes multiple memory blocks BLK1 to BLKn. Each of the multiple memory blocks may include multiple cell strings. Each of the multiple cell strings may be connected to the address decoding circuit 220 via row lines and to the page buffer circuit 240 via bit lines BL. The row lines may include a drain select line DSL, a word line WL, and a source select line SSL.

[0069] Each of the multiple cell strings may include multiple memory cells. Each memory cell may correspond to a multiple cell transistor connected in series between the bit line BL and the select line. The multiple cell transistors may be connected to the drain select line DSL, the word line WL, and the source select line SSL.

[0070] In this embodiment, the address decoding circuit 220, voltage generation circuit 230, page buffer circuit 240, and input / output circuit 250 can be collectively referred to as peripheral circuitry. The peripheral circuitry can drive the memory cell array 210 under the control of the control logic circuit 260. The peripheral circuitry can drive the memory cell array 210 to perform programming, reading, and erasing operations.

[0071] Address decoding circuit 220 can be connected to memory cell array 210 via row lines. Address decoding circuit 220 can receive address ADDR from control logic circuit 260. Address decoding circuit 220 can decode the block address in the received address ADDR. Address decoding circuit 220 can select at least one memory block from a plurality of memory blocks based on the decoded block address.

[0072] Address decoding circuit 220 can decode the row address in the received address ADDR. Address decoding circuit 220 can select at least one word line from the word lines of the selected memory block based on the decoded row address. In this embodiment, address decoding circuit 220 can decode the column address in the received address ADDR. Address decoding circuit 220 can connect input / output circuit 250 and memory cell array 210 according to the decoded column address.

[0073] The voltage generation circuit 230 can generate various voltages for the operation of the non-volatile memory device 200. For example, the voltage generation circuit 230 can generate various voltages based on the power supply voltage VCC, such as multiple programming voltages, multiple pass voltages, multiple verification voltages, multiple select read voltages, multiple unselect read voltages, multiple erase voltages, and multiple erase verification voltages.

[0074] Page buffer circuit 240 can be connected to memory cell array 210 via bit line BL. Page buffer circuit 240 can read data stored in memory cell array 210 by detecting voltage changes on bit line BL, and can temporarily store the read data. Page buffer circuit 240 can receive data from input / output circuit 250, and can store data in memory cell array 210 by controlling bit line BL based on the received data.

[0075] Input / output circuit 250 can transmit data DATA to and receive data DATA from an external device (e.g., a memory controller). For example, input / output circuit 250 can receive data DATA from an external device and pass the received data DATA to page buffer circuit 240. Input / output circuit 250 can also receive data DATA from page buffer circuit 240 and pass the received data DATA to an external device.

[0076] The control logic circuit 260 can control various operations of the non-volatile memory device 200. For example, the control logic circuit 260 can receive commands CMD and addresses ADDR from external devices (e.g., memory controllers) and generate control signals in response to commands CMD and addresses ADDR to control peripheral circuits.

[0077] Figure 4 This is a diagram illustrating the operation of counter 111.

[0078] exist Figure 4 The document describes an operation in which, upon receiving a write command from host 11, Figure 2 Counter 111 groups and manages logical page numbers obtained through conversion write commands in units of data of a specific size.

[0079] Host 11 can write data to or read data from storage device 12 based on multiple namespaces. A namespace can be a logical unit used to divide the data storage space of storage device 12. Each of the multiple namespaces can include multiple logical block addresses.

[0080] Reference Figure 4 Host 11 (see Figure 4The host view portion can manage the data storage space of storage device 12 based on the first namespace NS1 to the third namespace NS3. The first namespace NS1 can include the first logical block address LBA1_1 to the m-th logical block address LBAAm_1, the second namespace NS2 can include the first logical block address LBA1_2 to the k-th logical block address LBAk_2, and the third namespace NS3 can include the first logical block address LBA1_3 to the i-th logical block address LBAi_3. m, k, and i are natural numbers greater than 1.

[0081] When a write command is received from host 11, processor 130's HIL 132 (see Figure 4 The HIL view portion can translate the logical block address corresponding to the write command into a logical page number (LPN) managed by the memory device 200. The memory device 200 can then write data to the location corresponding to the logical page number.

[0082] HIL 132 can manage the data storage space of memory device 200 based on the first logical page number LPN1 to the qth logical page number LPNq. j, o, p, and q are natural numbers greater than 1, o can be greater than j, p can be greater than o, and q can be greater than p.

[0083] HIL 132 can manage multiple logical pages based on logical page numbers from LPN1 to LPNq. Each of the multiple storage blocks can include multiple logical pages. A logical page is a unit used to read or write data in a logical address space, and a logical page can be mapped to a physical storage block.

[0084] Counter 111 (see Figure 4 The local GC module view portion can manage logical page numbers managed by HIL 132 in units of data of specific sizes. For example, counter 111 can generate a count table CT that groups logical page numbers in 1 GB units. Index 0 of the count table CT can group logical page numbers corresponding to 0 GB to 1 GB, and index 1 can group logical page numbers corresponding to 1 GB to 2 GB. When HIL 132 translates a logical block address corresponding to a write command into a logical page number, counter 111 can increment the count of the index corresponding to that logical page number.

[0085] In the following text, refer to Figure 4 This describes the operation of the HIL 132 of the processor 130 and the counter 111 of the local garbage collection module 110 when a write command is received from the host 11.

[0086] Reference Figure 4 When the host 11 receives a write command corresponding to the first logical block address LBA1_1, the HIL132 can convert the first logical block address LBA1_1 into the first logical page number LPN1.

[0087] Similarly, the arrow between the host view and the HIL 132 view indicates the following operation: when a write command is received from host 11, HIL 132 converts the logical block address corresponding to the write command into a logical page number.

[0088] Reference Figure 4 The logical page size is 512 bytes, and counter 111 can group logical page numbers in units of 1 GB. When a write command corresponding to the first logical page number LPN1 is received, counter 111 can increment the count at index 0. When a write command corresponding to the fourth logical page number LPN4 is received, counter 111 can increment the count at index 0.

[0089] Similarly, the arrow between the HIL 132 view and the local garbage collection module view can indicate the operation of increasing the count of the index corresponding to the logical page number.

[0090] Reference Figure 4 In the counting table CT, the count for index 0 can be 7200, the count for index 5 can be 130, the count for index 6 can be 10, and the count for index 1000 can be 1211.

[0091] exist Figure 4 In this embodiment, counter 111 groups logical page numbers in units of 1 GB, but this disclosure is not limited to this, and according to the embodiments, counter 111 can group logical page numbers in units of various sizes of data.

[0092] Figure 5 This is a diagram illustrating the mode determination operation of the localized waste collection controller 112.

[0093] exist Figure 5 In the middle, it is described by Figure 2 The localized waste collection controller 112 performs the mode determination operation.

[0094] The local garbage collection controller 112 can initiate a mode determination operation based on receiving a mode control request from the FTL 131 of the processor 130. The mode control request can be used as a start signal to request the local garbage collection controller 112 to continue performing the mode control operation.

[0095] When FTL 131 determines that the number of storage blocks managed by FTL 131 remains constant, FTL 131 may send a mode control request to the local garbage collection controller 112.

[0096] For example, when the number of allocated storage blocks remains constant, or when the number of storage blocks to which data is written remains constant, FTL 131 may send a mode control request to the local garbage collection controller 112.

[0097] Before receiving a mode control request, the local garbage collection controller 112 may not perform mode control operations. After receiving a mode control request, the local garbage collection controller 112 may periodically perform mode control operations.

[0098] In other words, after receiving a mode control request, the local garbage collection controller 112 can periodically perform mode determination and mode switching operations.

[0099] In this embodiment, upon receiving a mode control request, the local garbage collection controller 112 may first perform a mode determination operation during the mode control operation. The mode determination operation of the local garbage collection controller 112 is described below.

[0100] The local garbage collection controller 112 can calculate a percentage value for each index based on the counts in the counter table CT. When at least one of the multiple percentage values ​​exceeds a reference value, the local garbage collection controller 112 can determine the operating mode of the memory device 200 as a second mode. When none of the multiple percentage values ​​exceeds the reference value, the local garbage collection controller 112 can determine the operating mode of the memory device 200 as a first mode.

[0101] In other words, the locality garbage collection controller 112 can determine that when at least one of the multiple percentage values ​​exceeds a reference value, it is necessary to consider the locality of the memory device 200 (e.g., issue or initiate an instruction to do so) to perform a garbage collection operation, and when none of the multiple percentage values ​​exceeds the reference value, it is not necessary to consider the locality of the memory device 200 to perform a garbage collection operation.

[0102] Reference Figure 5 By way of example, when the reference value is “30”, the local garbage collection controller 112 can control the memory device 200 to operate in the second mode because the percentage value of index 0 is “84”.

[0103] Although the local garbage collection controller 112 is described herein as determining the operating mode of the memory device 200 by comparing a plurality of percentage values ​​with a reference value, this disclosure is not limited thereto. According to embodiments, the local garbage collection controller 112 may determine the operating mode of the memory device 200 by comparing the maximum value of a plurality of percentage values ​​with a reference value, comparing the variance of a plurality of percentage values ​​with a reference value, or comparing the average of a plurality of percentage values ​​with a reference value.

[0104] In an embodiment, each time the counter table CT is updated, the local garbage collection controller 112 can determine the operating mode of the memory device 200. For example, each time the counter table CT is updated, the local garbage collection controller 112 can calculate a percentage value for each index and determine the operating mode of the memory device 200 based on the calculated percentage value.

[0105] However, this disclosure is not limited thereto, and according to embodiments, the localized garbage collection controller 112 can periodically determine the operating mode of the memory device 200 based on a first reference period. The first reference period can be determined by the host 11.

[0106] In this embodiment, when the local waste collection controller 112 performs a mode determination operation for the first time after receiving a mode control request, the reference value may be received by the host 11, stored in the memory device 200, or stored in... Figure 2 The values ​​in ROM 140 shown.

[0107] When performing a mode switching operation, the local garbage collection controller 112 can change the reference value. (See below for reference.) Figure 7 and Figure 8 Describes the mode switching operation of the localized garbage collection controller 112.

[0108] For reference Figure 5 Based on the count table CT generated by counter 111 by grouping logical page numbers in units of 1 GB, the locality garbage collection controller 112 can determine whether to perform a local garbage collection operation. Therefore, the decision to perform a local garbage collection operation can be made by considering locality based on the workload of the storage device 12.

[0109] Furthermore, since the local garbage collection controller 112 periodically performs a mode determination operation after receiving a mode control request, the operating mode of the memory device 200 may not be fixed to one of the first mode and the second mode, but may be dynamically determined to be the first mode or the second mode according to the workload of the memory device 12.

[0110] Therefore, unnecessary local garbage collection operations can be avoided, and the efficiency of garbage collection operations can be improved.

[0111] Figure 6 This is a block diagram illustrating the mode determination operation of the local garbage collection module 110.

[0112] Reference Figure 2 and Figure 6 When a mode control request MR is received from FTL 131, the local garbage collection controller 112 can initiate mode control operation.

[0113] For ease of description, only the description required for pattern determination operations related to FTL 131 and HIL 132 is provided. However, in addition to the above, [further details are needed]. Figure 6 In addition to the operations described, FTL 131 and HIL 132 can also perform various other operations. Counter 111 can manage logical page numbers managed by HIL 132 in units of data of a specific size. Counter 111 can generate a count table CT, which groups logical page numbers in units of a specific size.

[0114] In operation ①, when HIL 132 converts the logical block address corresponding to the write command received from the host into a logical page number, counter 111 can increment the count of the index corresponding to the logical page number obtained by converting the logical block address.

[0115] In operation ②, when FTL 131 determines that the number of storage blocks managed by FTL 131 remains constant, FTL 131 may send a mode control request MR to the local garbage collection controller 112.

[0116] In operation ③, the local garbage collection controller 112 may initiate a mode control operation based on receiving a mode control request MR from the FTL 131. In an embodiment, when the local garbage collection controller 112 initiates the mode control operation, the local garbage collection controller 112 may first perform a mode determination operation to determine whether the operating mode of the memory device 200 is a first mode or a second mode based on the count in the counter table CT.

[0117] Figure 7 This is a diagram illustrating the operation of the localized waste collection controller 112 over time.

[0118] exist Figure 7 The operation of the localized waste collection controller 112 during the first time period P1 to the fourth time period P4 is shown in the figure.

[0119] The first time period P1 corresponds to the period preceding the Receive Mode Control Request (MR), during which the local garbage collection controller 112 may not perform mode determination operations. However, during the first time period P1, when Figure 6 When HIL132 translates the logical block address corresponding to the write command received from the host into a logical page number, counter 111 can increment the count of the index corresponding to the logical page number obtained by translating the logical block address.

[0120] When the local garbage collection controller 112 receives a mode control request MR from FTL 131 at time t2, it can perform a mode determination operation.

[0121] During the second time period P2 between time point t2 and time point t3, the local garbage collection controller 112 can determine the operating mode of the memory device 200 as the second mode. The second time period P2 can be after the first time period P1.

[0122] In an embodiment, the second time period P2 may be the following time period: during this time period, the local garbage collection controller 112 determines the operating mode of the memory device 200 to the second mode at time point t2, and the memory device 200 operates in the second mode.

[0123] In other embodiments, the second time period P2 may be a repeating time period during which the local garbage collection controller 112 periodically determines the operating mode of the memory device 200 as a second mode, and the time period during which the memory device 200 operates in the second mode is shorter than the second time period P2.

[0124] During the third time period P3 between time point t3 and time point t4, the local garbage collection controller 112 can determine the operating mode of the memory device 200 as the first mode. The third time period P3 can occur after the second time period P2.

[0125] In an embodiment, the third time period P3 may be the following time period: during this time period, the local garbage collection controller 112 determines the operating mode of the memory device 200 to the first mode at time point t3, and the memory device 200 operates in the first mode.

[0126] In other embodiments, the third time period P3 may be a repeating time period during which the local garbage collection controller 112 periodically determines the operating mode of the memory device 200 as a first mode, and the time period during which the memory device 200 operates in the first mode is shorter than the third time period P3.

[0127] At time t4, the local garbage collection controller 112 may perform a mode switching operation. The mode switching operation may be as follows: by comparing the throughput during each period when there is a period when the memory device 200 operates in a first mode and a period when the memory device 200 operates in a second mode, it is determined whether to maintain the previous mode or switch to another mode.

[0128] In an embodiment, the local garbage collection controller 112 can compare the first throughput TP1 of the memory device 200 during the second time period P2 with the second throughput TP2 of the memory device 200 during the third time period P3.

[0129] When the second throughput TP2 is greater than the first throughput TP1, the local garbage collection controller 112 can maintain the operating mode of the memory device 200 during the fourth time period P4 after time point t4 as the previous mode (i.e., the first mode during the third time period P3). The fourth time period P4 can be after the third time period P3.

[0130] In other words, the locality garbage collection controller 112 can determine that it is unnecessary to perform locality-considered garbage collection because the throughput of the memory device 200 during the third time period P3 when performing garbage collection without considering locality is greater than the throughput of the memory device 200 during the second time period P2 when performing garbage collection with locality considered.

[0131] Furthermore, when the second throughput TP2 is greater than the first throughput TP1, the local garbage collection controller 112 can increase the reference value after time point t4. For example, if the reference value before time point t4 is "30", the reference value after time point t4 can be "40". When performing a mode determination operation after time point t4, the local garbage collection controller 112 can determine the operating mode of the memory device 200 based on the increased reference value.

[0132] In an embodiment, when the amount of data transmitted from the memory device 200 to the host 11 per unit time during the second time period P2 is not greater than the amount of data transmitted from the memory device 200 to the host 11 per unit time during the third time period P3, the local garbage collection controller 112 can maintain the operating mode of the memory device 200 in the first mode during the fourth time period P4 after time point t4.

[0133] For example, if the direct memory access (DMA) count per unit time during the second time period P2 is not greater than the DMA count per unit time during the third time period P3, the operating mode of the memory device 200 can remain in the first mode during the fourth time period P4 after time point t4.

[0134] In an embodiment, the fourth time period P4 may be the following time period: during this time period, the local garbage collection controller 112 maintains the operating mode of the memory device 200 in the first mode at time point t4, and the memory device 200 operates in the first mode.

[0135] In other embodiments, the fourth time period P4 may be a repeating time period during which the local garbage collection controller 112 maintains the operating mode of the memory device 200 in the first mode at time point t4, and then periodically determines the operating mode of the memory device 200 in the first mode, wherein the time period during which the memory device 200 operates in the first mode is shorter than the fourth time period P4.

[0136] In other words, after the local garbage collection controller 112 performs a mode switching operation at time point t4, the local garbage collection controller 112 can periodically perform a mode determination operation during the time period between time point t4 and time point t5.

[0137] Reference Figure 7 The illustration shows a local garbage collection controller 112 performing a mode switching operation at time point t4, but this is only one embodiment of the present disclosure. In an embodiment, the local garbage collection controller 112 may perform the mode switching operation at at least one time point in a third time period P3 (i.e., before the end of the third time period P3), and determine to maintain the operating mode as the first mode.

[0138] Figure 8 This is a diagram illustrating the operation of the localized waste collection controller 112 over time.

[0139] exist Figure 8 The operation of the localized waste collection controller 112 during the first time period P1 to the fourth time period P4 is shown in the figure.

[0140] Figure 8 The first time period P1 to the third time period P3 are similar Figure 7 The first time period P1 to the third time period P3 are omitted, therefore repeated descriptions are omitted.

[0141] At time point t4, the local garbage collection controller 112 may perform a mode switching operation. In an embodiment, at time point t4, the local garbage collection controller 112 may compare the first throughput TP1 of the memory device 200 during the second time period P2 with the second throughput TP2 of the memory device 200 during the third time period P3.

[0142] When the second throughput TP2 is less than the first throughput TP1, the local garbage collection controller 112 can switch the operating mode of the memory device 200 during the fourth time period P4 after time point t4 to a second mode, which is different from the previous mode (i.e., the first mode during the third time period P3).

[0143] In other words, the locality garbage collection controller 112 can determine that it is necessary to perform locality-considered garbage collection because the throughput of the memory device 200 during the third time period P3 when performing garbage collection without considering locality is less than the throughput of the memory device 200 during the second time period P2 when performing garbage collection with locality considered.

[0144] Furthermore, when the second throughput TP2 is less than the first throughput TP1, the local garbage collection controller 112 can decrease the reference value after time point t4. For example, if the reference value before time point t4 is "30", the reference value after time point t4 can be "20". When performing a mode determination operation after time point t4, the local garbage collection controller 112 can determine the operating mode of the memory device 200 based on the decreased reference value.

[0145] In an embodiment, when the amount of data transmitted from the memory device 200 to the host 11 per unit time during the second time period P2 is greater than the amount of data transmitted from the memory device 200 to the host 11 per unit time during the third time period P3, the local garbage collection controller 112 can switch the operating mode of the memory device 200 to the second mode during the fourth time period P4 after time point t4.

[0146] For example, when the direct memory access (DMA) count per unit time during the second time period P2 is greater than the DMA count per unit time during the third time period P3, the operating mode of the memory device 200 can be switched to the second mode during the fourth time period P4 after time point t4.

[0147] In an embodiment, the fourth time period P4 may be the following time period: during which the local garbage collection controller 112 switches the operating mode of the memory device 200 to the second mode at time point t4, and the memory device 200 operates in the second mode.

[0148] In other embodiments, the fourth time period P4 may be a repeating time period during which the local garbage collection controller 112 switches the operating mode of the memory device 200 to the second mode at time point t4, and then periodically determines the operating mode of the memory device 200 to the second mode, wherein the time period during which the memory device 200 operates in the second mode is shorter than the fourth time period P4.

[0149] In other words, after the local garbage collection controller 112 performs a mode switching operation at time point t4, the local garbage collection controller 112 can periodically perform a mode determination operation during the time period between time point t4 and time point t5.

[0150] Reference Figure 8 The illustration shows a local garbage collection controller 112 performing a mode switching operation at time point t4, but this is only one embodiment of the present disclosure. In embodiments, the local garbage collection controller 112 may perform a mode switching operation at at least one time point in a third time period P3, and determine to maintain the operating mode as a first mode. The local garbage collection controller 112 may perform mode switching operations at multiple time points in the third time period P3, and may switch between operating modes multiple times (e.g., based on the performance of the storage device 12 according to the workload).

[0151] Already referred to Figure 7 and Figure 8 The first time period P1 to the fourth time period P4 are described, but the length of each time period is not limited to... Figure 7 and Figure 8 The embodiments shown are examples of embodiments of this disclosure and may vary.

[0152] In addition, Figure 7 and Figure 8 The diagram shows that the memory device 200 operates in a second mode during a second time period P2 and in a first mode during a third time period P3. However, this disclosure is not limited thereto; the memory device 200 may operate in the first mode during the second time period P2 and in the second mode during the third time period P3.

[0153] For reference Figure 7 and 8 As described, the local garbage collection controller 112 can determine whether to maintain the previous operating mode or switch to a different operating mode based on throughput. Therefore, the decision to perform a local garbage collection operation can be made by considering the performance of the storage device 12 based on the workload.

[0154] Furthermore, since the local garbage collection controller 112 determines the operation based on a reference value for the throughput change pattern, the workload can be appropriately reflected in the pattern determination operation. Therefore, unnecessary local garbage collection operations can be avoided, and the efficiency of garbage collection operations can be improved.

[0155] Figure 9 This is a flowchart illustrating the mode determination operation of the localized waste collection controller 112.

[0156] exist Figure 9 In the middle, it is shown that by Figure 2 The mode determination operation is performed by the local waste collection controller 112 to control the mode.

[0157] In operation S110, the local garbage collection controller 112 can determine whether it has received a mode control request from FTL 131. When the local garbage collection controller 112 receives a mode control request, it can perform operation S120. When the local garbage collection controller 112 does not receive a mode control request, it may not perform the mode determination operation.

[0158] In this embodiment, before operating S110, Figure 2 Counter 111 can generate a counter table and increment the count of the index corresponding to the write command received from the host.

[0159] In operation S120, the local garbage collection controller 112 can calculate the percentage value for each index based on the counting table.

[0160] In operation S130, the local garbage collection controller 112 can determine whether at least one of the percentage values ​​exceeds a reference value. When at least one of the percentage values ​​exceeds the reference value, the local garbage collection controller 112 can perform operation S140. When no percentage value exceeds the reference value, the local garbage collection controller 112 can perform operation S150.

[0161] During operation S140, the local garbage collection controller 112 can determine the operating mode of the memory device 200 as the second mode.

[0162] During operation S150, the local garbage collection controller 112 can determine the operating mode of the memory device 200 as the first mode.

[0163] Reference Figure 9 The illustration shows the local garbage collection controller 112 performing a pattern determination operation once, but this disclosure is not limited thereto, and the local garbage collection controller 112 may periodically repeat operations S120 to S150 after receiving a pattern control request from FTL 131. For example, after running operation S140 or operation S150, the process may return to operation S120 within the same time period based on, for example, predetermined factors.

[0164] In an embodiment, the localized garbage collection controller 112 may perform operations S120 to S150 each time the counter is updated, or may perform operations S120 to S150 during each first reference period.

[0165] Figure 10 This is a flowchart illustrating the mode switching operation of the localized waste collection controller 112.

[0166] exist Figure 10 In the middle, it is described by Figure 2 The mode switching operation performed by the local waste collection controller 112 is a mode control operation.

[0167] During operation S210, the local garbage collection controller 112 can check whether there is a second time period during which the memory device 200 operates in an operating mode different from the operating mode during the first time period.

[0168] When there is a second time period in which the memory device 200 operates in an operating mode different from the first time period, the local garbage collection controller 112 may execute operation S220. When there is no second time period in which the memory device 200 operates in an operating mode different from the first time period, the local garbage collection controller 112 may not execute the mode switching operation.

[0169] For example, refer to Figure 7 At a time point after time point t3, the local garbage collection controller 112 may perform a mode switching operation. At a time point in the second time period P2 between time point t2 and time point t3, the local garbage collection controller 112 may not perform a mode switching operation.

[0170] In operation S220, the local garbage collection controller 112 can determine whether the throughput during the first time period is greater than the throughput during the second time period. When the throughput during the first time period is greater than the throughput during the second time period, the local garbage collection controller 112 can execute operation S230. When the throughput during the first time period is not greater than the throughput during the second time period, the local garbage collection controller 112 can execute operation S240.

[0171] During operation S230, the local garbage collection controller 112 can switch the operating mode of the memory device 200 to the operating mode during the first time period.

[0172] During operation S240, the local garbage collection controller 112 can maintain the operating mode of the memory device 200 as the operating mode during the second time period.

[0173] During operation S250, the localized garbage collection controller 112 can change the reference value. In an embodiment, when the switched operating mode is the second mode or the maintained operating mode is the second mode, the reference value can be decreased. When the switched operating mode is the first mode or the maintained operating mode is the first mode, the reference value can be increased.

[0174] Based on the changed reference value after operation S250, the local garbage collection controller 112 can execute the reference... Figure 9 The described pattern determines the operation.

[0175] Reference Figure 10 The illustration shows that the local garbage collection controller 112 performs a mode switching operation once, but the present disclosure is not limited thereto, and when there is a second time period in which the memory device 200 operates in an operating mode different from the operating mode during the first time period, the local garbage collection controller 112 may thereafter periodically repeat operations S220 to S250.

[0176] Reference Figure 9 and Figure 10 The local garbage collection controller 112 can first perform a mode determination operation of the mode control operation, and then perform the mode determination operation and the mode switching operation in parallel.

[0177] In this embodiment, after receiving a mode control request, a mode determination operation can be performed each time the counter table is updated, or the mode determination operation can be performed periodically during each first reference time period. When there is a second time period in which the memory device 200 operates in an operating mode different from the operating mode during the first time period, a mode switching operation can be performed periodically during each second reference time period. The first and second reference time periods can be determined by... Figure 1 and Figure 2 The host 11 receives and stores Figure 2 The memory device 200 or stored in Figure 2 The value in ROM 140.

[0178] Figure 11 This is a block diagram illustrating a memory card system 1000, in which a storage device according to an embodiment of the present disclosure is applied. (Refer to...) Figure 11 The memory card system 1000 may include a memory controller 1100, a memory device 1200, and a connector 1300.

[0179] Memory controller 1100 can be coupled to memory device 1200. Memory controller 1100 can be configured to access memory device 1200. For example, memory controller 1100 can be configured to control read operations, write operations, erase operations, and background operations of memory device 1200. Memory controller 1100 can be configured to provide an interface between memory device 1200 and a host. Memory controller 1100 can be configured to drive firmware for controlling memory device 1200. Memory device 1200 can be compared with reference to... Figure 1 The memory device 200 described is implemented in the same manner.

[0180] For example, the memory controller 1100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error correction circuitry.

[0181] The memory controller 1100 can communicate with external devices via connector 1300. The memory controller 1100 can communicate with external devices (e.g., a host) based on a specific communication protocol. For example, the memory controller 1100 can communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-e), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe). For example, connector 1300 can be defined by at least one of the aforementioned communication protocols.

[0182] For example, the memory device 1200 can be implemented as one of a variety of non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0183] The memory controller 1100 and the memory device 1200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the memory device 1200 can be integrated into a single semiconductor device to form memory cards such as: PCMCIA cards, compact flash (CF) cards, smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC, eMMC), SD cards (SD, mini SD, micro SD, SDHC), or universal flash memory (UFS).

[0184] The memory controller 1100 can execute reference Figures 1 to 10 The described mode control operation.

[0185] For example, memory controller 1100 can control the garbage collection operation mode of memory device 1200. Memory controller 1100 can generate a counter table that includes counts corresponding to indexes grouped into multiple logical page numbers in units of data of a specific size, and can increment the count of the index corresponding to a write command received from the host.

[0186] The memory controller 1100 can calculate a percentage value corresponding to the index based on the count, and can control the garbage collection operation mode of the memory device 1200 based on the percentage value.

[0187] Furthermore, when there is a second time period in which the memory device 1200 operates in a mode different from the garbage collection operation mode during the first time period, the memory controller 1100 can compare the first throughput of the memory device 1200 during the first time period with the second throughput of the memory device 1200 during the second time period.

[0188] When the first throughput is not greater than the second throughput, the memory controller 1100 can maintain the garbage collection operation mode during the third time period following the second time period as the same as the garbage collection operation mode during the second time period. When the first throughput is greater than the second throughput, the memory controller 1100 can switch the garbage collection operation mode during the third time period to be the same as the garbage collection operation mode during the first time period.

[0189] Figure 12 This is a block diagram illustrating a solid-state drive (SSD) system 2000, in which a storage device according to an embodiment of the present disclosure is applied.

[0190] Reference Figure 12The SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 can send and receive signals SIG to and from the host 2100 via signal connector 2001, and receive power PWR via power connector 2002. The SSD 2200 may include an SSD controller 2210, multiple flash memory units 2221 to 222x, an auxiliary power supply 2230, and a cache memory 2240. x is a natural number greater than 1.

[0191] According to an embodiment, the SSD controller 2210 can execute reference... Figures 1 to 10 The functions of the memory controller 100 are described. For example, the SSD controller 2210 can control the garbage collection operation mode of each of the multiple flash memory memories 2221 to 222x.

[0192] The SSD controller 2210 can generate a counter table that includes counts corresponding to indexes grouped by multiple logical page numbers in units of data of a specific size, and can increment the count of the indexes corresponding to write commands received from the host 2100.

[0193] SSD controller 2210 can calculate a percentage value corresponding to an index based on a count, and can control the garbage collection operation mode of each of the multiple flash memory devices 2221 to 222x based on the percentage value.

[0194] Furthermore, when there is a second time period in which multiple flash memory devices 2221 to 222x operate in a mode different from the garbage collection operation mode during the first time period, the SSD controller 2210 can compare the first throughput of the multiple flash memory devices 2221 to 222x during the first time period with the second throughput of the multiple flash memory devices 2221 to 222x during the second time period.

[0195] When the first throughput is not greater than the second throughput, the SSD controller 2210 can maintain the garbage collection operation mode during the third time period following the second time period as the same as the garbage collection operation mode during the second time period. When the first throughput is greater than the second throughput, the SSD controller 2210 can switch the garbage collection operation mode during the third time period to be the same as the garbage collection operation mode during the first time period.

[0196] SSD controller 2210 can control multiple flash memory devices 2221 to 222x in response to a signal SIG received from host 2100. For example, the signal SIG can be based on the interface between host 2100 and SSD 2200. For example, the signal SIG can be defined by at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-e), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) interface.

[0197] Auxiliary power supply 2230 can be connected to host 2100 via power connector 2002. Auxiliary power supply 2230 can receive power PWR from host 2100 and can be charged. When the power supply from host 2100 is unstable, auxiliary power supply 2230 can provide power to SSD 2200. For example, auxiliary power supply 2230 can be located inside SSD 2200 or outside SSD 2200. For example, auxiliary power supply 2230 can be located on the motherboard and can provide auxiliary power to SSD 2200.

[0198] Buffer memory 2240 can operate as a buffer memory for SSD 2200. For example, buffer memory 2240 can temporarily store data received from host 2100 or data received from multiple flash memories 2221 to 222x, or it can temporarily store metadata (e.g., a mapping table) of multiple flash memories 2221 to 222x. Buffer memory 2240 may include volatile memory such as DRAM, Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) SDRAM, Low Power Double Data Rate (LPDDR) SDRAM, or Graphics Random Access Memory (GRAM), or non-volatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0199] The embodiments disclosed herein illustrate the technical spirit of this disclosure, but do not limit it, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and all technical spirit within the equivalent scope should be interpreted as being included within the scope of this disclosure.

[0200] Embodiments of this disclosure may provide a storage device including a memory controller and a method for operating the memory controller, the memory controller dynamically determining whether to perform a local garbage collection operation by considering the actual workload of the storage device, and thus avoiding unnecessary local garbage collection operations and improving the efficiency of garbage collection operations.

Claims

1. A storage device, comprising: A memory device comprising multiple memory blocks; as well as The memory controller controls the garbage collection operation mode of the memory device. The memory controller includes: The host interface layer, or HIL, manages multiple logical pages based on multiple logical page numbers, and these multiple logical pages are respectively mapped to the multiple storage blocks. A counter is used to generate a counter table, the counter table including counts corresponding to indexes, the indexes grouping the plurality of logical page numbers into units of data of a specific size, and the counter incrementing the count of the index corresponding to the write command when a write command is received from the host; and A localized garbage collection controller calculates a percentage value corresponding to the index based on the count, and determines the garbage collection operation mode as a mode that performs garbage collection operations that take into account locality based on the percentage value.

2. The storage device according to claim 1, wherein, The localized waste collection controller: When the percentage value does not exceed the reference value, the garbage collection operation mode is determined to be the first mode. In the first mode, garbage collection operation that does not consider locality is performed. and When at least one of the percentage values ​​exceeds the reference value, the garbage collection operation mode is determined to be a second mode, in which a garbage collection operation taking into account locality is performed.

3. The storage device according to claim 2, wherein, The second mode is an operation mode that performs garbage collection by excluding the most recently invalidated logical storage block from the selection of the sacrificial block in the garbage collection operation.

4. The storage device according to claim 2, wherein, When the HIL receives the write command from the host: The HIL converts the logical block address corresponding to the write command into a logical page number; and The counter increments by the count of the index corresponding to the logical page number obtained by converting the logical block address.

5. The storage device according to claim 4, in, The memory controller further includes a flash translation layer, i.e., FTL, and Wherein, when the FTL determines that the number of storage blocks managed by the FTL remains constant: The FTL sends a mode control request to the local garbage collection controller; and After receiving the mode control request, the localized waste collection controller periodically performs a mode determination operation to determine the waste collection operation mode as either the first mode or the second mode based on the percentage value.

6. The storage device according to claim 5, wherein, The localized waste collection controller performs the pattern determination operation when the counting table is updated.

7. The storage device according to claim 6, wherein, The localized waste collection controller periodically performs the pattern determination operation according to a first reference time period.

8. The storage device according to claim 5, wherein, The localized waste collection controller: When there is a second time period in which the memory device operates in a garbage collection operation mode different from the garbage collection operation mode of the first time period, the first throughput of the memory device during the first time period is compared with the second throughput of the memory device during the second time period, the second time period being after the first time period. and When the first throughput is not greater than the second throughput, the garbage collection operation mode during the third time period after the second time period is kept the same as the garbage collection operation mode during the second time period.

9. The storage device according to claim 8, wherein, When the first throughput is greater than the second throughput, the localized garbage collection controller switches the garbage collection operation mode of the third time period to be the same as the garbage collection operation mode of the first time period.

10. The storage device according to claim 9, wherein, The first throughput is the direct memory access count of the memory device per unit time during the first time period, i.e., the DMA count; and The second throughput is the DMA count of the memory device per unit time during the second time period.

11. The storage device according to claim 9, wherein, The localized waste collection controller: When the garbage collection operation mode during the third time period is the first mode, the reference value is increased; and When the waste collection operation mode during the third time period is the second mode, the reference value is reduced.

12. The storage device according to claim 11, wherein, When the first time period and the second time period exist, the localized waste collection controller periodically performs a mode switching operation to determine the waste collection operation mode based on the first throughput and the second throughput.

13. The storage device according to claim 12, wherein, The localized waste collection controller periodically performs the mode switching operation according to the second reference time period.

14. A method for controlling a garbage collection operation mode of a memory device, the memory device comprising a plurality of memory blocks, the method comprising: Generate a counting table, which includes counts corresponding to an index, wherein the index groups multiple logical page numbers in units of data of a specific size; When a write command is received from the host, the count of the index corresponding to the write command is incremented; Calculate the percentage value corresponding to the index based on the count; as well as Based on the percentage value, the waste collection operation mode is determined to be a mode that performs waste collection operations that take into account locality.

15. The method according to claim 14, wherein, Calculating the percentage value includes calculating the percentage value while keeping the number of memory blocks managed by the memory controller constant.

16. The method according to claim 15, wherein, Determining the waste collection operation mode includes: Compare the percentage value with the reference value; When the percentage value does not exceed the reference value, the garbage collection operation mode is determined to be the first mode, in which garbage collection operation that does not consider locality is performed; and When at least one of the percentage values ​​exceeds the reference value, the garbage collection operation mode is determined to be a second mode, in which a garbage collection operation taking into account locality is performed.

17. The method of claim 16, further comprising: When there is a second time period in which the memory device operates in a second garbage collection operation mode different from the first garbage collection operation mode of the first time period, the first throughput of the memory device during the first time period is compared with the second throughput of the memory device during the second time period, the second time period being after the first time period; as well as When the first throughput is not greater than the second throughput, the garbage collection operation mode during the third time period after the second time period is kept the same as the garbage collection operation mode during the second time period.

18. The method of claim 17, further comprising: When the first throughput is greater than the second throughput, the garbage collection operation mode of the third time period is switched to be the same as the garbage collection operation mode of the first time period.

19. The method of claim 18, further comprising: When the garbage collection operation mode during the third time period is the first mode, the reference value is increased.

20. The method of claim 18, further comprising: When the waste collection operation mode during the third time period is the second mode, the reference value is reduced.

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