A Method and System for Industrial Database Breakpoint Resumption Based on SD NAND Bad Block Prediction

Abstract

The application relates to the technical field of industrial database breakpoint continuation, and discloses an industrial database breakpoint continuation method and system based on SD NAND bad block prediction, which comprises the following steps: acquiring an industrial database real-time writing frequency and a flash medium initial bad block interval, deducing a wear evolution trend to obtain a potential failure area, analyzing industrial production line to-be-written data to obtain data value weights, planning a safe storage path in combination with the failure area when the weights are higher than a preset threshold, otherwise distributing a regular storage path according to bad block distribution, executing breakpoint continuation along the corresponding path and collecting real-time read-write states, updating the failure area according to abnormal addresses, and completing data writing after planning a safe path again. The method can realize stable and reliable operation of industrial database breakpoint continuation in a high-frequency writing scene.

Description

Technical Field

[0001] This invention relates to the field of industrial database breakpoint resume technology, and in particular to an industrial database breakpoint resume method and system based on SD NAND bad block prediction. Background Technology

[0002] Currently, industrial databases serve as the core infrastructure of intelligent manufacturing systems, undertaking the tasks of collecting, storing, and tracing massive amounts of real-time data throughout the entire production process. The stable operation of storage media directly determines the data reliability of the production system. SD NAND-based flash memory solutions have become the mainstream choice for industrial storage due to their cost advantages and deployment flexibility. Application-specific integrated circuits (ASICs), as the hardware carriers of flash memory control logic, directly determine bad block management efficiency and write response performance through their scheduling strategies.

[0003] In one existing technology, the flash storage control method for industrial databases employs a post-event detection and address redirection mechanism. Bad block marking and address remapping are only performed after a write failure triggers an error. From a technical perspective, this mechanism cannot predict the spatial spread of bad blocks. When the database performs breakpoint resume, the recovery path is prone to falling into areas with concentrated bad blocks. Frequent retries and jumps cause repeated oscillations in the write path, prolonging data persistence. Furthermore, this method does not differentiate between the business value of the data; critical control data and ordinary monitoring data share the same address allocation rules, and the scheduling power of the dedicated integrated circuit is not tilted towards high-reliability scenarios, failing to adapt to the differentiated storage needs of industrial scenarios.

[0004] In summary, existing technologies lack the ability to predict bad block propagation and differentiated value scheduling mechanisms, resulting in insufficient reliability of industrial databases in high-frequency write scenarios. Summary of the Invention

[0005] This invention provides a method and system for breakpoint resume in industrial databases based on SD NAND bad block prediction, so as to achieve stable and reliable operation of breakpoint resume in industrial databases under high-frequency writing scenarios.

[0006] Firstly, to address the aforementioned technical problems, this invention provides a method for resuming interrupted data in an industrial database based on SD NAND bad block prediction, comprising: The real-time write frequency of the industrial database and the initial bad block range of the flash memory medium are obtained. Wear evolution is deduced based on the real-time write frequency and the initial bad block range to obtain potential failure areas. The data to be written to the industrial production line is acquired, and the data to be written is identified and parsed to obtain the data value weight. If the data value weight is greater than the preset weight threshold, the idle physical address of the flash memory chip is obtained, the idle physical address is filtered according to the potential failure area to obtain a safe address set, and then the storage cost is analyzed according to the safe address set and the data value weight to obtain the first storage path. If the data value weight is not greater than the preset weight threshold, a conventional path is planned based on the initial bad block interval to obtain a conventional storage path; Based on the first storage path or the conventional storage path, the data to be written is resumed from breakpoint, and the real-time read and write status during the resumption process is collected. The real-time read and write status includes four status indicators: write successful, write failed, busy, and ready. Based on the real-time read / write status, abnormal addresses are updated to obtain potential failure areas. Based on the potential failure areas, a new security path is planned to obtain a second storage path. The data to be written is then written according to the second storage path.

[0007] Secondly, the present invention provides an industrial database breakpoint recovery system based on SD NAND bad block prediction, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention combines real-time write frequency and initial bad block interval to deduce wear evolution trend, and predetermines the predicted failure area in advance. It integrates forward-looking risk prediction into the entire address allocation process, replaces the traditional passive bad block response mode, solves the problem of repeated adjustment of breakpoint continuation path caused by the inability of existing technology to predict bad block diffusion, effectively smooths write path oscillation, and improves the performance stability of continuous write process.

[0010] (2) This invention calculates the data value weight by parsing the business identifier of the data to be written, performs two-level risk filtering security path planning for high-value data, and adopts wear leveling conventional path allocation for ordinary data, thereby realizing differentiated storage scheduling based on business value, so that the control computing power is tilted towards high-value data, and further enhances the storage reliability of key data in the scenario of breakpoint resume storage.

[0011] (3) This invention collects the read and write status in real time during the breakpoint continuation process, extracts abnormal physical addresses to update the failed area and triggers path reconstruction, and synchronously completes the data migration of damaged nodes and continuous writing recovery, forming a closed-loop scheduling mechanism. This solves the risk of secondary failure caused by the lag in bad block updates in the existing technology and significantly improves the overall operational stability of industrial databases in high-frequency writing scenarios. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a method for resuming interrupted data in an industrial database based on SD NAND bad block prediction, provided in the first embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Reference Figure 1 The first embodiment of the present invention provides a method for resuming interrupted data in an industrial database based on SD NAND bad block prediction, comprising the following steps: S11, obtain the real-time write frequency of the industrial database and the initial bad block range of the flash memory medium, and perform wear evolution deduction based on the real-time write frequency and the initial bad block range to obtain potential failure areas; S12, acquire the data to be written from the industrial production line, perform identifier parsing on the data to be written, and obtain the data value weight; S13, if the data value weight is greater than the preset weight threshold, obtain the free physical address of the flash memory chip, filter the free physical address according to the potential failure area to obtain a safe address set, and then perform storage cost analysis according to the safe address set and the data value weight to obtain the first storage path; S14, if the data value weight is not greater than the preset weight threshold, perform conventional path planning based on the initial bad block interval to obtain a conventional storage path; S15, according to the first storage path or the conventional storage path, perform breakpoint resumption on the data to be written, and collect the real-time read and write status during the resumption process. The real-time read and write status includes four status indicators: successful writing, failed writing, busy, and ready. S16, update the abnormal address according to the real-time read / write status to obtain the updated potential failure area, re-plan the security path according to the updated potential failure area to obtain the second storage path, and write the data to be written according to the second storage path.

[0015] In step S11, the real-time write frequency of the industrial database and the initial bad block range of the flash memory are obtained. Wear evolution is then extrapolated based on the real-time write frequency and the initial bad block range to obtain potential failure areas, including: Acquire real-time write data, perform sliding window statistics on the real-time write data, and obtain the real-time write frequency; The physical storage area is located based on the real-time write frequency, and a bad block scan is performed on the physical storage area to obtain the initial bad block range. Wear observation is performed based on the real-time write frequency and the initial bad block interval to obtain a wear degree matrix; Based on the wear degree matrix, a bad block prediction analysis is performed to obtain the bad block propagation probability. Based on the probability of bad block spread, the diffusion trend is deduced to obtain the potential failure area.

[0016] It should be noted that real-time write data is collected through the storage interface monitoring unit of the industrial database. The collection object is the data load corresponding to all write requests flowing into the flash memory controller per unit time. The collection granularity is aligned with the page programming cycle of the flash memory, which can fully cover various industrial data write forms such as batch writes and burst writes. The sliding window statistics adopt a fixed time window for traffic accumulation calculation. The time length of the sliding window is set to 10 seconds. This parameter is calibrated based on the burst characteristics of industrial production data and the wear response cycle of the flash memory medium. It can accurately capture second-level write traffic fluctuations and avoid drastic fluctuations in frequency statistics due to excessively short windows. During the statistics process, the fixed window of 10 seconds slides along the time axis second by second. The amount of all write data in each window is accumulated and summed, and then divided by the window length to obtain the average write rate of the corresponding window. The final output real-time write frequency is the calculation result of the latest window, and the unit is megabytes per second. For example, when 500 megabytes of write data are received within a single sliding window, the calculated real-time write frequency is 50 megabytes per second. This frequency value is synchronously updated to the global parameter cache of the flash memory scheduler for direct use in subsequent scheduling stages. The calculation time for a single round of frequency statistics is no more than 1 millisecond, which is suitable for the real-time scheduling requirements of high-frequency writes in industrial databases.

[0017] It's worth noting that when locating physical storage areas, the real-time write frequency is referenced, combined with the wear leveling scheduling rules of the flash memory medium. High-frequency write loads are concentrated within a specified physical block range. Therefore, the range of physical blocks undertaking write tasks can be mapped to the numerical range of the write frequency. During the location process, the entire storage array is pre-divided into several continuous block units based on the physical topology of the flash memory chips. Each block unit contains a fixed number of physical blocks and physical pages. When the real-time write frequency reaches a high-frequency threshold, the block unit currently undertaking the write task is automatically locked as the target physical storage area, which can effectively narrow down the scope of bad block investigation and avoid the performance overhead of full-chip scanning. Bad block scanning is achieved by reading the underlying status register of the corresponding physical storage area. Each bit in the status register corresponds to the valid or invalid status of a physical block. After scanning, all storage blocks marked as invalid in that area can be directly obtained, forming an initial bad block set. The physical row address and column address of all invalid blocks are extracted, and the neighborhood determination range is based on the distance between two physical pages. The number of adjacent invalid blocks around each invalid block is counted. A continuous region with at least three adjacent failed blocks is identified as a bad block cluster. The combination of the address ranges of all bad block clusters is the initial bad block interval, which can intuitively reflect the severity of local wear on the flash memory medium.

[0018] The threshold for determining the number of adjacent failed blocks is set at 3. New bad blocks in industrial-grade SD NAND primarily originate from localized oxide layer degradation caused by accumulated erase and write stress. This degradation is physically concentrated; when a single bad block is surrounded by at least 3 adjacent bad blocks, it indicates that the erase and write stress in that area has exceeded the medium's tolerance threshold, classifying it as a concentrated wear zone rather than an occasional single-point failure. The initial bad block region characterizes the spatial boundary of the confirmed concentrated wear area within the flash memory medium. The degree of medium degradation in this region is significantly higher than in isolated bad block areas. After subsequent erase and write operations, the probability of new bad blocks appearing and the rate of expansion are far greater than in normal areas. Therefore, it can serve as the starting state benchmark for wear evolution prediction.

[0019] It is worth further explaining that when conducting wear observation, it is necessary to first construct an initial hidden state covering all physical blocks of the flash memory medium, and then deduce the wear state evolution process of each physical block sequentially along the observation sequence timeline. The construction rule for the initial hidden state is as follows: physical blocks falling within the initial bad block range are directly marked as heavily worn hidden states; for external physical blocks, their historical erase / write counts are read, and those with erase / write counts less than 30% of the rated lifespan are marked as lightly worn hidden states, those between 30% and 80% are marked as moderately worn hidden states, and those exceeding 80% are marked as heavily worn hidden states. The observation sequence is obtained by expanding the real-time write frequency along the timeline. The real-time write frequencies obtained from each sliding window are arranged chronologically, with those above 30 megabytes per second mapped as high-frequency observation symbols, those between 10 and 30 megabytes per second mapped as medium-frequency observation symbols, and those below 10 megabytes per second mapped as low-frequency observation symbols. These three types of observation symbols together constitute the observation sequence, and the sequence length is equal to the number of statistical counts of the sliding window.

[0020] The state transition matrix was obtained from historical wear time-series data. The statistical sample consisted of 50 test chips of the same model as the target flash memory medium. These chips were continuously written at a high frequency of 30 megabytes per second for 1000 erase / write cycles on an accelerated wear test platform. After each erase / write cycle, the actual wear state of each physical block was recorded, along with the average write frequency within that cycle as the observed state. The statistical process involved grouping the chips by their observed states. Within each group, the transition frequency of the physical block's wear state between two adjacent erase / write cycles was counted. The transition frequency was then divided by the total transition frequency within that group to obtain the transition probability. This resulted in a 3x3 state transition matrix, where the rows correspond to the state before the transition and the columns correspond to the state after the transition.

[0021] For each physical block, starting from the initial hidden state, state transitions are performed step-by-step along the time axis of the observation sequence. At each transition, the transition probability distribution corresponding to the observed symbol at the current moment is used, and the state corresponding to the highest probability is taken as the inference result for that moment. The wear degree matrix is ​​obtained by summing the inferences of all physical blocks up to the end of the observation sequence. Each physical block corresponds to one inferred state: light wear corresponds to a wear index of 30, moderate wear to 60, and heavy wear to 90. This wear degree matrix covers all physical blocks within the flash memory medium, fully reflecting the wear evolution of each physical block under high-frequency write loads.

[0022] Next, during the bad block prediction analysis, the wear level matrix was used to systematically identify the risk of bad block propagation in areas with excessive wear. A preset wear level threshold of 80 was set, calibrated based on 1500 sets of flash memory wear lifecycle test data. This threshold corresponds to approximately 15% of the physical block's remaining lifespan, representing a critical wear value for a concentrated outbreak of bad blocks. During the comparison process, the wear index of the wear level matrix was read block by block. Blocks with a wear index greater than 80 were designated as areas with excessive wear, triggering subsequent propagation probability analysis. The calculation of the bad block propagation probability was based on the physical block's own erase / write cycles and error correction status. Higher erase / write cycles and more error correction code flips indicate more severe media degradation in the physical block, increasing the probability of it becoming a bad block. During calculation, the historical erase / write counts and the number of error correction code flipped bits during the most recent read are extracted from each adjacent physical block around the wear-exceeding area. The erase / write counts are divided by the rated maximum erase / write count of 100,000 times to obtain the erase / write stress ratio, and the number of flipped bits is divided by the maximum error correction capability of 64 bits to obtain the error correction margin occupancy rate. The two ratios are weighted and averaged, with the erase / write stress ratio having a weight of 0.6 and the error correction margin occupancy rate having a weight of 0.4. The result is multiplied by 100 and mapped to the interval of 0 to 100 as the bad block propagation probability.

[0023] Subsequently, when extrapolating the diffusion trend, the existing bad block cluster area is used as the origin, and the diffusion probability of bad blocks is used as the criterion to gradually expand to adjacent physical blocks. When the diffusion probability of an adjacent physical block is higher than a preset risk threshold, it is included in the potential failure area, and the expansion stops when the diffusion probability of the adjacent physical blocks is lower than the threshold. The preset risk threshold is fixed at 0.3, which is calibrated according to the false alarm rate control requirements of flash memory failure prediction, and can control the prediction false alarm rate within 10%. When the diffusion probability of an adjacent physical block is higher than this threshold, it is included in the potential failure area. The final defined potential failure area is a continuous physical address interval, containing all physical pages facing a high failure risk, which can be directly used as the basis for risk avoidance in the address scheduling process. For example, extrapolating outward from 12 clustered bad blocks as the origin, it is finally predicted that 20 physical pages radiating outward from the bad block cluster area will face an extremely high failure risk, and the continuous address interval formed by these 20 physical pages is the potential failure area. After multiple rounds of accelerated wear tests, the potential failure area obtained by this simulation has a coverage accuracy of no less than 90% for newly generated bad blocks that will appear within the next 1,000 erase and write cycles, which can effectively identify the forward-looking risks of flash memory media in advance.

[0024] In step S12, the data to be written from the industrial production line is obtained, and the data to be written is identified and parsed to obtain data value weights, including: Acquire the data to be written from the industrial production line, and perform business identifier parsing on the data to be written to obtain the production batch code and sensor acquisition frequency; The business level node is obtained by performing node positioning based on the production batch code, the sensor acquisition frequency, and the preset business level multi-branch tree. Calculate the node correlation degree of the business-level nodes, perform weight analysis based on the node correlation degree, and obtain the weight allocation matrix; The data to be written is weighted according to the weight allocation matrix to obtain the data value weight.

[0025] It should be noted that the data to be written is generated by various sensing devices and control units in the industrial production line and transmitted to the database storage node via the industrial bus. Each data packet carries a standardized business identifier field in its header. Business identifier parsing is completed through message field stripping. The parsing process reads the identifier field in the header of the data packet at fixed byte offsets, extracting two types of parameters in sequence: production batch code and sensor acquisition frequency. The production batch code is a unique number for the corresponding production batch, reflecting the data's business affiliation in the production process; the sensor acquisition frequency is the sampling rate of the corresponding data, reflecting the data generation density and real-time requirements. The parsing rules for both types of parameters follow the message protocol specifications commonly used in industrial settings. The parsing accuracy is perfectly aligned with the field lengths defined in the message, preventing field misalignment or parsing errors. For example, from the header identifier of the data packet to be written, the production batch code can be parsed as 1005, and the sensor acquisition frequency as 500 times per second. These two parameters together form the basic input for subsequent business hierarchy division. The parsing time for a single data packet is less than 0.1 microseconds, which will not significantly affect the throughput of high-frequency writing.

[0026] It's worth noting that the pre-defined business-level multi-branch tree is a multi-branch tree structure pre-built offline based on the static business attributes of each sensing device on the industrial production line. When constructing the business-level multi-branch tree, for the industrial production line, all deployed sensing devices and control units are traversed, collecting business attribute information such as the type, purpose, and production stage of each device. The production batch code is used as the root node, the sensor acquisition frequency as the first-level child node, the sensor type as the second-level child node, and the data purpose as the leaf layer of the third-level child node. The multi-branch tree structure is constructed layer by layer according to a top-down hierarchical logic. The depth and number of branches of the tree structure are dynamically adjusted according to the business complexity of the production line. In typical discrete manufacturing scenarios, the tree depth is set to 3 to 4 layers, which can fully cover the business hierarchy relationships of most industrial data. The constructed business-level multi-branch tree can clearly represent the logical belonging relationship of different sensor data in the overall production process. For example, temperature sensor data and pressure sensor data are mapped to different leaf nodes, clearly distinguishing the business attributes of the two types of data. This tree structure is updated synchronously with production batch switching to ensure that the business hierarchy remains consistent with the on-site production status. During the online writing process, each time data to be written arrives, only the production batch code and sensor acquisition frequency it carries need to be used as query keys to quickly locate the corresponding leaf node in the business hierarchy multi-branch tree, and the business hierarchy node to which the current data belongs can be obtained.

[0027] Subsequently, node correlation is used to quantify the tightness of data association between nodes at different business levels. This is calculated by statistically analyzing the fluctuation matching degree of two sets of data sequences. During the calculation, the original data sequences corresponding to two leaf nodes are collected within a fixed 10-second time window. First, mean normalization is performed on both sets of sequences, i.e., each data point is divided by the mean of the sequence. Then, the Pearson correlation coefficient of the normalized two sets of sequences is calculated. The absolute value of the correlation coefficient is multiplied by 100 to obtain the node correlation degree in the range of 0 to 100, where 100 indicates that the fluctuations of the two sets of data are completely consistent. The preset correlation threshold is 70. This threshold is statistically calibrated based on the correlation characteristics of industrial production data. Two types of data with a correlation degree higher than 70 usually belong to the same process link and have similar storage reliability requirements.

[0028] Using the obtained business-level nodes as a baseline, traverse all leaf nodes in the business-level multi-branch tree, calculate the node correlation degree between the current node and each leaf node, and filter out all leaf nodes with a correlation degree higher than the preset correlation threshold of 70 to form a correlation node group. All leaf nodes in this correlation node group, due to their highly similar data fluctuation characteristics, belong to the same set of correlation parameters in the same process step and should be included in a unified weight allocation system for storage priority sorting.

[0029] For each leaf node within the associated node group, three types of information are collected: total data write volume, data sampling frequency, and data usage identifier for the most recent 30 days. The total data write volume reflects the data scale characteristics of the node, the data sampling frequency reflects real-time requirements, and the data usage identifier reflects the node's classification among real-time control, process monitoring, and quality traceability. The data usage identifier is mapped to a usage priority coefficient, where real-time control is 3, process monitoring is 2, and quality traceability is 1. For all leaf nodes within the associated node group, the three dimensions are normalized to the interval 0 to 1 using minimum-maximum normalization. The normalization benchmark is the maximum and minimum values ​​of each dimension within the same group of leaf nodes. Multiplying these three values ​​yields the initial weight value for the leaf node, which is then divided by the sum of the initial weight values ​​of all leaf nodes in the same group to obtain the normalized weight value. This normalized weight value is then filled into the corresponding position on the diagonal of the weight allocation matrix, which is a diagonal matrix.

[0030] It's important to note that the weight mapping operation maps the data to be written to the numerical space corresponding to the weight allocation matrix, thus quantifying the data's value. The mapping process first matches the business attributes of the data to be written with business-level nodes. After locating the corresponding leaf node, it queries the diagonal weight value of that leaf node in the weight allocation matrix. This weight value is multiplied by 100 to obtain the initial value score, ranging from 0 to 100. A higher score indicates a higher basic business value for the data. The dynamic correction factor is calculated based on an inverse proportional rule of remaining capacity. Using a baseline correction factor of 1.0, the ratio of the total number of physical blocks to the number of currently available physical blocks is the correction factor value. The fewer the remaining available physical blocks, the larger the correction factor value, used to prioritize high-value data when storage space is limited. The final data value weight is obtained by multiplying the initial value score by the dynamic correction factor; a higher value indicates a higher storage priority. For example, if the data to be written has an initial value score of 60 after matrix mapping, and a dynamic correction factor of 2 based on the number of remaining physical blocks, the final data value weight after multiplication is 120. This weight value serves as the basis for determining the differentiated allocation of subsequent storage paths, enabling tiered storage scheduling based on business value.

[0031] In step S13, if the data value weight is greater than a preset weight threshold, the free physical addresses of the flash memory chip are obtained, and the free physical addresses are filtered according to the potential failure regions to obtain a set of secure addresses, including: If the data value weight is greater than the preset weight threshold, obtain the free physical address in the flash memory chip that is in an idle and unoccupied state; Based on the potential failure regions, the free physical addresses are eliminated to obtain candidate valid regions; The wear degree of the candidate effective regions is calculated to obtain the wear uniformity. Based on the wear evenness, the candidate valid regions are filtered for safe addresses to obtain a set of safe addresses; Based on the set of secure addresses and the weighted data value, a storage cost analysis is performed to obtain the first storage path.

[0032] It should be noted that the preset weight thresholds are set as follows: Logs from 10 different types of industrial production lines, each running continuously for 72 hours, are manually categorized into three levels based on their business impact: critical control data, process monitoring data, and quality traceability data. Data value weights are calculated for each categorized record. By statistically analyzing the business characteristic distribution of these three types of data across multiple industrial production lines, the minimum weight value that ensures a correct identification rate of over 95% for each type of data is selected as the segmentation threshold. The comparison process compares the calculated data value weights with the weight thresholds for each data packet. If a data value weight is greater than the preset weight threshold, the corresponding data is considered high-value data, triggering the safe path planning process. High-value data requires higher storage reliability; therefore, before path planning, all physical addresses in the flash memory chip that are in an idle, unused state are first obtained, forming a complete set of idle physical addresses. The determination of an idle state is based on the page status bitmap of the physical blocks. Physical blocks whose pages have not been written with valid data and have not been marked as bad blocks are included in the range of idle physical addresses. The complete set of free physical addresses is obtained by reading the free block linked list of the flash translation layer. The linked list is updated in real time with the occupancy status of physical blocks, and the acquisition time is no more than 0.5 milliseconds, ensuring the real-time performance of the address pool data. This complete set of addresses provides a complete range of candidate addresses for subsequent risk filtering and path planning, ensuring that high-value data can be selected for optimal storage locations from all free blocks.

[0033] It's worth noting that potential failure region removal is the first risk filter in high-value data path planning, used to preemptively eliminate forward-looking failure risks. The physical address range corresponding to the potential failure region is compared and removed against the entire set of free physical addresses, directly eliminating all physical addresses belonging to the potential failure region, thus completing coarse-grained risk filtering. This process applies the results of bad block propagation prediction to the address scheduling stage, preventing high-value data from being allocated to storage areas about to fail. The removal operation quickly completes address filtering by judging the range of start and end addresses, without needing to traverse address by address, and its computational efficiency is adaptable to the scheduling requirements of high-frequency writes. After removal, the remaining physical addresses constitute candidate valid regions, and all addresses within these regions do not belong to the predicted high-risk range, thus mitigating the future failure risk caused by bad block propagation at a macro level.

[0034] It is worth further explaining that the wear uniformity calculation is used to quantify the wear dispersion of physical blocks within the candidate valid area, providing a basis for subsequent refined screening. The calculation process extracts the historical erase / write counts of all physical blocks within the candidate valid area, forming an erase / write count distribution sequence. The wear uniformity is calculated using the coefficient of variation rule, taking the ratio of the standard deviation to the average of the erase / write counts of physical blocks within the candidate area, and then multiplying by 100 to obtain the final value. The smaller the value, the more uniform the wear of the physical blocks within the area, and the lower the risk of local wear overload; the larger the value, the more significant the wear difference, and the higher the probability of the existence of locally high-wear blocks. For example, if the erase / write count distribution sequence of physical blocks 45 to 80 is collected, the calculated wear uniformity is 45, indicating that the wear dispersion of physical blocks within this area is at a moderate level. The calculation of wear uniformity can accurately identify the wear distribution characteristics within the candidate area, avoiding the reliability risks caused by the existence of locally high-wear blocks after overall risk elimination, and providing a quantitative judgment indicator for the second-level refined screening.

[0035] Next, during the secure address screening process, the physical blocks within the candidate valid area are first classified according to two parameters: historical write / erase cycles and leakage current characteristics, based on a preset physical block lifespan baseline. Physical blocks with more than 5000 historical write / erase cycles and abnormal leakage current characteristics are classified as high-risk wear blocks. The historical write / erase cycle threshold is determined by performing continuous write / erase tests on 50 industrial-grade SD NAND chips, performing a full block read verification and recording the number of bad blocks every 500 write / erase cycles. After more than 5000 write / erase cycles, the block failure probability jumps from the baseline of 0.3% to 2.1%, an increase of approximately 7 times the normal level. Therefore, 5000 cycles is used as the classification boundary. The abnormal leakage current threshold is set at 80 microamps. According to the industrial-grade SD NAND electrical characteristics datasheet, the gate leakage current of a normal memory cell does not exceed 50 microamps. When approaching failure, it can rise above 80 microamps due to the degradation of the tunneling oxide layer. This critical value is used as the abnormal judgment standard. Leakage current data is read from address 0x80 of the flash memory chip status register, and the unit of measurement is microamps. The preset leakage current abnormal threshold is 80 microamps, which is calibrated according to the electrical characteristics manual of industrial-grade SLCNAND.

[0036] The high-risk blocks identified earlier are further removed from the candidate valid region, and the remaining physical addresses constitute the safe address set. For example, physical blocks 50 to 55 within the candidate valid region meet the conditions of exceeding the write / erase cycle limit and abnormal leakage current, and are therefore identified as high-risk blocks and removed. The remaining physical blocks constitute the safe address set. The safe address set obtained through two levels of filtering avoids both forward-looking diffusion risks and immediate high-risk risks, thus fully ensuring the storage reliability of high-value data.

[0037] Subsequently, storage cost analysis, combined with data value weights and address read / write performance parameters, completes optimal path planning. Page programming latency parameters for each physical page in the secure address set are extracted. This parameter reflects the write response speed of the corresponding physical page; lower latency indicates higher write efficiency. The unit value write cost is calculated by the ratio of page programming latency to data value weight. A lower ratio indicates a smaller unit value write cost for the corresponding physical page, resulting in higher scheduling priority. Path selection uses physical pages as the basic granularity and unit value write cost as the criterion, prioritizing consecutive idle physical pages with lower write costs. Selection constraints include completely avoiding potential failure areas, prioritizing consecutive addresses on the same channel, and ensuring the total capacity meets the length requirement of the data to be written. The final output first storage path is a sequence of consecutive physical page addresses, containing three types of information: the starting physical block number, the starting page number, and the number of consecutive pages. For example, if the programming latency of the target physical page is 1500 microseconds, and the write cost is calculated based on a data value weight of 120, the first storage path planned based on this cost can completely bypass the risk area from physical block 50 to physical block 55. This path planning method can ensure storage reliability while taking into account write performance, adapting to the dual requirements of reliability and real-time performance for high-value data.

[0038] In step S14, if the data value weight is not greater than a preset weight threshold, conventional path planning is performed based on the initial bad block interval to obtain a conventional storage path, including: If the data value weight is not greater than a preset weight threshold, obtain the global physical address of the flash memory chip; The global physical address is indexed and filtered based on the initial bad block interval to obtain the usable physical address; The wear rate of the available physical addresses is calculated and sorted to obtain the target physical block set; A continuous idle scan is performed on the target physical block set to obtain the conventional storage path.

[0039] It should be noted that when the data value weight is not greater than the preset weight threshold, the corresponding data is determined to be ordinary value data, triggering the regular path planning process. Ordinary data has relatively low storage reliability requirements; therefore, path planning starts from the global physical address of the flash memory chip, without needing to pre-limit the free address range. The global physical address includes the address range corresponding to all physical blocks within the flash memory chip, including both marked bad blocks and normal occupied and free blocks, covering the entire physical space of the storage array. The global physical address is obtained by reading the physical topology configuration table of the flash memory chip. This table records basic parameters such as the starting address, block size, and page size of all physical blocks, serving as the underlying address base for storage scheduling. Starting from the global address for regular path allocation maximizes the utilization of available storage resources, adapts to the high-throughput write requirements of ordinary data, and avoids address resource waste caused by excessive risk filtering.

[0040] It should be further explained that the index filtering operation is performed with reference to the initial bad block interval and is the basic availability filtering for the regular path. Ordinary high-value data does not use potential failure area filtering to maximize the available address space. If the regular path also uses potential failure area filtering, when the bad block propagation prediction range is large, the available address pools of the safe path and the regular path will highly overlap, compressing the space dedicated to high-value data. Using the initial bad block interval only removes confirmed failed blocks, retaining unconfirmed failed blocks within the predicted risk area as optional addresses. This avoids write failures of confirmed bad blocks and makes full use of storage capacity. The coordinates of all failed physical blocks recorded in the initial bad block interval are read, and the indices corresponding to these bad blocks are removed from the global physical address index list, excluding all confirmed failed storage blocks. The filtering operation uses an index marking method. All bad block addresses are first marked as failed, and then batch removal is completed through a single index traversal. This eliminates the need for address-by-address comparison, resulting in high execution efficiency. After filtering, all remaining physical addresses constitute the available physical addresses. This address set only excludes confirmed bad blocks and retains all normal physical blocks, including occupied and free blocks, ensuring sufficient address space for allocation for ordinary data. Compared to the two-level risk filtering of high-value data, the conventional path only performs basic bad block removal, with more lenient filtering rules. It can make full use of storage capacity and adapt to the large-capacity storage needs of ordinary monitoring data.

[0041] It's worth noting that wear leveling and sorting are used to achieve wear leveling for ordinary data, extending the overall lifespan of the flash memory. The program erase counts of each physical block in the available physical addresses are extracted. These erase counts are used as the sorting key, and all available physical addresses are arranged in ascending order, with physical blocks having fewer erase counts appearing earlier. The size of the target physical block set is dynamically calculated based on the total length of the data to be written. This is achieved by dividing the total number of bytes of data to be written by the byte capacity of a single physical block, and rounding the result up to the nearest integer. The target physical block set is formed by selecting the corresponding number of low-wear physical blocks at the beginning of the sorted sequence. The byte capacity of a single physical block is fixed at 256 kilobytes. The key objective of this sorting and filtering logic is to prioritize the allocation of low-wear physical blocks to write tasks, preventing some physical blocks from failing prematurely due to frequent writing and balancing the wear level of the entire storage medium. For example, physical block 200, with 100 program erase counts, is prioritized for inclusion in the target physical block set, as it appears before physical block 300, which has 150 erase counts. This wear leveling scheduling method can increase the overall lifespan of flash memory media by approximately 20%, meeting the long-term operational requirements of industrial storage.

[0042] Continuous free space scanning is used to locate contiguous writable storage space within the target physical block set, generating the final conventional storage path. The page status bitmap of each physical block in the target physical block set is extracted, with each bit in the bitmap corresponding to the free or occupied state of a physical page. A fixed-length window traversal is used to scan the bitmap, with the scanning window length set to 64, corresponding to 64 physical pages, consistent with the number of pages in a single physical block. When the sliding window reaches the end of a physical block, it automatically connects to the starting page of the next physical block and continues scanning, prioritizing physical blocks with contiguous addresses. If an adjacent physical block is not free, it jumps to the next low-wear physical block in the sorted sequence and continues scanning until a contiguous free page interval that meets the length requirement is found. The window length matches the typical batch write length of industrial data, ensuring that most write requests can be allocated to contiguous physical space. When a contiguous free page interval that meets the length requirement is scanned, sequential write addresses are generated based on this interval, arranged in ascending order of address to form a continuous write path, which is the conventional storage path.

[0043] In step S15, the data to be written is resumed from breakpoint according to the first storage path or the regular storage path, and the real-time read / write status during the resumption process is collected. The real-time read / write status includes four status indicators: successful write, failed write, busy, and ready. The data to be written is resumed from the breakpoint according to the first storage path or the regular storage path to obtain a transmission interruption flag. Data frames are parsed according to the transmission interruption flag to obtain the length of stored data and the data block checksum. Obtain the stored data of the flash page corresponding to the transmission interruption location, and calculate the real-time check value of the stored data; The data block checksum is compared with the real-time checksum. If the comparison results match, the write operation is directly restored. If the comparison results are inconsistent, the data to be written is offset and truncated according to the length of the existing data to obtain the remaining fragment to be written, and the writing operation is resumed according to the remaining fragment to be written. Throughout the entire process of performing the recovery write operation, the real-time read and write status during the breakpoint resume operation is collected.

[0044] It should be noted that the breakpoint resume operation is triggered when the write process is interrupted due to anomalies such as communication interruption or power fluctuations. It supports resuming writing along the first storage path or the regular storage path. During the write operation, the data to be written is written page by page in the order of physical page addresses in the storage path. The transmission interruption flag is generated by the transmission status register of the storage controller. When an anomaly occurs in the write link, such as data verification failure, bus timeout, or physical layer disconnection, the status register automatically sets the corresponding interruption flag bit and latches the write progress information at the time of the interruption. After triggering breakpoint resume, the system first suspends the scheduling of the current write queue, reads the status bit of the transmission interruption flag, and confirms the trigger type and location of the interruption, providing a triggering basis for subsequent data parsing and resume operations. Bus interference and momentary power outages in industrial environments are the main causes of write interruptions. This breakpoint resume mechanism ensures that data can continue writing from the breakpoint after the anomaly is cleared, without the need for retransmission of the entire segment, effectively improving write efficiency and data integrity.

[0045] It's worth noting that data frame parsing is triggered by a transmission interruption flag. It reads the write context data corresponding to the interruption moment and parses out the length of the stored data and the data block checksum. The length of the stored data is the number of bytes successfully written to the flash memory before the interruption, obtained by parsing the progress count field in the interruption frame. This accurately represents the amount of data written, in bytes. Data block checksums use a 32-bit cyclic redundancy check rule, covering the entire 4096-byte valid data area of ​​the corresponding physical page. The checksum is stored at byte offsets 0 to 3 in the spare area of ​​the corresponding physical page. It is calculated synchronously during data writing and written to the spare area. During data reading, it is recalculated and compared with the stored value to verify the integrity of the written data. The parsing process reads corresponding parameters at fixed field offsets. The precision of the parameter reading is perfectly aligned with the frame structure definition, preventing any progress deviation. For example, after a write interruption, the parsed stored data length is 4096 bytes, and the corresponding data block checksum is extracted. These two types of parameters together form the basis for subsequent data integrity verification and breakpoint location. The single-round parsing operation is completed directly by the hardware logic without the need for the processor. The parsing time is no more than 0.2 microseconds, and it can quickly enter the subsequent verification process.

[0046] It's worth further explaining that flash page status comparison is used to verify the integrity of written data and determine whether the flash page at the interrupted location has suffered data corruption. The actual stored data of the flash page corresponding to the interrupted location is read, and the checksum is recalculated using the same verification rules. The calculated real-time checksum is then hash-compared with the extracted data block checksum. If the comparison results match, it indicates that the page data has been written completely without corruption, the flash page status is normal, and there is no need to adjust the write position; the write operation can be resumed directly from the next address of the current page. Resuming write directly under normal conditions reduces unnecessary address jumps and data retransmissions, maximizes the continuity of the write path, and reduces the impact of breakpoint resumption on write performance. The comparison operation is performed using a hardware verification engine, with the verification calculation rate synchronized with the flash page read rate. The single-page verification time coincides with the page read time, without adding additional resumption latency.

[0047] Next, when the checksum comparison results are inconsistent, the current flash page state is determined to be abnormal, indicating that the data at the corresponding position is corrupted or partially written, requiring a relocation of the start point for continuation. Using the length of the existing data as a baseline, a write offset is calculated. This offset points to the end position of the last complete and valid data, which is the starting offset of the continuation operation. Based on this write offset, a sliding truncation is performed on the original data to be written, removing corrupted or duplicate portions and retaining all data after the offset, forming the remaining segment to be written. The header of the remaining segment is perfectly aligned with the breakpoint position of the original data stream, ensuring seamless connection between the continuation data and the existing data, preventing data duplication or loss. For example, if the existing data length is 4096 bytes, the corresponding write offset is calculated to be 4096 bytes. The remaining segment is obtained by truncating the content after 4096 bytes from the original data to be written. This truncation operation accurately removes abnormal data, ensuring the integrity and continuity of the continuation data and avoiding data errors caused by page corruption.

[0048] Finally, the write resumption and status acquisition are executed synchronously. Based on the header identifiers of the remaining unwritten segments, a new resume start address is mapped in the corresponding storage path. This resume start address is generated using sequential addressing. Starting from the page following the physical page where the breakpoint is located, the page status bitmap is queried sequentially to find the first free page as the resume start address. If there are not enough free pages in the current physical block, the process jumps to the starting page of the next physical block in the same path in ascending address order to continue addressing. Throughout the entire breakpoint resume execution process, the read / write status during the resume process is collected in real-time by polling the flash memory chip's status register. This includes status indicators such as busy, ready, successful write, and failed write. The status update frequency is consistent with the flash memory's page programming cycle. The collected real-time read / write status is synchronously fed back to the storage scheduling unit. This serves two purposes: monitoring the execution progress of the resume process and triggering a new round of exception handling and path updates if an exception is encountered again during the resume process. The response latency of real-time status acquisition does not exceed one page programming cycle, allowing for timely detection of abnormal situations during the resume process and ensuring the controllability of the entire write process.

[0049] In step S16, the abnormal address is updated according to the real-time read / write status to obtain the updated potential failure area, including: Based on the real-time read / write status, abnormal addresses are extracted to obtain abnormal physical addresses; A health assessment is performed on the abnormal physical address to obtain a health metric value; Physical blocks are filtered based on the health metrics to obtain updated potential failure regions.

[0050] It should be noted that the abnormal address extraction is triggered by the write failure flag in the real-time read / write status. During extraction, the built-in error log register of the flash memory controller is read first to obtain the error code information corresponding to the write failure. Different error codes correspond to different reasons for write failure, such as abnormal programming voltage, memory cell breakdown, page buffer check errors, etc. These error codes are predefined by the flash memory chip manufacturer in the datasheet. Based on the error code parsing results, the instruction entry corresponding to the write operation in the underlying instruction execution queue is traced back to extract the physical block address and page offset corresponding to the abnormal instruction. These are combined to obtain the abnormal physical address, with address precision down to a single physical page. The address extraction process is automatically completed by the hardware abnormal log unit. After an abnormality occurs, the abnormal address is automatically recorded without processor intervention, with a recording delay of no more than 1 microsecond. This allows for precise location of the abnormal physical address, avoiding loss of the abnormal location due to instruction queue clearing. The extracted abnormal physical address is a key location basis for subsequent health assessment and failure area updates.

[0051] It is worth noting that the health assessment performs quantitative calculations on the physical blocks corresponding to abnormal physical addresses from two dimensions: erase / write wear and electrical degradation. First, the wear leveling record table in the flash memory translation layer is queried to extract the historical erase / write counts of the physical block, reflecting the degree of mechanical wear. Simultaneously, the error correction coding data of the spare area of ​​the physical page is read, and the number of bit flips corrected by the error correction code is counted, reflecting the degree of electrical degradation of the physical block. The health metric is calculated using an exponential non-linear weighted average, with the following formula: ; In the formula, H is a health metric, ranging from 0 to 100, with higher values ​​indicating better physical block health. N represents the number of times the physical block has been erased and rewritten in the past. The maximum number of erase / write cycles is set to 100,000. B represents the number of error correction code toggles. The maximum number of error correction bits is set to 64 bits, which corresponds to the maximum error correction capability of the built-in error correction code in industrial-grade SD NAND. Take 0.55, The weighting coefficient is set to 0.45. It is obtained by recording the number of erase / write operations and the number of bit flips at the time of failure of each physical block during the full life cycle test of 50 chips of the same model, and then calibrating the erase / write dimension ratio and the flip bit dimension ratio by least squares fitting.

[0052] It is worth further explaining that the physical block screening combines health metrics with a preset health threshold for comparison and judgment, used to determine whether abnormal blocks should be included in the updated failure area. The preset health threshold is 60. Using 500 chips of the same model, the number of erase / write cycles and the number of bit flips were collected during the full-life test before failure. These data were then substituted into the aforementioned non-linear health metric formula to calculate the cycle-by-cycle health, recording the distribution of health metrics for each physical block at the time of actual failure in the subsequent 100 erase / write cycles. The probability of subsequent failure corresponding to different health values ​​was statistically analyzed, and the health metric corresponding to the inflection point with the largest increase in failure probability was taken as the judgment threshold, with a calibration result of 60. The comparison process compares the calculated health metric with the health threshold one by one. If the health metric is lower than the health threshold, the corresponding block is determined to be in a severely worn state, and an isolation mark is generated for the physical block. After the mark is generated, it is immediately written to the bad block mapping table. The currently executing write operation stops writing to this block after completing the current page, and subsequent address allocations will no longer include this physical block. Valid data already written within a block is automatically migrated to other healthy physical blocks during background idle periods. The migration process does not consume foreground write bandwidth and does not affect normal business operations. If the health metric value is not lower than the threshold, it is judged as a minor anomaly, and the original available state remains unchanged. All physical block addresses that have generated isolation tags are appended to the original potential failure region, completing the dynamic update of the failure region and obtaining the updated potential failure region.

[0053] In one possible implementation, a second storage path is obtained by replanning the security path based on the updated potential failure region, and the data to be written is written according to the second storage path, including: Based on the updated potential failure region and the first storage path, damaged nodes are eliminated to obtain candidate usable physical blocks; A second storage path is generated based on the candidate available physical blocks, and the data to be written is written along the second storage path.

[0054] It should be noted that the damaged node removal process is used to identify address segments in the original first storage path that fall into the updated failure region, preparing for path reconstruction. The address range of the potentially failed region is compared with the address sequence of the first storage path, and intersection calculations are performed. Physical blocks belonging to both are identified as damaged nodes; these physical blocks are in a high-risk state and cannot continue to store high-value data. The intersection operation quickly locates overlapping intervals by comparing the ranges of the start and end addresses, without needing to traverse address by address, resulting in high computational efficiency. For example, if the first storage path contains physical blocks 150 to 160, and the potentially failed region contains physical blocks 150 and 158, after comparison and calculation, physical blocks 150 and 158 are identified as damaged nodes. After identifying damaged nodes, they are removed from the set of physical blocks in the first storage path. The remaining normal physical blocks constitute candidate usable physical blocks, serving as the basic components of the new path. This removal operation can accurately remove risky nodes from the path, preventing high-value data from continuing to be stored in blocks with increased failure risk.

[0055] It's worth noting that the second storage path is generated based on the reconstruction of candidate available physical blocks and is used to replace the original first storage path. The free block list of the flash controller is read, and supplementary physical blocks equal in number to the number of damaged nodes are extracted. Supplementary physical blocks are preferentially selected from those adjacent to the original path address and have undergone two levels of security screening: risk removal and high-wear block filtering. If no adjacent available blocks are available, the nearest qualified physical block is selected in ascending address order to ensure optimal path continuity. The candidate available physical blocks and supplementary physical blocks are rearranged in ascending order of physical address and concatenated to form a continuous address sequence, which is the second storage path. During path reconstruction, the overall address direction and channel distribution of the original path remain unchanged; only the address segments corresponding to the damaged nodes are replaced, minimizing the impact of path adjustment on the write process. For example, after removing physical blocks 150 and 158, supplementing with physical blocks 210 and 211, the rearranged second storage path is physical blocks 151 to 157, physical blocks 159 to 160, and physical blocks 210 to 211. The reconstructed second storage path completely avoids the potential failure areas after the update and maintains good address continuity, which can ensure the continuous and reliable writing of high-value data.

[0056] It is worth further explaining that the write operation along the second storage path includes data migration and continuous writing executed sequentially, completing the final process of breakpoint resumption. First, the written data originally residing in the damaged node is read and temporarily stored as a migration data block in the on-chip static random access memory. Data integrity verification is performed simultaneously during the temporary storage process to prevent data corruption during migration. The flash memory controller's direct memory access engine is invoked to move the temporary migration data block to the first available physical block on the second storage path, completing the safe migration of data from the damaged node. After migration, the data integrity of the target address is verified to ensure error-free migration. After data migration, the page allocation register of the target physical block is read, and the index of the last page after the migration data is occupied is extracted as the write offset. Starting from the next page corresponding to the offset, subsequent physical page addresses are allocated sequentially along the second storage path, guiding the continuous writing of the data to be written, completing the entire resumption process. This method ensures that both existing data and newly written data are in a safe path while maintaining the continuity of the write process, preventing prolonged write interruptions due to path reconstruction, and adapting to the high-frequency continuous write requirements of industrial databases.

[0057] In summary, this invention discloses a method for breakpoint resumption of industrial databases based on SD NAND bad block prediction. The method includes obtaining the real-time write frequency of the industrial database and the initial bad block range of the flash memory medium, deducing the wear evolution trend to obtain potential failure areas, then analyzing the data to be written on the industrial production line to obtain data value weights. When the weight is higher than a preset threshold, a safe storage path is planned based on the failure area; otherwise, a regular storage path is allocated according to the bad block distribution. Breakpoint resumption is then performed along the corresponding path, and real-time read / write status is collected. The failure area is updated based on the abnormal address, and the safe path is replanned to complete the data writing. This invention achieves stable and reliable operation of breakpoint resumption of industrial databases in high-frequency write scenarios by predicting flash memory bad block propagation, combining data value-based differentiated storage path planning, and dynamically updating failure areas.

[0058] The second embodiment of the present invention provides an industrial database breakpoint recovery system based on SD NAND bad block prediction, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0059] It should be noted that the industrial database breakpoint resume system based on SD NAND bad block prediction provided in this embodiment of the invention is used to execute all the process steps of the industrial database breakpoint resume method based on SD NAND bad block prediction in the above embodiment. The working principle and beneficial effect of the two are one-to-one, so they will not be described again.

[0060] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0061] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for resuming interrupted data in an industrial database based on SD NAND bad block prediction, characterized in that, include: The real-time write frequency of the industrial database and the initial bad block range of the flash memory medium are obtained. Wear evolution is deduced based on the real-time write frequency and the initial bad block range to obtain potential failure areas. The data to be written to the industrial production line is acquired, and the data to be written is identified and parsed to obtain the data value weight. If the data value weight is greater than the preset weight threshold, the idle physical address of the flash memory chip is obtained, the idle physical address is filtered according to the potential failure area to obtain a safe address set, and then the storage cost is analyzed according to the safe address set and the data value weight to obtain the first storage path. If the data value weight is not greater than the preset weight threshold, a conventional path is planned based on the initial bad block interval to obtain a conventional storage path; Based on the first storage path or the conventional storage path, the data to be written is resumed from breakpoint, and the real-time read and write status during the resumption process is collected. The real-time read and write status includes four status indicators: write successful, write failed, busy, and ready. Based on the real-time read / write status, abnormal addresses are updated to obtain potential failure areas. Based on the potential failure areas, a new security path is planned to obtain a second storage path. The data to be written is then written according to the second storage path.

2. The industrial database breakpoint resume method based on SD NAND bad block prediction according to claim 1, characterized in that, The process involves acquiring the real-time write frequency of the industrial database and the initial bad block range of the flash memory medium, and then performing wear evolution analysis based on the real-time write frequency and the initial bad block range to obtain potential failure areas, including: Acquire real-time write data, perform sliding window statistics on the real-time write data, and obtain the real-time write frequency; Based on the real-time write frequency, the physical storage area is located, and a bad block scan is performed on the physical storage area to obtain the initial bad block range; Wear observation is performed based on the real-time write frequency and the initial bad block interval to obtain a wear degree matrix; Based on the wear degree matrix, a bad block prediction analysis is performed to obtain the bad block propagation probability. Based on the probability of bad block spread, the diffusion trend is deduced to obtain the potential failure area.

3. The industrial database breakpoint resume method based on SD NAND bad block prediction according to claim 1, characterized in that, The process of acquiring the data to be written from the industrial production line, performing identifier parsing on the data to be written, and obtaining data value weights includes: Acquire the data to be written from the industrial production line, and perform business identifier parsing on the data to be written to obtain the production batch code and sensor acquisition frequency; The business level node is obtained by performing node positioning based on the production batch code, the sensor acquisition frequency, and the preset business level multi-branch tree. Calculate the node correlation degree of the business-level nodes, perform weight analysis based on the node correlation degree, and obtain the weight allocation matrix; The data to be written is weighted according to the weight allocation matrix to obtain the data value weight.

4. The industrial database breakpoint resume method based on SD NAND bad block prediction according to claim 1, characterized in that, If the data value weight is greater than a preset weight threshold, the idle physical addresses of the flash memory chip are obtained. These idle physical addresses are then filtered according to the potential failure regions to obtain a set of secure addresses. Finally, storage cost analysis is performed based on the secure address set and the data value weight to obtain a first storage path, including: If the data value weight is greater than the preset weight threshold, obtain the free physical address in the flash memory chip that is in an idle and unoccupied state; Based on the potential failure regions, the free physical addresses are eliminated to obtain candidate valid regions; The wear degree of the candidate effective regions is calculated to obtain the wear uniformity. Based on the wear evenness, the candidate valid regions are filtered for safe addresses to obtain a set of safe addresses; Based on the set of secure addresses and the weighted data value, a storage cost analysis is performed to obtain the first storage path.

5. The industrial database breakpoint resume method based on SD NAND bad block prediction according to claim 1, characterized in that, If the data value weight is not greater than a preset weight threshold, conventional path planning is performed based on the initial bad block interval to obtain a conventional storage path, including: If the data value weight is not greater than a preset weight threshold, obtain the global physical address of the flash memory chip; The global physical address is indexed and filtered based on the initial bad block interval to obtain the usable physical address; The wear rate of the available physical addresses is calculated and sorted to obtain the target physical block set; A continuous idle scan is performed on the target physical block set to obtain the conventional storage path.

6. The industrial database breakpoint resume method based on SD NAND bad block prediction according to claim 1, characterized in that, The process involves resuming interrupted writes of the data to be written according to the first storage path or the conventional storage path, and collecting real-time read / write status during the resumption process. The real-time read / write status includes four status indicators: successful write, failed write, busy, and ready. The data to be written is resumed from the breakpoint according to the first storage path or the regular storage path to obtain a transmission interruption flag. Data frames are parsed according to the transmission interruption flag to obtain the length of stored data and the data block checksum. Obtain the stored data of the flash page corresponding to the transmission interruption location, and calculate the real-time check value of the stored data; The data block checksum is compared with the real-time checksum. If the comparison results match, the write operation is directly restored. If the comparison results are inconsistent, the data to be written is offset and truncated according to the length of the existing data to obtain the remaining fragment to be written, and the writing operation is resumed according to the remaining fragment to be written. Throughout the entire process of performing the recovery write operation, the real-time read and write status during the breakpoint resume operation is collected.

7. The industrial database breakpoint resume method based on SD NAND bad block prediction according to claim 1, characterized in that, The step of updating the abnormal address based on the real-time read / write status to obtain the updated potential failure area includes: Based on the real-time read / write status, abnormal addresses are extracted to obtain abnormal physical addresses; A health assessment is performed on the abnormal physical address to obtain a health metric value; Physical blocks are filtered based on the health metrics to obtain updated potential failure regions.

8. The industrial database breakpoint resume method based on SD NAND bad block prediction according to claim 1, characterized in that, The step of replanning the security path based on the updated potential failure region to obtain a second storage path, and writing the data to be written according to the second storage path, includes: Based on the updated potential failure region and the first storage path, damaged nodes are eliminated to obtain candidate usable physical blocks; A second storage path is generated based on the candidate available physical blocks, and the data to be written is written along the second storage path.

9. An industrial database breakpoint recovery system based on SD NAND bad block prediction, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1 to 8.

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