Solid state disk data write control method and system based on trusted check

Abstract

The application discloses a solid state disk data write control method and system based on trusted check, relates to the technical field of trusted storage, obtains a write request issued by an application terminal host side, performs trusted check on the write request to form trusted write information, after to-be-written data enters a cache space of a solid state disk, forms a write trusted undertaking relationship according to a state transition relationship of the to-be-written data between request receiving, caching, address mapping and flash memory writing, determines a trusted continuation state corresponding to the to-be-written data, when the trusted continuation state does not satisfy a write requirement, re-matches the to-be-written data in the cache to determine a continuous write state, and performs result checking. The above technical scheme is favorable to solving the problem that, in the process that a solid state disk of an application terminal executes data writing, invalid write instructions may still drive cache data to continue writing to a non-matching physical storage area, and further cause an untrusted write result.

Description

Technical Field

[0001] This invention relates to the field of trusted storage technology, and in particular to a method and system for controlling solid-state drive data writing based on trusted verification. Background Technology

[0002] Solid-state drives (SSDs) are crucial storage components in computer devices, smart terminals, and in-vehicle infotainment systems. The security, integrity, and reliability of their data writing process directly impact the data storage and operational stability of these devices. With the increasing application of SSDs in laptops, smart homes, in-vehicle infotainment systems, and AI computing devices, different terminal devices exhibit variations in interface protocols, access subjects, write tasks, and data types. Especially during the production and adaptation of SSD semi-finished products, SSDs may need to handle data write requests from different hosts, testing devices, or application terminals. Abnormal write request sources, tampered instruction content, incomplete data to be written, or mismatched write permissions can easily affect the reliability of the stored data. To prevent abnormal data from being written to the storage medium, existing technologies typically introduce a trusted verification mechanism during the SSD data writing process to verify the write request and the data to be written. The specific processing flow is as follows: The host, test equipment, or application terminal sends a write command and the data to be written to the solid-state drive (SSD) controller. The SSD controller parses the interface type, logical address, data length, and access permissions in the write command, and allocates corresponding cache space for the data to be written after confirming the validity of the write request. For example, Chinese invention patent CN111752484B discloses an SSD controller, solid-state drive, and data writing method, including: an NVMe controller for obtaining write commands; a central processing unit (CPU) electrically connected to the NVMe controller for receiving and parsing the write command and returning it to the NVMe controller, enabling the NVMe controller to search for the base address of the available cache space in the cache memory according to the write command and obtain host data from the host; a cache controller electrically connected to the NVMe controller for writing host data to the cache memory according to the base address of the available cache space and causing the CPU to generate a data migration command; and a NAND Flash controller electrically connected to both the cache controller and the CPU, for moving host data to the NAND Flash memory according to the data migration command and causing the CPU to generate a release command so that the NVMe controller can release the available cache space according to the release command.

[0003] After the data to be written enters the cache space, the solid-state drive controller determines the corresponding data write location based on the mapping relationship between logical addresses and physical addresses, combined with the flash memory block status, flash memory page availability status, and bad block information. Then, it performs error correction encoding, data scrambling, and write path configuration on the cached data, and moves it to the NAND Flash memory. For example, the data writing method, system, and solid-state drive disclosed in Chinese invention patent CN111580757B include: acquiring the data to be written sent by the host, writing the data to be written to the cache area, writing the data to be written from the cache area to the first data block, and writing the data to be written from the cache area to the spare block when the data to be written fails to be written to the first data block. Since the data to be written is first written to the cache area of ​​the flash memory chip and then from the cache area to the first data block, when the data to be written fails to be written to the first data block, the data to be written is still cached in the cache area. At this time, the data to be written in the cache area can be directly written to the spare block of the flash memory chip.

[0004] Solid-state drives (SSDs), with their high read / write speeds, strong vibration resistance, small size, and low power consumption, are increasingly being used in various fields. For example, in response to the market trend of advancing automotive technology and continuously increasing performance demands of functional devices, SSDs are increasingly being used in some in-vehicle infotainment systems to store data such as navigation maps, audio-visual resources, system configurations, and software upgrades. When performing data write operations, the SSD in an in-vehicle infotainment system needs to handle write requests from different data sources, such as the vehicle's main control unit, navigation module, and communication module, and complete data storage through processes such as caching, logical address resolution, address mapping, and NAND flash memory writing. When the in-vehicle infotainment system performs online software upgrades, the upper-level upgrade program typically sends continuous write requests to the SSD according to the software version and target logical address range corresponding to the current upgrade task. After the upgrade task is replaced, canceled, or interrupted, data that has entered the SSD's cache space but has not yet been persistently written may still be in a cache waiting or data migration state. If the SSD cannot obtain the change status of the current upgrade task in a timely manner, or if the write task identifier is not continuously associated with the cached data and address mapping relationship, the cached data corresponding to the original upgrade task may still continue to be written according to the original write command, causing invalid upgrade data to be written to a logical address range that does not correspond to the current valid upgrade task, or causing a write conflict between interrupted recovery data and the current task data.

[0005] Existing technologies focus on verifying the write command, access conditions, and data to be written when a write request enters the solid-state drive (SSD). After successful verification, subsequent writing is performed according to predetermined cache allocation and address mapping relationships. However, this approach struggles to continuously associate the valid state of the upgrade task with cached data, target logical addresses, actual physical mapping units, and write results during cache waiting, data migration, task switching, and interrupt recovery. When the upper-layer upgrade task changes, the incomplete write process within the SSD may fail to respond promptly to the task failure status, causing the data corresponding to the original write task to continue to be persistently written. This makes it difficult to guarantee the task trustworthiness, address correspondence consistency, and storage result reliability during the vehicle software upgrade data writing process.

[0006] Therefore, during the data writing process of solid-state drives in such application terminals, there may be invalid write commands that may still drive cached data to continue writing to mismatched physical storage areas, thus making the write results unreliable. Summary of the Invention

[0007] This invention provides a solid-state drive (SSD) data write control method and system based on trusted verification. Addressing the issue that during data write operations on an application terminal's SSD, a failed write command may still drive cached data to continue writing to a mismatched physical storage area, leading to unreliable write results. One aspect of this invention provides a SSD data write control method based on trusted verification, comprising: acquiring a write request issued by the application terminal host; performing trusted verification on the write request; and associating the verified task identifier, task validity status, version identifier, and target logical address range to form trusted write information; after the data to be written enters the SSD's cache space, forming a write... The system establishes a trusted continuation relationship; it obtains the current write task status provided by the application terminal host side, as well as the cache status and candidate address mapping status inside the solid-state drive controller. When the data to be written transitions from the cache status to the data transfer status, flash write preparation status, or interrupt recovery status, it performs a corresponding verification with the trusted continuation relationship to determine the trusted continuation status corresponding to the data to be written. When the trusted continuation status meets the write requirements, it executes the flash write of the data to be written according to the target logical address and the current address mapping status. When the trusted continuation status does not meet the write requirements, it re-matches the data to be written in the cache according to the currently valid write task information to determine the continued write status. It obtains the flash write result, address mapping submission result, and data verification result corresponding to the data to be written, and performs result verification.

[0008] In another aspect, the present invention provides a solid-state drive (SSD) data write control system based on trusted verification, comprising: a trusted association module: acquiring write requests issued by the application terminal host side, performing trusted verification on the write requests, and associating the verified task identifier, task validity status, version identifier, and target logical address range to form trusted write information; a trusted acceptance module: after the data to be written enters the cache space of the SSD, forming a trusted write acceptance relationship based on the state transition relationship of the data to be written between request reception, caching, address mapping, and flash memory writing; and an acceptance relationship verification module: acquiring the current write task status provided by the application terminal host side, as well as the cache status and candidate data within the SSD controller. The address mapping status is checked against the trusted continuation status when the data to be written transitions from the cache state to the data migration state, flash write preparation state, or interrupt recovery state, to determine the trusted continuation status corresponding to the data to be written. The trusted requirement confirmation module performs flash write of the data to be written based on the target logical address and the current address mapping status when the trusted continuation status meets the write requirements. When the trusted continuation status does not meet the write requirements, it re-matches the data to be written in the cache based on the currently valid write task information to determine the continued write status. The trusted result verification module obtains the flash write result, address mapping submission result, and data verification result corresponding to the data to be written, and performs result verification.

[0009] The beneficial effects achieved by the technical solutions provided in the embodiments of the present invention include at least the following: (1) By obtaining the write request sent by the application terminal host, the write request is verified with trust. The verified task identifier, task validity status, version identifier and target logical address range are associated to form trusted write information. Compared with the traditional method, it realizes a trusted correspondence between the write request and the upper layer write task. It can identify write requests with untrusted source, mismatched permissions, inconsistent versions or out-of-bounds target logical address before the data to be written enters the cache space, reducing the situation of invalid data or wrong version data entering the subsequent writing process.

[0010] (2) By forming a reliable write succession relationship based on the state transition relationship between request reception, caching, address mapping and flash writing of the data to be written after it enters the cache space of the solid-state drive, compared with the traditional method, it realizes the continuous association between the same write task in different write processing stages, enabling the solid-state drive controller to continuously locate the corresponding cache location, target logical address, candidate physical storage area and flash writing status according to the task identifier, write instruction identifier and data segment identifier, thereby improving the traceability and succession accuracy of the write status in multiple stages.

[0011] (3) By obtaining the current write task status provided by the application terminal host side and the cache status and candidate address mapping status inside the solid-state drive controller, when the data to be written changes from the cache status to the data transfer status, flash write preparation status or interrupt recovery status, it performs corresponding verification with the write trusteeship relationship to determine the trusteeship continuation status corresponding to the data to be written. Compared with the traditional method, it realizes the transformation from one-time trustee verification at the write entry point to continuous trustee verification during the write process. It can promptly identify task failure, version change, incomplete cache data or abnormal candidate address mapping, and reduce the possibility of abnormal data continuing to enter the flash programming stage.

[0012] (4) When the write requirement is met in the trusted continuation state, the flash memory write of the data to be written is performed according to the target logical address and the current address mapping state. When the write requirement is not met in the trusted continuation state, the data to be written in the cache is re-matched according to the currently valid write task information to determine the state to continue writing. Compared with the traditional method, it realizes the differentiation of normal write data, recoverable abnormal data and unrecoverable abnormal data. It can directly perform flash memory write on the data that meets the requirements, and can also recover the data that can continue to be written by adjusting the cache retention time, data moving order, segmented write order and write priority, and promptly prevent the failed data from being repeatedly scheduled or continued to be written.

[0013] (5) By obtaining the flash write result, address mapping submission result and data verification result corresponding to the data to be written, and performing result verification, compared with the traditional method, it realizes the joint confirmation between flash programming result, actual write location, readback data and address mapping submission result. When all results are consistent, the candidate physical storage area can be confirmed as a valid physical storage area, and when the result is abnormal, the candidate address mapping is prevented from taking effect and the original valid address mapping relationship is retained, thereby reducing the impact of data write abnormality or mapping error on the original valid data and improving the accuracy and reliability of solid-state drive data write results.

[0014] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1This is a flowchart illustrating the solid-state drive data write control method based on trusted verification according to Embodiment 1 of the present invention. Figure 2 This is a graph showing the relationship between the write data length distribution and concurrent processing time according to Embodiment 1 of the present invention; Figure 3 This is a distribution diagram of the processing time of different processing stages in the write trusted acceptance process according to Embodiment 1 of the present invention; Figure 4 This is a diagram illustrating the relationship between the write results provided in Embodiment 1 of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] Example 1

[0020] Figure 1A flowchart illustrating a solid-state drive (SSD) data write control method based on trusted verification is provided. This method includes: obtaining write requests from the application terminal host; performing trusted verification on the write requests; and associating the verified task identifier, task validity status, version identifier, and target logical address range to form trusted write information; after the data to be written enters the SSD's cache space, forming a trusted write succession relationship based on the state transition relationship between request reception, caching, address mapping, and flash writing; and obtaining the current write task status provided by the application terminal host, as well as the cache status and candidate address mapping within the SSD controller. In the write state, when the data to be written transitions from the cache state to the data transfer state, flash write preparation state, or interrupt recovery state, the corresponding trusted continuation state is checked with the write trusted continuation relationship to determine the trusted continuation state corresponding to the data to be written. When the trusted continuation state meets the write requirements, the flash write of the data to be written is performed according to the target logical address and the current address mapping state. When the trusted continuation state does not meet the write requirements, the data to be written in the cache is re-matched according to the currently valid write task information to determine the continue write state. The flash write result, address mapping submission result, and data verification result corresponding to the data to be written are obtained and the results are verified.

[0021] In one specific embodiment, the application terminal is an in-vehicle information system. If the in-vehicle information system is equipped with a 256GB NVMe solid-state drive, the nominal read speed of the solid-state drive is 3000MB / s, the nominal write speed is 2500MB / s, and the size of a single logical block is 512 bytes. The in-vehicle information system executes an online software upgrade task, the task identifier is OTA-001, the upgrade version is V2.2, and the allowed write target logical address range is 0x400000 to 0x47FFFF.

[0022] Taking data segment SEG-01 as an example, its data size is 8MB, and the target logical address is from 0x410000 to 0x413FFF. The system receives the corresponding write request at 0ms, and the request source trust status, write permission status, version matching status, and logical address range matching status are all recorded as 1, confirming that the write request has passed the trust verification. At 4ms, data segment SEG-01 completes cache writing, corresponding to cache region C-03, with a cache data integrity rate of 100%. At 6ms, the solid-state drive controller determines the candidate physical storage region P-128, records the address mapping status as pending submission, and records the candidate physical storage region's callable status as 1. At 8ms, data segment SEG-01 enters the flash write preparation state. At this time, the task validity status is 1, the version matching status is 1, the cache data integrity rate is 100%, and the candidate address mapping consistency status is 1. Therefore... The system determines that the data to be written is in a trusted continuation state and performs flash programming on candidate physical storage region P-128. At 14ms, the flash programming completion rate reaches 100%, and the verification results of the data to be written and the readback data are consistent, with the data consistency status recorded as 1. Subsequently, the address mapping commit status changes from 0 to 1, confirming candidate physical storage region P-128 as the valid physical storage region corresponding to the target logical address, and releasing cache region C-03. For data segment SEG-02, during the flash write preparation phase, the callable status of candidate physical storage region P-129 changes from 1 to 0, while the task validity status remains 1 and the cache data integrity rate remains 100%. The SSD controller re-determines candidate physical storage region P-135. After re-matching, the callable status of the candidate physical storage region returns to 1, the data to be written again meets the trusted continuation requirements, and flash writing continues.

[0023] The above process needs further explanation. The specific process for forming trusted write information is as follows: The write instruction type, write data length, starting logical block address, number of logical blocks, and target logical address obtained based on the starting logical block address and number of logical blocks are extracted from the write request. Write task information associated with the write request is also obtained. This write task information includes the request source identifier, access permissions, task identifier, task validity status, version identifier, and target logical address range. The target logical address range represents the range of logical block addresses that the current write task allows the data to be written to occupy, including the start and end addresses of the corresponding logical address range and the range of data allowed to be written. The data to be written represents the data content generated and distributed to the solid-state drive (SSD) by the application terminal host based on the current write task, waiting to be written to the physical storage area corresponding to the target logical address. It should be explained that the write request, the data to be written, etc., enter the SSD through the data interface on the application terminal host side.

[0024] The request source identifier is matched with the pre-configured trusted write sources in the SSD controller. Based on access permissions, it is determined whether the data to be written corresponding to the current request source identifier has write permissions for the data type and target logical address range. Write requests with write permissions and matching trusted write sources are marked as trusted sources; write requests with mismatched trusted write sources and / or lacking write permissions are marked as untrusted sources, thus obtaining the source trust verification result. The write instruction type, write data length, and target logical address are compared with the write operation type, allowed write data length, and target logical address range limited by the corresponding write task. Write requests that meet all task constraints are marked as consistent, while write requests that do not meet at least one constraint are marked as inconsistent. This yields a consistency check result. Task constraints refer to the constraints imposed by the current write task on the allowed types of write operations, the length of the written data, and the allowed logical address range. Based on the task identifier, the current set of write tasks is obtained from the host side of the application terminal. The corresponding write task is located from the current set of write tasks, and the version identifier and target logical address associated with the write request are matched with the current version identifier and target logical address range of the corresponding write task to obtain a valid task check result.

[0025] Furthermore, when the source trust verification result indicates that the write request source is trustworthy, the instruction consistency verification result indicates that the write instruction meets the task constraints, and the task validity verification result indicates that the corresponding write task is in an executeable state, the current write request is determined to have passed the trust verification. For write requests that fail the trust verification, the corresponding write request is rejected, no cache space is allocated for the data to be written, and a write rejection status is returned to the application terminal host. The task identifier allocated by the application terminal host for the current write task is obtained, and based on the task identifier, the task validity status, version identifier, and target logical address range corresponding to the current write task, as well as the write instruction identifier, target logical address, and write data length corresponding to the current write request, are determined. The data digest and trusted verification results are uniformly associated and recorded to generate trusted write information. This information is used to associate the corresponding write task with the cached data, cache location, and target logical address after the data to be written enters the cache space. The cache location represents the cache area allocated by the SSD controller for the data to be written and the starting position and occupied range of the data to be written within that cache area. The data digest represents fixed-length feature data obtained by processing the data to be written according to a preset digest algorithm. It is used to characterize the content features of the data to be written and to determine whether the corresponding data content has changed during cache writing, flash programming, and readback verification. The preset digest algorithm includes a hash algorithm and / or a cyclic redundancy check algorithm.

[0026] The valid verification result mentioned refers to the judgment result of whether the write task corresponding to the write request is in an allowed execution state. An allowed execution state means that the corresponding write task has not been canceled, replaced or terminated, the version identifier associated with the write request is consistent with the current version identifier of the corresponding write task, and the target logical address is within the target logical address range currently defined by the corresponding write task. Wherein, the target logical address being within the target logical address range currently defined by the corresponding write task means that the starting logical block address is not less than the starting address of the target logical address range, and the starting logical block address and the end logical block address (which determines the number of logical blocks) are not greater than the end address of the target logical address range.

[0027] In one specific embodiment, by performing a collaborative verification of the request source, write permission, write instruction, version identifier, and target logical address before the data segment SEG-01 enters the cache area C-03, the trusted correspondence between the data segment and the software online upgrade task OTA-001 can be confirmed in advance. Specifically, the trusted status of the request source, the write permission status, the version matching status, and the logical address range matching status are all 1, and the target logical address 0x410000 to 0x413FFF corresponding to the data segment SEG-01 is within the range of 0x400000 to 0x47FFFF limited by the task OTA-001. Therefore, the data segment is allowed to enter the cache space, and the task identifier OTA-001, version identifier V2.2, write data length of 8MB, target logical address, and trusted verification result are uniformly associated to form trusted write information.

[0028] Figure 2 This application provides a diagram showing the relationship between the write data length distribution and concurrent processing time in an embodiment of the application; as follows: Figure 2 As shown in (a), this is a cumulative distribution chart of the written data length in this embodiment. The horizontal axis represents the written data length in units of 512-byte logical blocks, and the vertical axis represents the cumulative proportion of the corresponding written data length. In this embodiment, 984 software online upgrade data segments with n as the statistical object are selected, and the data volume of each data segment is 8MB; calculated based on a single logical block of 512 bytes, each data segment corresponds to 16384 logical blocks, i.e., 2 14 The cumulative percentage increases from 0 to 1 when the write length reaches 16384 logical blocks; for example... Figure 2(b) shows the relationship between the number of 8MB data segments waiting to be processed simultaneously and the average completion time of a single data segment. The horizontal axis represents the number of 8MB data segments waiting to be processed simultaneously, and the vertical axis represents the average completion time of a single data segment. The background darkness represents the data segment density within different concurrency levels and completion time intervals. The record density is represented by logarithmic counts. The curve represents the conditional median completion time for the corresponding concurrency level, and the interval around the curve represents the quartile range of the completion time. As shown in the figure, as the number of data segments waiting to be processed simultaneously gradually increases from 1 to 32, the conditional median completion time of a single data segment generally shows an upward trend. This is because after the number of concurrent data segments increases, different write requests need to share cache space, data transfer channels, flash write channels, and address mapping processing resources, causing some data segments to wait. Under some concurrency conditions, the quartile range expands significantly, indicating that a small number of data segments have longer completion times due to the reselection of candidate physical storage areas, write channel conflicts, or rematching processing, but most records are still concentrated in the lower time interval.

[0029] In this embodiment, by forming trusted write information, data segments can always locate their corresponding upgrade task, cached data, and target logical address based on the task identifier and write instruction identifier during subsequent cache residency, candidate physical storage area allocation, flash programming, and address mapping submission processes. When an upgrade task is canceled, the version identifier changes, the request source becomes untrustworthy, or the target logical address exceeds the allowed range, the corresponding write request can be blocked before the data to be written enters the cache space, preventing invalid upgrade data from occupying the cache space or being written to a non-target logical address. After the data has entered the cache space, the trusted write information can also serve as the basis for trusted continuation verification and write result verification, enabling the solid-state drive controller to determine whether the cached data, candidate physical storage area, and actual write result are still consistent with the original write task, thereby reducing the possibility of erroneous data continuing to be written due to task switching, version updates, or write interruptions, and improving the continuity, accuracy, and reliability of data writing during online upgrades of the vehicle information system software.

[0030] The specific process for establishing and writing trusted inheritance relationships is as follows: Based on the write command reception status, the cache status of the data to be written, the mapping processing status of the target logical address, and the flash write status of the data to be written, the corresponding receive status data, cache status data, mapping processing status data, and flash write status data are confirmed. According to the processing order of the data to be written from request reception, caching, and candidate address mapping to flash write, based on the same task identifier, write command identifier, and data segment identifier, the receive status data, cache status data, mapping processing status data, and flash write status data are correlated to form a reliable write succession relationship.

[0031] The receive status indicates the progress of the SSD controller in receiving, parsing, and verifying write requests; the cache status indicates the completion, residence, occupation, movement, and release status of data to be written after it enters the cache space; the mapping processing status indicates the generation, adjustment, pending submission, and submission status of the candidate physical storage area corresponding to the target logical address; the flash write status indicates the waiting, execution, completion, or interruption status of flash programming of data to be written to the candidate physical storage area; the receive status data includes the write instruction identifier, write request reception time, and request reception completion time, etc.; the cache status data includes the cache area identifier, cache start position, cache write completion status, and cache data digest, etc.; the mapping processing status data includes the target logical address, mapping processing identifier, and candidate physical storage area, etc. The mapping processing identifier represents the identification information allocated by the SSD controller for the address mapping process corresponding to the current target logical address, used to distinguish different write requests. The corresponding candidate address mapping and candidate physical storage area represent the range of physical pages and / or physical blocks temporarily determined by the solid-state drive controller based on the target logical address, the available state of flash memory space, and the state of physical media. The candidate physical storage area is not considered a valid physical storage area corresponding to the target logical address before the address mapping relationship is submitted. Flash write status data includes flash write instructions, flash programming execution instructions, and write interrupts. For stages that have not yet been executed, the corresponding stage is recorded as pending processing. When the data to be written enters the corresponding processing stage, the corresponding write status is updated. For example, for address mapping stages and flash write stages that have not yet been executed, the corresponding stage is recorded as pending processing. When the data to be written enters the corresponding processing stage, the mapping processing status and flash write status in the trusted write relationship are updated. The data segment identifier represents the identification information corresponding to different data segments to be written under the same write task or write request, used to distinguish the segment sequence number of each data segment.

[0032] like Figure 3 The figure shows the distribution of processing time for different stages in the trusted write process. The horizontal axis represents the write stage, and the vertical axis represents the processing time of each stage. The stages are: request reception, trusted verification, cache writing, cache residency, candidate address mapping, data migration, trusted continuation verification, re-matching, flash write preparation, flash programming, readback verification, and address mapping submission, arranged sequentially according to the data writing process. The vertical axis represents the processing time for each stage. As can be seen from the figure, the processing time for the status judgment stages such as request reception, trusted verification, trusted continuation verification, and address mapping submission is relatively short. The cache writing, candidate address mapping, flash programming, and readback verification stages require data transmission, physical page filtering, or data reading, and therefore have relatively long processing times.

[0033] In this embodiment, by forming a trusted write connection, the state data generated by data segments at different write stages can be continuously associated. For example, after receiving a write request at 0ms, the write instruction identifier, request reception time, and trusted verification result are recorded as reception state data. After completing cache writing at 4ms, the cache region C-03, cache start position, and cache data integrity rate of 100% are recorded as cache state data. After determining the candidate physical storage region P-128 at 6ms, the corresponding target logical address, mapping processing identifier, candidate physical storage region, and pending submission status are recorded as mapping processing state data. After entering the flash write preparation state at 8ms, the flash programming waiting state is updated to the flash write state data, and the corresponding programming completion state is further updated after the flash programming is completed at 14ms.

[0034] By associating the aforementioned status data using the task identifier OTA-001, write command identifier, and data segment identifier SEG-01, the SSD controller can locate the cache location, target logical address, candidate physical storage area, and flash memory write progress corresponding to the data segment at any processing stage. This prevents the loss of status correspondence between different processing stages due to cache relocation, candidate physical storage area adjustment, or write interruption. For data segment SEG-02, when the candidate physical storage area is adjusted from P-129 to P-135, the mapping processing status data can also be updated synchronously, allowing subsequent reliable continuation verification to be performed based on the adjusted candidate physical storage area. This improves the traceability and write succession accuracy of the data to be written during multi-stage status transitions.

[0035] Then, the specific process for determining the trusted continuation state corresponding to the data to be written is as follows: Monitor whether the data to be written has transitioned from the cache state to the data migration state, flash write preparation state, or interrupt recovery state; the flash write preparation state indicates that flash programming has not yet begun; if no corresponding state transition result is detected, it indicates that the data to be written is still in the current cache resident state, so the current trusted continuation relationship is retained. After detecting the state transition, the corresponding verification of the write task, cache data, and address mapping relationship is performed; if the corresponding state transition result is detected, the corresponding verification of the write task, cache data, and address mapping relationship is triggered, specifically as follows: Based on the task identifier, write instruction identifier, and data segment identifier, locate the cache state corresponding to the data to be written from the trusted continuation relationship. The process involves processing state data and mapping status data. The current write task status is compared with the task validity status, version identifier, and target logical address range recorded in the trusted write information to determine if the write task is valid. Specifically, the process is as follows: The current write task is retrieved from the host side of the application terminal based on the task identifier. It is determined whether the current write task is in a continuing execution state. The version identifier of the current write task is compared with the version identifier recorded in the trusted write information to determine if they match. It is also determined whether the target logical address corresponding to the data to be written is still within the current target logical address range. If the current write task is in a continuing execution state (i.e., the write task has not been canceled or replaced, the version identifier matches, and the target logical address is still within the current target logical address range), the write task is determined to be valid; otherwise, the write task is determined to be invalid.

[0036] The current cache state obtained from the SSD controller is compared with the cache state data to determine whether the data to be written is completely stored in the corresponding cache space. The specific process is as follows: When the data to be written is still in the corresponding cache space and has not been overwritten, released, or missing, it is determined that the data to be written is completely stored in the corresponding cache space; otherwise, it is determined that the data to be written is not completely stored in the corresponding cache space. Overwriting indicates that the cache area corresponding to the data to be written has been reclaimed and reallocated to other write requests; releasing indicates that the corresponding cache space has been reclaimed by the SSD controller and remarked as allocable; missing indicates that the data length, data segments, or data content of the data to be written is incomplete.

[0037] The current address mapping status obtained from the SSD controller is compared with the mapping processing status data to determine whether the corresponding address mapping process is normal. The specific process is as follows: the current mapping processing identifier, target logical address, and candidate physical storage area are compared with the corresponding content recorded in the mapping processing status data to determine whether the candidate physical storage area has not been occupied by other write requests, reallocated, or pre-submitted as a valid address mapping. If the above requirements are met, it is determined that the candidate physical storage area corresponds to the data to be written and has not been abnormally submitted; otherwise, it is determined that the address mapping relationship is abnormal. When it is determined that the write task is valid, the data to be written is completely stored in the corresponding cache space, and the address mapping process is normal, the corresponding data to be written is recorded as being in a trusted continuation state; otherwise, it is recorded as being in an untrusted continuation state. The candidate physical storage area represents the range of physical pages and / or physical blocks that the SSD controller filters and temporarily reserves based on the complete target logical address range, the available physical page status, the bad block status, and the physical area occupancy status, and is used to undertake the flash programming of the current data to be written. The candidate physical storage area has a corresponding reservation identifier and remains in a reserved state before the address mapping is published. It is not used as a valid physical storage area corresponding to the complete target logical address range.

[0038] In one embodiment, when data segment SEG-01 transitions from cache-resident state to flash write preparation state at 8ms, the solid-state drive controller locates the corresponding status data from trusted write information and trusted write succession relationships based on task identifier OTA-001, write command identifier, and data segment identifier SEG-01. At this time, the host-side feedback upgrade task OTA-001 is still in the continuing execution state, the version identifier is still V2.2, and the target logical address 0x410000 to 0x413FFF is still within the allowed write range 0x400000 to 0x47FFFF; cache area C-03 has not been released or reallocated, and the cache data integrity rate is 100%; candidate physical storage area P-128 is still in the callable state, and the current mapping processing identifier, target logical address, and candidate physical storage area are consistent with the records in the mapping processing status data. Therefore, the task valid state, cache data integrity state, and address mapping processing normal state are all recorded as 1, determining that data segment SEG-01 is in a trusted continuation state, allowing it to continue executing flash programming.

[0039] In this embodiment, by performing trusted continuation verification at state transition nodes such as data migration, flash write preparation, or interrupt recovery, it is possible to avoid relying solely on a single trusted verification at the time of the write request. This allows for timely identification of task failures, version changes, missing cached data, or abnormal candidate physical storage areas that occur after data enters the cache. For example, for data segment SEG-02, when the callable state of candidate physical storage area P-129 changes from 1 to 0, even if the task validity state remains 1 and the cached data integrity rate remains 100%, it can still be determined as an untrusted continuation state. Flash programming to P-129 is then suspended, and a new candidate physical storage area P-135 is determined. This prevents data to be written from continuing to be written to failed or abnormal physical storage areas, improving the continuous correspondence between cached data, write tasks, and address mapping relationships, as well as the reliability of flash writes during online software upgrades.

[0040] Next, when the trusted continuation state meets the write requirements, the flash memory write of the data to be written is performed according to the target logical address and the current address mapping state. When the trusted continuation state does not meet the write requirements, the data to be written in the cache is re-matched according to the currently valid write task information to determine the write continuation state. The specific process is as follows: When the data to be written is detected as being in a trusted continuation state, it is determined that the write requirements are met. The corresponding physical storage area is determined according to the target logical address and the current address mapping state. The specific process is as follows: The address mapping state inside the solid-state drive controller is queried according to the target logical address. Combined with the available physical pages, bad block status, and physical area occupancy status, the target physical storage area is determined from the candidate physical storage areas in the writable state. The target physical storage area is associated with the current data to be written and recorded as the address mapping to be committed for subsequent flash programming. If the data to be written is detected as being in an untrusted continuation state, it is determined that the write requirements are not met. The movement or writing of the corresponding data to be written is paused. The data to be written in the cache is re-matched according to the currently valid write task information to determine whether the write continuation requirements are met. Specifically, this includes: The solid-state drive controller adjusts one or more of the following parameters for the data to be written: cache retention time, data migration order, segmented write order, and write priority. Based on the adjusted cache state, data migration state, and address mapping state, it synchronously updates the write trust relationship. When the write requirements are met, it continues to determine the corresponding physical storage area based on the target logical address and the current address mapping state. If the number of adjustments reaches a preset rematching threshold, or in another embodiment, the number of adjustments reaches the upper limit of a preset rematching range, and the data to be written still does not meet the write requirements, it is marked as a write failure state, and the corresponding data migration, flash programming, and address mapping submission are stopped. By setting a preset rematching threshold and a preset rematching range, a limited recovery opportunity can be reserved for effective write tasks when the candidate physical storage area is unavailable, the write channel conflicts, or a recoverable write interruption occurs.

[0041] In one embodiment, when data segment SEG-01 is determined to be in a trusted continuation state, the solid-state drive controller, based on its target logical addresses 0x410000 to 0x413FFF, available physical page status, bad block status, and physical region occupancy status, confirms that candidate physical storage region P-128 meets the write conditions and records the corresponding address mapping relationship as pending submission to continue flash programming. Therefore, for data to be written that is valid, has complete cached data, and a normal address mapping status, writing can continue directly along the established trusted continuation relationship, avoiding repeated cache scheduling and candidate physical storage region allocation, and improving the continuity of data writing during online software upgrades.

[0042] For data segment SEG-02, when the callable status of candidate physical storage region P-129 changes from 1 to 0, although task OTA-001 is still valid, version ID is still V2.2, and cache data integrity is still 100%, the current address mapping status no longer meets the write requirements. Therefore, flash programming to P-129 is paused. The SSD controller adapts and adjusts the cache retention time, data migration order, segment write order, or write priority based on the current valid write task information, and re-determines candidate physical storage region P-135, synchronously updating the write trusteeship relationship. After one re-matching, the callable status of P-135 is 1, and data segment SEG-02 again meets the trusteeship continuation requirements. Because the preset re-matching threshold of 3 times has not been reached, it is allowed to continue flash writing.

[0043] The cache retention time mentioned refers to the length of time that the data to be written is allowed to remain in the cache resident state from the completion of the cache writing until it is moved, released or re-matched. The data moving order refers to the order in which different data to be written is transferred from the cache space to the flash write channel. The segmented write order refers to the order in which each data segment in the same write task is written to the flash according to the segment identifier and the target logical address relationship. The write priority refers to the processing priority determined by the solid-state drive controller when multiple data to be written are waiting to be processed at the same time, based on the write task status, data timeliness requirements and write recovery requirements. It should be noted that, in order to balance the handling requirements of recoverable write anomalies with avoiding repeated rescheduling of data to be written, this solution pre-stores preset data such as a threshold for the number of rematches and a preset range for the number of rematches in the system database. For example, regarding the preset threshold for the number of rematches, in one embodiment, abnormal write records formed when performing historical online software upgrade tasks using a 256GB NVMe SSD of the same specifications are obtained. The write task is still valid and the cached data remains intact, but data segments that trigger rematching due to unavailable candidate physical storage areas, write channel conflicts, or interruption of recoverable writes are counted. Taking 20 abnormal data segments as an example, 12 data segments meet the write requirements after one rematch, 5 data segments meet the write requirements after two rematches, 2 data segments meet the write requirements after three rematches, and the remaining 1 data segment still does not meet the write requirements after three rematches.

[0044] Therefore, the cumulative recovery rates corresponding to 1, 2, and 3 rematches are 60%, 85%, and 95%, respectively. The minimum number of rematches required to meet the preset recovery rate requirement is determined as the preset rematch number threshold; when the preset recovery rate requirement is 95%, the preset rematch number threshold is determined to be 3 times, and this is stored in the system database.

[0045] The preset rematch count range is determined based on the actual number of rematches required to recover and write each segment of abnormal data. The rematch counts corresponding to the 19 successfully recovered abnormal data segments are arranged in ascending order. Since recovery requires at least one rematch and the cumulative recovery rate reaches 95% when the number of rematches reaches three, one rematch is determined as the lower limit of the preset rematch count range, and three rematches are determined as the upper limit of the preset rematch count range, resulting in a preset rematch count range of one to three rematches.

[0046] In this embodiment, normal write data and recoverable abnormal data can be distinguished based on the trusted continuation status: normal write data is directly written to the flash memory, recoverable abnormal data is re-matched within a limited number of times, and data exceeding the recovery limit is terminated in time. This ensures the continuity of software online upgrade task writing while reducing cache occupation and control resource consumption caused by invalid retries.

[0047] Finally, the specific process for verifying the results is as follows: The system compares the actual target logical address of the flash programming with the target logical address recorded in the trusted write information, and compares the actual physical storage area of ​​the flash programming with the candidate physical storage area recorded in the mapping processing status data. It then determines whether the flash programming is complete and whether the readback data matches the data to be written. When flash programming is complete, the actual target logical address matches the target logical address recorded in the trusted write information, the actual physical storage area matches the candidate physical storage area recorded in the mapping processing status data, and the readback data matches the data to be written, the initial selection result is deemed successful, and the address mapping relationship between the target logical address and the candidate physical storage area is submitted. The address mapping relationship between the target logical address and the candidate physical storage area represents the temporary correspondence established by the SSD controller for the current write request between the target logical block address and the physical page and / or physical block to be written. This correspondence is used after flash programming and data verification are completed and the address mapping is successful. Before a successful submission, the address mapping relationship is in a pending submission state and does not replace the original valid address mapping relationship of the target logical address. The readback data indicates that the solid-state drive controller rereads the data content obtained from the actual written physical storage area after the flash memory programming is completed. The address mapping submission result between the logical address and the physical address is obtained, and the actual submitted target logical address and physical storage area are compared with the target logical address recorded in the trusted write information and the candidate physical storage area recorded in the mapping processing status data, respectively. When the address mapping submission is successful and the actual submitted target logical address and physical storage area are consistent with the corresponding recorded content, the final selection result verification is determined to be passed, the actual physical storage area is confirmed as the valid physical storage area corresponding to the target logical address, and the corresponding cache space is released. When there is a failure in the initial selection result verification or the final selection result verification, a write exception prompt is generated to prevent the corresponding candidate address mapping from taking effect, and the original valid address mapping relationship of the target logical address is retained.

[0048] In one embodiment, data segment SEG-01 completes flash programming in 14ms. The target logical address associated with this flash programming is 0x410000 to 0x413FFF, and the actual physical storage area written is P-128, which is consistent with the target logical address recorded in the trusted write information and the candidate physical storage area recorded in the mapping processing status data. At the same time, the flash programming completion rate is 100%, the verification result of the readback data and the data to be written is consistent, and the data consistency status is 1. Therefore, the initial selection result is determined to be passed, and the address mapping relationship between the target logical address 0x410000 to 0x413FFF and the candidate physical storage area P-128 is submitted.

[0049] During the address mapping submission process, the address mapping submission status changes from 0 to 1. The actual target logical address submitted is still 0x410000 to 0x413FFF, and the actual physical storage area submitted is still P-128, which is consistent with the corresponding record content. Therefore, the final selection result verification is confirmed, P-128 is confirmed as the valid physical storage area corresponding to the target logical address, and the cache area C-03 occupied by data segment SEG-01 is released.

[0050] Figure 4 This is a diagram illustrating the relationship between the write results provided in the embodiments of this application; for example... Figure 4 As shown in (a), this is a diagram illustrating the combined relationships between flash programming status, readback data consistency status, address mapping submission status, and the final processing result. The horizontal axis represents the final write result, and the vertical axis represents the programming-readback-mapping-submission combination. The color intensity represents the number of records. The statistical objects in the diagram are data segment records that have passed the trusted continuation verification and entered the flash writing process. Among them, 5465 records have completed flash programming, readback data consistency, and address mapping submission, corresponding to complete writing; 26 records have completed flash programming and readback data consistency, but address mapping submission failed, corresponding to retaining the original valid address mapping; 55 records have completed flash programming, but the readback data is inconsistent with the data digest in the trusted write information, corresponding to data verification anomalies and preventing address mapping publication; 46 records have flash programming failures and have not entered the valid address mapping publication stage, corresponding to retaining the original valid address mapping; as shown in the diagram... Figure 4As shown in (b), this is a distribution chart of end-to-end processing time corresponding to different final processing results. The horizontal axis represents the final write result, and the vertical axis represents the time taken for each data segment from receiving the write request to determining the final processing result, i.e., the end-to-end processing time. The write completion group needs to go through trusted verification, cache acceptance, trusted continuation verification, flash programming, readback verification, and address mapping submission in sequence. Therefore, its processing time remains within the normal write range. The programming or data verification anomaly group also needs to go through part or all of the flash programming and verification process. Therefore, its processing time is close to that of the normal write group, but some records have a longer processing time due to anomaly confirmation or retries. The address mapping submission failure group needs to perform mapping submission and failure handling after flash programming and readback verification are completed. Therefore, its median processing time and maximum processing time are relatively high.

[0051] This invention also provides a solid-state drive (SSD) data write control system based on trusted verification, comprising: a trusted association module: acquiring write requests issued by the application terminal host, performing trusted verification on the write requests, and associating the verified task identifier, task validity status, version identifier, and target logical address range to form trusted write information; a trusted acceptance module: after the data to be written enters the cache space of the SSD, forming a trusted write acceptance relationship based on the state transition relationship of the data to be written between request reception, caching, address mapping, and flash memory writing; and an acceptance relationship verification module: acquiring the current write task status provided by the application terminal host, as well as the cache status and candidate address mapping within the SSD controller. The system performs a series of checks on the write continuation state and the corresponding trusted continuation state. The first check involves the data transfer state, flash write preparation state, or interrupt recovery state, transitioning from the cache state to the data transfer state, flash write, and the trusted continuation state. The second check involves the trusted requirement confirmation module, which performs flash write of the data to be written based on the target logical address and the current address mapping state when the trusted continuation state meets the write requirements. When the trusted continuation state does not meet the write requirements, the system re-matches the data to be written in the cache based on the currently valid write task information to determine the continued write state. The third check involves the trusted result verification module, which obtains the flash write result, address mapping submission result, and data verification result corresponding to the data to be written and performs result verification.

[0052] In this embodiment, by performing preliminary selection verification on the flash programming results, actual write area, and readback data before address mapping submission, physical storage areas with incomplete programming, inconsistent data, or offset write areas can be prevented from entering the valid address mapping; by performing final selection verification on the actual submitted logical address and physical storage area after address mapping submission, it is possible to further prevent address mapping submission errors from causing subsequent read requests to point to non-target physical storage areas.

[0053] When the initial selection result verification fails, the candidate physical storage area will not enter the address mapping submission stage; when the final selection result verification fails, the corresponding candidate address mapping will be prevented from taking effect, and the original valid address mapping relationship of the target logical address will be preserved. Therefore, even if an anomaly occurs during this flash programming or address mapping submission process, the original valid data will not be directly replaced. This improves the consistency between data writing results and address mapping relationships during online upgrades of the vehicle information system software, reducing the possibility of upgrade data being unreadable due to data writing errors or mapping errors.

[0054] When the vehicle information system performs an online software upgrade, if there are situations such as temporary cancellation of the upgrade task, upgrade version switching, communication link interruption, changes in vehicle ignition status, insufficient solid-state drive cache space, or flash memory write anomalies, it may lead to the cancellation or replacement of write tasks, changes in the target logical address range, or overwriting, release, or segmentation loss of data in the cache. It may not be possible to restore the correspondence between the cache state and the current valid write task by adjusting the cache state or write execution order. If the cache retention time, data migration order, segmented write order, or write priority are still adjusted according to Example 1, since the corresponding anomalies cannot be eliminated by adjusting the write parameters, invalid data may continue to occupy cache space, invalid write tasks may be repeatedly scheduled, or incomplete data may enter the subsequent flash memory write stage. Based on this, taking Example 1 as a basis, the data to be written in the cache is re-matched and it is determined whether the requirements for continuing to write are met. This also includes: distinguishing the abnormal reasons corresponding to the untrusted continuation state and judging whether the following situations exist: when it is detected that the write task is canceled, replaced or terminated, the version identifier is inconsistent, the target logical address exceeds the current allowed write range, or the data to be written is released, missing or incompletely segmented, the corresponding data to be written is directly marked as a write failure state, the corresponding data migration, flash programming and address mapping release are stopped, and the corresponding cache space is released. If the above conditions are not detected, the solid-state drive controller adjusts one or more of the following: cache retention time, data migration order, segmented write order and write priority corresponding to the data to be written.

[0055] In this embodiment, by distinguishing the causes of anomalies corresponding to untrusted continuation states, unrecoverable anomalies such as write task failure, inconsistent version identifiers, out-of-bounds target logical address, and incomplete data to be written can be differentiated and processed from recoverable anomalies such as unavailable candidate physical storage areas, write channel conflicts, or recoverable write interruptions. For unrecoverable anomalies, the corresponding data to be written is directly marked as write-failed, which can prevent failed tasks or incomplete data from continuing to occupy cache space, participate in repeated scheduling, or enter the flash programming and address mapping submission stages. For data to be written that does not have unrecoverable conditions, the write conditions adapted to the current valid write task are re-established by adjusting the cache retention time, data migration order, segmented write order, and write priority.

[0056] This helps avoid using the same rematching method for different abnormal states, reduces invalid parameter adjustments and repeated write processing, and while preserving the opportunity for recoverable write tasks to continue execution, it promptly blocks unrecoverable data write processes, thereby reducing the invalid occupation of cache resources and flash write channels, preventing old version data, out-of-bounds data, or incomplete data from being written to solid-state drives, and improving the accuracy, recovery efficiency, and security of data write control during online upgrades of vehicle information system software.

[0057] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0058] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0059] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0060] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0061] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A solid-state drive data write control method based on trusted verification, characterized in that, include: Obtain the write request sent by the application terminal host, perform trusted verification on the write request, and associate the verified task identifier, task validity status, version identifier and target logical address range to form trusted write information; After the data to be written enters the cache space of the solid-state drive, a reliable write succession relationship is formed based on the state transition relationship between request reception, caching, address mapping and flash writing of the data to be written. The system obtains the current write task status provided by the application terminal host side, as well as the cache status and candidate address mapping status inside the solid-state drive controller. When the data to be written changes from the cache status to the data transfer status, flash write preparation status, or interrupt recovery status, it performs corresponding verification with the write trust succession relationship to determine the trust continuation status corresponding to the data to be written. When the trusted continuation state meets the write requirements, the flash memory write of the data to be written is performed according to the target logical address and the current address mapping state. When the trusted continuation state does not meet the write requirements, the data to be written in the cache is re-matched according to the currently valid write task information to determine the write continuation state. Obtain the flash write result, address mapping submission result, and data verification result corresponding to the data to be written, and verify the results.

2. The solid-state drive data write control method based on trusted verification according to claim 1, characterized in that, The process of obtaining the write request sent by the application terminal host and performing a trust verification on the write request is as follows: Extract the write instruction type, write data length, starting logical block address, number of logical blocks, and target logical address obtained based on the starting logical block address and number of logical blocks from the write request. Also obtain the write task information associated with the write request, including request source identifier, access permissions, task identifier, task validity status, version identifier, and target logical address range. The request source identifier is matched with the trusted write sources pre-configured in the solid-state drive controller. Based on the access permissions, it is determined whether the data to be written corresponding to the current request source identifier has write permissions for the type of data to be written and the target logical address range. Write requests that have write permissions and are matched with trusted write sources are marked as trusted sources. Write requests that do not match trusted write sources and / or do not have write permissions are marked as untrusted sources, thus obtaining the source trust verification result. The write instruction type, write data length, and target logical address are compared with the write operation type, allowed write data length, and target logical address range limited by the corresponding write task. Write requests that meet all the task's limitations are marked as instruction-consistent, and write requests that do not meet at least one of the task's limitations are marked as instruction-inconsistent, thus obtaining the instruction consistency verification result. Based on the task identifier, the current write task set is obtained from the host side of the application terminal, and the corresponding write task is located from the current write task set. The version identifier and target logical address associated with the write request are matched with the current version identifier and target logical address range of the corresponding write task to obtain the valid verification result of the task. The task validity verification result indicates whether the write task corresponding to the write request is in an allowed execution state; The allowed execution status indicates that the corresponding write task has not been canceled, replaced, or terminated, the version identifier associated with the write request is consistent with the current version identifier of the corresponding write task, and the target logical address is within the target logical address range currently defined by the corresponding write task.

3. The solid-state drive data write control method based on trusted verification according to claim 2, characterized in that, The process of associating the verified task identifier, task validity status, version identifier, and target logical address range to form trusted write information is as follows: When the source trust verification result indicates that the source of the write request is trustworthy, the instruction consistency verification result indicates that the write instruction meets the task limit conditions, and the task validity verification result indicates that the corresponding write task is in an allowed execution state, the current write request is determined to pass the trust verification. For write requests that fail the trust verification, the corresponding write request is rejected, no cache space is allocated for the data to be written, and a write rejection status is returned to the application terminal host side. Obtain the task identifier assigned to the current write task by the application terminal host. Based on the task identifier, uniformly associate and record the task validity status, version identifier, target logical address range, write instruction identifier, target logical address, write data length, data digest, and trusted verification result corresponding to the current write task, and generate trusted write information.

4. The solid-state drive data write control method based on trusted verification according to claim 3, characterized in that, The specific process for forming and writing a trusted inheritance relationship is as follows: Based on the receive status of the write instruction, the cache status of the data to be written, the mapping processing status of the target logical address, and the flash write status of the data to be written, confirm the corresponding receive status data, cache status data, mapping processing status data, and flash write status data. Based on the processing order of the data to be written, from request reception, caching, and candidate address mapping to flash memory writing, and using the same task identifier, write instruction identifier, and data segment identifier, the received status data, cached status data, mapping processing status data, and flash memory writing status data are correlated to form a reliable write succession relationship.

5. The solid-state drive data write control method based on trusted verification according to claim 4, characterized in that, The specific process for determining the trusted continuation state corresponding to the data to be written is as follows: Monitor whether the data to be written has transitioned from the cache state to the data transfer state, the flash write preparation state, or the interrupt recovery state; If no corresponding state transition result is detected, the current trusted write connection is retained. Once a state transition is detected, the corresponding verification of the write task, cached data, and address mapping relationship is performed. If the corresponding status transition result is detected, the corresponding verification of the write task, cached data and address mapping relationship is triggered. The specific process is as follows: Based on the task identifier, write instruction identifier and data segment identifier, locate the cached status data and mapping processing status data corresponding to the data to be written from the trusted write connection relationship. The current write task status is compared with the task validity status, version identifier, and target logical address range recorded in the trusted write information to determine whether the write task is valid. The specific process is as follows: the current write task is obtained from the host side of the application terminal based on the task identifier, it is determined whether the current write task is in the continuing execution state, the version identifier of the current write task is compared with the version identifier recorded in the trusted write information to see if they are consistent, and it is determined whether the target logical address corresponding to the data to be written is still within the current target logical address range. The write task is considered valid if the current write task is in a continuing execution state, the version identifier is consistent, and the target logical address is still within the current target logical address range; otherwise, the write task is considered invalid. The current cache state obtained from the SSD controller is compared with the cache state data to determine whether the data to be written is completely stored in the corresponding cache space. The specific process is as follows: If the data to be written is still in the corresponding cache space and has not been overwritten, released or missing, it is determined that the data to be written is completely saved in the corresponding cache space; otherwise, it is determined that the data to be written is not completely saved in the corresponding cache space. The current address mapping status obtained from the solid-state drive controller is compared with the mapping processing status data to determine whether the corresponding address mapping process is normal. The specific process is as follows: compare whether the current mapping processing identifier, target logical address and candidate physical storage area are consistent with the corresponding content recorded in the mapping processing status data, and determine whether the candidate physical storage area has not been occupied by other write requests, reallocated or submitted in advance as a valid address mapping. If the above requirements are met, it is determined that the candidate physical storage area corresponds to the data to be written and has not been abnormally submitted; otherwise, it is determined that the address mapping relationship is abnormal. If it is determined that the write task is valid, the data to be written is completely stored in the corresponding cache space, and the address mapping process is normal, the corresponding data to be written is recorded as being in a trusted continuation state; otherwise, it is recorded as being in an untrusted continuation state.

6. The solid-state drive data write control method based on trusted verification according to claim 5, characterized in that, When the trusted continuation state meets the write requirements, the flash memory write of the data to be written is performed according to the target logical address and the current address mapping state. When the trusted continuation state does not meet the write requirements, the data to be written in the cache is re-matched according to the currently valid write task information to determine the write continuation state, including: When the data to be written is detected as being in a trusted continuation state, it is determined that the write requirement is met. The corresponding physical storage area is determined based on the target logical address and the current address mapping status. The specific process is as follows: The address mapping status inside the solid-state drive controller is queried based on the target logical address. Combined with the available physical pages, bad block status, and physical area occupancy status, the target physical storage area is determined from the candidate physical storage areas in the writable state. The target physical storage area is associated with the current data to be written and recorded as the address mapping to be submitted for subsequent flash programming. If the data to be written is detected as being in an untrusted continuation state, it is determined that the writing requirements are not met. The movement or writing of the corresponding data to be written is paused, and the data to be written in the cache is re-matched based on the currently valid write task information to determine whether the requirements for continuing to write are met.

7. The solid-state drive data write control method based on trusted verification according to claim 6, characterized in that, The step of re-matching the data to be written in the cache and determining whether the writing requirement is met specifically includes: The solid-state drive controller adjusts one or more of the following: cache retention time, data migration order, segmented write order, and write priority for the data to be written. Based on the adjusted cache status, data migration status, and address mapping status, it synchronously updates the write trust relationship. When the write requirements are met, it continues to determine the corresponding physical storage area based on the target logical address and the current address mapping status. If the number of adjustments reaches the preset rematch threshold and the data to be written still does not meet the writing requirements, it will be marked as a write failure state, and the corresponding data transfer, flash programming and address mapping submission will be stopped.

8. The solid-state drive data write control method based on trusted verification according to claim 7, characterized in that, The specific process of obtaining the flash memory write result, address mapping submission result, and data verification result corresponding to the data to be written, and verifying the results, is as follows: The target logical address for actual flash programming is compared with the target logical address recorded in the trusted write information. The physical storage area for actual flash programming is compared with the candidate physical storage area recorded in the mapping processing status data. The system then determines whether flash programming is complete and whether the readback data is consistent with the data to be written. When flash programming is completed, the target logical address of the actual flash programming is consistent with the target logical address recorded in the trusted write information, the physical storage area of ​​the actual flash programming is consistent with the candidate physical storage area recorded in the mapping processing status data, and the readback data is consistent with the data to be written, the initial selection result is confirmed to be passed, and the address mapping relationship between the target logical address and the candidate physical storage area is submitted. Obtain the address mapping submission result between the logical address and the physical address, and compare the actual submitted target logical address and physical storage area with the target logical address recorded in the trusted write information and the candidate physical storage area recorded in the mapping processing status data, respectively. When the address mapping is successfully submitted, and the actual submitted target logical address and physical storage area are consistent with the corresponding record content, the final selection result is confirmed as passed, the actual physical storage area is confirmed as the valid physical storage area corresponding to the target logical address, and the corresponding cache space is released. If the initial selection result verification or the final selection result verification fails, a write exception prompt is generated to prevent the corresponding candidate address mapping from taking effect, while preserving the original valid address mapping relationship of the target logical address.

9. The solid-state drive data write control method based on trusted verification according to claim 6, characterized in that, The step of re-matching the data to be written in the cache and determining whether the writing requirement is met also includes: Distinguish the abnormal causes corresponding to the untrusted continuation state and determine whether the following situations exist: When it is detected that a write task is canceled, replaced, or terminated, the version identifier is inconsistent, the target logical address exceeds the current allowed write range, or the data to be written is released, missing, or the data segment is incomplete, the corresponding data to be written is directly marked as a write failure state. If the above conditions are not detected, the solid-state drive controller will adjust one or more of the following: cache retention time, data migration order, segmented write order, and write priority corresponding to the data to be written.

10. A solid-state drive data write control system based on trusted verification, characterized in that, include: Trusted Association Module: Obtains write requests sent from the application terminal host side, performs trusted verification on the write requests, and associates the verified task identifier, task validity status, version identifier, and target logical address range to form trusted write information; Trusted Acceptance Module: After the data to be written enters the cache space of the solid-state drive, a trusted acceptance relationship for writing is formed based on the state transition relationship between request reception, caching, address mapping and flash writing of the data to be written. The succession relationship verification module obtains the current write task status provided by the application terminal host side, as well as the cache status and candidate address mapping status inside the solid-state drive controller. When the data to be written changes from the cache status to the data transfer status, flash write preparation status, or interrupt recovery status, it performs corresponding verification with the write trust succession relationship to determine the trustworthy continuation status corresponding to the data to be written. Trusted Requirement Confirmation Module: When the trusted continuation state meets the write requirements, the flash memory write of the data to be written is performed according to the target logical address and the current address mapping state. When the trusted continuation state does not meet the write requirements, the data to be written in the cache is re-matched according to the currently valid write task information to determine the write continuation state. Trusted Result Verification Module: Obtains the flash write result, address mapping submission result, and data verification result corresponding to the data to be written, and performs result verification.

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