Asynchronous fifo circuit, processor, chip, electronic device, and data read / write method
Patent Information
- Application Number
- CN202510511707.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-22
- Publication Date
- 2026-10-23
AI Technical Summary
[0005]通过上述公式可以看出，上述异步FIFO电路中所采用的指针同步机制存在较大延迟
[0020]而相关的异步FIFO电路中所采用的指针同步机制，通常是在读指针和写指针均复位完成之后，才开始执行数据写入操作及写指针传输操作，并且，在数据写入过程中，需要额外通过读写指针相互同步机制将写指针传输至读指针控制单元。
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Figure CN122963497A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an asynchronous FIFO circuit, processor, chip, electronic device, and data read / write method. Background Technology
[0002] An asynchronous FIFO (First-In-First-Out) circuit is a first-in-first-out data storage and buffer used to transfer data between different clock domains.
[0003] To ensure smooth data read and write operations, current asynchronous FIFO circuits typically employ a pointer synchronization mechanism to synchronize the read pointer control unit and the write pointer control unit. The specific synchronization process includes: after both the read and write pointers are reset, during the data write process, when the write pointer control unit receives a write request, it moves the write pointer and stores the data in the corresponding memory location; then, the write pointer is converted into Gray code and transmitted to the read pointer control unit via a synchronizer. Similarly, after both the read and write pointers are reset, during the data read process, when the read pointer control unit receives a read request, it moves the read pointer and retrieves the data from the corresponding memory location; then, the read pointer is converted into Gray code and transmitted to the write pointer control unit via a synchronizer.
[0004] For the pointer synchronization mechanism used in the above asynchronous FIFO circuit, if the synchronizer uses an N-level register, then the delay time T fifo The calculation formula is: T fifo =T w +N*T r Among them, T fifo T represents the delay time of the asynchronous FIFO circuit, that is, the time interval from when data is written to the asynchronous FIFO circuit to when the data can be read out. w T represents the write clock cycle. r This indicates the clock cycle to be read.
[0005] As can be seen from the above formula, the pointer synchronization mechanism used in the asynchronous FIFO circuit has a significant delay. Summary of the Invention
[0006] In view of this, embodiments of the present disclosure provide an asynchronous FIFO circuit, processor, chip, electronic device, and data read / write method to at least solve or alleviate the above-mentioned problems.
[0007] According to a first aspect of the present disclosure, an asynchronous FIFO circuit is provided, comprising:
[0008] The reset control module is used to generate an asynchronous reset signal;
[0009] The write pointer control module is used to generate a write reset signal based on the asynchronous reset signal; send the write reset signal to the read pointer control module; and after the write pointer control module performs a write pointer reset operation based on the write reset signal, it toggles the write pointer according to the write clock frequency to continuously perform data write operations.
[0010] The read pointer control module is used to generate a read reset signal based on the write reset signal, and after performing a read pointer reset operation based on the read reset signal, toggles the read pointer according to the read clock frequency to continuously perform data reading operations; wherein, the write clock frequency is the same as the read clock frequency.
[0011] According to a second aspect of the present disclosure, a processor is provided, comprising: the asynchronous FIFO circuit described in the first aspect above.
[0012] According to a third aspect of the present disclosure, a chip is provided, comprising: the processor described in the second aspect above.
[0013] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: the processor described in the second aspect above, or the chip described in the third aspect above.
[0014] According to a fifth aspect of the present disclosure, a data read / write method is provided, applied to an asynchronous FIFO circuit, the asynchronous FIFO circuit including: a reset control module, a write pointer control module, and a read pointer control module, the method including:
[0015] The reset control module generates an asynchronous reset signal.
[0016] The write pointer control module generates a write reset signal based on the asynchronous reset signal; the write reset signal is sent to the read pointer control module, and after the write pointer control module performs a write pointer reset operation based on the write reset signal, the write pointer is toggled according to the write clock frequency to continuously perform data write operations.
[0017] The read pointer control module generates a read reset signal based on the write reset signal, and after performing a read pointer reset operation based on the read reset signal, it moves the read pointer according to the read clock frequency to continuously perform data reading operations; wherein, the write clock frequency is the same as the read clock frequency.
[0018] According to the asynchronous FIFO circuit provided in this embodiment, the reset control module generates an asynchronous reset signal and sends it to the write pointer control module. The write pointer control module first generates a write reset signal based on the asynchronous reset signal. Then, the write pointer control module performs two operations simultaneously: on the one hand, it performs a write pointer reset operation based on the write reset signal, and then toggles the write pointer according to the write clock frequency to continuously perform data writing operations; on the other hand, the write pointer control module transmits the write reset signal to the read pointer control module, so that after receiving the write reset signal, the read pointer control module generates a read reset signal and performs a read pointer reset operation based on the generated read reset signal, and then toggles the read pointer according to the read clock frequency to continuously perform data writing operations.
[0019] In this embodiment, after generating the write reset signal, the write pointer control module begins executing the write pointer reset operation and the data writing operation, while the read pointer control module also generates a read reset signal based on the write reset signal and executes a read pointer reset operation based on the read reset signal in parallel. That is, in this embodiment, while the read pointer control module is resetting the read pointer, the write pointer control module has already begun the data writing operation; that is, the data writing operation begins before the read pointer reset is completed. After both the read and write pointers are reset, during the data read / write process, both the read pointer control module and the write pointer control module maintain the same frequency to continuously toggle their pointers for continuous data read / write operations. Therefore, a fixed phase difference (i.e., a fixed difference relationship) between the read and write pointers can be maintained through a fixed time difference between the read and write pointer resets (this time difference depends on the time required for the read pointer control module to generate the read reset signal based on the write reset signal). Thus, without needing a mechanism for synchronizing the read and write pointers, the read pointer control module can always know the position of the write pointer in the write pointer control module and perform the data reading operation accordingly.
[0020] The pointer synchronization mechanism used in the related asynchronous FIFO circuit usually starts the data writing operation and the write pointer transmission operation only after both the read pointer and the write pointer have been reset. Furthermore, during the data writing process, an additional read-write pointer synchronization mechanism is required to transmit the write pointer to the read pointer control unit.
[0021] In summary, compared to asynchronous FIFO circuits employing pointer synchronization mechanisms, the asynchronous FIFO circuit in this embodiment maintains a fixed phase difference between the read and write pointers through a fixed time difference between their reset and release. Furthermore, the data writing operation begins before the read pointer reset is complete. Therefore, the latency of the asynchronous FIFO circuit is determined solely by the fixed time difference between the read and write pointer resets, without needing to consider the additional time required for data to be written to the asynchronous FIFO circuit. Consequently, the asynchronous FIFO circuit provided in this embodiment has lower latency. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.
[0023] Figure 1 This is a schematic diagram of the structural framework of an asynchronous FIFO circuit according to an embodiment of the present disclosure;
[0024] Figure 2 This is a schematic diagram of the structural framework of a reset control module according to an embodiment of the present disclosure;
[0025] Figure 3 This is a schematic diagram of the structural framework of a clock state detection unit according to an embodiment of the present disclosure;
[0026] Figure 4 This is a timing diagram of a clock state detection unit according to an embodiment of the present disclosure;
[0027] Figure 5 This is a schematic diagram of the structural framework of an asynchronous FIFO circuit according to another embodiment of the present disclosure;
[0028] Figure 6 This is a schematic diagram of the structural framework of an asynchronous FIFO circuit according to yet another embodiment of this disclosure;
[0029] Figure 7 This is a flowchart of a data read / write method according to an embodiment of this disclosure. Detailed Implementation
[0030] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.
[0031] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.
[0032] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.
[0033] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.
[0034] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.
[0035] See Figure 1 , Figure 1This is a schematic diagram of the structural framework of an asynchronous FIFO circuit according to an embodiment of the present disclosure. The asynchronous FIFO circuit 100 includes: a reset control module 102, a write pointer control module 104, and a read pointer control module 106.
[0036] Reset control module 102 is used to generate an asynchronous reset signal;
[0037] The write pointer control module 104 is used to generate a write reset signal based on the asynchronous reset signal; send the write reset signal to the read pointer control module; and after the write pointer control module performs a write pointer reset operation based on the write reset signal, it toggles the write pointer according to the write clock frequency to continuously perform data writing operations.
[0038] The read pointer control module 106 is used to generate a read reset signal based on the write reset signal, and after performing a read pointer reset operation based on the read reset signal, toggles the read pointer according to the read clock frequency to continuously perform data reading operations; wherein, the write clock frequency is the same as the read clock frequency.
[0039] Specifically, the reset control module 102 is a module for generating an asynchronous reset signal. An active asynchronous reset signal can be used to instruct the read and write pointers in the asynchronous FIFO circuit to be reset to their initial positions (typically pointing to a memory cell of a certain threshold), ensuring that the asynchronous FIFO circuit is in a known empty state. The active state of the asynchronous reset signal can also be predefined. For example, an asynchronous reset signal in a low-level state can typically be set as active, while an asynchronous reset signal in a high-level state can be set as released; conversely, an asynchronous reset signal in a high-level state can also be set as active, while an asynchronous reset signal in a low-level state can be set as released. In this embodiment, the definition of the active state of the asynchronous reset signal is not limited and can be customized according to actual conditions.
[0040] When a preset reset trigger condition is met, the reset control module 102 generates an asynchronous reset signal. For example, the preset reset trigger condition may be: asynchronous FIFO circuit initialization, asynchronous FIFO circuit being empty (read pointer equal to write pointer), one of the read clock signal and write clock signal being turned off, the read clock frequency corresponding to the read clock signal and the write clock frequency corresponding to the write clock signal being different, other custom reset trigger conditions, etc. In this embodiment, the specific content of the preset reset trigger condition is not limited.
[0041] After generating the asynchronous reset signal, the reset control module 102 sends the signal to the write pointer control module 104. Upon receiving the asynchronous reset signal, the write pointer control module 104 generates a write reset signal. If the write reset signal is in a valid state (the state of the write reset signal depends on the asynchronous reset signal; when the asynchronous reset signal is valid, the write reset signal will also be valid; conversely, when the asynchronous reset signal is released, the write reset signal will also be released), then a write pointer reset operation is performed, thereby resetting the write pointer to its initial position. Afterward, when the write reset signal is released, i.e., when the asynchronous reset signal is detected to be in a released state, the write pointer is toggled according to the write clock frequency to continuously perform data write operations.
[0042] In addition, after the write pointer control module 104 generates a write reset signal, it sends the write reset signal to the read pointer control module 104 while performing write pointer reset and data write operations based on the write reset signal. Upon receiving the write reset signal, the write pointer control module 104 generates a read reset signal. If the read reset signal is valid (the state of the read reset signal depends on the write reset signal; when the write reset signal is valid, the read reset signal will also be valid; conversely, when the write reset signal is released, the read reset signal will also be released), it performs a read pointer reset operation, thereby resetting the read pointer to its initial position. Then, when the read reset signal is released, i.e., when the asynchronous reset signal is detected to be released, the read pointer is toggled according to the read clock frequency to continuously perform data read operations.
[0043] According to the asynchronous FIFO circuit provided in this embodiment, the reset control module 102 generates an asynchronous reset signal and sends it to the write pointer control module 104. The write pointer control module 104 first generates a write reset signal based on the asynchronous reset signal. Then, the write pointer control module 104 performs two operations simultaneously: on the one hand, it performs a write pointer reset operation based on the write reset signal, and then toggles the write pointer according to the write clock frequency to continuously perform data writing operations; on the other hand, the write pointer control module 104 transmits the write reset signal to the read pointer control module 106, so that after receiving the write reset signal, the read pointer control module 106 generates a read reset signal and performs a read pointer reset operation based on the generated read reset signal, and then toggles the read pointer according to the read clock frequency to continuously perform data writing operations.
[0044] In this embodiment of the present disclosure, after generating the write reset signal, the write pointer control module 104 begins to execute the write pointer reset operation and the data write operation, while the read pointer control module 106 also generates a read reset signal based on the write reset signal and executes a read pointer reset operation based on the read reset signal in parallel. That is to say, in this embodiment of the present disclosure, while the read pointer control module 106 is performing the read pointer reset, the write pointer control module 104 has already begun to perform the data write operation, that is, the data write operation begins to be executed before the read pointer reset is completed. After both the read and write pointers have been reset, during the data read and write process, the read pointer control module 106 and the write pointer control module 104 maintain the same frequency to continuously toggle the pointers to perform data read and write operations. Therefore, a fixed phase difference (i.e., a fixed difference relationship) between the read pointer and the write pointer can be maintained by using a fixed time difference between the read pointer and the write pointer reset (this time difference depends on the time required for the read pointer control module 106 to generate the read reset signal based on the write reset signal). Thus, without the need for a mechanism to synchronize the read and write pointers, the read pointer control module 106 can always know the position of the write pointer in the write pointer control module 104 and then perform the data read operation.
[0045] The pointer synchronization mechanism used in the related asynchronous FIFO circuit usually starts the data writing operation and the write pointer transmission operation only after both the read pointer and the write pointer have been reset. Furthermore, during the data writing process, an additional read-write pointer synchronization mechanism is required to transmit the write pointer to the read pointer control unit.
[0046] In summary, compared to asynchronous FIFO circuits employing pointer synchronization mechanisms, the asynchronous FIFO circuit in this embodiment maintains a fixed phase difference between the read and write pointers through a fixed time difference between their reset and release. Furthermore, the data writing operation begins before the read pointer reset is complete. Therefore, the latency of the asynchronous FIFO circuit is determined solely by the fixed time difference between the read and write pointer resets, without needing to consider the additional time required for data to be written to the asynchronous FIFO circuit. Consequently, the asynchronous FIFO circuit provided in this embodiment has lower latency.
[0047] See Figure 1 Optionally, in some embodiments, the write pointer control module 104 may include a write reset synchronizer 1042 and a write pointer control unit 1044; the read pointer control module 106 includes a read reset synchronizer 1062 and a read pointer control unit 1064.
[0048] The write reset synchronizer 1042 is used to receive the asynchronous reset signal generated by the reset control module, and to process the asynchronous reset signal across clock cycles to obtain the write reset signal; the write reset signal is then sent to the write pointer control unit 1044 and the read reset synchronizer 1062 respectively.
[0049] The write pointer control unit 1044 is used to, after performing a write pointer reset operation based on a write reset signal, respond to the write reset signal being in a released state, to toggle the write pointer according to the write clock frequency and continuously perform data write operations.
[0050] The read reset synchronizer 1062 is used to process the write reset signal across clock cycles to obtain a read reset signal; and sends the read reset signal to the read pointer control unit 1064 so that after the read pointer control unit 1064 performs a read pointer reset operation based on the read reset signal, it responds to the read reset signal being in a released state, and moves the read pointer according to the read clock frequency to continuously perform data reading operations.
[0051] Specifically, in the asynchronous FIFO circuit of this embodiment, the write pointer control module 104 may include a write reset synchronizer 1042 and a write pointer control unit 1044. The write reset synchronizer 1042 performs cross-clock processing on the asynchronous reset signal received from the reset control module 102, thereby synchronizing the asynchronous reset signal, which is asynchronous with the write clock signal, to the write clock domain, transforming the asynchronous reset signal into a write reset signal synchronized with the write clock signal. Then, the write pointer control unit 1044 performs a write pointer reset operation based on the write reset signal, and when the write reset signal is in a released state, it toggles the write pointer according to the write clock frequency and continuously performs data writing operations.
[0052] Accordingly, the read pointer control module 106 may also include a read reset synchronizer 1062 and a read pointer control unit 1064. The read reset synchronizer 1062 performs cross-clock processing on the write reset signal received from the write reset synchronizer 1042, thereby synchronizing the write reset signal, which is asynchronous with the read clock signal, to the read clock domain, i.e., converting the write reset signal into a read reset signal synchronized with the read clock signal. Then, the read pointer control unit 1064 performs a read pointer reset operation based on the read reset signal, and when the read reset signal is in the released state, it toggles the read pointer according to the read clock frequency and continuously performs data reading operations.
[0053] In the above embodiments, a write reset synchronizer 1042 is provided in the pointer control module 104 to synchronize the generated write reset signal with the write clock signal, and a read reset synchronizer 1062 is provided in the read pointer control module 106 to synchronize the generated read reset signal with the read clock signal. By performing cross-clock processing on the signals, the clock domain mismatch problem in the internal operation of the asynchronous FIFO circuit can be effectively solved, thereby improving the performance and stability of the asynchronous FIFO circuit.
[0054] against Figure 1 The asynchronous FIFO circuit shown includes a write-reset synchronizer 1042 and a read-reset synchronizer 1062. The delay is determined by the delay of the read-reset synchronizer 1062. Assuming the read-reset synchronizer 1062 uses an N-level register structure, the delay calculation formula is as follows:
[0055] T fifo =N*T r
[0056] Among them, T fifo The delay of the asynchronous FIFO circuit; T r This is the clock cycle for reading.
[0057] N is the level of the N-level register, and N is an integer greater than 1.
[0058] As can be seen from the above formula, compared with the asynchronous FIFO circuit that uses a read-write pointer synchronization mechanism, the delay of the asynchronous FIFO circuit in this embodiment of the present disclosure is reduced by one write clock cycle.
[0059] Optionally, in some embodiments, when performing the step of performing a write pointer reset operation based on a write reset signal, the write pointer control unit 1044 is specifically configured to: control the write pointer to the initial value pointer position in response to the write reset signal being in an active state;
[0060] The read pointer control unit 1064, when performing the step of performing a read pointer reset operation based on the read reset signal, is specifically used to: control the read pointer to be at the initial value pointer position in response to the read reset signal being in an active state.
[0061] Specifically, in the above embodiments, the write pointer control unit 1044 and the read pointer control unit 1064 enable the write pointer and read pointer to be reset to the same position when the asynchronous reset signal is active. Resetting the read and write pointers to the same position simplifies the initial state management of the asynchronous FIFO circuit, ensuring that the asynchronous FIFO circuit is in a clear and consistent state after reset, facilitating subsequent data read and write operations. Resetting the read and write pointers to the same position also reduces logical complexity. If the read and write pointers are reset to different positions, additional logic may be needed to handle the inconsistency, increasing design complexity. Furthermore, resetting the read and write pointers to the same position during reset can avoid data conflicts or errors caused by pointer inconsistency, reduce the risk of metastability caused by pointer inconsistency, and help ensure the stable operation of the asynchronous FIFO circuit after reset.
[0062] Optionally, in some embodiments, the reset control module 102 may include: a clock state detection unit 1022 and a reset signal generation unit 1024;
[0063] The clock state detection unit 1022 is used to detect whether the write clock signal and the read clock signal are turned off, and when it detects that either the write clock signal or the read clock signal is turned off, it sends a turn-off reset signal to the reset signal generation unit 1024.
[0064] The reset signal generation unit 1024 is used to generate an asynchronous reset signal that is in an active state when a shutdown reset signal is received.
[0065] Specifically, see Figure 2 , Figure 2 This is a schematic diagram of the structural framework of a reset control module according to an embodiment of the present disclosure. The reset control module 102 of this embodiment includes a clock state detection unit 1022 and a reset signal generation unit 1024. By setting the clock state detection unit 1022 in the reset control module 102, it can promptly detect if either the write clock signal or the read clock signal is turned off. Upon detecting that either signal is turned off, the reset signal generation unit 1024 is triggered to generate a valid asynchronous reset signal, thereby causing the write pointer control unit 1044 and the read pointer control unit 1064 to reset the write pointer and read pointer to their initial positions, respectively.
[0066] As mentioned above, regarding Figure 1As indicated in the description, in the asynchronous FIFO circuit of this embodiment, after both the read and write pointers have been reset, during data read and write operations, the read pointer control module 106 and the write pointer control module 104 maintain the same frequency to continuously toggle the pointers, thereby maintaining a fixed phase difference between the read and write pointers through the fixed time difference between their reset and release. Therefore, maintaining a fixed phase difference between the read and write pointers requires that the read clock signal and the write clock signal be at the same frequency and neither is turned off. If either the read clock signal or the write clock signal is turned off, the aforementioned fixed phase difference cannot be maintained.
[0067] Based on the above analysis, in the embodiments of this disclosure, a clock state detection unit 1022 is provided in the reset control module 102 for detecting the shutdown of the read clock signal and the write clock signal. When either signal is shut down, an asynchronous reset signal in an active state is generated in a timely manner through the reset signal generation unit 1024, thereby causing the read / write pointer to re-enter the reset state, thus avoiding read / write errors and improving the stability and reliability of the asynchronous FIFO circuit's data read / write operations.
[0068] In addition, such as Figure 2 As shown, the reset signal generation unit 1024 can generate an asynchronous reset signal in an active state when it receives a shutdown reset signal, and it can also generate an asynchronous reset signal in an active state when it receives a regular reset signal issued by the outside world according to the actual situation.
[0069] In this embodiment of the disclosure, the specific implementation of the clock state detection unit 1022 is not limited. Existing detection units that can realize signal shutdown detection can be selected according to the actual situation, or hardware development can be carried out to design a new clock state detection unit 1022 that can realize signal shutdown detection.
[0070] Optionally, in some embodiments, a clock state detection unit 1022 with an innovative structure is provided. The clock state detection unit 1022 may include: an N-bit counter, a synchronizer, an M-bit register, and a sample detection unit; the N-bit counter is driven by the clock signal being detected, and the N-bit counter, synchronizer, and M-bit register are cascaded in sequence; the clock signal being detected is a write clock signal or a read clock signal; N and M are both integers greater than 1.
[0071] The sample detection unit is used to acquire the latest output signal of the synchronizer in the latest detected clock cycle, and to acquire the historical output signals of the synchronizer in the most recent M historical detected clock cycles from the M-bit register; to construct a detection sample signal based on the latest output signal and the historical output signal, and to detect whether the detected clock signal has been turned off according to the detection sample signal; when the detected clock signal is detected to be turned off, a turn-off reset signal is sent to the reset signal generation unit; when the detected clock signal is a write clock signal, the detected clock cycle is the write clock cycle; when the detected clock signal is a read clock signal, the detected clock cycle is the read clock cycle.
[0072] Specifically, the clock state detection unit 1022 provided in this embodiment is composed of four device units: an N-bit counter, a synchronizer, an M-bit register, and a sample detection unit. Therefore, compared with the signal shutdown detection unit in related technologies, it has the advantages of simple structure and easy implementation.
[0073] Furthermore, in some embodiments, M≥2 N-1 +2, Detect whether the clock signal being detected has been turned off based on the detected sample signal, including:
[0074] If the detected sample consists of M+1 consecutive 0s, or if the detected sample consists of M+1 consecutive 1s, then it is determined that the detected clock signal has been turned off.
[0075] Specifically, see Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the structural framework of a clock state detection unit according to an embodiment of the present disclosure. Figure 4 This is a timing diagram of a clock state detection unit according to an embodiment of the present disclosure. Figure 3 In this case, N is 3 and M is 2, that is... Figure 3 The clock state detection unit uses a two-bit counter and a three-bit shift register, as described below. Figure 3 and Figure 4 The specific implementation of the clock state detection unit 1022 provided in the embodiments of this disclosure will be explained and described below:
[0076] The two-digit counter operates under the detected clock signal (read clock signal or write clock signal). If the detected clock signal is not turned off, then refer to [the relevant documentation]. Figure 4The high-order bits of the two counters will generate a continuous sequence like 00110011......0011....... The synchronizer operates on a different clock signal that is asynchronous with the clock signal being detected. Due to the metastability within the synchronizer, the output sequence is 0x1x0x1x......0x1x......, where x is a random 0 or 1. The three-bit shift register stores the output results of the synchronizer for the most recent three detected clock cycles. Specifically, the output sequences of registers 0, 1, and 2 in the three-bit shift register can be found in [reference needed]. Figure 4 The outputs of the three registers in the three-bit shift register and the latest output of the synchronizer will constitute a four-bit sample. As long as the detected clock signal is not turned off, the above four-bit sample will not be four 0s or four 1s; conversely, if the detected clock signal is turned off, the high bit of the two-bit counter will remain unchanged, and thus the result of the synchronizer will also remain unchanged. After three detected clock cycles, the output of the shift register will also remain unchanged. At this time, the sample detection unit will detect a sample of four 0s or four 1s. At this time, the sample detection unit will output a status indication that the detected clock signal is turned off, thereby triggering the reset signal generation unit 1024 to generate an asynchronous reset signal.
[0077] Alternatively, in some embodiments, see Figure 2 The clock state detection unit 1022 may further include:
[0078] The write clock status detection unit 10222 is used to detect whether the write clock signal is turned off, and when the write clock signal is detected to be turned off, it sends a turn-off reset signal to the reset signal generation unit 1024.
[0079] The read clock status detection unit 10224 is used to detect whether the read clock signal is turned off, and when the read clock signal is detected to be turned off, it sends a turn-off reset signal to the reset signal generation unit 1024.
[0080] Specifically, separate detection units can be set up for the write clock signal and the read clock signal, that is, a separate detection unit is set up for each signal to detect whether the signal has been turned off. In this way, the turn-off detection operations for the two signals can be decoupled, thereby ensuring that the state of each signal is accurately monitored, and thus more accurately capturing changes in each signal. Furthermore, using a single detection unit for the turn-off detection of two different signals may lead to misjudgments due to signal mixing or interference, while setting up independent detection units can reduce the possibility of such misjudgments and improve the reliability of the detection.
[0081] Optionally, in some embodiments, the asynchronous FIFO circuit may further include: a write pointer synchronizer and a read pointer synchronizer;
[0082] The reset signal generation unit is also used to receive a mode control signal, which indicates whether the write clock frequency of the write clock signal is the same as or different from the read clock frequency of the read clock signal; when the mode control signal indicates that the write clock frequency is different from the read clock frequency, the received shutdown reset signal is shielded.
[0083] The write pointer control unit is also used to receive the above-mentioned mode control signal, and when the mode control signal indicates that the write clock frequency and the read clock frequency are different, in response to receiving a data write request, toggles the write pointer and performs a single data write operation; and sends the write pointer to the write pointer synchronizer so that the write pointer can be transmitted to the read pointer control unit through the write pointer synchronizer.
[0084] The read pointer control unit is also used to receive the above-mentioned mode control signal, and when the mode control signal indicates that the write clock frequency and the read clock frequency are different, in response to receiving a data read request, toggles the read pointer and performs a single data read operation; and sends the read pointer to the read pointer synchronizer so that the read pointer can be transmitted to the write pointer control unit through the read pointer synchronizer.
[0085] Specifically, the reset signal generation unit shields the received shutdown reset signal, that is, after receiving the shutdown reset signal, it ignores the signal and does not perform the subsequent operation of "generating an asynchronous reset signal in a valid state".
[0086] As mentioned above, regarding Figure 1 As indicated in the description, in the asynchronous FIFO circuit of this embodiment, after both the read and write pointers have been reset, during data read and write operations, the read pointer control module 106 and the write pointer control module 104 maintain the same frequency to continuously toggle the pointers, thereby maintaining a fixed phase difference between the read and write pointers through the fixed time difference between their reset and release. Therefore, maintaining a fixed phase difference between the read and write pointers also depends on the read clock signal and the write clock signal being at the same frequency. When the read clock signal and the write clock signal are not at the same frequency, the aforementioned fixed phase difference cannot be maintained.
[0087] For the reasons mentioned above, see Figure 5 , Figure 5 This is a schematic diagram of the structural framework of an asynchronous FIFO circuit according to another embodiment of this disclosure. In the above embodiments of this disclosure, by adding a write pointer synchronizer and a read pointer synchronizer, the read and write pointer synchronization mechanism is retained, so that even when the read clock signal and the write clock signal are not at the same frequency, i.e. Figure 2 Even when the mode control signal indicates that the read clock signal and the write clock signal are not at the same frequency, the read pointer control module can still know the position of the write pointer in the write pointer control module at any time, and thus successfully execute data read and write operations.
[0088] See Figure 6 , Figure 6 This is a schematic diagram of the structural framework of an asynchronous FIFO circuit according to another embodiment of this disclosure. Figure 6 A more detailed structural framework of the asynchronous FIFO circuit according to an embodiment of this disclosure is shown. The following is in conjunction with... Figure 6 The reset and data read / write processes of the asynchronous FIFO circuit according to embodiments of this disclosure will be described. The operation process of the asynchronous FIFO circuit according to embodiments of this disclosure under the condition that the write clock signal and the read clock signal are asynchronous and have the same frequency is as follows:
[0089] Reset Process: Unlike asynchronous FIFO circuits that employ a read / write pointer synchronization mechanism, the asynchronous FIFO circuit in this embodiment does not use a read / write pointer synchronization mechanism in the same-frequency asynchronous mode. Instead, it maintains a fixed difference between the read and write pointers through the reset release time difference of the read / write pointer control units. Specifically, when the asynchronous reset signal is valid, both the read and write pointer control units enter a reset state, and both pointers are set to the same initial value. When the asynchronous reset signal is released, it first undergoes cross-clock processing through the write reset signal synchronizer 1042. After synchronization, a write reset signal is generated and sent to the read reset synchronizer 1062 and the write pointer control unit 1044. After receiving the write reset release signal, the write pointer control unit 1044 begins to move the write pointer according to the write clock frequency. Meanwhile, another path, after processing by the read reset synchronizer 1062, generates a read reset signal. Similarly, after receiving the read reset release signal, the read pointer control unit 1064 begins to move the read pointer according to the read clock frequency. If the read and write clocks are asynchronous and both clocks are always present, the read and write pointers will maintain a fixed phase difference until they re-enter the reset state.
[0090] Write process: Under asynchronous conditions, the asynchronous FIFO circuit ignores the write request signal. After the write pointer control unit 1044 receives the write reset release signal, data is continuously written into the corresponding memory cell. When the write reset signal is valid, the write status indicates that writing is currently not allowed.
[0091] Reading process: Similarly, after receiving the read reset release signal, the read pointer control unit 1064 continuously reads data from the corresponding memory cell. When the read reset signal is valid, the read status indicates that the currently read data is invalid.
[0092] This disclosure also provides a processor, including: an asynchronous FIFO circuit as described in the above embodiments.
[0093] This disclosure also provides a chip, including the processor described in the above embodiments.
[0094] This disclosure also provides an electronic device, including: the processor in the above embodiments, or the chip in the above embodiments.
[0095] Figure 7 A flowchart of a data read / write method according to an embodiment of this disclosure is shown. This data read / write method can be executed by the asynchronous FIFO circuit in the above embodiments. It should be noted that the specific structure of the asynchronous FIFO circuit has been described in detail in conjunction with the structural diagram in the above asynchronous FIFO circuit embodiment section, and the specific content can be found in the description of the aforementioned asynchronous FIFO circuit embodiment, so it will not be repeated here. The following mainly explains the data read / write method applied to the asynchronous FIFO circuit.
[0096] like Figure 7 As shown, this data read / write method may include the following steps:
[0097] Step 702: Generate an asynchronous reset signal through the reset control module.
[0098] Step 704: The write pointer control module generates a write reset signal based on the asynchronous reset signal; the write reset signal is sent to the read pointer control module; and after the write pointer control module performs a write pointer reset operation based on the write reset signal, the write pointer is turned according to the write clock frequency to continuously perform data writing operations.
[0099] Step 706: The read pointer control module generates a read reset signal based on the write reset signal, and after performing a read pointer reset operation based on the read reset signal, it moves the read pointer according to the read clock frequency to continuously perform data reading operations; wherein, the write clock frequency is the same as the read clock frequency.
[0100] The data read / write method provided in this embodiment involves a write pointer control module that generates a write reset signal after the reset control module in the asynchronous FIFO circuit generates the write reset signal. Simultaneously, the read pointer control module generates a read reset signal and performs a read pointer reset operation based on the write reset signal. In other words, in this embodiment, the write pointer control module begins performing the data write operation while the read pointer control module is resetting the read pointer; that is, the data write operation begins before the read pointer reset is complete. After both the read and write pointers are reset, during the data read / write process, both the read pointer control module and the write pointer control module maintain the same frequency to continuously toggle their pointers for continuous data read / write operations. Therefore, a fixed phase difference between the read and write pointers can be maintained through a fixed time difference between their reset and release, eliminating the need for a synchronization mechanism between the read and write pointers. This ensures that the read pointer control module can always know the position of the write pointer in the write pointer control module and thus perform the data read operation.
[0101] Compared to data read / write methods implemented using asynchronous FIFO circuits with pointer synchronization mechanisms, the data read / write scheme in this disclosure maintains a fixed phase difference between the read and write pointers through a fixed time difference between their reset and release. Furthermore, the data write operation begins before the read pointer reset is complete. Therefore, the latency of the asynchronous FIFO circuit is determined solely by the fixed time difference between the read and write pointer resets, without needing to consider the additional time required for data to be written into the asynchronous FIFO circuit. Thus, the data read / write scheme provided in this disclosure effectively reduces the time interval between data writing and data being read, thereby reducing data read / write latency.
[0102] Optionally, in some embodiments, the write pointer control module includes: a write reset synchronizer and a write pointer control unit; the read pointer control module includes: a read reset synchronizer and a read pointer control unit;
[0103] The write reset synchronizer is used to receive the asynchronous reset signal generated by the reset control module, and to process the asynchronous reset signal across clock cycles to obtain the write reset signal; the write reset signal is then sent to the write pointer control unit and the read reset synchronizer respectively.
[0104] After the write pointer control unit performs a write pointer reset operation based on the write reset signal, it responds to the write reset signal being in the released state, and then moves the write pointer according to the write clock frequency to continuously perform data writing operations.
[0105] The write reset signal is processed across clock cycles by the read reset synchronizer to obtain the read reset signal. The read reset signal is then sent to the read pointer control unit so that after the read pointer control unit performs a read pointer reset operation based on the read reset signal, it responds to the read reset signal being in a released state, and moves the read pointer according to the read clock frequency to continuously perform data reading operations.
[0106] Optionally, in some embodiments, the step of performing a write pointer reset operation based on a write reset signal is executed by the write pointer control unit, including: controlling the write pointer to the initial value pointer position in response to the write reset signal being in an active state;
[0107] The steps of performing a read pointer reset operation based on a read reset signal are executed through the read pointer control unit, including: controlling the read pointer to the initial value pointer position in response to the read reset signal being in an active state.
[0108] Optionally, in some embodiments, the reset control module includes: a clock state detection unit and a reset signal generation unit;
[0109] The clock state detection unit detects whether the write clock signal and the read clock signal are turned off, and sends a turn-off reset signal to the reset signal generation unit when it detects that either the write clock signal or the read clock signal is turned off.
[0110] When a shutdown reset signal is received, the reset signal generation unit generates an asynchronous reset signal that is in an active state.
[0111] Optionally, in some embodiments, the clock state detection unit includes: an N-bit counter, a synchronizer, an M-bit register, and a sample detection unit; the N-bit counter is driven by the clock signal being detected, and the N-bit counter, synchronizer, and M-bit register are cascaded in sequence; the clock signal being detected is a write clock signal or a read clock signal; N and M are both integers greater than 1;
[0112] The sample detection unit acquires the latest output signal of the synchronizer in the latest detected clock cycle and obtains the historical output signals of the synchronizer in the most recent M historical detected clock cycles from the M-bit register. A detection sample signal is constructed based on the latest and historical output signals, and the detection sample signal is used to detect whether the detected clock signal has been turned off. When the detected clock signal is detected to be turned off, a turn-off reset signal is sent to the reset signal generation unit. Specifically, when the detected clock signal is a write clock signal, the detected clock cycle is the write clock cycle; when the detected clock signal is a read clock signal, the detected clock cycle is the read clock cycle.
[0113] Alternatively, in some embodiments, M≥2 N-1+2, Detect whether the clock signal being detected has been turned off based on the detected sample signal, including:
[0114] If the detected sample consists of M+1 consecutive 0s, or if the detected sample consists of M+1 consecutive 1s, then it is determined that the detected clock signal has been turned off.
[0115] Optionally, in some embodiments, the clock state detection unit includes: a write clock state detection unit and a read clock state detection unit;
[0116] The write clock status detection unit detects whether the write clock signal is turned off, and sends a turn-off reset signal to the reset signal generation unit when the write clock signal is detected to be turned off.
[0117] The read clock status detection unit detects whether the read clock signal has been turned off, and sends a shutdown reset signal to the reset signal generation unit when the read clock signal is detected to be turned off.
[0118] Optionally, in some embodiments, the asynchronous FIFO circuit further includes: a write pointer synchronizer and a read pointer synchronizer; the data read / write method further includes:
[0119] The reset signal generation unit receives a mode control signal, which indicates whether the write clock frequency of the write clock signal is the same as or different from the read clock frequency of the read clock signal. When the mode control signal indicates that the write clock frequency is different from the read clock frequency, the received shutdown reset signal is shielded.
[0120] The write pointer control unit receives the aforementioned mode control signal, and when the mode control signal indicates that the write clock frequency and the read clock frequency are different, it responds to the received data write request by toggling the write pointer and performing a single data write operation; it sends the write pointer to the write pointer synchronizer so that the write pointer can be transmitted to the read pointer control unit through the write pointer synchronizer.
[0121] The read pointer control unit receives the aforementioned mode control signal, and when the mode control signal indicates that the write clock frequency and the read clock frequency are different, it responds to the received data read request by moving the read pointer and performing a single data read operation; it sends the read pointer to the read pointer synchronizer so that the read pointer can be transmitted to the write pointer control unit through the read pointer synchronizer.
[0122] It should be noted that the details of the data read / write method have been explained in detail with reference to the structural diagram in the above asynchronous FIFO circuit embodiment section. The specific process can be found in the description of the above asynchronous FIFO circuit embodiment, and will not be repeated here.
[0123] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.
[0124] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0125] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.
[0126] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.
Claims
1. An asynchronous FIFO circuit, comprising: The reset control module is used to generate an asynchronous reset signal; A write pointer control module is used to generate a write reset signal based on the asynchronous reset signal; The write reset signal is sent to the read pointer control module, and after the write pointer control module performs a write pointer reset operation based on the write reset signal, the write pointer is turned according to the write clock frequency to continuously perform data writing operations. The read pointer control module is used to generate a read reset signal based on the write reset signal, and after performing a read pointer reset operation based on the read reset signal, toggles the read pointer according to the read clock frequency to continuously perform data reading operations; wherein, the write clock frequency is the same as the read clock frequency.
2. The asynchronous FIFO circuit according to claim 1, wherein, The write pointer control module includes a write reset synchronizer and a write pointer control unit; the read pointer control module includes a read reset synchronizer and a read pointer control unit. The write reset synchronizer is used to receive the asynchronous reset signal generated by the reset control module, and to process the asynchronous reset signal across clock cycles to obtain a write reset signal; the write reset signal is then sent to the write pointer control unit and the read reset synchronizer respectively. The write pointer control unit is used to, after performing a write pointer reset operation based on the write reset signal, respond to the write reset signal being in a released state, to toggle the write pointer according to the write clock frequency and continuously perform data write operations. The read reset synchronizer is used to process the write reset signal across clock cycles to obtain a read reset signal; and to send the read reset signal to the read pointer control unit, so that after the read pointer control unit performs a read pointer reset operation based on the read reset signal, in response to the read reset signal being in a released state, the read pointer is turned according to the read clock frequency and data reading operations are continuously performed.
3. The asynchronous FIFO circuit according to claim 2, wherein, When performing the step of performing the write pointer reset operation based on the write reset signal, the write pointer control unit is specifically used to: control the write pointer to be at the initial value pointer position in response to the write reset signal being in an active state; When performing the step of resetting the read pointer based on the read reset signal, the read pointer control unit is specifically configured to: control the read pointer to be at the initial value pointer position in response to the read reset signal being in an active state.
4. The asynchronous FIFO circuit according to claim 3, wherein, The reset control module includes: a clock state detection unit and a reset signal generation unit; The clock state detection unit is used to detect whether the write clock signal and the read clock signal are turned off, and when it detects that either the write clock signal or the read clock signal is turned off, it sends a turn-off reset signal to the reset signal generation unit. The reset signal generation unit is used to generate an asynchronous reset signal that is in an active state when the shutdown reset signal is received.
5. The asynchronous FIFO circuit according to claim 4, wherein, The clock state detection unit includes: an N-bit counter, a synchronizer, an M-bit register, and a sample detection unit; the N-bit counter is driven by the clock signal being detected, and the N-bit counter, the synchronizer, and the M-bit register are cascaded in sequence; the clock signal being detected is a write clock signal or a read clock signal; N and M are both integers greater than 1; The sample detection unit is configured to acquire the latest output signal of the synchronizer in the latest detected clock cycle, and acquire the historical output signals of the synchronizer in the most recent M historical detected clock cycles from the M-bit register; construct a detection sample signal based on the latest output signal and the historical output signals, and detect whether the detected clock signal is turned off according to the detection sample signal; when the detected clock signal is detected to be turned off, send a turn-off reset signal to the reset signal generation unit; wherein, when the detected clock signal is a write clock signal, the detected clock cycle is a write clock cycle; when the detected clock signal is a read clock signal, the detected clock cycle is a read clock cycle.
6. The asynchronous FIFO circuit according to claim 5, wherein, M≥2 N-1 +2, the step of detecting whether the detected clock signal is turned off based on the detected sample signal includes: If the detection sample consists of M+1 consecutive 0s, or if the detection sample consists of M+1 consecutive 1s, then it is determined that the detected clock signal has been turned off.
7. The asynchronous FIFO circuit according to any one of claims 4-6, wherein, The clock state detection unit includes: The write clock status detection unit is used to detect whether the write clock signal is turned off, and when the write clock signal is detected to be turned off, it sends a turn-off reset signal to the reset signal generation unit. The read clock status detection unit is used to detect whether the read clock signal is turned off, and when the read clock signal is detected to be turned off, it sends a turn-off reset signal to the reset signal generation unit.
8. The asynchronous FIFO circuit according to any one of claims 4-6, wherein, The asynchronous FIFO circuit also includes: a write pointer synchronizer and a read pointer synchronizer; The reset signal generation unit is also used to receive a mode control signal, wherein the mode control signal indicates that the write clock frequency of the write clock signal is the same as or different from the read clock frequency of the read clock signal; when the mode control signal indicates that the write clock frequency is different from the read clock frequency, the received shutdown reset signal is shielded. The write pointer control unit is further configured to receive the mode control signal, and when the mode control signal indicates that the write clock frequency is different from the read clock frequency, respond to receiving a data write request, move the write pointer and perform a single data write operation; and send the write pointer to the write pointer synchronizer so that the write pointer can be transmitted to the read pointer control unit through the write pointer synchronizer. The read pointer control unit is further configured to receive the mode control signal, and when the mode control signal indicates that the write clock frequency is different from the read clock frequency, respond to receiving a data read request, move the read pointer and perform a single data read operation; and send the read pointer to the read pointer synchronizer so that the read pointer can be transmitted to the write pointer control unit through the read pointer synchronizer.
9. A processor, comprising: The asynchronous FIFO circuit as described in any one of claims 1-8.
10. A chip, comprising: The processor as described in claim 9.
11. An electronic device, comprising: The processor as described in claim 9, or the chip as described in claim 10.
12. A data read / write method applied to an asynchronous FIFO circuit, the asynchronous FIFO circuit comprising: The method includes a reset control module, a write pointer control module, and a read pointer control module, and includes: The reset control module generates an asynchronous reset signal. The write pointer control module generates a write reset signal based on the asynchronous reset signal; the write reset signal is sent to the read pointer control module, and after the write pointer control module performs a write pointer reset operation based on the write reset signal, the write pointer is toggled according to the write clock frequency to continuously perform data write operations. The read pointer control module generates a read reset signal based on the write reset signal, and after performing a read pointer reset operation based on the read reset signal, it moves the read pointer according to the read clock frequency to continuously perform data reading operations; wherein, the write clock frequency is the same as the read clock frequency.