A parallel phase accumulation and complex sum hardware circuit
Patent Information
- Application Number
- CN202611319053.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-28
- Publication Date
- 2026-10-23
AI Technical Summary
[0014]本发明旨在解决现有多路径相位累加与求和计算中存在的多重技术瓶颈，具体技术问题如下：
[0039]（一）本发明以K条并行相位累加链实现路径级全并行，单周期完成K条路径的相位累积，流水线满载时吞吐率为每周期一条路径，多路径采样在微秒级完成，相比软件方案提升约三个数量级。
Smart Images
Figure CN122963498A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital integrated circuit technology, specifically relating to a hardware circuit that performs parallel accumulation, complex summation and normalization of the phases of multiple candidate paths, which can be integrated into various digital chips as a standardized IP core. Background Technology
[0002] In multi-path phase accumulation and summation calculations, each path requires point-by-point phase accumulation along the path. After accumulation, the complex contributions of all paths are summed and normalized. Phase accumulation and complex summation are the two most computationally intensive steps, with completely different data dependencies—phase accumulation is a time-series accumulation along a single path, while complex summation is a parallel aggregation across multiple paths. These two steps are currently handled by different methods in existing chips, lacking a unified hardware acceleration solution.
[0003] There are currently three main ways for chips to implement multi-path phase accumulation and summation calculations:
[0004] (a) General-purpose processor / GPU software solution. Phase accumulation for each path is executed sequentially on a general-purpose ALU, with paths running in parallel via threads. The problems with this solution are: each step of phase accumulation requires repeated reading and writing of register files and shared memory, resulting in a throughput of only a few thousand to tens of thousands of paths per second for millions of paths; phase accumulation uses floating-point operations, and floating-point rounding errors accumulate with the path length when accumulating long paths; path generation and phase accumulation are executed separately, resulting in a large amount of intermediate data movement and an overall latency of milliseconds, which cannot meet real-time requirements.
[0005] (II) Scheme for Separating Path Generation and Phase Accumulation. The existing scheme separates path generation and phase accumulation. After path generation, the data is temporarily stored in memory, and then the processor reads it and accumulates the phase point by point. The problem with this scheme is that the data transfer between path generation and phase accumulation is large, intermediate results need to be repeatedly read and written to external storage, and the overall latency is limited by storage bandwidth rather than computing power.
[0006] (III) Single-path phase measurement scheme. Existing phase measurement circuits calculate the cumulative phase value of a single path and output the phase scalar of that single path. The problem with this scheme is that it only supports processing one path at a time and cannot utilize the parallelism between paths; it does not have the ability to perform complex summation across paths and cannot output the global response.
[0007] The above three solutions have the following drawbacks:
[0008] Defect 1: The phase accumulation step relies on software to execute point by point, and the multi-path sampling delay reaches the millisecond level, which does not match the real-time requirements.
[0009] Defect 2: Phase accumulation uses floating-point operations. During long-path accumulation, floating-point rounding errors accumulate point by point, causing the final phase to deviate from the true value.
[0010] Defect 3: Complex summation and normalization for multiple paths require additional loops in the software, further increasing latency.
[0011] Defect 4: Existing dedicated circuits (scalar weighted summation circuit and single-path phase measurement circuit) are designed for "scalar synthesis" and "single-path measurement" respectively, and do not have the complete capabilities of multi-path parallel accumulation, cross-path complex summation and normalization.
[0012] In summary, there is currently no dedicated circuit in the chips that integrates path generation, point-by-point phase accumulation, cross-path complex summation, and normalization into the same hard-wired pipeline. Summary of the Invention
[0013] The technical problem to be solved by the present invention
[0014] This invention aims to solve multiple technical bottlenecks in existing multipath phase accumulation and summation calculations. The specific technical problems are as follows:
[0015] (i) The phase accumulation step relies on software to execute point by point, and the multi-path sampling delay reaches the millisecond level, which cannot meet the requirements of real-time systems;
[0016] (ii) Floating-point phase accumulation generates cumulative rounding errors in long paths, causing the final phase to deviate from the true value;
[0017] (iii) Complex summation and normalization in multi-path operations require additional software to be executed in a loop, which increases latency;
[0018] (iv) Existing dedicated circuits do not have the ability to perform multi-path parallel accumulation and complex summation.
[0019] Inventive concept
[0020] This invention includes the following technical solution: K parallel phase accumulation chains are used to simultaneously perform point-by-point phase accumulation on K candidate paths (K equals the hardware parallelism). Each accumulation chain models a 2π winding process to prevent long-path accumulation overflow. The complex contributions of the order complex number and the addition tree to the K paths are summed, and the global response is output as a normalized unit.
[0021] This includes the following three aspects:
[0022] (i) Path-level parallel accumulation. K phase accumulation chains work simultaneously, each chain corresponding to a candidate path, accumulating the phase increment of the path point by point. When the pipeline is fully loaded, the phase accumulation of one path is completed per cycle, and multi-path sampling is completed in microseconds.
[0023] (ii) Fixed-point modulo 2π winding. Each accumulation chain accumulates the phase using a fixed-point adder. When the accumulation result exceeds 2π, it automatically winds up to modulo 2π (the high-order carry is discarded when the adder overflows), eliminating floating-point rounding errors in long-path accumulation.
[0024] (III) Complex Summation and Normalization. The complex contributions of K paths are calculated using... The multi-stage additive tree performs pipelined summation, outputting the global response after normalization. The weight type register supports switching between uniform weight and Boltzmann weight modes.
[0025] Overall technical solution
[0026] This invention implements the entire multi-path phase accumulation, complex summation, and normalization process in hardware, achieving real-time throughput for multi-path sampling with a fixed pipeline delay. Using a path generator, K parallel phase accumulation chains, a complex summation tree, and a normalization unit as core components, the following computational chains are solved in hardware parallelism:
[0027] ① Path generation: Generate phase increment sequences and weights for K candidate paths based on the number of configurable paths K;
[0028] ② Parallel accumulation: K phase accumulation chains simultaneously accumulate the phase increments of each path;
[0029] ③ Summation of complex numbers: Sum of the complex contributions of an additive tree to K paths;
[0030] ④ Normalized output: The normalized unit outputs the global response.
[0031] Specific technical solutions
[0032] (i) Path Generator. This is used to generate path description data for K candidate paths based on a configurable number of paths K. The path description data includes phase increments and path weights point-by-point along the path. The number of paths K is a configurable register value, equal to the hardware parallelism, typically 64 or 256. In one embodiment, the path generator is an LFSR pseudo-random sequence generator (typically 32 stages), which generates candidate paths according to the configured number of paths and pipelines the path description data to the corresponding phase accumulation chain cycle by cycle.
[0033] (ii) K parallel phase accumulation chains. Connected to the path generator, each phase accumulation chain corresponds to a candidate path. The phase increment of the path is accumulated point by point, and the cumulative phase of the path is output. The K phase accumulation chains work in parallel, and each outputs the cumulative phase of one path in a single cycle.
[0034] Each phase accumulation chain includes: a phase accumulator (fixed-point adder) that accumulates the phase increment point by point along the path, with the accumulated result wrapped modulo 2π (discarding high-order carry bits when the adder overflows, equivalent to angle modulo arithmetic) to prevent phase accumulation overflow along long paths and eliminate floating-point rounding errors; an accumulation length counter that records the number of steps accumulated along the path and outputs the accumulated phase when the configured length is reached; and a weighting unit that processes the path weights and combines them with the accumulated phase to output a weighted complex phase (real part). imaginary part ).
[0035] (III) Complex Sum Addition Tree. Connect the K parallel phase accumulation chains, perform a complex summation on the accumulated phases of the K paths, and output the path sum. The complex sum addition tree is... The pipeline structure consists of K / 2 complex units in the first stage, K / 4 units in the second stage, and so on, with each stage delayed by one clock cycle, operating in a fully pipelined manner.
[0036] (iv) Normalization Unit. Connect the complex number and the addition tree, normalize the path sum, and output the global response. The normalization factor Z is determined by the path weights (Z=K for uniform weights, Z=K for Boltzmann weights). (), calculated by the adder tree bypass or provided by the configuration register.
[0037] Basic pipeline timing rules: Path generation and phase accumulation are executed pipelined from cycle 1 (K chains in parallel), and complex summation is performed over the cycle. The result is then output by the addition tree and normalized in subsequent cycles. Once the pipeline is full, a global response is output each cycle, with no branches and no software intervention throughout the process.
[0038] Beneficial effects
[0039] (i) This invention achieves full parallelism at the path level with K parallel phase accumulation chains, completes phase accumulation of K paths in a single cycle, and achieves a throughput of one path per cycle when the pipeline is fully loaded. Multi-path sampling is completed in microseconds, which is about three orders of magnitude higher than the software solution.
[0040] (ii) Each accumulation chain uses fixed-point modulus 2π winding accumulation. When the adder overflows, the high-order carry is automatically discarded, which is equivalent to angle modulus operation, eliminating floating-point rounding errors in long-path accumulation. The phase accuracy is uniquely determined by the fixed-point bit width.
[0041] (III) Complex numbers and addition trees are The system features a fully pipelined architecture, allowing complex summation and phase accumulation to be performed in parallel without adding extra latency. The weight type register supports switching between uniform weight and Boltzmann weight modes.
[0042] (iv) The number of paths K is a configurable parameter and equal to the hardware parallelism. The area and accuracy can be balanced according to the scenario. The same circuit can adapt to both low-precision high-speed and high-precision high-fidelity requirements.
[0043] (v) This circuit can be integrated into various digital chips as a standardized IP core.
[0044] Terminology Definition
[0045] Phase accumulation: This refers to the operation of accumulating phase increments point by point along the path. It is the most frequently executed calculation step in multi-path phase accumulation.
[0046] Modulo 2π winding: This refers to the operation of automatically subtracting 2π (or a multiple thereof) when the phase accumulation result exceeds 2π. It is equivalent to angle modulo operation and prevents long-path accumulation overflow.
[0047] Complex summation: refers to the operation of summing the complex contributions (real part + imaginary part) of multiple paths, where the contribution of each path is a weighted complex phase.
[0048] Boltzmann weights: refer to weighting based on energy exponents. kT is a configurable temperature parameter used for weight calculation.
[0049] Global response: refers to the result of weighted summation and normalization of all paths. Attached Figure Description
[0050] Figure 1 This is a schematic diagram of the overall architecture of the parallel phase accumulation and summation hardware circuit of this invention. The left side of the diagram shows the phase increment input and configuration parameter input; the solid arrow indicates the positive data flow direction; the dotted-dash arrow indicates the configuration control signal; the circled labels ① to ④ sequentially indicate four modules (① path generator, ② K parallel phase accumulation chains, ③ complex number addition tree, ④ normalization unit); the data flow direction is fixed, and the hardwired connections between each stage are direct. Detailed Implementation
[0051] Example 1: Complete Implementation (K=64, 16-bit fixed-point)
[0052] like Figure 1 The overall architecture shown in this embodiment uses the phase accumulation and summation of K=64 candidate paths as an example to verify the functional correctness and timing performance of the parallel phase accumulation and summation hardware circuit.
[0053] Configuration parameters: number of paths K=64, phase and weight data paths adopt 16-bit fixed-point Q4.12 format, and weight type is uniform weight.
[0054] Starting from cycle T1: The path generator (LFSR pseudo-random sequence generator, 32 stages) generates path description data (including point-by-point phase increments and path weights) for 64 candidate paths according to K=64, and outputs it to the corresponding phase accumulation chain cycle by cycle. The 64 phase accumulation chains start working simultaneously, and each chain accumulates the phase increment of the corresponding path point by point (fixed-point adder, modulo 2π winding). The accumulation length counter records the number of accumulated steps, and outputs the accumulated phase when the configured length is reached.
[0055] Period T ( Then: The complex sum addition tree (6-stage pipeline structure) sums the complex contributions of the 64 paths. The first stage has 32 complex sum units, the second stage has 16, and so on, merging level by level. Each stage is delayed by one clock cycle, and the output path sum is given.
[0056] Normalization unit: In uniform weight mode, the normalization factor Z=64. The path sum is divided by 64 to output the global response.
[0057] Real-world results: With 64 paths accumulating in parallel, the pipeline outputs a global response result per cycle when fully loaded. In multi-path sampling, the software solution takes approximately 1-10 milliseconds, while this circuit takes approximately 1-10 microseconds (depending on the path length), representing an improvement of about three orders of magnitude.
[0058] Hardware resource and timing verification: Based on a 28nm standard process and a 1GHz clock frequency, the estimated total number of gates is approximately 0.5k for the path generator, approximately 6k for K parallel phase accumulation chains (K=64, including winding and weighting units), approximately 2k for the complex summation and addition tree (6-stage pipeline), and approximately 0.5k for the normalization unit, totaling approximately 9k gates. The critical path of the pipeline consists of three stages of combinational logic: phase accumulation, complex summation, and normalization. Static timing analysis shows sufficient establishment and hold margins, with no timing violations. This circuit, with approximately 9k gates, can be integrated as a standardized IP core into various digital chips.
[0059] Example 2: Boltzmann Weighted and Global Response Calculation
[0060] This embodiment verifies the functionality of the weight type register when configured in Boltzmann mode.
[0061] Configuration parameters: The weight type register is configured to Boltzmann mode, and kT is configured to a value corresponding to the system temperature (typical value 1.0, fixed-point representation).
[0062] Working principle: The path description data output by the path generator includes the path energy E_k. The weight unit of each phase accumulation chain calculates the path energy E_k using an exponential lookup table. The weighted complex phase is output by combining the accumulated phase. The adder tree sums the K-strip weighted complex phases. The normalization unit calculates the normalization factor. Output global response The weight type is switched between uniform mode and Boltzmann mode by the configuration register.
[0063] Example 3: Variance Adaptive Termination
[0064] This embodiment verifies the adaptive termination function of the variance determination unit in multipath sampling.
[0065] The circuit includes a variance determination unit, which consists of a window register (W=16), a variance calculator, and a comparator. The variance determination unit calculates the relative fluctuation of the path sum (the ratio of the variance to the mean of the path sum magnitude within the sliding window) for every W sampled paths. When the fluctuation is below a preset threshold... When the typical value is 1e-3, a sampling termination signal is output to stop path generation and accumulation in advance, reducing dynamic power consumption; sampling continues if the threshold is not reached and the number of paths is less than K. The output of the variance determination unit is connected to the enable terminal of the path generator, and the path generator stops generating new paths when the sampling termination signal is valid.
Claims
1. A hardware circuit for path integral phase accumulation and summation, characterized in that, include: A path generator is used to generate path description data for K candidate paths according to a configurable number of paths K. The path description data includes phase increments and path weights at each point along the path. The number of paths K is a configurable register value and is equal to the hardware parallelism. K parallel phase accumulation chains are connected to the path generator. Each phase accumulation chain corresponds to a candidate path. The phase increment of the path is accumulated point by point, and the cumulative phase of the path is output. The K phase accumulation chains work in parallel, and each outputs the cumulative phase of one path in a single cycle. A complex sum addition tree connects the K parallel phase accumulation chains, performs a complex summation on the accumulated phases of the K paths, and outputs the path sum. The complex sum addition tree is... A multi-stage flow structure; A normalization unit connects the complex number and the addition tree, normalizes the path sum, and outputs the global response. The entire circuit has a fixed pipeline delay from phase increment input to global response output. All operational paths are pure combinational logic plus pipelined register architecture, with no software scheduling and no microcode operation.
2. The path integral phase accumulation and summation hardware circuit according to claim 1, characterized in that, The path generator is an LFSR pseudo-random sequence generator, and the typical value of the number of paths K is 64 or 256; the phase and weight data paths adopt a 16-bit fixed-point format.
3. The path integral phase accumulation and summation hardware circuit according to claim 1, characterized in that, Each phase accumulation chain includes a phase accumulator and an accumulation length counter. The phase accumulator accumulates in a modulo 2π winding manner (discarding high-order carry when the adder overflows). The accumulation length counter records the cumulative number of steps in the path and outputs the accumulated phase when the configured length is reached.
4. The path integral phase accumulation and summation hardware circuit according to claim 1, characterized in that, Each phase accumulation chain also includes a weighting unit, which outputs a constant weight in uniform weighting mode and calculates the path energy exponentially using a lookup table in Boltzmann weighting mode. kT is a configurable register value that, when combined with the accumulated phase, outputs a weighted complex phase; the weight type is selected by the configuration register.
5. The path integral phase accumulation and summation hardware circuit according to claim 1, characterized in that, The complex sum addition tree is a fully pipelined structure, with K / 2 complex sum units in the first level, and the number of units halved at each level. Each stage has a delay of one clock cycle, and the full-load throughput is one path sum output per clock cycle.
6. The path integral phase accumulation and summation hardware circuit according to claim 1, characterized in that, It also includes a variance determination unit, which calculates the relative fluctuation of the path sum once for each W sampled path. When the fluctuation is lower than a preset threshold, it outputs a sampling termination signal to stop path generation and accumulation in advance.
7. The path integral phase accumulation and summation hardware circuit according to claim 1, characterized in that, The number of paths K, weight type, and kT parameter are written by the host via the configuration bus.
8. The path integral phase accumulation and summation hardware circuit according to claim 1, characterized in that, The path sum output by the complex number and the addition tree is in complex form, and the global response output by the normalization unit is a normalized complex cross section.