Ultra-high-speed true random number generator and cryptographic chip
Patent Information
- Application Number
- CN202510474597.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2026-10-23
AI Technical Summary
[0005]鉴于上述的分析，本发明实施例旨在提供一种超高速真随机数发生器及密码芯片，用以解决现有超高速真随机数发生器的超高频信号的生成受工艺尺寸和环振级数的限制并且被采样时存在亚稳态的问题
[0035]与现有技术相比，本发明至少可实现如下有益效果之一：
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Figure CN122963503A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an ultra-high-speed true random number generator and a cryptographic chip. Background Technology
[0002] With the rapid development of information technology, people's lives have become much more convenient, but the security of information systems has also become increasingly prominent. As a result, cryptographic technology has been widely used, and random numbers play a very important role in the encryption and decryption process of information systems.
[0003] Currently, in ultra-high-speed true random number generators using oscillator sampling, the higher the sampling high-frequency clock frequency, the higher the quality of the random numbers. However, directly outputting the clock signal generated by a traditional ring oscillator to a D flip-flop for sampling has two limitations. First, the highest frequency achievable by a ring oscillator composed of three stages of inverters can only increase with the reduction of process dimensions, and it cannot generate ultra-high frequency signals at any stage and under any process. Second, if the sampling high-frequency clock frequency is too high, it is difficult to meet the setup and hold times of a typical D flip-flop, resulting in metastability issues.
[0004] Therefore, the generation of ultra-high frequency signals in traditional ultra-high speed true random number generators is limited by process size and ring oscillation level, and metastability exists when the signals are sampled. Summary of the Invention
[0005] Based on the above analysis, the present invention aims to provide an ultra-high-speed true random number generator and a cryptographic chip to solve the problems of existing ultra-high-speed true random number generators having limitations in the generation of ultra-high frequency signals due to process size and ring oscillation levels, and the existence of metastability during sampling.
[0006] On one hand, embodiments of the present invention provide an ultra-high-speed true random number generator, including a high-frequency ring oscillation module, an entropy source acquisition module, a clock status register module, and an entropy source selection module;
[0007] The high-frequency ring resonator module is used to output N high-frequency clock signals based on the received enable signal.
[0008] The entropy source acquisition module is used to sample the received N high-frequency clock signals and generate N random number sequences.
[0009] The clock status register module is used to record the waveform flipping state of the received N high-frequency clock signals and generate 2N clock status indication signals at each division time of each clock cycle.
[0010] The entropy source selection module is used to select from the received N random number sequences based on the 2N clock status indication signals at each division time of each clock cycle, and generate one random number sequence.
[0011] Furthermore, the entropy source acquisition module includes a low-frequency ring vibration module and an N-channel acquisition module;
[0012] The low-frequency ring resonator module is used to output low-frequency signals;
[0013] The i-th acquisition module is used to sample the received i-th high-frequency clock signal based on the received low-frequency signal to obtain the i-th random number sequence; where i = 1, 2, ..., N.
[0014] Furthermore, the i-th acquisition module includes an i-th first-level D flip-flop and an i-th second-level D flip-flop;
[0015] The data input terminal of the i-th first-level D flip-flop serves as the data input terminal of the i-th acquisition module, receiving the i-th high-frequency clock signal; the output terminal of the i-th first-level D flip-flop is connected to the data input terminal of the i-th second-level D flip-flop; the output terminal of the i-th second-level D flip-flop serves as the output terminal of the i-th acquisition module, outputting the i-th random number sequence.
[0016] The clock input terminals of the i-th primary D flip-flop and the i-th secondary D flip-flop serve as the clock input terminals of the i-th acquisition module, receiving low-frequency signals.
[0017] Furthermore, the clock status register module includes N rising edge recording modules and N falling edge recording modules;
[0018] The i-th rising edge recording module is used to count the rising edges of the i-th high-frequency clock signal at each division time of each clock cycle and output the i-th clock status indication signal at each division time of each clock cycle; it is also used to receive a reset signal for resetting.
[0019] The i+Nth falling edge recording module is used to count the falling edges of the i-th high-frequency clock signal at each division time of each clock cycle and output the i+Nth clock status indication signal at each division time of each clock cycle; it is also used to receive a reset signal for reset.
[0020] Where i = 1, 2, ..., N.
[0021] Furthermore, the i-th rising edge recording module includes an i-th asynchronous reset D flip-flop;
[0022] The data input terminal of the i-th asynchronous reset D flip-flop is connected to the inverting output terminal. The clock input terminal of the i-th asynchronous reset D flip-flop serves as the input terminal of the i-th rising edge recording module, receiving the i-th high-frequency clock signal. The asynchronous set terminal of the i-th asynchronous reset D flip-flop serves as the reset terminal of the i-th rising edge recording module, receiving a reset signal. The data output terminal of the i-th asynchronous reset D flip-flop serves as the output terminal of the i-th rising edge recording module, outputting the i-th clock status indication signal.
[0023] Furthermore, the (i+N)th falling edge recording module includes an (i+N)th asynchronous reset D flip-flop and an (i+N)th inverter;
[0024] The input terminal of the (i+N)th inverter serves as the input terminal of the (i+N)th falling edge recording module, receiving the i-th high-frequency clock signal; the output terminal of the (i+N)th inverter is connected to the clock input terminal of the (i+N)th asynchronous reset D flip-flop; the data input terminal of the (i+N)th asynchronous reset D flip-flop is connected to the inverted output terminal; the asynchronous set terminal of the (i+N)th asynchronous reset D flip-flop serves as the reset terminal of the (i+N)th falling edge recording module, receiving a reset signal; the data output terminal of the (i+N)th asynchronous reset D flip-flop serves as the output terminal of the (i+N)th falling edge recording module, outputting the i+Nth clock status indication signal.
[0025] Furthermore, the entropy source selection module includes an encoding circuit and a selection module;
[0026] The encoding circuit is used to determine the number of random number sequences to be output at each time division of each clock cycle based on the 2N clock status indication signals received at each time division of each clock cycle.
[0027] The selection module is used to generate one random number sequence by outputting random numbers at each division time of each clock cycle, based on the number of random number sequences to be output at each division time of each clock cycle.
[0028] Furthermore, the encoding circuit determines the number of paths for the expected output random number sequence in each clock cycle in the following manner:
[0029] Based on the 2N clock status indication signals of the current division time and the previous division time, determine the number of high-frequency clock signals that have undergone waveform reversal.
[0030] Based on the number of high-frequency clock signals that undergo waveform reversal and the total number of high-frequency clock signals, determine the number of random number sequences to be output at the current time of division.
[0031] Furthermore, the number of paths n of the random number sequence to be output at the current partitioning time is expressed as:
[0032]
[0033] In the formula, m represents the number of high-frequency clock signals whose waveforms reverse at the current division time, N represents the total number of high-frequency clock signals, and mod represents modulo operation.
[0034] On the other hand, embodiments of the present invention provide a cryptographic chip, which includes the ultra-high-speed true random number generator described above.
[0035] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0036] This invention provides an ultra-high-speed true random number generator and a cryptographic chip. The ultra-high-speed true random number generator includes a high-frequency ring oscillation module, an entropy source acquisition module, a clock status register module, and an entropy source selection module. The clock status register module records the rising and falling edges of each high-frequency signal. Based on this, rules are set, and the entropy source selection module selects the random numbers output by the entropy source acquisition module to generate a random number sequence. It is not limited by the number of stages and process dimensions in the ring oscillation, and its clock frequency can be higher. The ultra-high-speed clock sampling architecture can also avoid the metastability problem of sampling by general D flip-flops, and better meets the key design indicator of "strong randomness" of true random number generators. It meets the needs of practical information security applications and can be applied to key generation and device / chip authentication in cryptographic chips.
[0037] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0038] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0039] Figure 1 This is a schematic diagram of the structure of the ultra-high-speed true random number generator provided in Embodiment 1 of the present invention;
[0040] Figure 2 This is a schematic diagram of the high-frequency ring vibration module provided in Embodiment 1 of the present invention;
[0041] Figure 3 This is a schematic diagram showing the specific connection of the entropy source acquisition module provided in Embodiment 1 of the present invention;
[0042] Figure 4This is a schematic diagram showing the specific connection of the clock status register module provided in Embodiment 1 of the present invention;
[0043] Figure 5 This is a schematic diagram of the entropy source selection module provided in Embodiment 1 of the present invention;
[0044] Figure 6 This is a schematic diagram showing the timing relationship between the reset signal, enable signal, and various high-frequency clock signals provided in Embodiment 1 of the present invention. Detailed Implementation
[0045] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0046] Example 1
[0047] A specific embodiment of the present invention discloses an ultra-high-speed true random number generator, such as... Figure 1 As shown, it includes a high-frequency ring oscillation module, an entropy source acquisition module, a clock status register module, and an entropy source selection module;
[0048] The high-frequency ring resonator module is used to output N high-frequency clock signals based on the received enable signal.
[0049] The entropy source acquisition module is used to sample the received N high-frequency clock signals and generate N random number sequences.
[0050] The clock status register module is used to record the waveform flipping state of the received N high-frequency clock signals and generate 2N clock status indication signals at each division time of each clock cycle.
[0051] The entropy source selection module is used to select from the received N random number sequences based on the 2N clock status indication signals at each division time of each clock cycle, and generate one random number sequence.
[0052] In implementation, the high-frequency ring oscillator module is an N-stage ring oscillator composed of NAND gates, consisting of N-stage NAND gates and N-1 inverters connected end-to-end. The first input terminal of the NAND gate is connected to the output terminal of the (N-1)th inverter, and the second input terminal is used to receive the enable signal. The output terminals of the NAND gate and the N-1 inverters connected end-to-end serve as the first to Nth output terminals of the high-frequency ring oscillator module, outputting the first to Nth high-frequency clock signals respectively. The truth table of the NAND gate is shown in Table 1, where EN represents the enable signal, A represents the input signal at the first input terminal of the NAND gate, B represents the output signal of the NAND gate, "1" represents a high level, and "0" represents a low level.
[0053] Table 1 Truth Table of NAND Gates
[0054] EN A B 0 0 1 0 1 1 1 0 1 1 1 0
[0055] Specifically, the enable signal is provided by the main controller. The high-frequency ring oscillation module is initialized through the enable signal to ensure the initial waveform state of the first to Nth high-frequency clock signals output by the high-frequency ring oscillation module.
[0056] It should be noted that N must be an odd number to construct a ring oscillator.
[0057] For example, in this embodiment, N is 5. Figure 2 As shown, the high-frequency ring oscillator module includes NAND gates and four inverters, outputting the first to fifth high-frequency clock signals CLK1 to CLK5.
[0058] In practice, the entropy source acquisition module includes a low-frequency ring vibration module and an N-channel acquisition module;
[0059] The low-frequency ring resonator module is used to output low-frequency signals;
[0060] The i-th acquisition module is used to sample the received i-th high-frequency clock signal based on the received low-frequency signal to obtain the i-th random number sequence; where i = 1, 2, ..., N.
[0061] In specific implementation, the i-th acquisition module includes an i-th first-level D flip-flop and an i-th second-level D flip-flop;
[0062] The data input terminal D of the i-th first-level D flip-flop serves as the data input terminal of the i-th acquisition module, receiving the i-th high-frequency clock signal; the output terminal Q of the i-th first-level D flip-flop is connected to the data input terminal D of the i-th second-level D flip-flop; the output terminal Q of the i-th second-level D flip-flop serves as the output terminal of the i-th acquisition module, outputting the i-th random number sequence.
[0063] The clock input terminal CK of the i-th primary D flip-flop and the i-th secondary D flip-flop serves as the clock input terminal of the i-th acquisition module, receiving low-frequency signals.
[0064] For example, in this embodiment, N is 5. Figure 3 As shown, the entropy source acquisition module consists of a low-frequency ring oscillation module and two-stage D flip-flops. The low-frequency ring oscillation output signal serves as a slow clock, and the output signals CLK1-CLK5 of the high-frequency ring oscillation module are sampled to output five random number sequences Q1 to Q5 respectively.
[0065] In implementation, the clock status register module includes N rising edge recording modules and N falling edge recording modules;
[0066] The i-th rising edge recording module is used to count the rising edges of the i-th high-frequency clock signal at each division time of each clock cycle and output the i-th clock status indication signal at each division time of each clock cycle; it is also used to receive a reset signal for resetting.
[0067] The i+Nth falling edge recording module is used to count the falling edges of the i-th high-frequency clock signal at each division time of each clock cycle and output the i+Nth clock status indication signal at each division time of each clock cycle; it is also used to receive a reset signal for reset.
[0068] Where i = 1, 2, ..., N.
[0069] Specifically, each clock cycle is divided into segments based on the delay time of a NOT gate, meaning that half a clock cycle is divided into N segments.
[0070] In specific implementation, the i-th rising edge recording module includes an i-th asynchronous reset D flip-flop;
[0071] The data input terminal D of the i-th asynchronous reset D flip-flop is connected to the inverting output terminal Q. The clock input terminal CK of the i-th asynchronous reset D flip-flop serves as the input terminal of the i-th rising edge recording module, receiving the i-th high-frequency clock signal. The asynchronous set terminal RSTB of the asynchronous reset D flip-flop serves as the reset terminal of the i-th rising edge recording module, receiving the reset signal RST. The data output terminal Q of the i-th asynchronous reset D flip-flop serves as the output terminal of the i-th rising edge recording module, outputting the i-th clock status indication signal.
[0072] In specific implementation, the i+Nth falling edge recording module includes the i+Nth asynchronous reset D flip-flop and the i+Nth inverter;
[0073] The input terminal of the (i+N)th inverter serves as the input terminal of the (i+N)th falling edge recording module, receiving the i-th high-frequency clock signal; the output terminal of the (i+N)th inverter is connected to the clock input terminal CK of the (i+N)th asynchronous reset D flip-flop; the data input terminal D of the (i+N)th asynchronous reset D flip-flop is connected to the inverted output terminal Q; the asynchronous set terminal RSTB of the (i+N)th asynchronous reset D flip-flop serves as the reset terminal of the (i+N)th falling edge recording module, receiving a reset signal; the data output terminal Q of the (i+N)th asynchronous reset D flip-flop serves as the output terminal of the (i+N)th falling edge recording module, outputting the i+Nth clock status indication signal.
[0074] Specifically, the asynchronous reset D flip-flop's data input terminal is connected to its inverted output terminal to achieve a frequency divide-by-two operation.
[0075] Specifically, each clock status indicator signal completes one cycle after 2 clock cycles, therefore, there are N*2*2 sets of clock status indicator signals.
[0076] For example, in this embodiment, N is 5. Figure 4 As shown, the clock status register module includes 10 asynchronous reset D flip-flops and 5 inverters. The inputs to the rising edge recording modules (channels 1-5) and the falling edge recording modules (channels 1-5) are the high-frequency clock signals CLK1-CLK5 (channels 1-5). The outputs of the rising edge recording modules (channels 1-5) are the clock status indicator signals D1-D5 (channels 1-5), and the outputs of the falling edge recording modules (channels 1-5) are the clock status indicator signals D6-D10 (channels 6-10). When the rising or falling edge of the high-frequency clock signal arrives, the output level of the D flip-flops changes, realizing a counting function and generating 10 clock status indicator signals D1-D10. D1-D10, as a group of clock status indicator signals, can represent the waveform of the high-frequency output signals CLK1-CLK5 at that moment, thus yielding 20 groups of clock status indicator signals.
[0077] In implementation, the entropy source selection module includes an encoding circuit and a selection module;
[0078] The encoding circuit is used to determine the number of channels of the random number sequence to be output at each division time of each clock cycle based on the 2N channels of clock status indication signals received at each division time of each clock cycle.
[0079] The selection module is used to generate one random number sequence by outputting random numbers at each division time of each clock cycle, based on the number of random number sequences to be output at each division time of each clock cycle.
[0080] In specific implementation, the encoding circuit determines the number of paths for the expected output random number sequence in each clock cycle in the following way:
[0081] Based on the 2N clock status indication signals of the current division time and the previous division time, determine the number of high-frequency clock signals that have undergone waveform reversal.
[0082] Based on the number of high-frequency clock signals that undergo waveform reversal and the total number of high-frequency clock signals, determine the number of random number sequences to be output at the current time of division.
[0083] Specifically, based on the changes in the 2N clock status indication signals at the current division time and the 2N clock status indication signals at the previous division time, the high-frequency clock signals that have rising or falling edges are determined, and the number of high-frequency clock signals that have undergone waveform inversion can be obtained.
[0084] Specifically, the number of paths n of the random number sequence to be output at the current partitioning time is represented as:
[0085]
[0086] In the formula, m represents the number of high-frequency clock signals whose waveforms reverse at the current division time, N represents the total number of high-frequency clock signals, and mod represents modulo operation.
[0087] Specifically, the clock status register module generates N*2*2 types of 2N clock status indication signals. The encoding circuit encodes the number of high-frequency clock signals that undergo waveform inversion corresponding to each type of 2N clock status indication signal to obtain a selection signal. The selection module selects the corresponding random number at each division time according to the selection signal and outputs it.
[0088] It is understandable that the change time of the 2N clock status indication signals is the delay time of one NOT gate. Based on the 2N clock status indication signals, the waveform of the high-frequency signal at the middle position of half a cycle can be selected as the output signal. The N high-frequency signals are equivalent to one ultra-high frequency signal. At this time, the sampled high-frequency clock satisfies the setup time and hold time of a general D flip-flop. The frequency of the generated ultra-high frequency signal is as high as 1 / (2 * the delay time of a single NOT gate), which is N times higher than the frequency of the ring oscillation composed of traditional N NOT gates. This realizes the generation of ultra-high frequency signals and avoids the metastability problem when a general D flip-flop samples ultra-high frequency signals.
[0089] For example, in this embodiment, N is 5. Figure 5 As shown, the entropy source selection module includes an encoding circuit and a 5-to-1 selection module; the 2N clock status indication signals D1-D10 of the clock status register module generate selection signals sel0, sel1, and sel2 through the encoding circuit, and the truth table of the encoding circuit is shown in Table 2; subsequently, the 5-to-1 selection module selects the output sampling waveform as the middle position of half a cycle of the high-frequency signal according to the selection signals sel0, sel1, and sel2, as shown in Table 3, the truth table of the 5-to-1 selection module, and finally outputs a random number sequence T. At this moment, the sampled high-frequency clock satisfies the setup time and hold time of a general D flip-flop.
[0090] Table 2 Truth Table of Encoding Circuit
[0091]
[0092]
[0093] Table 3 Truth Table for the Five-Choice Selection Module
[0094] sel0 sel1 sel2 Output random numbers 0 0 0 Q4 0 0 1 Q5 0 1 0 Q1 0 1 1 Q2 1 0 0 Q3
[0095] For example, in this embodiment, taking N as 5, the process of the ultra-high-speed true random number generator of this embodiment will be described. The timing relationship between the reset signal RST, the enable signal EN, and the five high-frequency clock signals CLK1 to CLK5 is as follows: Figure 6 As shown.
[0096] At the moment when the enable signal EN changes from "0" to "1", the initial state waveforms of the five high-frequency clock signals CLK1 to CLK5 are as follows: Figure 6 As shown, one clock cycle of CLK1-5 can be divided into 10 parts. Figure 6 The document describes the correspondence between the first 11 sets of clock status indication signals and the output high-frequency signals CLK1-CLK5.
[0097] At the first division point, the initial state of the clock state indicator signal is 0000000000. At the second division point, CLK2 flips on the falling edge, D7 becomes 1, and the others remain unchanged. At this moment, the output waveform of CLK5 reaches the middle position of half a cycle.
[0098] At the third division point, CLK3 flips on the rising and falling edge, D3 becomes 1, and D1, D2, and D5-D10 remain unchanged from the previous division point; at this division point, the output waveform of CLK1 reaches the middle position of half a cycle.
[0099] Similarly, each group of clock status indicator signals corresponds to a group of CLK1-5 output waveforms. After 20 time intervals, at the 21st time interval, all waveforms become the output waveforms of the first group of CLK1-CLK5, and the clock status indicator signal becomes 0000000000, completing one cycle. Therefore, there are a total of 20 groups of clock status indicator signals.
[0100] The correspondence between the sampled random number sequence selected by the 5-to-1 data selector and the clock status indication signal is also as follows: Figure 6 As shown, the gray shaded area represents the sampled high-frequency waveform selected for output. Furthermore, based on each clock state, the shaded portion of the random number sequence Q1 to Q5 is selected as the output signal, effectively transforming the five random number sequences into a single ultra-high-frequency random number sequence. The change time of each clock state indicator signal is equal to the delay time of a single NOT gate, resulting in a generated ultra-high-frequency signal with a frequency as high as 1 / (2 * the delay time of a single NOT gate). This represents a 5-fold increase in frequency compared to the ring oscillation frequency composed of N NOT gates, thus achieving the generation of an ultra-high-frequency signal.
[0101] Compared with existing technologies, this embodiment provides an ultra-high-speed true random number generator, including a high-frequency ring oscillator module, an entropy source acquisition module, a clock status register module, and an entropy source selection module. The clock status register module records the rising and falling edges of each high-frequency signal. Based on this, rules are set, and the entropy source selection module selects the random numbers output by the entropy source acquisition module to generate a random number sequence. On the one hand, it can generate ultra-high-frequency signals that are not limited by the number of stages in the ring oscillator, that is, it can generate ultra-high-frequency clock signals without using the minimum number of inverter stages. Moreover, compared with the ring oscillator composed of the minimum number of stages (i.e., three pairs of inverters), it is not limited by the integrated circuit process size, and its clock frequency can be higher. On the other hand, the ultra-high-speed clock sampling architecture can also avoid the metastability problem of D flip-flop sampling, and better meet the key design indicator of "strong randomness" of true random number generators, which meets the needs of practical information security applications and can be applied to key generation and device / chip authentication in cryptographic chips.
[0102] Example 2
[0103] The present invention provides a specific embodiment of a cryptographic chip, which includes the ultra-high-speed true random number generator described in embodiment 1.
[0104] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.
[0105] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A high-speed true random number generator, characterized in that, It includes a high-frequency ring oscillation module, an entropy source acquisition module, a clock status register module, and an entropy source selection module; The high-frequency ring resonator module is used to output N high-frequency clock signals based on the received enable signal. The entropy source acquisition module is used to sample the received N high-frequency clock signals and generate N random number sequences. The clock status register module is used to record the waveform flipping state of the received N high-frequency clock signals and generate 2N clock status indication signals at each division time of each clock cycle. The entropy source selection module is used to select from the received N random number sequences based on the 2N clock status indication signals at each division time of each clock cycle, and generate one random number sequence.
2. The ultra-high-speed true random number generator according to claim 1, characterized in that, The entropy source acquisition module includes a low-frequency ring vibration module and an N-channel acquisition module; The low-frequency ring resonator module is used to output low-frequency signals; The i-th acquisition module is used to sample the received i-th high-frequency clock signal based on the received low-frequency signal to obtain the i-th random number sequence; where i = 1, 2, ..., N.
3. The ultra-high-speed true random number generator according to claim 2, characterized in that, The i-th acquisition module includes an i-th first-level D flip-flop and an i-th second-level D flip-flop; The data input terminal of the i-th first-level D flip-flop serves as the data input terminal of the i-th acquisition module, receiving the i-th high-frequency clock signal. The The output of the i-th primary D flip-flop is connected to the data input of the i-th secondary D flip-flop. The output terminal of the i-th secondary D flip-flop is used as the output terminal of the i-th acquisition module to output the i-th random number sequence. The clock input terminals of the i-th primary D flip-flop and the i-th secondary D flip-flop serve as the clock input terminals of the i-th acquisition module, receiving low-frequency signals.
4. The ultra-high-speed true random number generator according to claim 1, characterized in that, The clock status register module includes an N-way rising edge recording module and an N-way falling edge recording module; The i-th rising edge recording module is used to count the rising edges of the i-th high-frequency clock signal at each division time of each clock cycle and output the i-th clock status indication signal at each division time of each clock cycle; it is also used to receive a reset signal for resetting. The i+Nth falling edge recording module is used to count the falling edges of the i-th high-frequency clock signal at each division time of each clock cycle and output the i+Nth clock status indication signal at each division time of each clock cycle; it is also used to receive a reset signal for reset. Where i = 1, 2, ..., N.
5. The ultra-high-speed true random number generator according to claim 4, characterized in that, The i-th rising edge recording module includes an i-th asynchronous reset D flip-flop; The data input terminal of the i-th asynchronous reset D flip-flop is connected to the inverted output terminal, and the clock input terminal of the i-th asynchronous reset D flip-flop serves as the input terminal of the i-th rising edge recording module to receive the i-th high-frequency clock signal. The asynchronous set terminal of the i-th asynchronous reset D flip-flop serves as the reset terminal of the i-th rising edge recording module, receiving a reset signal; the data output terminal of the i-th asynchronous reset D flip-flop serves as the output terminal of the i-th rising edge recording module, outputting the i-th clock status indication signal.
6. The ultra-high-speed true random number generator according to claim 4, characterized in that, The i+Nth falling edge recording module includes an i+Nth asynchronous reset D flip-flop and an i+Nth inverter. The input terminal of the (i+N)th inverter serves as the input terminal of the (i+N)th falling edge recording module, receiving the i-th high-frequency clock signal; the output terminal of the (i+N)th inverter is connected to the clock input terminal of the (i+N)th asynchronous reset D flip-flop. The data input terminal of the (i+N)th asynchronous reset D flip-flop is connected to the inverted output terminal; the asynchronous set terminal of the (i+N)th asynchronous reset D flip-flop serves as the reset terminal of the (i+N)th falling edge recording module, receiving a reset signal. The data output terminal of the (i+N)th asynchronous reset D flip-flop serves as the output terminal of the (i+N)th falling edge recording module, outputting the (i+N)th clock status indication signal.
7. The ultra-high-speed true random number generator according to claim 1, characterized in that, The entropy source selection module includes an encoding circuit and a selection module; The encoding circuit is used to determine the number of random number sequences to be output at each time division of each clock cycle based on the 2N clock status indication signals received at each time division of each clock cycle. The selection module is used to generate one random number sequence by outputting random numbers at each division time of each clock cycle, based on the number of random number sequences to be output at each division time of each clock cycle.
8. The ultra-high-speed true random number generator according to claim 7, characterized in that, The encoding circuit determines the number of paths for the expected output random number sequence in each clock cycle in the following manner: Based on the 2N clock status indication signals of the current division time and the previous division time, determine the number of high-frequency clock signals that have undergone waveform reversal. Based on the number of high-frequency clock signals that undergo waveform reversal and the total number of high-frequency clock signals, determine the number of random number sequences to be output at the current time of division.
9. The ultra-high-speed true random number generator according to claim 8, characterized in that, The number of paths, n, of the random number sequence to be output at the current partitioning time is represented as: In the formula, m represents the number of high-frequency clock signals whose waveforms reverse at the current division time, N represents the total number of high-frequency clock signals, and mod represents modulo operation.
10. A cryptographic chip, characterized in that, The cryptographic chip includes the ultra-high-speed true random number generator as described in any one of claims 1-9.