Firmware upgrading method and device, electronic equipment, storage medium and program product

Abstract

The application discloses a firmware upgrading method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of computer hardware. The method comprises the following steps: obtaining a firmware upgrading package of a CPLD; writing the firmware upgrading package into a storage unit of the CPLD, and after the writing of the firmware upgrading package is completed, controlling a reset pin of a BMC to be connected to a pull-up power supply circuit based on a control module; sending a first firmware updating instruction to the CPLD, so that the CPLD completes a firmware upgrading process based on the first firmware updating instruction and the firmware upgrading package in the storage unit; monitoring firmware upgrading state information of the CPLD; and based on the firmware upgrading state information and the control module, controlling the reset pin of the BMC to be connected to a reset control pin of the CPLD. In this way, even if the new firmware of the CPLD fails to operate normally, the BMC can continuously update the firmware of the CPLD or troubleshoot the CPLD, and the convenience of server maintenance and the stability of the system are significantly improved.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, and in particular to a firmware upgrade method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] With the rapid development of artificial intelligence (AI) and large-scale modeling technology, servers, as the core computing infrastructure of the digital economy, are crucial for supporting the intelligent upgrading of industries such as autonomous driving, biomedicine, and intelligent manufacturing. Complex programmable logic devices (CPLDs) in servers handle low-level logic management functions such as power-on reset and interface expansion for multi-processor clusters, operating independently of the central processing unit (CPU). The baseboard management controller (BMC), as an independent small system, is responsible for hardware monitoring and management, and its power-on reset process must strictly adhere to power sequence requirements. Since the BMC's reset signal typically relies on the CPLD output, the two are tightly coupled: the CPLD can perform a forced hardware reset when the BMC is stuck, but the CPLD itself lacks autonomous upgrade capabilities and needs to be updated via firmware written through the BMC via the integrated circuit bus (I2C). When the BMC writes new firmware to the CPLD, if the new version fails to function properly due to logical errors, the CPLD will be unable to output a valid reset signal, causing the BMC to lose network connectivity and control capabilities. At this point, the system is in a deadlock state; the BMC cannot remotely update the CPLD firmware or restore its own functionality and can only perform offline flashing by physically accessing the server and using a programmer connected to the JTAG interface. In high-density AI servers, the computing node space is highly compressed and powered by high-density connectors. Offline refresh processes require dedicated power supply fixtures, significantly increasing operational complexity and leading to prolonged system downtime. Existing solutions have significant drawbacks: adding a dedicated CPLD to the BMC card is difficult to implement due to increased server integration and GPU computing node space limitations; using the CPLD's internal backup area is ineffective in handling firmware upgrade failures because the primary and backup firmware are usually updated simultaneously, or the backup version also has logical issues. These limitations expose servers to the risk of unrecoverable system failures during CPLD firmware upgrades, especially in unattended remote data center environments, where maintenance costs and business interruption losses increase dramatically. Summary of the Invention

[0003] In view of this, embodiments of this application provide a firmware upgrade method, apparatus, electronic device, storage medium, and program product.

[0004] According to a first aspect of this application, a firmware upgrade method is provided, applied to a baseboard management controller (BMC). The BMC is connected to a complex programmable logic device (CPLD) and a control module. The control module is connected to the control terminal of a channel switching module. The first input terminal of the channel switching module is connected to the reset control pin of the CPLD, the second input terminal is connected to a pull-up power supply circuit, and the output terminal is connected to the reset pin of the BMC. The method includes: Obtain the firmware upgrade package for the CPLD; The firmware upgrade package is written to the storage unit of the CPLD. After the firmware upgrade package is written, the first input terminal and the output terminal of the control channel switching module are disconnected and the second input terminal and the output terminal are connected, so that the reset pin of the BMC is connected to the pull-up power supply circuit, and the BMC maintains normal operation during the CPLD firmware upgrade. Send a first firmware update command to the CPLD so that the CPLD can complete the firmware upgrade process based on the first firmware update command and the firmware upgrade package in the storage unit; Monitor the firmware upgrade status information of the CPLD; Based on the firmware upgrade status information and the control module, the second input terminal and output terminal of the control channel switching module are disconnected, while the first input terminal and output terminal are connected, so that the BMC's reset pin is connected to the CPLD's reset control pin.

[0005] Furthermore, this application also proposes a control module that controls the channel switching module, wherein the first input terminal is disconnected from the output terminal and the second input terminal is connected to the output terminal, including: Write the first target value into the first target register of the control module so that the pin state connecting the control module and the channel switching module is the output state; Write a second target value to the second target register of the control module so that the control module inputs a first signal to the control terminal of the channel switching module based on the second target value, so that the first input terminal and the output terminal of the channel switching module are disconnected and the second input terminal and the output terminal are connected.

[0006] Furthermore, this application also proposes that, based on firmware upgrade status information and the control module, the second input terminal and output terminal of the control channel switching module are disconnected, while the first input terminal and output terminal are connected, including: If the firmware upgrade status information indicates that the CPLD firmware upgrade is complete, based on the control module, the second input terminal and the output terminal of the control channel switching module are disconnected, and the first input terminal and the output terminal are connected, so that the BMC reset pin is connected to the CPLD reset control pin. If the firmware upgrade status information indicates that the CPLD firmware upgrade is not complete, a notification message is sent to the user; and when the user inputs a new firmware upgrade package for the CPLD based on the notification message, the new firmware upgrade package is written into the CPLD's storage unit; a second firmware update command is sent to the CPLD so that the CPLD can re-upgrade the firmware based on the second firmware update command and the new firmware upgrade package in the storage unit.

[0007] Furthermore, this application also proposes that, based on the control module, the second input terminal and output terminal of the control channel switching module are disconnected, while the first input terminal and output terminal are connected, including: Write a third target value to the second target register of the control module so that the control module inputs a second signal to the control terminal of the channel switching module based on the third target value, so that the second input terminal and the output terminal of the channel switching module are disconnected and the first input terminal and the output terminal are connected.

[0008] Furthermore, this application also proposes monitoring the firmware upgrade status information of the CPLD, including: Monitor the level status of the flag pins of the CPLD; If the flag pin is at a high level, the CPLD firmware upgrade is not complete. If the flag pin is at a low level, the firmware upgrade status information of the CPLD is obtained.

[0009] Furthermore, this application also proposes that if the level of the flag bit pin is high and the duration of the high level exceeds a duration threshold, the status information of the CPLD firmware upgrade not being completed is obtained.

[0010] Furthermore, this application also proposes that the BMC and the control module are connected via an integrated circuit bus, and the control module is an integrated circuit bus to general-purpose input / output port expansion chip.

[0011] Furthermore, this application also proposes that the channel switching module includes multiple four-channel two-to-one bus switches, each four-channel two-to-one bus switch including a first input terminal of four channels, a second input terminal of four channels, and an output terminal of four channels.

[0012] Furthermore, this application also proposes writing the firmware upgrade package into the storage unit of the CPLD, including: Determine the integrated circuit bus address of the CPLD; Erase the data in the memory cell of the CPLD based on the integrated circuit bus address; Based on the integrated circuit bus address, the firmware upgrade package is written to the CPLD's storage unit.

[0013] According to a second aspect of this application, a firmware upgrade device is proposed, applied to a baseboard management controller (BMC). The BMC is connected to a complex programmable logic device (CPLD) and a control module. The control module is connected to the control terminal of a channel switching module. The first input terminal of the channel switching module is connected to the reset control pin of the CPLD, the second input terminal is connected to a pull-up power supply circuit, and the output terminal is connected to the reset pin of the BMC. The device includes: The acquisition module is used to obtain the firmware upgrade package for the CPLD; The writing module is used to write the firmware upgrade package into the storage unit of the CPLD. After the firmware upgrade package is written, the first input terminal and the output terminal of the control module are disconnected and the second input terminal and the output terminal are connected based on the control module, so that the reset pin of the BMC is connected to the pull-up power supply circuit, and the BMC maintains normal operation during the CPLD firmware upgrade. The sending module is used to send a first firmware update command to the CPLD, so that the CPLD can complete the firmware upgrade process based on the first firmware update command and the firmware upgrade package in the storage unit. The monitoring module is used to monitor the firmware upgrade status information of the CPLD; The switching module is used to control the channel switching module based on firmware upgrade status information and the control module. The second input terminal of the control channel switching module is disconnected from the output terminal, and the first input terminal is connected to the output terminal, so that the BMC's reset pin is connected to the CPLD's reset control pin.

[0014] Furthermore, this application also proposes that the writing module is used to write a first target value to the first target register of the control module, so that the pin state of the control module connected to the channel switching module is the output state; Write a second target value to the second target register of the control module so that the control module inputs a first signal to the control terminal of the channel switching module based on the second target value, so that the first input terminal and the output terminal of the channel switching module are disconnected and the second input terminal and the output terminal are connected.

[0015] Furthermore, this application also proposes that if the firmware upgrade status information indicates that the firmware upgrade of the CPLD is complete, the switching module is used to disconnect the second input terminal and the output terminal of the control channel switching module based on the control module, and connect the first input terminal and the output terminal, so that the reset pin of the BMC is connected to the reset control pin of the CPLD. If the firmware upgrade status information indicates that the CPLD firmware upgrade is not complete, a notification message is sent to the user; and when the user inputs a new firmware upgrade package for the CPLD based on the notification message, the new firmware upgrade package is written into the CPLD's storage unit; a second firmware update command is sent to the CPLD so that the CPLD can re-upgrade the firmware based on the second firmware update command and the new firmware upgrade package in the storage unit.

[0016] Furthermore, this application also proposes that the switching module is used to write a third target value to the second target register of the control module, so that the control module inputs a second signal to the control terminal of the channel switching module based on the third target value, so that the second input terminal and the output terminal of the channel switching module are disconnected, and the first input terminal and the output terminal are connected.

[0017] Furthermore, this application also proposes that the monitoring module is used to monitor the level state of the flag bit pin of the CPLD; If the flag pin is at a high level, the CPLD firmware upgrade is not complete. If the flag pin is at a low level, the firmware upgrade status information of the CPLD is obtained.

[0018] Furthermore, this application also proposes that the monitoring module is used to obtain the status information that the firmware upgrade of the CPLD is not completed if the level state of the flag bit pin is high and the duration of the high level exceeds a duration threshold.

[0019] Furthermore, this application also proposes that the BMC and the control module are connected via an integrated circuit bus, and the control module is an integrated circuit bus to general-purpose input / output port expansion chip.

[0020] Furthermore, this application also proposes that the channel switching module includes multiple four-channel two-to-one bus switches, each four-channel two-to-one bus switch including a first input terminal of four channels, a second input terminal of four channels, and an output terminal of four channels.

[0021] Furthermore, this application also proposes that the writing module is used to determine the integrated circuit bus address of the CPLD; Erase the data in the memory cell of the CPLD based on the integrated circuit bus address; Based on the integrated circuit bus address, the firmware upgrade package is written to the CPLD's storage unit.

[0022] According to a third aspect of this application, this application proposes an electronic device comprising: The circuit connects the Baseboard Management Controller (BMC), the Complex Programmable Logic Device (CPLD), the control module, the channel switching module, and the pull-up power supply circuit. The BMC is connected to the CPLD and the control module respectively. The control module is connected to the control terminal of the channel switching module. The first input terminal of the channel switching module is connected to the reset control pin of the CPLD, the second input terminal is connected to the pull-up power supply circuit, and the output terminal is connected to the reset pin of the BMC. BMC is used to perform the firmware upgrade method described above.

[0023] According to a fourth aspect of this application, this application proposes a computer-readable storage medium storing computer instructions for causing a computer to perform the aforementioned firmware upgrade method.

[0024] According to the fifth aspect of this application, this application proposes a computer program product, including a computer program or instructions, which, when executed by a processor, implement the above-described firmware upgrade method.

[0025] The firmware upgrade method, apparatus, electronic device, storage medium, and program product of this embodiment, by adding a hardware control module, a channel switching module, and a pull-up power supply circuit, and by enabling the control module to temporarily switch the BMC's reset pin to the pull-up power supply circuit during CPLD firmware upgrades, ensures that the BMC can continue to operate normally even when the new CPLD firmware is unstable. Therefore, even if the new CPLD firmware fails to operate normally, the BMC can continue to perform firmware updates or troubleshooting for the CPLD, avoiding the problem of BMC deadlock due to CPLD failure in traditional solutions, which necessitates the use of complex and inefficient offline programmers for flashing. This significantly improves the convenience of server maintenance and the stability of the system.

[0026] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application; Figure 2 This is a flowchart illustrating a firmware upgrade method according to an embodiment of this application; Figure 3 This is a schematic diagram of the hardware state of the electronic device when it is initially powered on in the embodiments of this application; Figure 4 This is a schematic diagram of the hardware state when the BMC upgrades the CPLD in the embodiments of this application; Figure 5 This is a schematic diagram of the hardware state when the CPLD upgrade is completed in the embodiments of this application; Figure 6 This is a schematic diagram of the firmware upgrade device in the embodiments of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] This application proposes a firmware upgrade method applied to a baseboard management controller (BMC). Figure 1 As shown, the BMC is connected to both the complex programmable logic device (CPLD) and the control module. The control module is connected to the control terminal (S) of the channel switching module. The first input terminal of the channel switching module is connected to the reset control pin (RST MODULE) of the CPLD, the second input terminal is connected to the pull-up power supply circuit (P3V3 STBY), and the output terminal is connected to the reset pin (RST) of the BMC. This method is as follows... Figure 2 As shown, it includes: S201, obtain the firmware upgrade package for CPLD.

[0030] S202, write the firmware upgrade package into the storage unit of the CPLD, and after the firmware upgrade package is written, disconnect the first input terminal and output terminal of the control channel switching module based on the control module, and connect the second input terminal and output terminal, so that the BMC reset pin is connected to the pull-up power supply circuit, and the BMC maintains normal operation during the CPLD firmware upgrade.

[0031] S203, send a first firmware update command to the CPLD so that the CPLD can complete the firmware upgrade process based on the first firmware update command and the firmware upgrade package in the storage unit.

[0032] S204 monitors the firmware upgrade status information of the CPLD.

[0033] S205, based on firmware upgrade status information and the control module, disconnects the second input terminal and output terminal of the control channel switching module, and connects the first input terminal and output terminal, so that the BMC reset pin is connected to the CPLD reset control pin.

[0034] For ease of understanding, the following explains some key terms in this embodiment: The Baseboard Management Controller (BMC) is an embedded management system whose main function is to monitor the physical status of the server and provide remote management capabilities to ensure the stable operation of the server.

[0035] Complex Programmable Logic Devices (CPLDs) are programmable logic devices that contain programmable logic macrocells and interconnect resources. They are capable of implementing complex digital logic functions and are commonly used in servers for low-level hardware logic control, such as power-on reset and interface expansion.

[0036] The control module receives control signals from the BMC and converts them into specific actions that drive the channel switching module. This module typically serves as the interface between the BMC and the channel switching module, enabling precise control of channel switching.

[0037] A channel switching module is an electronic switching device that can selectively connect different input terminals to its output terminal according to a control signal. In this embodiment, the module is used to switch between the BMC's reset pin and the CPLD's reset control pin or pull-up power supply circuit.

[0038] The pull-up power supply circuit provides a stable high-level voltage. When the BMC's reset pin is connected to this pull-up power supply circuit, it ensures that the BMC's reset signal remains high, thereby enabling the BMC to maintain normal operation.

[0039] The reset pin is a set of input pins on the BMC, and its voltage level determines whether the BMC is in a reset state. Typically, a low level indicates a reset, and a high level indicates normal operation.

[0040] The reset control pin is a set of input pins on the CPLD used to output signals that control the BMC reset state. In normal operating mode, the CPLD controls the BMC reset timing through this pin.

[0041] A firmware upgrade package is a data set containing a new version of the CPLD firmware program, used to update the internal program logic of the CPLD to fix defects or add new features.

[0042] Storage units are non-volatile storage areas within a CPLD used to store firmware upgrade packages and running programs, such as flash memory.

[0043] Firmware update commands are commands sent by the BMC to the CPLD to trigger the CPLD to perform firmware upgrade operations, such as loading the firmware in the storage unit into SRAM and running it.

[0044] Firmware upgrade status information is the status feedback generated by the CPLD during the firmware upgrade process, used to indicate whether the upgrade is complete, successful, or whether there is an error.

[0045] In this embodiment, the BMC, CPLD, control module, and channel switching module can be located on the motherboard, while the pull-up power supply circuit can be located outside the motherboard.

[0046] In practice, upon initial power-on, the actual operating state of the system is as follows: Figure 3 As shown. The S-terminal (control terminal) of the channel switching module is connected to both the control module and the pull-down resistor. Since the control module requires BMC configuration, and the BMC is not activated during initial power-up, the control module's output is initially set to high impedance (OUTPUT=Z). At this time, the pull-down resistor configures the S-terminal of the channel switching module to low level (S=0), connecting the first input terminal (1B1, 2B1, 3B1, 4B1) and the output terminal (1A, 2A, 3A, 4A) of the switching channel module. That is, during initial power-up, after the CPLD completes initialization, the CPLD's RST module controls the BMC's RST signal to be pulled high sequentially, completing the initial power-up process of the BMC. The flag signal between the BMC and CPLD is defaulted to 0 in the CPLD module; that is, as long as the CPLD program runs normally, the BMC will continuously receive a FLAG signal of 0. After the BMC completes initialization, it is ready for normal operation.

[0047] Firmware upgrade packages for the CPLD can be obtained in several ways. For example, the firmware upgrade package can be pre-stored on the BMC's local storage media and read when needed. Alternatively, the firmware upgrade package can be uploaded by the user to the BMC via a network interface, and then received and processed by the BMC.

[0048] Furthermore, after obtaining the firmware upgrade package, it is transmitted to the CPLD's storage unit. Specifically, after receiving the CPLD firmware upgrade package uploaded by the user, the BMC first confirms the required I2C channel and the target CPLD's I2C address based on the configuration file. Then, it writes to the corresponding registers of the CPLD to initiate the FLASH update process. Subsequently, after the CPLD completes its configuration, the BMC first erases the data in the CPLD's FLASH, then writes the firmware upgrade package and completes verification. After successful verification, the BMC confirms that the firmware upgrade package has been successfully written.

[0049] After the firmware upgrade package is written, the control module is activated to perform a channel switching operation. For example... Figure 4 As shown, the control module can directly control the physical control pins of the channel switching module. For example, by changing the level of the physical control pins of the channel switching module control terminal to a high level (S=1), the first input terminal and the output terminal of the channel switching module are disconnected, while the second input terminal (1B2, 2B2, 3B2, 4B2) and the output terminal (1A, 2A, 3A, 4A) are connected. Thus, the BMC's reset pin is connected to the pull-up power supply circuit, ensuring that the BMC can continuously receive a high-level reset signal during the CPLD firmware upgrade process, thereby maintaining its normal operating state and preventing the BMC from hanging due to abnormal CPLD reset signals.

[0050] Subsequently, a first firmware update command is sent to the CPLD, enabling the CPLD to complete the firmware upgrade process based on this command and the firmware upgrade package in the storage unit. When the BMC sends the first firmware update command to the CPLD, it can transmit the data through a communication interface supported by the CPLD (such as an I2C bus or an SPI bus). Upon receiving the command, the CPLD will, according to its internal logic, read the written firmware upgrade package from the storage unit, for example, load the new firmware into the internal SRAM, and begin execution.

[0051] Subsequently, during the firmware upgrade of the CPLD, the BMC continuously monitors the firmware upgrade status information of the CPLD. This monitoring can be achieved in several ways. For example, the BMC can periodically send query commands to the CPLD to obtain the value of the CPLD's internal status register, thereby determining the upgrade progress or whether it is complete. Alternatively, the CPLD can be configured to output its current status through a dedicated flag signal line during the firmware upgrade phase, and the BMC can obtain status information by reading the level changes of this flag signal line; for example... Figure 4 As shown, after the upgrade module in the CPLD detects the first firmware update command, it sets FLAG to 1. The BMC will then continuously receive a signal with FLAG set to 1, indicating that the CPLD firmware upgrade is not complete.

[0052] Finally, when the BMC determines that the CPLD firmware upgrade process has reached a predetermined state, the control module is instructed to change the connection state of the channel switching module. For example, as... Figure 5 As shown, after the CPLD upgrade is completed, the FLAG signal is set to 0. When the BMC receives the FLAG signal of 0, it indicates that the CPLD firmware upgrade is complete. Then, based on the control module, the control terminal of the control channel switching module is set to low level (S=0), which disconnects the second input terminal from the output terminal and connects the first input terminal (1B1,2B1,3B1,4B1) to the reset output terminal (1A,2A,3A,4A), so that the BMC's reset pin is connected to the CPLD's reset control pin.

[0053] The firmware upgrade method in this embodiment adds a hardware control module, a channel switching module, and a pull-up power supply circuit. During the CPLD firmware upgrade, the control module controls the channel switching module to temporarily switch the BMC's reset pin to the pull-up power supply circuit, ensuring that the BMC can still function normally even when the new CPLD firmware is unstable. Therefore, even if the new CPLD firmware fails to run properly, the BMC can continue to update the CPLD firmware or troubleshoot the fault, avoiding the BMC deadlock caused by CPLD failure in traditional solutions, which necessitates complex and inefficient offline programmers for flashing. This significantly improves the convenience of server maintenance and the stability of the system.

[0054] In an optional embodiment, this application further proposes specific steps in step S202, where the first input terminal and output terminal of the control module are disconnected and the second input terminal and output terminal are connected, based on the control module controlling the channel switching module. These steps include: writing a first target value to the first target register of the control module to make the pin state connected to the channel switching module an output state; and writing a second target value to the second target register of the control module to make the control module input a first signal to the control terminal of the channel switching module based on the second target value, thereby disconnecting the first input terminal and output terminal of the channel switching module and connecting the second input terminal and output terminal.

[0055] Specifically, the control module contains a register, known as the first target register, for configuring the operating modes of its general purpose input / output (GPIO) pins. These GPIO pins are connected to the control terminals of the channel switching module. By writing a specific first target value (e.g., a binary bit pattern) to this first target register, the GPIO pins connected to the control terminals of the channel switching module can be configured as output pins. If a pin is incorrectly configured as an input pin, the control module will be unable to effectively drive the channel switching module, resulting in control failure. This step ensures that the first signal is correctly issued from the control module.

[0056] After the GPIO pin is configured to output mode, a first signal is generated and output by writing a specific second target value to the second target register of the control module (e.g., a data output register). This second target value represents the specific logic level or signal mode that the channel switching module needs to receive. When the control module sends this first signal to the control terminal of the channel switching module, the channel switching module responds to this signal according to its internal logic and performs the corresponding switching operation. Specifically, this operation will cause the connection between the first input and output terminals of the channel switching module to be disconnected, while establishing a connection between the second input and output terminals. This means that the BMC's reset pin will be disconnected from the CPLD's reset control pin and instead connected to the pull-up power supply circuit, thereby allowing the BMC to maintain normal operation during CPLD firmware upgrades.

[0057] The above technical solution clarifies the specific operational steps for the control module to control the channel switching module. First, by writing a first target value to the first target register of the control module, the pin connecting the control module and the channel switching module is configured as an output, ensuring that the control module can actively and effectively send control signals to the channel switching module, avoiding control failures caused by incorrect pin configuration. Second, by writing a second target value to the second target register of the control module, a specific first signal is generated and input to the control terminal of the channel switching module, thus precisely achieving the preset state where the first input terminal of the channel switching module is disconnected from the output terminal and the second input terminal is connected to the output terminal. This register-based control method provides a clear and programmable interface, greatly improving the accuracy and reliability of control. It ensures that during CPLD firmware upgrades, the BMC's reset pin can stably connect to the pull-up power supply circuit, thereby guaranteeing the continuous normal operation of the BMC and avoiding the risk of system interruption or upgrade failure due to inaccurate control.

[0058] In an optional embodiment, this application further proposes step S205, which involves disconnecting the second input and output of the control channel switching module and connecting the first input and output based on the firmware upgrade status information and the control module. This includes: if the firmware upgrade status information indicates that the CPLD firmware upgrade is complete, disconnecting the second input and output of the control channel switching module and connecting the first input and output based on the control module, so that the BMC's reset pin connects to the CPLD's reset control pin; if the firmware upgrade status information indicates that the CPLD firmware upgrade is not complete, sending a notification message to the user; and upon receiving a new firmware upgrade package for the CPLD input by the user based on the notification message, writing the new firmware upgrade package into the CPLD's storage unit; and sending a second firmware update instruction to the CPLD, so that the CPLD re-upgrades the firmware based on the second firmware update instruction and the new firmware upgrade package in the storage unit.

[0059] Specifically, when the CPLD firmware upgrade status information indicates that the upgrade has been successfully completed, the system needs to restore the BMC's normal reset control over the CPLD. This is achieved by the control module operating the channel switching module. Specifically, the control module sends a corresponding control signal, causing the channel switching module to disconnect the second input terminal originally connected to the pull-up power supply circuit from the output terminal, while simultaneously reconnecting the first input terminal connected to the CPLD's reset control pin from the output terminal. In this way, the BMC's reset pin is once again directly connected to the CPLD's reset control pin, restoring the BMC's direct reset control capability over the CPLD. This ensures that the system can operate and manage normally after the CPLD firmware upgrade is completed and respond to the BMC's reset commands.

[0060] If the monitored firmware upgrade status information indicates that the CPLD firmware upgrade has failed, the system will generate and send a notification message to the user. This notification message may include key information such as the type of upgrade failure, possible causes, and the current status of the CPLD, allowing the user to be promptly aware of any anomalies during the upgrade process. The notification message can be sent in various ways, such as through the BMC's system logs, by sending an alarm email to a pre-set administrator email address via a network interface, by sending it to the network management system via an SNMP trap, or by displaying a clear error message on the local management interface, ensuring that the user is quickly informed of the upgrade failure and can take appropriate action.

[0061] After receiving a notification message indicating an upgrade failure, the user can analyze the message and potentially receive a new firmware upgrade package. This new package could be a patch that corrects issues from the previous version or a firmware rollback to a known stable version, designed to resolve the problems from the previous upgrade failure. When the system receives this new CPLD firmware upgrade package from the user through its interface (e.g., network interface, USB interface, or local storage media), it securely writes it to the CPLD's memory. The writing process typically involves data transfer via the communication interface between the BMC and the CPLD (e.g., I2C bus or SPI bus) to ensure the new firmware package is accurately stored in the CPLD's internal programmable memory, preparing for subsequent upgrade retry attempts.

[0062] After the new firmware upgrade package is successfully written to the CPLD's storage, the BMC sends a second firmware update command to the CPLD. The content of the second firmware update command can be the same as the first firmware update command. This command acts as a trigger signal, instructing the CPLD to initiate its internal firmware update mechanism. Upon receiving this command, the CPLD reads the newly written firmware upgrade package from its storage and reprograms or updates its own firmware according to the package's content. This re-upgrade process is the same as the initial upgrade mechanism, but uses a new firmware package, designed to correct or overcome problems from previous upgrade failures, thereby attempting a successful firmware upgrade and ensuring the CPLD can load the correct, functional firmware version.

[0063] Through the above technical solution, this application can accurately determine the completion status of CPLD firmware upgrades and adopt different processing strategies based on the determination results. When the upgrade is successful, the BMC can promptly restore normal reset control of the CPLD, ensuring the integrity of system functions. More importantly, when the CPLD firmware upgrade fails, the system can promptly send a notification message to the user, enabling the user to intervene and provide a new firmware upgrade package for retry. This mechanism effectively avoids the system becoming unavailable due to a single upgrade failure, significantly improves the robustness and reliability of the firmware upgrade process, reduces the complexity of system maintenance, and provides users with flexible fault recovery methods, thereby ensuring the continuous and stable operation of electronic devices.

[0064] In an optional embodiment, this application further proposes a specific implementation method based on the control module, wherein the second input terminal and the output terminal of the control channel switching module are disconnected, and the first input terminal and the output terminal are connected. The method includes: writing a third target value to the second target register of the control module, so that the control module inputs a second signal to the control terminal of the channel switching module based on the third target value, thereby disconnecting the second input terminal and the output terminal of the channel switching module and connecting the first input terminal and the output terminal.

[0065] Specifically, to restore the aforementioned reset control link, a specific third target value must first be written to the second target register inside the control module. This second target register is a dedicated storage unit within the control module used to configure its output pin control logic; for example, it could be a general-purpose input / output (GPIO) control register. The third target value is a preset, specifically encoded numerical value that instructs the control module to generate a second signal.

[0066] Upon receiving the third target value, the control module generates and inputs a second signal to the control terminal of the channel switching module based on this value. The control module can be a microcontroller, a dedicated logic chip, or a bus expansion chip. Its internal logic outputs the corresponding level or pulse sequence as the second signal according to the written third target value.

[0067] When the channel switching module receives the second signal, its internal switching logic is triggered, thereby changing its connection state. Specifically, the second input terminal of the channel switching module (which is typically connected to the pull-up power supply circuit) is disconnected from the output terminal (connected to the BMC's reset pin), while the first input terminal of the channel switching module (which is connected to the CPLD's reset control pin) is connected to the output terminal. This switching allows the CPLD's reset control to be returned from the pull-up power supply circuit to the BMC, thus restoring the BMC's normal reset control over the CPLD.

[0068] Through the above technical solution, by writing a specific third target value to the second target register of the control module, the control module can accurately generate and input a second signal to the control terminal of the channel switching module. This second signal can reliably drive the channel switching module to disconnect the second input terminal from the output terminal, while connecting the first input terminal to the output terminal. This ensures that after the CPLD firmware upgrade is completed or a successful re-upgrade, the BMC can resume normal reset control of the CPLD, thereby enabling the entire system to smoothly transition from the firmware upgrade state to the normal operating state. This avoids system instability or functional failure caused by abnormal reset control links, improving the system's reliability and maintainability.

[0069] In an optional embodiment, this application further proposes monitoring the firmware upgrade status information of the CPLD, including: monitoring the level status of the flag pin of the CPLD; if the level status of the flag pin is high, obtaining the status information that the firmware upgrade of the CPLD is not completed; if the level status of the flag pin is low, obtaining the status information that the firmware upgrade of the CPLD is completed.

[0070] Specifically, the CPLD's flag pin can be connected to the BMC via a flag signal line. This allows the BMC to directly read the voltage state of the flag pin on the CPLD, thus determining the CPLD's firmware upgrade status. During firmware upgrades, the CPLD can set this flag pin to different levels based on its internal upgrade status. For example, the CPLD's internal firmware upgrade logic can control this pin to output a high level when the upgrade is in progress or has failed, and a low level when the upgrade is successful. This approach avoids complex communication protocols, allowing the BMC to obtain the CPLD's upgrade status in a simple and direct manner. This flag pin can also be a general purpose input / output (GPIO) pin on the CPLD, programmable and controlled by the CPLD's internal logic.

[0071] When the BMC detects that the CPLD's flag pin is high, it indicates that the CPLD's firmware upgrade process has not been completed or has failed. A high level serves as a clear signal, indicating that the CPLD is currently in an abnormal or incomplete upgrade state. The BMC can use this to determine whether to retry, issue an alarm, or notify the user. This mechanism is simple, intuitive, and easy to implement.

[0072] When the BMC detects that the CPLD's flag pin is low, it indicates that the CPLD firmware upgrade process has been successfully completed. The low level serves as another clear signal, indicating that the CPLD has successfully loaded and is running the new firmware. The BMC can then perform subsequent system recovery operations, such as reconnecting the BMC's reset pin to the CPLD's reset control pin, to restore the system to normal operation. This approach provides a clear success indication, ensuring the correctness of the upgrade process.

[0073] Through the above technical solution, the BMC can directly determine the completion status of the firmware upgrade by monitoring the level state of the CPLD's flag pin, without needing complex communication protocols or frequent polling of the CPLD's internal registers. This hardware-based level signal monitoring method greatly simplifies the status acquisition logic, reduces the BMC's software overhead and processing burden, and improves the real-time performance and reliability of firmware upgrade status determination. When the flag pin is high, the BMC can quickly identify incomplete or failed upgrades, and thus take timely retry or alarm measures; when the flag pin is low, it can accurately determine that the upgrade was successful, and then safely execute subsequent system recovery operations. This not only improves the efficiency and stability of the firmware upgrade process, but also reduces the complexity of the system design.

[0074] In an optional embodiment, this application further proposes that the firmware upgrade incomplete status information of the CPLD is obtained only if the level state of the flag bit pin is high and the duration of the high level exceeds a duration threshold.

[0075] Specifically, the duration threshold refers to a preset time length, the value of which can be set according to the characteristics of the CPLD, the real-time requirements of the system for judging the upgrade status, and actual test data. For example, CPLD firmware upgrades typically complete in 2-4 minutes, so a duration threshold of 5 minutes can be set. When the level of the flag pin is detected to go high, the system starts a timer. This timer continuously records the time the flag pin remains high. Only when the flag pin remains high for a period exceeding the preset duration threshold is the CPLD firmware upgrade confirmed to be in an incomplete state. This mechanism avoids misjudging brief high levels and ensures the accuracy of status judgment.

[0076] The above technical solution introduces the determination of the duration of the high level on the flag pin, effectively avoiding misjudgments caused by transient interference or brief state changes. This significantly improves the accuracy and robustness of CPLD firmware upgrade status monitoring, ensuring that the system only takes appropriate action, such as sending a notification message to the user or retrying, when the CPLD firmware upgrade is indeed in an incomplete state for an extended period. This not only reduces unnecessary system resource consumption and user intervention but also enhances the reliability and user experience of the entire firmware upgrade process.

[0077] In an optional embodiment, this application further proposes that the BMC and the control module are connected via an integrated circuit bus, and the control module is an integrated circuit bus to general purpose input / output port expansion chip.

[0078] Specifically, the Integrated Circuit Bus (I2C) is a serial communication interface used for inter-chip communication. By using an I2C connection, data transmission and control command sending between the BMC and the control module can be accomplished with only a few signal lines. This connection method significantly reduces the number of physical pins required, reduces the complexity of hardware routing, and provides greater flexibility and scalability for system design.

[0079] An integrated circuit bus-to-general-purpose input / output (GPIO) expansion chip is an integrated circuit specifically designed to expand the general-purpose input / output (GPIO) capabilities of a microcontroller (such as a BMC). This chip communicates with the host controller (BMC) via the integrated circuit bus (I2C), receives commands from the host controller, and translates these commands into controls for its own GPIO pins, thereby enabling the driving or status reading of external devices. For example, the BMC can send instructions to this expansion chip via the I2C bus to make a specific GPIO pin output a high or low level, thus controlling the control terminal of a channel switching module.

[0080] The above technical solution connects the BMC and the control module via an integrated circuit bus, and uses an integrated circuit bus to general-purpose input / output port expansion chip as the control module. This effectively solves the problems of high GPIO resource consumption, complex wiring, and poor scalability that may result from the BMC directly controlling the channel switching module.

[0081] In an optional embodiment, this application further proposes that the channel switching module includes a plurality of four-channel two-to-one bus switches, each four-channel two-to-one bus switch including a first input terminal of four channels, a second input terminal of four channels, and an output terminal of four channels.

[0082] Specifically, a four-channel 2-to-1 bus switch is an integrated circuit designed to select between two sets of four-channel input signals and route the selected four-channel signal to the corresponding four-channel output. This switch can simultaneously handle four independent signal switching paths; for example, it can simultaneously switch four reset signals or reset-related control signals. Using multiple four-channel 2-to-1 bus switches means that the channel switching module has the ability to handle more signal channels or implement more complex signal routing logic. The specific number of four-channel 2-to-1 bus switches can be selected based on the RST signal of different BMC models, ensuring that the RST signal of all BMCs is controlled by the channel switching module.

[0083] The first and second input terminals of the four-channel circuit represent two sets of four selectable input signals, while the output terminals of the four-channel circuit output four signals from the selected input signal sets. This design allows each switch to function as an independent unit, efficiently managing the switching of four related signals. For example, in a reset control scenario, the CPLD's reset pin, reset status indicator pin, or other related control pins can be switched simultaneously, ensuring that these signals remain synchronized and consistent during switching.

[0084] By employing multiple four-channel 2-to-1 bus switches to construct the channel switching module, this application effectively overcomes the limitations of single or simple switches in handling multiple reset signals or complex reset control scenarios. Specifically, when the CPLD needs to control the BMC's reset pin and other related control or status pins, or when multiple CPLDs in the system need to perform independent or coordinated reset control, multiple four-channel 2-to-1 bus switches can provide sufficient channel capacity and flexible switching capabilities. Each four-channel 2-to-1 bus switch can synchronously switch four signals, thereby ensuring that during CPLD firmware upgrades, the connection between the BMC's reset pin and the pull-up power supply circuit, as well as the subsequent connection to the CPLD's reset control pin, can be stable, reliable, and synchronous, avoiding system instability or upgrade failure due to signal asynchrony.

[0085] In an optional embodiment, this application further proposes specific steps in step S202 of writing the firmware upgrade package into the storage unit of the CPLD, including: determining the integrated circuit bus address of the CPLD; erasing the data in the storage unit of the CPLD based on the integrated circuit bus address; and writing the firmware upgrade package into the storage unit of the CPLD based on the integrated circuit bus address.

[0086] Specifically, before communicating with the CPLD, the Baseboard Management Controller (BMC) needs to obtain the CPLD's integrated circuit bus address. This address can be a fixed address preset during the CPLD's design or manufacturing, or an address dynamically assigned during system startup via hardware configuration pins or software protocols. The BMC obtains the CPLD's current address by querying preset values, scanning the bus, or reading configuration registers to ensure it can accurately locate and communicate with the target CPLD.

[0087] When erasing data in the CPLD's memory cells based on the integrated circuit bus address, the BMC sends a specific erase command to the CPLD via the integrated circuit bus. This command triggers the CPLD's internal erase mechanism to clear a specified memory area, such as the entire firmware memory area or a specific sector. This operation aims to remove existing firmware data or any residual data from the CPLD's memory cells, making room for new firmware upgrade packages and ensuring the integrity of the new firmware, preventing data mixing between old and new firmware, and avoiding potential compatibility issues or functional abnormalities. For large-capacity memory cells, the erase operation can be performed in blocks or sectors; the BMC needs to send the corresponding block erase command according to the CPLD's memory structure. During the erase process, the BMC can monitor the CPLD's status pins or read the status register to confirm whether the erase operation has been successfully completed.

[0088] Subsequently, when writing the firmware upgrade package to the CPLD's storage unit based on the integrated circuit bus address, the BMC decomposes the acquired firmware upgrade package into multiple data segments and sends them to the CPLD segment by segment via the integrated circuit bus. Before each transmission, the BMC specifies the starting address and data length for writing. When receiving the firmware upgrade package, the CPLD typically enters a special programming mode, in which its storage unit can be written to by external devices. To ensure the accuracy of data transmission, a data verification mechanism, such as Cyclic Redundancy Check (CRC), can be introduced during the writing process. After sending each data segment, the BMC can read the CPLD's verification result. After receiving and writing each data segment, the CPLD can also send an acknowledgment signal to the BMC, indicating that the data segment has been successfully written.

[0089] The above technical solutions ensure the integrity and correctness of the firmware upgrade package, significantly improve the reliability and success rate of CPLD firmware upgrades, and guarantee that the CPLD can successfully complete the firmware upgrade based on the firmware upgrade package in the storage unit after receiving the first firmware update command, thereby maintaining the stable operation of the entire system during the firmware upgrade.

[0090] This application also proposes a firmware upgrade device applied to a baseboard management controller (BMC). The BMC is connected to a complex programmable logic device (CPLD) and a control module. The control module is connected to the control terminal of a channel switching module. The first input terminal of the channel switching module is connected to the reset pin of the BMC, the second input terminal is connected to a pull-up power supply circuit, and the output terminal is connected to the reset control pin of the CPLD. Figure 6 As shown, the device includes: Module 61 is used to obtain the firmware upgrade package for the CPLD; The writing module 62 is used to write the firmware upgrade package into the storage unit of the CPLD. After the firmware upgrade package is written, the first input terminal and the output terminal of the control channel switching module are disconnected and the second input terminal and the output terminal are connected based on the control module, so that the reset pin of the BMC is connected to the pull-up power supply circuit, and the BMC maintains normal operation during the CPLD firmware upgrade. Sending module 63 is used to send a first firmware update instruction to the CPLD so that the CPLD can complete the firmware upgrade process based on the first firmware update instruction and the firmware upgrade package in the storage unit. Monitoring module 64 is used to monitor the firmware upgrade status information of the CPLD; The switching module 65 is used to control the channel switching module based on firmware upgrade status information and the control module. The second input terminal and the output terminal of the control channel switching module are disconnected, and the first input terminal and the output terminal are connected, so that the reset pin of the BMC is connected to the reset control pin of the CPLD.

[0091] The firmware upgrade device in this embodiment adds a hardware control module, a channel switching module, and a pull-up power supply circuit to the electronic device. During CPLD firmware upgrades, the control module controls the channel switching module to temporarily switch the BMC's reset pin to the pull-up power supply circuit, ensuring that the BMC can continue to operate normally even when the new CPLD firmware is unstable. Therefore, even if the new CPLD firmware fails to operate normally, the BMC can continue to update the CPLD firmware or troubleshoot the fault, avoiding the BMC deadlock caused by CPLD failure in traditional solutions, which necessitates complex and inefficient offline programmers for flashing. This significantly improves the convenience of server maintenance and the stability of the system.

[0092] In some embodiments, the writing module is used to write a first target value to the first target register of the control module so that the pin state of the control module connected to the channel switching module is the output state; and to write a second target value to the second target register of the control module so that the control module inputs a first signal to the control terminal of the channel switching module based on the second target value so that the first input terminal and the output terminal of the channel switching module are disconnected and the second input terminal and the output terminal are connected.

[0093] In some embodiments, the switching module is configured to, if the firmware upgrade status information indicates that the CPLD firmware upgrade is complete, disconnect the second input terminal and output terminal of the control channel switching module based on the control module, and connect the first input terminal and output terminal, so that the BMC reset pin is connected to the CPLD reset control pin; if the firmware upgrade status information indicates that the CPLD firmware upgrade is not complete, send a notification message to the user; and when a new firmware upgrade package for the CPLD is obtained from the user based on the notification message, write the new firmware upgrade package into the CPLD's storage unit; and send a second firmware update instruction to the CPLD so that the CPLD can re-upgrade the firmware based on the second firmware update instruction and the new firmware upgrade package in the storage unit.

[0094] In some embodiments, the switching module is used to write a third target value to the second target register of the control module, so that the control module inputs a second signal to the control terminal of the channel switching module based on the third target value, so that the second input terminal and the output terminal of the channel switching module are disconnected, and the first input terminal and the output terminal are connected.

[0095] In some embodiments, the monitoring module is used to monitor the level state of the flag bit pin of the CPLD; if the level state of the flag bit pin is high, the status information that the firmware upgrade of the CPLD is not completed is obtained; if the level state of the flag bit pin is low, the status information that the firmware upgrade of the CPLD is completed is obtained.

[0096] In some embodiments, the monitoring module is used to obtain the status information that the firmware upgrade of the CPLD is not completed if the level state of the flag bit pin is high and the duration of the high level exceeds a duration threshold.

[0097] In some embodiments, the BMC is connected to the control module via an integrated circuit bus, and the control module is an integrated circuit bus to general purpose input / output port expansion chip.

[0098] In some embodiments, the channel switching module includes a plurality of four-channel two-to-one bus switches, each four-channel two-to-one bus switch including a first input terminal with four channels, a second input terminal with four channels, and an output terminal with four channels.

[0099] In some embodiments, the writing module is used to determine the integrated circuit bus address of the CPLD; erase the data in the storage cell of the CPLD based on the integrated circuit bus address; and write the firmware upgrade package into the storage cell of the CPLD based on the integrated circuit bus address.

[0100] This application also proposes an electronic device, such as Figure 1 As shown, it includes: Baseboard Management Controller (BMC), Complex Programmable Logic Device (CPLD), Control Module, Channel Switching Module, and Pull-up Power Supply Circuit (P3V3 STBY). The BMC is connected to the CPLD and the control module respectively. The control module is connected to the control terminal (S) of the channel switching module. The first input terminal of the channel switching module is connected to the reset control pin (RST MODULE) of the CPLD, the second input terminal is connected to the pull-up power supply circuit, and the output terminal is connected to the reset pin (RST) of the BMC. BMC is used to perform the firmware upgrade method described in the above embodiments.

[0101] Specifically, the control module in this electronic device is an integrated circuit bus-to-general-purpose input / output port expansion chip, used to receive control commands from the BMC and convert them into drive signals for the channel switching module. The channel switching module includes multiple four-channel 2-to-1 bus switches. The first input terminal of each switch is connected to the reset control pin of the CPLD, the second input terminal is connected to the pull-up power supply circuit, and the output terminal is connected to the reset pin of the BMC. During the initial power-on phase, the control terminal of the channel switching module is configured to low level by default, so that the reset control pin of the CPLD is directly connected to the reset pin of the BMC, ensuring that the CPLD can control the BMC to complete the power-on reset process in sequence. When the BMC receives the CPLD firmware upgrade package, it writes the firmware into the CPLD's storage unit through the integrated circuit bus. After the writing is completed, it writes the second target value into the second target register of the control module, causing the control terminal of the channel switching module to switch to high level, thereby disconnecting the connection between the CPLD and the BMC reset pin, while connecting the pull-up power supply circuit and the BMC reset pin. Since the pull-up power supply circuit provides a stable high-level voltage, the BMC reset pin remains high during this period, ensuring that the BMC continues to work normally. Subsequently, the BMC sends a firmware update command to the CPLD, triggering the CPLD to load the new firmware from the storage unit and perform the upgrade operation. During this process, the BMC obtains firmware upgrade status information in real time by monitoring the flag pin level of the CPLD: if the flag is low, it indicates that the upgrade is complete, and the BMC immediately controls the channel switching module to restore the CPLD's control over the reset pin; if the flag remains high for more than a certain duration threshold, the upgrade is determined to have failed, and the BMC displays an error message through the user interface and supports re-uploading the firmware upgrade package to avoid the system falling into a deadlock state.

[0102] Through the above technical solution, this electronic device establishes an independent reset control switching mechanism at the hardware level, effectively decoupling the strong dependency between the BMC and CPLD during the upgrade process. Compared to traditional solutions that rely on a CPLD backup area or additional CPLD hardware, this embodiment only requires the addition of low-cost external circuitry to achieve fault-tolerant control during the upgrade process, significantly reducing maintenance complexity in high-density AI server integration scenarios. Especially in space-constrained environments such as GPU computing nodes, it eliminates the need for disassembly and offline flashing using a programmer, greatly improving system reliability and operational efficiency, and providing solid technical support for the intelligent management of large-scale data centers.

[0103] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the firmware upgrade method described above in this application.

[0104] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are executed by a processor, causing the processor to execute the firmware upgrade method provided in this application.

[0105] In some embodiments, a computer-readable storage medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may be a machine-readable signal medium or a machine-readable storage medium. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of computer-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Claims

1. A firmware upgrade method, characterized in that, The method is applied to a baseboard management controller (BMC), wherein the BMC is connected to a complex programmable logic device (CPLD) and a control module, the control module is connected to the control terminal of a channel switching module, the first input terminal of the channel switching module is connected to the reset control pin of the CPLD, the second input terminal is connected to a pull-up power supply circuit, and the output terminal is connected to the reset pin of the BMC; the method includes: Obtain the firmware upgrade package for the CPLD; The firmware upgrade package is written into the storage unit of the CPLD. After the firmware upgrade package is written, the first input terminal and the output terminal of the channel switching module are disconnected and the second input terminal and the output terminal are connected based on the control module, so that the reset pin of the BMC is connected to the pull-up power supply circuit. The BMC maintains normal operation during the CPLD firmware upgrade. Send a first firmware update command to the CPLD so that the CPLD completes the firmware upgrade process based on the first firmware update command and the firmware upgrade package in the storage unit; Monitor the firmware upgrade status information of the CPLD; Based on the firmware upgrade status information and the control module, the second input terminal and the output terminal of the channel switching module are disconnected, and the first input terminal and the output terminal are connected, so that the reset pin of the BMC is connected to the reset control pin of the CPLD.

2. The firmware upgrade method according to claim 1, characterized in that, Based on the control module controlling the first input terminal and output terminal of the channel switching module to be disconnected and the second input terminal and output terminal to be connected, the following is included: Write a first target value into the first target register of the control module so that the pin state of the control module connected to the channel switching module is the output state; Write a second target value to the second target register of the control module, so that the control module inputs a first signal to the control terminal of the channel switching module based on the second target value, so that the first input terminal and the output terminal of the channel switching module are disconnected, and the second input terminal and the output terminal are connected.

3. The firmware upgrade method according to claim 1, characterized in that, Based on the firmware upgrade status information and the control module, the second input terminal and output terminal of the channel switching module are disconnected, while the first input terminal and output terminal are connected, including: If the firmware upgrade status information indicates that the firmware upgrade of the CPLD is complete, based on the control module, the second input terminal and the output terminal of the channel switching module are disconnected, and the first input terminal and the output terminal are connected, so that the reset pin of the BMC is connected to the reset control pin of the CPLD. If the firmware upgrade status information indicates that the firmware upgrade of the CPLD is not complete, a notification message is sent to the user; and when a new firmware upgrade package for the CPLD is obtained from the user based on the notification message, the new firmware upgrade package is written into the storage unit of the CPLD; a second firmware update instruction is sent to the CPLD so that the CPLD can re-upgrade the firmware based on the second firmware update instruction and the new firmware upgrade package in the storage unit.

4. The firmware upgrade method according to claim 3, characterized in that, Based on the control module, controlling the second input terminal and output terminal of the channel switching module to disconnect, and the first input terminal and output terminal to connect, includes: A third target value is written to the second target register of the control module, so that the control module inputs a second signal to the control terminal of the channel switching module based on the third target value, so that the second input terminal and the output terminal of the channel switching module are disconnected, and the first input terminal and the output terminal are connected.

5. The firmware upgrade method according to claim 1, characterized in that, Monitoring the firmware upgrade status information of the CPLD includes: Monitor the level state of the flag pin of the CPLD; If the level of the flag pin is high, the firmware upgrade status information of the CPLD is obtained. If the level of the flag pin is low, the firmware upgrade status information of the CPLD is obtained.

6. The firmware upgrade method according to claim 5, characterized in that, If the level of the flag pin is high and the duration of the high level exceeds the duration threshold, the firmware upgrade status information of the CPLD is obtained.

7. The firmware upgrade method according to claim 1, characterized in that, The BMC and the control module are connected via an integrated circuit bus, and the control module is an integrated circuit bus to general-purpose input / output port expansion chip.

8. The firmware upgrade method according to claim 1, characterized in that, The channel switching module includes multiple four-channel two-to-one bus switches, each of which includes a first input terminal for four channels, a second input terminal for four channels, and an output terminal for four channels.

9. The firmware upgrade method according to claim 1, characterized in that, Writing the firmware upgrade package into the storage unit of the CPLD includes: Determine the integrated circuit bus address of the CPLD; Based on the integrated circuit bus address, erase the data in the memory cell of the CPLD; Based on the integrated circuit bus address, the firmware upgrade package is written into the storage unit of the CPLD.

10. A firmware upgrade device, characterized in that, An application is provided in a baseboard management controller (BMC), wherein the BMC is connected to a complex programmable logic device (CPLD) and a control module. The control module is connected to the control terminal of a channel switching module. The first input terminal of the channel switching module is connected to the reset control pin of the CPLD, the second input terminal is connected to a pull-up power supply circuit, and the output terminal is connected to the reset pin of the BMC. The device includes: The acquisition module is used to acquire the firmware upgrade package of the CPLD; The writing module is used to write the firmware upgrade package into the storage unit of the CPLD. After the firmware upgrade package is written, the control module controls the first input terminal and the output terminal of the channel switching module to be disconnected and the second input terminal and the output terminal to be connected, so that the reset pin of the BMC is connected to the pull-up power supply circuit. The BMC maintains normal operation during the CPLD firmware upgrade. The sending module is used to send a first firmware update instruction to the CPLD, so that the CPLD can complete the firmware upgrade process based on the first firmware update instruction and the firmware upgrade package in the storage unit. The monitoring module is used to monitor the firmware upgrade status information of the CPLD; The switching module is used to control the second input terminal and the output terminal of the channel switching module to disconnect and the first input terminal and the output terminal to connect, based on the firmware upgrade status information and the control module, so that the reset pin of the BMC is connected to the reset control pin of the CPLD.

11. An electronic device, characterized in that, include: The circuit connects the Baseboard Management Controller (BMC), the Complex Programmable Logic Device (CPLD), the control module, the channel switching module, and the pull-up power supply circuit. The BMC is connected to the CPLD and the control module respectively. The control module is connected to the control terminal of the channel switching module. The first input terminal of the channel switching module is connected to the reset control pin of the CPLD, the second input terminal is connected to the pull-up power supply circuit, and the output terminal is connected to the reset pin of the BMC. The BMC is used to perform the firmware upgrade method as described in any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the firmware upgrade method as described in any one of claims 1-9.

13. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, they implement the firmware upgrade method according to any one of claims 1 to 9.

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