A method for defining an instruction set of a parallel processor, a parallel processing module and an electronic device

Abstract

The application discloses a kind of instruction set definition method for parallel processor, parallel processing module and electronic equipment, belong to integrated circuit technical field.The instruction set includes 8 kinds of fixed 32 bit instructions.SET, JMP, LDR and STR instruction adopt unified register bit mapping relationship to multiplex hardware decoding logic;IO instruction completes the parallel data transmission of specified number of channels in single instruction, the control of two additional IO level with side control and FIFO / DMA automatic interaction;WAIT instruction supports signal waiting with polarity and period delay;LDM / STM adopts immediate address left shift alignment addressing, and LDR / STR adopts register base address plus signed offset addressing.The application realizes the period level accurate multi-channel IO control, flexible task scheduling and memory access with very simple instruction set, significantly reduces hardware decoding overhead and instruction storage space, and is suitable for high real-time, low-power parallel processing scene.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an instruction set definition method, a parallel processing module, and an electronic device for a parallel processor. Background Technology

[0002] With the explosive growth of the Internet of Things (IoT), smart sensors, and wearable devices, embedded chips need to simultaneously handle multiple real-time data acquisitions, high-speed protocol communication, and precise timing control, while being extremely sensitive to response latency and power consumption. Traditional single-core CPUs, using polling or interrupt methods, struggle to balance the parallelism of multitasking with periodic determinism, while adding dedicated hardware logic leads to insufficient flexibility and extended development cycles. Therefore, achieving high real-time performance and programmable parallel control within the chip with low hardware overhead has become an important research direction in the field of embedded design.

[0003] In existing technologies, common solutions involve using multi-core processors with general-purpose I / O and timer peripherals, and implementing task switching through software scheduling; or integrating programmable state machines (such as CPLD / FPGA small logic units) within the chip to solidify specific timing sequences. While some high-end MCUs offer custom instruction extensions, the instruction sets often consist of dozens of different types with independently defined fields, resulting in large hardware decoder areas and high power consumption. When handling batch operations of multi-channel I / O, existing instructions often require multiple instructions to complete the "condition judgment—data transfer—level toggle—delay wait" step by step. This not only results in low code density but also makes it difficult to complete the parallel acquisition and output of multi-channel data within a single cycle, failing to meet the microsecond-level precise synchronization requirements of industrial / sensing applications. Summary of the Invention

[0004] The technical problems to be solved by the present invention are: the large number of instruction sets in existing parallel control schemes, which leads to large hardware decoding overhead; the need for multiple instructions to be executed step by step for multi-channel IO operations, which makes it difficult to meet periodic-level synchronization; and the low hardware reusability caused by the inconsistency between the encoding of general-purpose registers and immediate digital segments.

[0005] To address the aforementioned technical problems, one aspect of the present invention provides an instruction set definition method for a parallel processor, wherein the instruction set includes eight instructions, each instruction being fixed at 32 bits, and the eight instructions include:

[0006] The assignment instruction SET is used to perform the operation between the source operand and the immediate value specified by the SET instruction, and then write the result to the destination operand of the SET instruction.

[0007] The WAIT instruction is used to wait for the specified signal of the WAIT instruction to meet the polarity condition of the WAIT instruction, and then delay for the number of cycles specified by the WAIT instruction.

[0008] The jump instruction JMP is used to jump to the target address specified by the JMP instruction after a delay of the number of cycles specified by the JMP instruction if the two operands of the JMP instruction meet the comparison conditions specified by the JMP instruction; otherwise, execution proceeds sequentially.

[0009] Multi-channel I / O read / write instructions (IO) are used to perform input and output operations on a specified number of I / O channels when the hardware execution conditions are met, and to delay for a specified number of cycles after the input and output operations are completed.

[0010] The Read Immediate Address instruction (LDM) is used to read data from the bus address recorded in the address field of the LDM instruction and store it into the general-purpose register specified by the LDM instruction.

[0011] The Write Immediate Address (STM) instruction is used to write the data of the general-purpose register specified by the STM instruction to the bus address recorded in the address field of the STM instruction.

[0012] The Read Register Address (LDR) instruction is used to read data from the bus address specified in the LDR instruction and store it in the second general-purpose register specified in the LDR instruction, using the value of the first general-purpose register specified in the LDR instruction plus the offset specified in the LDR instruction as the bus address.

[0013] The write register address instruction STR is used to write the data of the second general-purpose register specified in the STR instruction to the bus address, which is the value of the first general-purpose register specified in the STR instruction plus the offset specified in the STR instruction.

[0014] Another aspect of the present invention provides a parallel processing module comprising multiple processing cores, each processing core independently executing the instruction sequence defined by the instruction set definition method.

[0015] Another aspect of the present invention provides an electronic device including the parallel processing module.

[0016] The present invention has at least the following beneficial effects

[0017] This invention significantly reduces hardware decoder complexity and circuit area overhead by constructing a simplified instruction set containing only 8 instructions, each fixed at 32 bits. Combined with the unified bit mapping relationship of general-purpose registers in the SET, JMP, LDR, and STR instructions, it improves instruction execution efficiency. In particular, through multi-channel I / O read / write instructions that simultaneously complete parallel data transmission of a specified number of I / O channels within a single instruction, level-following control of two additional I / Os, built-in FIFO / DMA automatic interaction, and programmable cycle delay, batch I / O operations that originally required multiple instructions can be completed within a single cycle or a controllable delay, thus ensuring deterministic microsecond-level cycle synchronization. Simultaneously, the polarity judgment and delay combination mechanism of the WAIT instruction enables the processing core to accurately synchronize external signal changes at a single-cycle granularity. The immediate address left-shift alignment of LDM / STM and the signed offset addressing mode of LDR / STR optimize the access density of the bus and on-chip peripherals, respectively. Therefore, the parallel processing module based on this instruction set can achieve high-precision custom interface protocols, multi-core parallel task scheduling, and low-latency sensor data preprocessing with minimal instruction storage space and hardware resource overhead, effectively balancing the engineering requirements of flexible programmability and low hardware cost and low power consumption. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall architecture of the present invention;

[0019] Figure 2 This is an example of the instruction encoding for the SET, JMP, LDR, and STR instructions provided by this invention;

[0020] Figure 3 This is an example of the instruction encoding for the WAIT instruction provided by the present invention;

[0021] Figure 4 This is an example of instruction encoding for the I / O instructions provided by the present invention;

[0022] Figure 5 This is an example of instruction encoding for LDM and STM instructions provided by the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In one embodiment of the present invention, application code for parallel control tasks is written in C or assembly language. After being processed by a compiler or assembler, this code generates corresponding 32-bit binary instruction sequences according to the eight instruction formats defined in the present invention. These binary instruction sequences are loaded into the instruction tightly coupled memory (TCM) of each processing core in the parallel processing module via a debug interface or direct memory access (DMA).

[0025] During instruction execution, each processing core independently reads a 32-bit instruction from its respective TCM at the address indicated by the program counter (PC). The instruction decoder of each processing core identifies the instruction type based on the high-order opcode field—for example, opcode 0011 indicates a SET instruction, 0000 indicates a WAIT instruction, 0010 indicates a JMP instruction, and 0100 indicates an I / O instruction—and routes each field in the instruction (such as Rn, Rd, Imm16, Cond, Dly, etc.) to the corresponding execution unit. The execution unit performs operations such as register file reads, arithmetic and logical operations, comparisons, I / O port reads and writes, or bus accesses based on the field configuration, and writes the results back to general-purpose registers, I / O channels, FIFOs, or memory addresses. The instruction fetching, decoding, and execution of each processing core are independent of each other, enabling true parallel processing of multiple tasks.

[0026] In practical applications, this parallel processing module is particularly suitable for the following scenarios: industrial automation control requires periodic acquisition and preprocessing of data from multiple sensors, and precise real-time response to actuators at the microsecond level; IoT terminal devices require simultaneous processing of data streams from multiple sensors such as accelerometers and microphone arrays, and completion of encoding and decoding of custom communication protocols; motor drive and control requires precise output of multiple PWM signals and real-time detection of hardware events such as overcurrent and overtemperature; custom interface protocol adaptation requires flexible simulation of standard protocols such as SPI, I2C, and UART and their variant timings; and multi-module collaborative task scheduling requires multiple processing cores to execute independent or collaborative instruction sequences in parallel.

[0027] For this purpose, please refer to Figures 1-5 One aspect of the present invention provides a method for defining an instruction set for a parallel processor, the instruction set comprising eight instructions, each instruction being fixed at 32 bits, the eight instructions including:

[0028] The assignment instruction SET is used to perform the operation between the source operand and the immediate value specified by the SET instruction, and then write the result to the destination operand of the SET instruction.

[0029] Preferably, the assignment operation instruction SET includes: a source operand field (Rn), a 16-bit immediate operand field (Imm16), an operator field (Op), and a destination operand field (Rd).

[0030] The SET instruction is used to perform an operation between the source operand indicated by the source operand field (Rn) and the immediate number indicated by the 16-bit immediate operand field (Imm16), as specified by the operator field (Op), and then write the result to the target operand indicated by the target operand field (Rd).

[0031] The source operand indicated by the source operand field (Rn) and the target operand indicated by the target operand field (Rd) are each independently selected from any one of the following: the general-purpose registers of the current processing core, the I / O channels mapped by the current processing core, the built-in FIFO of the current processing core, the hardware event flags of each module of the chip, and the hardware execution conditions.

[0032] like Figure 2 As shown, the 32-bit encoding of the SET instruction, from high to low bits, consists of: a 4-bit opcode field (fixed to 0011), a 4-bit operator field Op, a 4-bit destination operand field Rd, a 4-bit source operand field Rn, and a 16-bit immediate numeric field Imm16, i.e.:

[0033]

[0034] The 4-bit opcode field is fixed at 0011 and is used to identify the current instruction as a SET instruction during the instruction decoding stage. The 4-bit source operand field Rn is used to indicate the source operands involved in the operation. The 16 encoded values ​​of Rn each correspond to a data source type, including but not limited to: the general-purpose registers of the current processing core (e.g., R0~R7, each general-purpose register can be configured with a 16-bit or 32-bit width), the IO channels mapped by the current processing core (e.g., IO0~IO3, 16-bit width), the built-in FIFO status of the current processing core (16-bit width), the hardware event flags output by each module of the chip (e.g., timer overflow flag, DMA transfer completion flag, analog comparator output flag, etc., 32-bit width), and the hardware execution conditions (32-bit width) generated by logical combination of the aforementioned hardware event flags.

[0035] The 4-bit target operand field Rd is used to indicate the write target of the operation result. The 16 possible values ​​of Rd are mapped exactly to the encoding of Rn, meaning Rd can independently select a general-purpose register, I / O channel, built-in FIFO, hardware event flag, or hardware execution condition as the write target. When Rd points to an I / O channel, the SET instruction directly outputs the operation result to the corresponding I / O pin; when Rd points to a hardware event flag or hardware execution condition, the SET instruction writes the operation result to the corresponding status register or condition register for use by subsequent I / O instructions or WAIT instructions.

[0036] The 4-bit operator field Op is used to specify the type of operation between the source operand and the 16-bit immediate value. Each of the 16 encoded values ​​of Op corresponds to an operation, including but not limited to: bitwise AND, bitwise OR, bitwise XOR, logical left shift (SHL), logical right shift (SHR), arithmetic right shift (SAR), signed addition (ADD), signed subtraction (SUB), bit swap (BITREV), negation (NOT), and pass-through (MOV, i.e., the source operand is directly transferred to the target operand without any operation).

[0037] The 16-bit immediate field Imm16 is used to provide the 16-bit immediate value to be used in the operation. The value of Imm16 ranges from 0x0000 to 0xFFFF. During the execution of the SET instruction, the Imm16 field is directly sent to the arithmetic unit as a 16-bit input.

[0038] The SET instruction has a 32-bit operation width. After the decoder of the processing core recognizes the opcode 0011, it first reads the source operand from the specified data source according to the Rn field: if the source operand is 32 bits wide (such as a 32-bit general-purpose register, hardware event flag, or hardware execution condition), it is directly sent to the 32-bit arithmetic unit; if the source operand is 16 bits wide (such as a 16-bit general-purpose register, I / O channel, or built-in FIFO), the bit width is extended according to the type of the operator Op before being sent to the 32-bit arithmetic unit—for unsigned operations (such as AND, OR, XOR, SHL, SHR, MOV, etc.), the high-order bits are padded with zeros to achieve zero extension; for signed operations (such as ADD, SUB, SAR, etc.), the highest bit (bit 15) of the 16-bit source operand is extended to the high 16 bits as the sign bit to achieve signed extension. At the same time, the 16-bit immediate value of the Imm16 field is directly sent to the arithmetic unit as another 16-bit input without any extension. The arithmetic logic unit (ALU) executes the operation specified by Op with a width of 32 bits, obtaining a 32-bit result. Finally, the 32-bit result is written to the target operand based on the Rd field: if the target operand is 32 bits wide (such as a 32-bit general-purpose register, hardware event flag, or hardware execution condition), the complete 32-bit result is written; if the target operand is 16 bits wide (such as a 16-bit general-purpose register, I / O channel, or built-in FIFO), only the lower 16 bits of the 32-bit result (i.e., result[15:0]) are written to the target, and the higher 16 bits are automatically discarded. All of the above data fetching, expansion, arithmetic, and write-back operations are completed within a single processing core clock cycle, achieving single-cycle execution of the SET instruction.

[0039] In one application example, the chip's hardware event flag register aggregates the hardware event status of various modules. Bit 0 is the timer overflow flag (1 when overflowing), bit 1 is the DMA transfer completion flag (1 when complete), and bit 2 is the analog comparator output flag (1 when outputting a high level), etc. The user needs to use timer overflow and DMA transfer completion as trigger conditions for subsequent I / O instructions. At this point, the user executes a SET instruction: setting the Rn field to the hardware event flag register (encoded 1101), setting the Imm16 field to 0x0003 (binary...0011), setting the Op field to bitwise AND, and setting the Rd field to the hardware execution condition register (encoded 1110). During execution, the processing core reads the current 32-bit status value from the hardware event flag register, performs a bitwise AND operation with the mask 0x0003 provided by Imm16, and writes the result to the hardware execution condition register. The result is non-zero if and only if both bit 0 and bit 1 are 1, and the hardware execution condition is met. Subsequent I / O instructions, by setting the condition enable field to a valid state, will execute multi-channel I / O input and output operations only when the hardware execution condition is true. In this way, I / O instructions can be synchronously triggered by the combined results of multiple hardware events without software polling, ensuring periodic-level deterministic response.

[0040] The WAIT instruction is used to wait for the specified signal of the WAIT instruction to meet the polarity condition of the WAIT instruction, and then delay for the number of cycles specified by the WAIT instruction.

[0041] Preferably, the WAIT instruction includes: a data source field (Src), a polarity field (Pol), a delay field (Dly), and a reserved field (rsvd).

[0042] The WAIT instruction is used to determine whether the current signal indicated by the data source field (Src) is equal to the value specified by the polarity field (Pol). If so, the waiting ends after a delay of the number of cycles specified by the delay field (Dly). Otherwise, the instruction waits for the next execution cycle to repeat the determination.

[0043] The current signal indicated by the data source field (Src) is selected from any one of the following: the chip's IO input level, the current processing core's built-in FIFO state, the hardware event flags of each module of the chip, and the hardware execution conditions.

[0044] like Figure 3 The image shows an example of the instruction encoding for the WAIT instruction provided by this invention. The 32-bit encoding of the WAIT instruction, from high to low bits, consists of: a 4-bit opcode field (fixed at 0000), a 3-bit reserved field rsvd, a 1-bit polarity field Pol, an 8-bit data source field Src, and a 16-bit delay field Dly; that is:

[0045]

[0046] The 4-bit opcode field is fixed at 0000 and is used to identify the current instruction as a WAIT instruction during the instruction decoding stage; the 3-bit reserved field rsvd is reserved for future expansion and its value does not affect the instruction execution result, and is usually fixed at 0.

[0047] The 1-bit polarity field Pol is used to specify the target polarity of the wait condition. When Pol=0, the WAIT instruction waits for the specified signal to be logic low (i.e., the signal value is 0); when Pol=1, the WAIT instruction waits for the specified signal to be logic high (i.e., the signal value is 1).

[0048] The 8-bit data source field Src is used to indicate the current signal source that needs to be monitored. Each of the 256 encoded values ​​of Src corresponds to a signal source type, including but not limited to: the chip's IO input level (such as GPIO pin level), the current processing core's built-in FIFO status (such as FIFO full flag, FIFO empty flag, FIFO data valid flag, etc.), the hardware event flags output by each module of the chip (such as timer overflow flag, DMA transfer complete flag, analog comparator output flag, etc.), and the hardware execution conditions pre-generated by the SET instruction through logical combination of the hardware event flags of each module of the chip.

[0049] The 16-bit delay field Dly specifies the number of delay cycles after the waiting condition is met. The value of Dly ranges from 0x0000 to 0xFFFF, representing a delay of 0 to 65535 processing core clock cycles. When Dly=0, there is no delay after the condition is met; the waiting ends immediately and the next instruction is executed sequentially.

[0050] The execution logic of the WAIT instruction is as follows: After the decoder of the processing core recognizes the opcode 0000, in each clock cycle, it first reads the current signal value (a single-bit logic value of 0 or 1) from the specified signal source according to the Src field, and then compares this value with the target polarity specified by the Pol field. If the current signal value is not equal to the value specified by Pol (i.e., the condition is not met), the processing core pauses pipeline execution, waits for the next clock cycle to reread the signal source and compare again; if the current signal value is equal to the value specified by Pol (i.e., the condition is met), the processing core further judges the value of the Dly field—if Dly=0, the wait ends immediately and the next instruction is executed sequentially; if Dly>0, the processing core remains in a waiting state, ends the wait after the number of cycles specified by Dly has expired, and the next instruction is executed sequentially. It should be noted that the "delay" refers to the extra idle cycle inserted after the waiting condition is met and before the wait ends, which is independent of the number of cycles that continue to wait due to the condition not being met during the waiting process. Throughout the waiting process, the processing core pauses the fetching and execution of subsequent instructions, but continues to monitor the signal source status in each cycle.

[0051] like Figure 3 As shown, the opcode field 0000 in the WAIT instruction encoding is different from the opcodes 0011, 0010, and 0100 of the SET, JMP, and IO instructions, ensuring that the decoder can accurately distinguish between each instruction type. Although the Src field of the WAIT instruction and the Rn field of the SET instruction have different encoding values ​​(8 bits and 4 bits respectively), they maintain a consistent mapping logic in the definition of signal source types. For example, the hardware event flag is selected by the encoding 1101 of Rn in the SET instruction, and by the encoding range 0x10~0x1F of Src in the WAIT instruction. Their physical meanings are the same, making it easy for users to understand and use.

[0052] The jump instruction JMP is used to jump to the target address specified by the JMP instruction after a delay of the number of cycles specified by the JMP instruction if the two operands of the JMP instruction meet the comparison conditions specified by the JMP instruction; otherwise, execution proceeds sequentially.

[0053] Preferably, the jump instruction JMP includes: a first operand field (Rn), a second operand field (Rm), a condition field (Cond), a delay field (Dly), and an address field (Tgt);

[0054] The JMP instruction is used to determine whether the first operand indicated by the first operand field (Rn) and the second operand indicated by the second operand field (Rm) satisfy the comparison condition specified by the condition field (Cond). If they satisfy the condition, the instruction jumps to the target address specified by the address field (Tgt) after a delay of the number of cycles specified by the delay field (Dly). Otherwise, the next instruction is executed sequentially.

[0055] The first operand indicated by the first operand field (Rn) and the second operand indicated by the second operand field (Rm) are each independently selected from any one of the general-purpose registers of the current processing core, chip hardware status, I / O input level, and hardware event flags.

[0056] like Figure 2 As shown, the 32-bit encoding of the JMP instruction, from high to low bits, consists of: a 4-bit opcode field (fixed to 0010), a 1-bit reserved field rsvd, a 3-bit condition field Cond, a 4-bit second operand field Rm, a 4-bit first operand field Rn, a 6-bit delay field Dly, and a 10-bit address field Tgt; that is:

[0057]

[0058] The 4-bit opcode field is fixed at 0010 and is used to identify the current instruction as a JMP instruction during the instruction decoding stage; the 1-bit reserved field rsvd is reserved for future expansion and its value does not affect the instruction execution result, and is usually fixed at 0; when Tgt is 0x000, it is a reserved code to be used in future expansion.

[0059] The 3-bit condition field Cond specifies the type of comparison condition. Each of the eight encoded values ​​of Cond corresponds to a comparison condition, including but not limited to: equal (EQ), not equal (NE), greater than (GT), less than (LT), greater than or equal to (GE), less than or equal to (LE), and two special decrement comparison conditions—decreasing to zero (DEQ) and decreasing to not equal to zero (DNE). The decrement comparison means that before performing the comparison, the first operand (the value indicated by Rn) is decremented by 1, and then the decremented value is compared with the second operand (the value indicated by Rm). Simultaneously, the decremented value is written back to the source where the first operand resides (if the first operand is a general-purpose register, its value is updated). This decrement comparison mechanism, combined with conditional jumps, can efficiently implement loop control without requiring a separate subtraction instruction.

[0060] The 4-bit first operand field Rn and the 4-bit second operand field Rm are used to indicate the two operands involved in the comparison. The 16 encoded values ​​of Rn and Rm each independently correspond to a data source type, including: the eight general-purpose registers of the current processing core (R0~R7, each configurable to 16-bit or 32-bit width), chip hardware status (such as the current running state of the processing core, bus busy / idle status, low-power mode status, etc.), IO input levels (mapped to the IO pin input status of the current processing core), and hardware event flags (a bitwise combination of hardware event flags output by each module of the chip, which needs to be used in conjunction with an immediate value mask to extract specific values).

[0061] The 6-bit delay field Dly specifies the number of delay cycles after the condition is met. Dly ranges from 0 to 63, representing a delay of 0 to 63 processing core clock cycles. When Dly=0, there is no delay after the condition is met, and the jump is executed immediately.

[0062] The 10-bit address field Tgt is used to indicate the jump target address. The 1024 possible encoded values ​​of Tgt are interpreted into different types of jump targets based on different value ranges:

[0063] When Tgt takes the value 0x001~0x07F (i.e. 1~127), it represents a positive signed relative offset based on the current instruction address, and the jump target address = current instruction address + Tgt value;

[0064] When Tgt takes the value 0x081~0x0FF (i.e. 129~255), it represents a negative signed relative offset based on the current instruction address. The jump target address = current instruction address - (0x100 - Tgt value), that is, the offset range is -127~-1.

[0065] When Tgt takes the value 0x100~0x1FF (i.e. 256~511), it represents the absolute address of the TCM (tightly coupled memory) built into the current processing core. The jump target address is Tgt value shifted left by 2 bits (i.e. 4-byte alignment), and the range is 0x400~0x7FC.

[0066] When Tgt takes the value 0x200~0x3FF (i.e. 512~1023), it represents the bus address stored in general-purpose registers R0~R7. The jump target address = the value of the corresponding general-purpose register. The lower 3 bits of the Tgt value are used to select the general-purpose register number (i.e. R0~R7). At this time, it is possible to jump to any 32-bit address on the bus.

[0067] The execution logic of the JMP instruction is as follows: After the decoder of the processing core recognizes the opcode 0010, it first reads the first operand and the second operand (both 32-bit values) from the specified data source according to the Rn and Rm fields, respectively. Then, it compares the two operands according to the comparison condition specified in the Cond field and generates a comparison result. If the comparison result is false (the condition is not met), the JMP instruction does not execute the jump, the program counter PC increments normally, and the next instruction is executed sequentially. If the comparison result is true (the condition is met), the value of the Dly field is further checked. If Dly=0, the PC is immediately updated to the target address parsed from the Tgt field, and the jump is achieved. If Dly>0, the processing core maintains the current state and waits for Dly cycles before updating the PC, achieving a delayed jump. For cases where Cond is DEQ or DNE, before performing the comparison, the value of the data source indicated by Rn needs to be decremented by 1. The decremented value is then used for the comparison, and simultaneously written back to the data source indicated by Rn (if Rn points to a general-purpose register, the corresponding register value is updated; if Rn points to a non-register type data source, the decremented value is only used for comparison, and no write-back operation is performed). The above-mentioned read operand, comparison judgment, delay wait, and jump operations are all completed within the timing specified by the instruction. Through this mechanism, a single JMP instruction can complete loop counting, condition judgment, and jump operations without additional subtraction and comparison instructions, significantly improving code density and loop execution efficiency. The JMP instruction can perform precise jump control based on the chip hardware state, making it suitable for applications that respond to hardware events in real time. While maintaining a fixed 32-bit encoding length and a 10-bit Tgt field, it can still achieve jumps across the entire address space, balancing the needs for fast short-distance jumps and flexible long-distance jumps.

[0068] Multi-channel I / O read / write instructions (IO) are used to perform input and output operations on a specified number of I / O channels when the hardware execution conditions are met, and to delay for a specified number of cycles after the input and output operations are completed.

[0069] Preferably, the IO instruction includes a quantity field (Cnt), a direction field (Dir), a delay field (Dly), a condition enable field (Cond), a first control IO number field (Vm), a first control IO output value field (Om), a second control IO number field (Vn), and a second control IO output value field (On).

[0070] The IO instructions are used to perform input and output operations on the number of IO channels specified by the quantity field (Cnt) when the hardware execution conditions are met, and to delay for the number of cycles specified by the delay field (Dly) after the input and output operations are completed;

[0071] The condition enable field (Cond) is used to control the checking of the hardware execution conditions: when the value of the condition enable field (Cond) is true, the IO instruction executes the input and output operations only when the hardware execution conditions are met; when the value of the condition enable field (Cond) is false, the IO instruction executes the input and output operations unconditionally.

[0072] The direction field (Dir) is used to control the data transmission direction: when the direction field (Dir) is the output direction, the data of the general-purpose register of the current processing core is output to the IO channels mapped to the current processing core, the number of which is specified by the quantity field (Cnt); when the direction field (Dir) is the input direction, the data is input from the IO channels mapped to the current processing core, the number of which is specified by the quantity field (Cnt), and stored in the general-purpose register of the current processing core.

[0073] While executing the input and output operations of the number of IO channels specified by the quantity field (Cnt), the IO instruction also sets the level of the IO channel specified by the first control IO number field (Vm) to the output value specified by the first control IO output value field (Om), and sets the level of the IO channel specified by the second control IO number field (Vn) to the output value specified by the second control IO output value field (On).

[0074] The first control IO output value field (Om) and the second control IO output value field (On) each independently specify a high output level, a low output level, or a level toggle.

[0075] The hardware execution condition on which the IO instruction depends is pre-generated by the SET instruction through logical combination of hardware event flags of each module of the chip. The IO instruction determines whether to detect the hardware execution condition through the condition enable field (Cond).

[0076] like Figure 4 The image shows an example of the instruction encoding for the I / O instruction provided by this invention. The 32-bit encoding of the I / O instruction, from high to low bits, consists of: a 4-bit opcode field (fixed to 0100), a 2-bit first control I / O number field Vm, a 4-bit first control I / O output value field Om, a 2-bit second control I / O number field Vn, a 4-bit second control I / O output value field On, a 6-bit delay field Dly, a 4-bit condition enable field Cond, a 1-bit direction field Dir, and a 5-bit quantity field Cnt; that is:

[0077]

[0078]

[0079] The 4-bit opcode field is fixed at 0100 and is used to identify the current instruction as an I / O instruction during the instruction decoding stage. The 5-bit quantity field Cnt specifies the number of I / O channels involved in this I / O operation. The value of Cnt ranges from 1 to 32, representing 1 to 32 I / O channels respectively. Based on the value of the Cnt field, the processing core sequentially selects the corresponding number of channels (numbered consecutively starting from IO0) from the I / O channels mapped to the current processing core and performs parallel input or output operations.

[0080] The 1-bit direction field Dir is used to control the data transmission direction. When Dir=0, the IO instruction performs an output direction operation, that is, the processing core outputs the data in the general-purpose register to the number of IO channels mapped to the current processing core, specified by the Cnt field; when Dir=1, the IO instruction performs an input direction operation, that is, the processing core inputs data from the number of IO channels mapped to the current processing core, specified by the Cnt field, into the general-purpose register.

[0081] The 4-bit condition enable field Cond is used to control the checking of hardware execution conditions. The highest bit (bit 3) of Cond serves as the condition enable bit: when bit 3 = 1, the I / O instruction needs to check whether the preset hardware execution conditions are met before performing input and output operations, and only performs the I / O operation if the conditions are met; when bit 3 = 0, the I / O instruction performs input and output operations unconditionally and does not check the hardware execution conditions. The lower 3 bits of Cond (bits 2 to 0) are reserved for future expansion and can support multiple different hardware execution condition sources; in this embodiment, they are fixed at 0. The hardware execution conditions are pre-generated by the SET instruction through logical combination of the hardware event flags of each module of the chip and written into the hardware execution condition register.

[0082] The 6-bit delay field Dly specifies the number of delay cycles after the I / O operation is completed. Dly takes values ​​from 0 to 63, representing a delay of 0 to 63 processing core clock cycles. When Dly=0, there is no delay after the I / O operation is completed; the instruction immediately ends and the next instruction is executed sequentially.

[0083] The 2-bit first control IO number field Vm is used to specify an IO channel number that requires additional control output value. Its value range is 0~3, corresponding to IO0~IO3 of the current processing core. The 4-bit first control IO output value field Om is used to specify the output value or output action of the IO channel. The 16 encoded values ​​of Om each correspond to an output control mode, including: output high level, output low level, level toggle, push-pull output mode, open-drain output mode, etc.

[0084] The 2-bit second control IO number field Vn is used to specify another IO channel number that requires additional control output values. Its value range is 0~3, corresponding to IO0~IO3 of the current processing core. Vm and Vn can point to the same IO channel or different IO channels. If they point to the same IO channel, the configuration of Vn and On overrides the configuration of Vm and Om. The 4-bit second control IO output value field On has the same encoding mapping relationship as Om, and is used to specify the output value or output action of the IO channel indicated by Vn.

[0085] The execution logic of I / O instructions is as follows: After the decoder of the processing core recognizes the opcode 0100, it first determines whether the hardware execution condition needs to be checked based on the Cond field. If the highest bit of Cond is 1, the value of the hardware execution condition register is read; if the condition is false (i.e., the hardware execution condition is not met), the I / O instruction does not perform any I / O operation and ends directly, executing the next instruction sequentially; if the condition is true (the hardware execution condition is met), or the highest bit of Cond is 0 (unconditional execution), the I / O operation execution stage begins.

[0086] During the I / O operation execution phase, the processing core first sets the level of the I / O channel specified by Vm to the output value specified by Om or executes the output action specified by Om based on the Vm and Om fields; simultaneously, it sets the level of the I / O channel specified by Vn to the output value specified by On or executes the output action specified by On based on the Vn and On fields. The level settings for these two additional control I / O operations are executed in parallel with the subsequent multi-channel I / O data transmission, meaning they are completed simultaneously within the same instruction execution cycle.

[0087] Subsequently, the processing core performs data transfer on the number of I / O channels specified by Cnt according to the direction field Dir:

[0088] When Dir=0 (output direction), the processing core retrieves the data to be output from the general-purpose register. Output operations have two modes: if Cnt≤16, the data is directly output sequentially from the lower Cnt bits of the general-purpose register to the corresponding I / O channel (the lowest bit is output to IO0, the next lowest bit to IO1, and so on), and the value in the general-purpose register remains unchanged after output. If Cnt>16 (i.e., 17~32 I / O channels need to be output), a single I / O instruction needs to process data from multiple general-purpose registers—the processing core first outputs the lower 16 bits from the current general-purpose register to IO0~IO15, then automatically increments the general-purpose register number, outputting the remaining bits (up to the highest Cnt-1 bit) from the next general-purpose register to IO16~IO31. The processing core internally maintains an output bit counter, which automatically interacts with the built-in FIFO after outputting Cnt bits: when the output counter reaches a preset threshold, the processing core automatically reads new data from the built-in FIFO and fills it into the general-purpose register, continuing the output of subsequent channels. The processing core can interact with the chip's DMA module via an internal DMA interface, whereby the DMA module automatically fills the FIFO with data without CPU intervention. It should be noted that at the start of an I / O instruction, if Cnt > 16, the processing core automatically fetches data sequentially starting from general-purpose register R0; if Cnt ≤ 16, only the lower 16 bits of general-purpose register R0 are used.

[0089] When Dir=1 (input direction), the processing core reads the input level status from a specified number of I / O channels in parallel. Input operations also have two modes: if Cnt≤16, the input levels read from IO0 to IO(Cnt-1) are sequentially stored in the lower Cnt bits of a general-purpose register (bit0 for IO0, bit1 for IO1, and so on), while the higher bits (bitCnt~bit31) of the general-purpose register are cleared; if Cnt>16 (i.e., 17~32 I / O channels need to be input), the processing core reads 16 bits of data from IO0 to IO15 and stores them in the current general-purpose register, then automatically increments the general-purpose register number, reading the remaining bits from IO16 to IO31 and storing them in the next general-purpose register, until all Cnt channels have been input. The processing core internally maintains an input bit counter, which automatically interacts with the built-in FIFO after each Cnt bit input: when the input counter reaches a preset threshold, the processing core automatically stores the data in the general-purpose register into the built-in FIFO and notifies the DMA module to remove the data from the FIFO. The processing core can interact with the chip's DMA module through an internal DMA interface, and the DMA module can automatically move the data in the FIFO to the system memory without CPU intervention.

[0090] After multi-channel I / O data transmission is completed, the processing core determines whether to delay based on the value of the Dly field: if Dly=0, the I / O instruction ends immediately, and the next instruction is executed sequentially; if Dly>0, the processing core maintains the current state and waits for Dly clock cycles before ending the instruction. The above two additional control I / O level settings, multi-channel I / O parallel data transmission, and delay waiting operations are completed sequentially in a single I / O instruction according to the aforementioned timing sequence, forming a complete I / O operation sequence.

[0091] It is important to note that during the execution of multi-channel input or output operations by I / O instructions, the processing core automatically interacts with the built-in FIFO and DMA modules: in the output direction, after the data in the general-purpose registers has been output, new data is automatically loaded from the FIFO to continue outputting; in the input direction, after the general-purpose registers are full, data is automatically stored in the FIFO to free up space for continued input. This automatic flow control mechanism enables I / O instructions to complete the continuous transmission of batch data within a single instruction. The data transmission length is limited only by the FIFO depth and DMA configuration, and is not limited to the 32-channel upper limit of the Cnt field in the instruction encoding, thus expanding the applicable scenarios of I / O instructions.

[0092] like Figure 4 As shown, the opcode field 0100 in the encoding of the IO instruction is different from the opcodes of other instructions, ensuring that the decoder can accurately distinguish them. The Cond field of the IO instruction works in conjunction with the hardware execution conditions generated by the SET instruction to realize a hardware event synchronization mechanism between multiple instructions; the Cnt field works with the Dir field to complete a configurable number and configurable direction of multi-channel parallel IO transmission within a single instruction, enabling the parallel processing module to complete batch IO data transfer tasks with extremely low instruction overhead.

[0093] The Read Immediate Address instruction (LDM) is used to read data from the bus address recorded in the address field of the LDM instruction and store it into the general-purpose register specified by the LDM instruction.

[0094] Preferably, the LDM instruction includes an immediate numeric field (Addr) and a general-purpose register field (Rd).

[0095] The LDM instruction is used to read 32 bits of data from the bus address recorded in the immediate digital field (Addr) and store it into the general-purpose register of the current processing core specified by the general-purpose register field (Rd).

[0096] The Write Immediate Address (STM) instruction is used to write the data of the general-purpose register specified by the STM instruction to the bus address recorded in the address field of the STM instruction.

[0097] Preferably, the STM instruction includes an immediate digital field (Addr) and a general-purpose register field (Rn).

[0098] The STM instruction is used to write 32-bit data of the general-purpose register of the current processing core to the access address, which is specified by the general-purpose register field (Rn). The bus address recorded in the immediate digital field (Addr) is used as the access address.

[0099] like Figure 5 The image shows an example of instruction encoding for the LDM and STM instructions provided by this invention. The 32-bit encoding of the LDM instruction, from most to least significant bit, consists of: a 1-bit opcode flag (fixed to 1), a 1-bit direction flag (fixed to 0), a 1-bit general-purpose register field Rd, and a 29-bit immediate number field Addr; that is:

[0100]

[0101] The 32-bit encoding of STM instructions, from most to least significant bit, consists of: a 1-bit opcode flag (fixed to 1), a 1-bit direction flag (fixed to 1), a 1-bit general-purpose register field Rn, and a 29-bit immediate numeric field Addr; that is:

[0102]

[0103] LDM and STM instructions use the same high-order encoding structure: the highest bit (bit 31) is fixed at 1, used to distinguish LDM / STM instructions from the aforementioned SET, WAIT, JMP, and IO instructions (whose highest bit is 0); bit 30 is the direction flag bit—bit 30 of LDM instructions is fixed at 0, and bit 30 of STM instructions is fixed at 1, used to distinguish LDM from STM during the instruction decoding stage; bit 29 is the general-purpose register field, used to select the general-purpose register used for data read / write; bits 28 to bit 0 are the 29-bit immediate number field Addr, used to record the bus address.

[0104] In LDM instructions, the 1-bit general-purpose register field Rd is used to specify the target general-purpose register for storing the read data. The two encoded values ​​of Rd correspond to the two general-purpose registers of the current processing core: when Rd=0, general-purpose register R0 is selected, and when Rd=1, general-purpose register R1 is selected.

[0105] In STM instructions, the 1-bit general-purpose register field Rn is used to specify the source general-purpose register from which the data to be written is provided. The two encoded values ​​of Rn correspond to the two general-purpose registers of the current processing core: when Rn=0, general-purpose register R0 is selected, and when Rn=1, general-purpose register R1 is selected.

[0106] The 29-bit immediate numeric field Addr is used to record the high 29 bits of the bus address. The value of Addr ranges from 0x00000000 to 0x1FFFFFFF. During actual bus access, the processing core shifts the value of the Addr field left by 2 bits (i.e., multiplies it by 4) to obtain the final 32-bit bus address. The address range after shifting left by 2 bits is 0x00000000 to 0x7FFFFFFC, covering a 2GB bus address space, and is forced to be 4-byte aligned.

[0107] The execution logic of the LDM instruction is as follows: When the decoder of the processing core detects that the highest bit is 1 and bit 30 is 0, it determines that the current instruction is an LDM instruction. During execution, the processing core first shifts the 29-bit Addr field left by 2 bits to generate a 32-bit bus address; then, using this address as the starting address, it reads a 32-bit data from the bus (including system memory, on-chip peripheral registers, configuration registers of other functional modules, etc.); finally, it stores the read 32-bit data into the general-purpose register (R0 or R1) specified by the Rd field. The above address generation, bus read, and register write operations are all completed within the timing specified by the instruction.

[0108] The execution logic of STM instructions is as follows: When the decoder of the processing core detects that the highest bit is 1 and bit 30 is 1, it determines that the current instruction is an STM instruction. During execution, the processing core first shifts the 29-bit Addr field left by 2 bits to generate a 32-bit bus address; then it reads 32 bits of data from the general-purpose register (R0 or R1) specified by the Rn field; finally, it writes this 32-bit data to the bus with the bus address as the destination. The above address generation, register reading, and bus writing operations are all completed within the timing specified by the instruction.

[0109] Both LDM and STM instructions complete a single 32-bit data read / write operation on the bus with a single instruction, requiring no additional address calculation, register loading, or address offset instructions, resulting in high instruction density and high execution efficiency.

[0110] like Figure 5 As shown, the LDM and STM instructions employ a compact 32-bit encoding scheme (1+1+1+29=32 bits), achieving 4-byte aligned 32-bit address access by left-shifting the 29-bit immediate value by 2 bits. The 29-bit width of the Addr field allows the instruction to cover a 2GB bus address space, sufficient to meet the address mapping requirements of most embedded chips' on-chip memory and peripherals. Compared to the LDR and STR instructions, the address of the LDM / STM instructions is directly encoded within the instruction, eliminating the need to rely on general-purpose registers as base addresses. Therefore, it is more efficient when accessing constant data or peripheral registers at fixed addresses, allowing a single instruction to complete a full bus read / write operation.

[0111] The Read Register Address (LDR) instruction is used to read data from the bus address specified in the LDR instruction and store it in the second general-purpose register specified in the LDR instruction, using the value of the first general-purpose register specified in the LDR instruction plus the offset specified in the LDR instruction as the bus address.

[0112] Preferably, the LDR instruction includes a general-purpose register field (Rn), a signed immediate number field (Offset), and a general-purpose register field (Rd).

[0113] The LDR instruction is used to read 32 bits of data from the bus address specified by the general-purpose register field (Rn) of the current processing core, plus the signed immediate number field (Offset), and store it into the general-purpose register of the current processing core specified by the general-purpose register field (Rd).

[0114] The write register address instruction STR is used to write the data of the second general-purpose register specified in the STR instruction to the bus address, which is the value of the first general-purpose register specified in the STR instruction plus the offset specified in the STR instruction.

[0115] Preferably, the STR instruction includes a general-purpose register field (Rd), a signed immediate number field (Offset), and a general-purpose register field (Rn).

[0116] The STR instruction is used to write 32 bits of data from the general-purpose register of the current processing core, specified by the general-purpose register field (Rd), to the bus address by adding the value of the general-purpose register of the current processing core to the signed immediate number field (Offset).

[0117] like Figure 2 The image shows an example of the instruction encoding for the SET, JMP, LDR, and STR instructions provided by this invention. The 32-bit encoding of the LDR instruction, from most to least significant bit, consists of: a 4-bit fixed field (0110), a 4-bit fixed field (0110), a 1-bit reserved field rsvd, a 3-bit destination general-purpose register field Rd, a 3-bit fixed field (000), a 1-bit base address general-purpose register field Rn, and a 16-bit signed immediate field Offset; that is:

[0118]

[0119] The 32-bit encoding of the STR instruction, from most significant bit to least significant bit, consists of: a 4-bit fixed field (0111), a 4-bit fixed field (0110), a 1-bit reserved field rsvd, a 3-bit source general-purpose register field Rn, a 3-bit fixed field (000), a 1-bit base address general-purpose register field Rd, and a 16-bit signed immediate field Offset; that is:

[0120]

[0121] In the LDR instruction, the 4-bit fixed field 0110 together with the adjacent 4-bit fixed field 0110 constitutes the unique opcode identifier 01100110 (i.e., hexadecimal 0x66) of the LDR instruction, which is used to identify the current instruction as an LDR instruction during the instruction decoding stage.

[0122] In the STR instruction, the 4-bit fixed field 0111 and the adjacent 4-bit fixed field 0110 together constitute the unique opcode identifier 01110110 (i.e., hexadecimal 0x76) of the STR instruction, which is used to identify the current instruction as the STR instruction during the instruction decoding stage.

[0123] In the LDR instruction, the 1-bit base general-purpose register field Rn and the 3-bit destination general-purpose register field Rd together constitute a complete 4-bit general-purpose register selection logic. Specifically, the base general-purpose register is indicated by the 1-bit Rn field (bit 16), which can select R0 or R1; the destination general-purpose register is indicated by the 3-bit Rd field (bits 22~20), which can select R0~R7. It should be noted that although the 1-bit Rn field and the 3-bit Rd field have different physical bit positions, they are both mapped to the same set of general-purpose register file read ports during hardware decoding. That is, the encoded values ​​of the Rn field and the Rd field correspond to the register numbers in the general-purpose register file (Rn is 0~1, Rd is 0~7). When the LDR instruction is executed, the base address value is read from the base address register indicated by Rn.

[0124] In the LDR instruction, the 16-bit signed immediate field Offset is used to provide the address offset. The value of Offset ranges from -32768 to +32767 (i.e., 0x8000 to 0x7FFF), encoded in two's complement form. When calculating the target address, the processing core sign-extends the value of Offset to 32 bits and adds it to the value in the base address register to generate the final 32-bit bus address.

[0125] The execution logic of the LDR instruction is as follows: After the decoder of the processing core recognizes the opcode 01100110, it first reads the 32-bit base address value from the base address general-purpose register (R0 or R1) specified by the Rn field. At the same time, it sign-extends the signed immediate value Offset to 32 bits. The base address is added to the extended offset to obtain the 32-bit target bus address. Then, a 32-bit data is read from the bus starting at this address. Finally, the read 32-bit data is stored in the target general-purpose register (one of R0 to R7) specified by the Rd field. The above base address read, address addition, bus read, and register write operations are all completed within the timing specified by the instruction.

[0126] In the STR instruction, the 1-bit base general-purpose register field Rd (bit 16) and the 3-bit source general-purpose register field Rn (bits 22-20) together constitute the complete 4-bit general-purpose register selection logic. Specifically, the base general-purpose register is indicated by the 1-bit Rd field, which can select R0 or R1; the source general-purpose register is indicated by the 3-bit Rn field, which can select R0 to R7. When the STR instruction is executed, the base address value is read from the base register indicated by Rd, and the data to be written is read from the source register indicated by Rn. In the STR instruction, the encoding method of the 16-bit signed immediate numeric field Offset is exactly the same as that of the LDR instruction, used to provide the address offset, with a value range of -32768 to +32767.

[0127] The execution logic of the STR instruction is as follows: After the core decoder recognizes the opcode 01110110, it first reads the 32-bit base address value from the base address general-purpose register (R0 or R1) specified by the Rd field. Simultaneously, it sign-extends the signed immediate value Offset to 32 bits. The base address is then added to the extended offset to obtain the 32-bit target bus address. Next, it reads 32 bits of data from the source general-purpose register (one of R0 to R7) specified by the Rn field. Finally, it writes this 32-bit data to the bus with the target bus address as the destination. All the above base address read, address addition, register read, and bus write operations are completed within the timing specified by the instruction.

[0128] Although the general-purpose register fields of LDR and STR instructions are physically located (some fields are adjacent to fixed-code fields), during hardware decoding, both are mapped to the general-purpose register file with unified addressing of the processing core. The base address register selection uses only R0 or R1 (Rn of LDR is 1 bit, and Rd of STR is 1 bit), while the destination / source register selection uses R0~R7 (Rd of LDR is 3 bits, and Rn of STR is 3 bits). This asymmetric field allocation scheme maximizes the compression of instruction code length while ensuring functional integrity, leaving sufficient bit space for the 16-bit signed offset.

[0129] Preferably, the bit offset values ​​used to indicate general-purpose registers in the SET instruction are the same as those used in the JMP instruction, LDR instruction, and STR instruction, and the bit offset values ​​used to indicate immediate values ​​are the same.

[0130] like Figure 2As shown, the encoded fields used to indicate general-purpose registers in the SET, JMP, LDR, and STR instructions use the same bit offset mapping relationship. Taking registers R0 to R7 as examples: in the SET and JMP instructions, R0~R7 are encoded as 0000~0111 respectively; in the destination register field (Rd, 3 bits) of the LDR instruction and the source register field (Rn, 3 bits) of the STR instruction, R0~R7 are encoded as 000~111 respectively; in the base address register field (Rn, 1 bit) of the LDR instruction and the base address register field (Rd, 1 bit) of the STR instruction, R0 and R1 are encoded as 0 and 1 respectively. That is, the encoded values ​​of all register fields point to the general-purpose register file according to the same mapping rule, and the least significant bit of the encoded value is consistent with the register number.

[0131] Because the above instructions reuse a unified register encoding mapping, the hardware decoder of the processing core does not need to set register selection logic separately for different instructions. The same set of decoding circuits can complete the parsing of register fields in all instructions. At the same time, the 16-bit immediate number field Imm16 of the SET instruction and the 16-bit signed immediate number field Offset of the LDR and STR instructions are all located in bits [15:0] in the instruction. The hardware can reuse the same set of 16-bit immediate number extension paths, and the only difference is the instruction type control over the extension mode (zero extension or sign extension).

[0132] When generating the above instructions, the compiler only needs to maintain a mapping table from register numbers to encoded values, without having to switch different encoding rules according to the instruction type, which simplifies the implementation of the compiler backend.

[0133] Another aspect of the present invention provides a parallel processing module comprising multiple processing cores, each processing core independently executing the instruction sequence defined by the instruction set definition method.

[0134] like Figure 1 As shown, the parallel processing module contains multiple processing cores, each with independent hardware resources, including: a tightly coupled instruction memory (TCM) for storing its own independently running instruction sequence; a program counter (PC) for indicating the current instruction address; an instruction decoder for recognizing the opcodes of the aforementioned eight types of instructions; a general-purpose register file (R0-R7); an arithmetic logic unit (ALU) for executing various operations specified by the SET instruction; a comparison unit for executing conditional judgments specified by the JMP instruction; an I / O control interface for executing multi-channel parallel input and output of I / O instructions; a bus interface for bus read / write access of LDM, STM, LDR, and STR instructions; and wait control logic for signal monitoring and periodic delay of the WAIT instruction. The above hardware resources of each processing core are independent of each other, ensuring that multiple processing cores can truly execute their respective instruction sequences in parallel without interference.

[0135] Each processing core's instruction TCM is loaded into the instruction sequence via the debug interface or DMA. Each processing core independently fetches, decodes, and executes instructions, sharing the chip's internal bus. Each core can independently initiate bus access to system memory or on-chip peripherals. If multiple processing cores access the bus simultaneously, the bus arbitrator will arbitrate the access.

[0136] Another aspect of the present invention provides an electronic device including the parallel processing module.

[0137] In this embodiment, the electronic device can be an industrial controller, an IoT terminal, a smart sensor, a motor driver, a wearable device, or a mobile terminal, etc. The parallel processing module inside the electronic device acts as a coprocessor or an independent acceleration unit, working in conjunction with the main CPU to undertake high real-time and high deterministic parallel control tasks, thereby freeing up the computing resources of the main CPU.

[0138] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for defining an instruction set for a parallel processor, characterized in that, The instruction set contains 8 types of instructions, each of which is fixed at 32 bits. The 8 instructions include: The assignment instruction SET is used to perform the operation between the source operand and the immediate value specified by the SET instruction, and then write the result to the destination operand of the SET instruction. The WAIT instruction is used to wait for the specified signal of the WAIT instruction to meet the polarity condition of the WAIT instruction, and then delay for the number of cycles specified by the WAIT instruction. The jump instruction JMP is used to jump to the target address specified by the JMP instruction after a delay of the number of cycles specified by the JMP instruction if the two operands of the JMP instruction meet the comparison conditions specified by the JMP instruction; otherwise, execution proceeds sequentially. Multi-channel I / O read / write instructions (IO) are used to execute input and output operations on a specified number of I / O channels when preset hardware execution conditions are met, and to delay for a specified number of cycles after the input and output operations are completed. The Read Immediate Address instruction (LDM) is used to read data from the bus address recorded in the address field of the LDM instruction and store it into the general-purpose register specified by the LDM instruction. The Write Immediate Address (STM) instruction is used to write the data of the general-purpose register specified by the STM instruction to the bus address recorded in the address field of the STM instruction. The Read Register Address (LDR) instruction is used to read data from the bus address specified in the LDR instruction and store it in the second general-purpose register specified in the LDR instruction, using the value of the first general-purpose register specified in the LDR instruction plus the offset specified in the LDR instruction as the bus address. The write register address instruction STR is used to write the data of the second general-purpose register specified in the STR instruction to the bus address, which is the value of the first general-purpose register specified in the STR instruction plus the offset specified in the STR instruction.

2. The instruction set definition method for a parallel processor according to claim 1, characterized in that, The assignment operation instruction SET includes: a source operand field, a 16-bit immediate numeric field, an operator field, and a destination operand field; The SET instruction is used to perform an operation between the source operand indicated by the source operand field and the immediate number indicated by the 16-bit immediate operand field, as specified by the operator field, and then write the result to the target operand indicated by the target operand field. The source operand indicated by the source operand field and the target operand indicated by the target operand field are each independently selected from any one of the following: the general-purpose registers of the current processing core, the I / O channels mapped by the current processing core, the built-in FIFO of the current processing core, the hardware event flags of each module of the chip, and the hardware execution conditions.

3. The instruction set definition method for a parallel processor according to claim 1, characterized in that, The WAIT instruction includes: a data source field, a polarity field, a delay field, and a reserved field; The WAIT instruction is used to determine whether the current signal indicated by the data source field is equal to the value specified by the polarity field. If it is, the waiting ends after a delay of the number of cycles specified by the delay field; otherwise, the determination is repeated in the next execution cycle. The current signal indicated by the data source field is selected from any one of the following: the chip's IO input level, the current processing core's built-in FIFO state, the hardware event flags of each module of the chip, and the hardware execution conditions.

4. The instruction set definition method for a parallel processor according to claim 1, characterized in that, The jump instruction JMP includes: a first operand field, a second operand field, a condition field, a delay field, and an address field; The JMP instruction is used to determine whether the first operand indicated by the first operand field and the second operand indicated by the second operand field satisfy the comparison condition specified by the condition field. If they satisfy the condition, the instruction will jump to the target address specified by the address field after a delay of the number of cycles specified by the delay field; otherwise, the next instruction will be executed sequentially. The first operand indicated by the first operand field and the second operand indicated by the second operand field are each independently selected from any one of the general-purpose registers of the current processing core, the chip hardware state, the I / O input level, and the hardware event flag.

5. The instruction set definition method for a parallel processor according to claim 1, characterized in that, The IO instruction includes a quantity field, a direction field, a delay field, a condition enable field, a first control IO number field, a first control IO output value field, a second control IO number field, and a second control IO output value field. The IO instructions are used to perform input and output operations on the number of IO channels specified by the quantity field when the hardware execution conditions are met, and to delay for the number of cycles specified by the delay field after the input and output operations are completed. The condition enable field is used to control the checking of the hardware execution conditions: when the value of the condition enable field is true, the IO instruction executes the input and output operations only when the hardware execution conditions are met; when the value of the condition enable field is false, the IO instruction executes the input and output operations unconditionally. The direction field is used to control the data transmission direction: when the direction field is the output direction, the data of the general-purpose register of the current processing core is output to the IO channels mapped to the current processing core, the number of which is specified by the quantity field; When the direction field is the input direction, the number of IO channel input data mapped to the current processing core, specified by the quantity field, is stored in the general-purpose register of the current processing core; While executing the input and output operations of the number of IO channels specified by the quantity field, the IO instruction also sets the level of the IO channel specified by the first control IO number field to the output value specified by the first control IO output value field, and sets the level of the IO channel specified by the second control IO number field to the output value specified by the second control IO output value field. The first control IO output value field and the second control IO output value field each independently specify an output high level, an output low level, or a level toggle. The hardware execution conditions upon which the IO instruction depends are pre-generated by the SET instruction through logical combination of hardware event flags of various modules of the chip. The IO instruction determines whether to detect the hardware execution conditions through the condition enable field.

6. The instruction set definition method for a parallel processor according to claim 1, characterized in that, The LDM instruction includes an immediate digital field and a general-purpose register field; the STM instruction includes an immediate digital field and a general-purpose register field. The LDM instruction is used to read 32 bits of data from the access address, which is recorded in the immediate digital field, and store it into the general-purpose register of the current processing core specified by the general-purpose register field. The STM instruction is used to write 32-bit data of the general-purpose register of the current processing core to the access address, using the bus address recorded in the immediate digital field as the access address.

7. The instruction set definition method for a parallel processor according to claim 1, characterized in that, The LDR instruction includes a general-purpose register field, a signed immediate number field, and a general-purpose register field; the STR instruction includes a general-purpose register field, a signed immediate number field, and a general-purpose register field. The LDR instruction is used to read 32 bits of data from the bus address specified by the general register field of the current processing core, plus the signed immediate number field, and store it into the general register of the current processing core specified by the general register field. The STR instruction is used to write 32-bit data from the general-purpose register of the current processing core, specified by the general-purpose register field, to the bus address by adding the value of the general-purpose register of the current processing core specified by the general-purpose register field to the bus address.

8. The instruction set definition method for a parallel processor according to claim 1, characterized in that, The SET instruction has the same bit offset value for indicating general-purpose registers and the same mapping relationship as the JMP instruction, LDR instruction and STR instruction, and the same bit offset value for indicating immediate values.

9. A parallel processing module, characterized in that, It contains multiple processing cores, each of which independently runs the instruction sequence defined by the instruction set definition method according to any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the parallel processing module as described in claim 9.

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