System for operating a modular computing system

Abstract

An operating system includes a baseboard management controller (BMC), a plurality of processing units electrically connected to the BMC, and a basic input / output system (BIOS) chip storing a BIOS firmware. During a boot-up process of the operating system, one or more of the plurality of processing units are configured to execute the BIOS firmware to collect processing unit information. One or more of the processing units are further configured to execute the BIOS firmware to determine a current configuration of the processing units based at least in part on the processing unit information. One or more of the processing units are further configured to execute the BIOS firmware to divide resources of the operating system among the processing units based at least in part on the current configuration of the processing units.

Description

[0001] This invention relates to a system and method for partitioning the resources of a computing system, and particularly to a BIOS for partitioning the resources of a modular computing system having a variable number of processor units. Background Technology

[0002] High-end servers and other computing systems may include multiple processing units for performing complex tasks. These processing units may be mounted on multiple different circuit boards (e.g., motherboards, processing unit boards, etc.). A computing system initially manufactured for a specific number of processing units and processing unit boards can function normally using standard basic input / output system (BIOS) firmware. However, some computing systems are modular and may consist of multiple processing unit boards that were not originally intended to be used together. In such computing systems, standard BIOS firmware may struggle to recognize the configuration of the processing units and operate the computing system. Therefore, new systems and methods are needed for operating modular computer systems. Summary of the Invention

[0003] The terms used, such as implementations, configurations, styles, examples, and options, are intended to broadly refer to all subject matter of this disclosure and the following claims. Statements including these terms should not be construed as limiting the subject matter described herein or limiting the meaning or scope of the following claims. The embodiments of this disclosure as covered herein are defined by the following claims, not by the content of this disclosure. This disclosure is a high-level overview of various styles of this disclosure and introduces some concepts further described in the following Description section. This disclosure is not intended to identify key or essential features of the claimed subject matter. Nor is it intended to be used alone to determine the scope of the claimed subject matter. The subject matter of this invention should be understood by referring to the entire specification of this disclosure, any or all of the accompanying drawings, and appropriate portions of each claim.

[0004] According to embodiments of this disclosure, the computing system includes a baseboard management controller (BMC), a plurality of processing units electrically connected to the BMC, and a BIOS chip storing BIOS firmware. During the power-on process of the computing system, one or more of these processing units are configured to execute the BIOS firmware to collect processing unit information. One or more of these processing units are also configured to execute the BIOS firmware to determine, at least in part, the current configuration of these processing units based on the processing unit information. One or more of these processing units are also configured to execute the BIOS firmware to allocate multiple resources of the computing system among the processing units, at least in part, based on the current configuration of these processing units.

[0005] The foregoing description is not intended to cover every embodiment or all variations of this disclosure. Rather, it provides examples of some of the novel features and functions presented in this disclosure. The foregoing features and advantages, as well as other features and advantages of this disclosure, will become clear from the following detailed description of representative embodiments, which is made more apparent when read in conjunction with the accompanying drawings and appended claims. Those skilled in the art will further understand other variations of this disclosure through the following detailed descriptions of various embodiments, which are described with reference to the accompanying drawings, a brief description of which is provided below. Attached Figure Description

[0006] This disclosure, its advantages, and the accompanying drawings will become clearer through the following description of representative embodiments, in conjunction with the accompanying drawings. These drawings depict only representative embodiments and should not be construed as limiting the various embodiments or claims.

[0007] Figure 1 This is a block diagram illustrating a modular computing system with a variable number of processing units, based on some aspects of the present disclosure.

[0008] Figure 2 This is a kind of illustration based on some of the states depicted in this disclosure. Figure 1 The flowchart shows how resources are allocated in a modular computing system.

[0009] Figures 3A to 3B This is an exemplary resource table drawn according to some of the forms of this disclosure, which is used for exemplary methods of allocating resources.

[0010] Figures 4A to 4B This is an exemplary table illustrating different bus allocation configurations based on some aspects of this disclosure.

[0011] Figure 4C Figure 4G shows an exemplary table of different configurations of low-address memory-mapped input / output (MMIO-L) resource allocation, based on some aspects of this disclosure. Detailed Implementation

[0012] Various embodiments are described with reference to the accompanying drawings, in which the same reference numerals are used throughout the drawings to denote similar or equivalent components. Each reference numeral identifies the figure in which the reference numeral first appears based on the first digit (for three-digit reference numerals) or the first two digits (for four-digit reference numerals) corresponding to the figure number. These drawings are not drawn to scale and are only used to illustrate the features and characteristics of this disclosure. Numerous specific details, relationships, and methods are set forth to provide a full understanding of some features and characteristics of this disclosure, although those skilled in the art will understand that these features and characteristics can be practiced without one or more specific details, other relationships, or other methods. In some cases, known structures or operations are not shown in detail for illustrative purposes. The various embodiments disclosed herein are not necessarily limited to the order of the actions or events shown, as some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all actions or events shown must implement some features and characteristics of this disclosure.

[0013] For the purposes of this embodiment, unless otherwise stated, the singular includes the plural where appropriate, and vice versa. The word “including” means “including but not limited to”. Furthermore, approximate words such as “about,” “almost,” “substantially,” “approximately,” etc., may be used herein to mean “in,” “near,” “close to,” “within 3 to 5%,” “within acceptable manufacturing tolerances,” or any logical combination thereof. Similarly, the terms “vertical” or “horizontal” are intended to additionally include “within 3 to 5%” in the vertical or horizontal direction, respectively. Furthermore, directional words such as “top,” “bottom,” “left,” “right,” “above,” and “below” are intended to relate to the equivalent directions shown in the reference figures; as understood from the context of the referenced object or component (e.g., from its usual location); or as described herein.

[0014] Figure 1Block diagrams of a modular multi-central processing unit (CPU) computing system 100 according to some embodiments of this disclosure are shown. In some implementations, the computing system 100 is a server, but the principles disclosed herein can be applied to any computing system having one or more of the components described herein. The computing system 100 includes processing units 102A to 102n. In the implementations shown, only processing units 102A and 102n are explicitly shown. However, it should be understood that processing units 102A and 102n generally represent the first and last processing unit in any plurality of processing units. For example, processing units 102A to 102n may include two, four, eight, sixteen, thirty-two, etc. Generally, the number of processing units in the computing system 100 is not a static number. Rather, the computing system 100 is modular because the actual number of processing units is variable, depending on the specific application in which the computing system 100 operates.

[0015] Processing units 102A and 102n are designated CPU0 and CPUn, respectively, and typically refer to a central processing unit. However, processing units can generally include any suitable type of processing unit, such as a graphics processing unit (GPU), a microcontroller, other types of coprocessors (e.g., neural processing units, digital signal processing units, field-programmable logic arrays, etc.), and / or any other suitable processing unit. Processing units 102A-102n are typically mounted on one or more processing unit boards along with any other supporting components. In some implementations, each of the processing units 102A-102n is mounted on its own respective processing unit board. In other embodiments, at least one processing unit board has multiple processing units mounted on it. For example, computing system 100 may include multiple processing unit boards, and each processing unit board includes two processing units mounted thereon.

[0016] The computing system 100 also includes one or more processor interconnects 103, in Figure 1The term is represented by a double arrow extending between processing unit 102A and processing unit 102n. Generally, the computing system 100 includes at least one processor interconnect between two processing units, which can be used for data transfer between the two processing units. In some implementations, the processor interconnect 103 between two individual processing units is formed by multiple separate lanes. The processor interconnect between two processing units mounted on the same processing unit board is typically physically formed within the processing unit board itself. However, processing units mounted on different processing unit boards can also be connected via one or more processor interconnects 103. In these implementations, the computing system 100 may include additional boards (e.g., frontbridge board, rear bridge board, midplane board, backplane board, etc.) that couple the processing units of different processing unit boards together. Generally, the computing system 100 includes multiple sockets mounted on one or more boards, with each processing unit 102A-102n electrically connected to a corresponding socket. The processor interconnect 103 between two processing units mounted on different circuit boards will be formed simultaneously on the two slots electrically connected to the two processing units and the circuit boards mounted on the two slots.

[0017] The computing system 100 also includes a basic input / output system (BIOS) 104. The BIOS 104 is a memory device that stores the BIOS firmware. As used herein, the term "BIOS 104" can refer to the memory device itself and the firmware stored thereon. The BIOS 104 can be any suitable memory device, such as a random access memory (RAM) chip, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a read-only memory (ROM) chip, a programmable read-only memory (PROM) chip, an erasable programmable read-only memory (EPROM) chip, an electrically erasable programmable read-only memory (EEPROM) chip, a flash memory chip (e.g., NOR flash, NAND flash, etc.), a synchronous dynamic random access memory (SDRAM) chip, a double data rate SDRAM (DDR SDRAM) chip, a hard disk, or any other suitable memory device.

[0018] The BIOS firmware can be executed to perform various basic tasks, including initializing and testing various components within the system when the computing system 100 is powered on (commonly referred to as performing the power-on self-test (POST) routine); loading a bootloader from a separate memory device (typically a hard disk or flash storage device); and allocating resources of the computing system 100 among processing units 102A-102n. The BIOS firmware can be executed by any one or more processing units 102A-102n, and / or by other processors or controllers within the computing system 100. Furthermore, although this boot firmware is called BIOS firmware, the BIOS chip can actually include any suitable firmware, including firmware conforming to the Unified Extensible Firmware Interface (UEFI) standard. As described later, the BIOS firmware is designed to operate correctly with varying numbers of processing units and / or processing unit boards. In some implementations, the BIOS firmware includes a resource table that defines the resource allocation scheme of the computing system 100 under various processing unit configurations. An exemplary resource table is shown below. Figures 3A to 3B As shown, and explained in detail below.

[0019] The computing system 100 also includes a baseboard management controller (BMC) 106, which is a dedicated controller for managing the operation of the computing system 100 and typically includes its own processing unit and storage device. The BMC 106 allows for remote monitoring of various components of the computing system 100. In some implementations, the BMC 106 is used to implement the Intelligent Platform Management Interface (IPMI) standard.

[0020] The computing system 100 may also include one or more memory devices 108. The one or more memory devices 108 may include any suitable memory device, including those discussed herein with respect to the BIOS chip. The one or more memory devices 108 typically include memory modules used by the processing units 102A–102n, which may be in the form of dual in-line memory modules (DIMMs) including individual memory chips (e.g., SDRAM chips, DDR SDRAM chips, etc.). The computing system 100 may also include various chipsets that can be used to perform a variety of different computing tasks. In the illustrated implementation, possible chipsets include a controller hub chipset 110 (common examples of which include platform controller hubs (PCHs) and fusion controller hubs (FCHs)), a northbridge chipset 112, and a southbridge chipset 114. Chipsets may also include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), memory controllers, I / O (input / output) controllers, etc.

[0021] The computing system 100 may also include various peripheral devices 116 that can be connected to the processing units 102A-102n, the BIOS chip, the BMC 106, and / or any other component of the computing system 100. These peripheral devices 116 typically include any peripheral device that can be connected (internal or externally) to the computing system 100, and may include, for example: fan modules; expansion cards, such as display adapters, capture cards, sound cards, other expansion cards, etc.; hard disk drives; solid-state drives; USB (universal serial bus) flash drives; network interface controllers or cards (NICs); input / output ports, including USB ports, Ethernet ports, other network ports, HDMI (high definition multimedia interface) ports, DVI (digital visual interface) ports, VGA (video graphics array) ports, etc.; input devices, including mice, keyboards, controllers, microphones, webcams, scanners, etc.; output devices, such as monitors, printers, headphones, speakers, etc.; and other circuit boards, such as daughterboards.

[0022] The computing system 100 also includes one or more bus segments 118. The bus segments 118 electrically connect the processing units 102A to 102n to any of the other components in the computing system 100, including the BIOS chip, BMC 106, memory device 108, controller hub chipset 110, northbridge chipset 112 and southbridge chipset 114, and peripheral devices 116.

[0023] The computing system 100 may also include a field replaceable unit (FRU) 120, which is used to indicate to the BIOS 104 that the computing system 100 is a modular computing system with a variable number of processing units / processing unit configurations. The FRU 120 is typically connected to the BMC 106.

[0024] In this example, FRU 120 is used to determine the platform configuration of the system under test. The platform configuration includes the original design manufacturer (ODM) name, product name, and unique serial number. When the motherboard is in the surface mount technology (SMT) process stage, the configuration is null. Before the motherboard (e.g., M1) begins running the manufacturing process (MFG test), the operator uses an ICT (in-circuit test) tool to burn the FRU information. In this example, BIOS 104 uses the ipmitool command to send raw data to BMC 106, and BMC 106 then reports the FRU information back to BIOS 104. During the POST phase, the FRU's product name configuration allows BIOS 104 to determine the stock keeping unit (SKU), as different SKUs have different hardware configurations and interface ports. An incorrect FRU product name configuration will result in a BIOSPOST hang code issue. Based on the current known process, if the 4S module uses a FRU product name belonging to the 8S module, a stall code issue will occur. If the FRU product name is not updated via ICT tools, the product name configuration will be empty. This will also cause boot failure during POST due to mismatched BIOS boot policies.

[0025] Using this exemplary method, all modular projects, such as 2S / 4S / 8S / 16S / 32S, can use the same FRU product name. Since the number of slots can be used as the SKU determination criterion, the same product name also supports the BIOS POST process. This method significantly improves MFG manufacturing processes on different motherboards (e.g., M1 or M3), spare parts replacement, demand switching between different modular SKUs, and fault handling capabilities when in downgraded configurations (e.g., from 8S to 4S or from 4S to 2S).

[0026] Figure 2A flowchart illustrating a method 200 for operating a computing system 100 (e.g., a modular computing system with a variable number of processing units) is shown. For computing systems designed to always have a fixed number of processing units (e.g., only two processing units, only four processing units, etc.), the manufacture and configuration of the computing device are generally straightforward. Specifically, a processing unit board with processing units is typically designed for use with a computing system having a fixed number of processing units, and the BIOS firmware on the BIOS chip is designed to allocate the computing system's resources among said fixed number of processors. Therefore, a computing system with four processing units has a single processing unit board specifically designed for use with four processing units.

[0027] However, modular computing systems (e.g., computing system 100) typically use multiple processing unit boards designed for a smaller number of processing units to achieve a computing system with a larger number of processing units. For example, to achieve a total of four processing units, a modular computing system may utilize two processing unit boards, each with two processing units, each originally designed for a computing system with only two processing units. In another example, to achieve a total of eight processing units, a modular computing system may utilize (i) four processing unit boards, each with two processing units and originally designed for a computing system with only two processing units, or (ii) two processing unit boards, each with four processing units and originally designed for a computing system with only four processing units. In any of these examples, a BIOS designed for a specific processing unit configuration (e.g., a single processing unit board with two processing units) typically does not function correctly on multiple processing unit boards. However, because the BIOS 104 of computing system 100 includes a resource table that defines the partitioning scheme for different processing unit configurations, BIOS 104 functions correctly.

[0028] Step 202 of the method 200 for operating the computing system includes collecting processing unit information. Generally, step 202 can occur when the computing system 100 is initially powered on or restarted. One or more processing units 102A-102n execute BIOS firmware to enable the processing unit to collect processing unit information, which typically includes communication with other processing units and / or processing unit boards. The processing unit executing the BIOS firmware may be referred to as the master processing unit / primary processing unit, or the processing unit of the master processing unit board / primary processing unit board. The processing unit information may be stored in one of the memory devices 108, the memory device of one of the processing units 102A-102n, the BIOS 104 (e.g., the memory device storing the BIOS firmware), the memory device of the peripheral device 116 (e.g., a hard disk drive, solid-state drive, etc.), or any other suitable location. The processing unit information typically includes any necessary information related to the currently used processing unit 102A-102n. For example, as described herein, each of the processing units 102A to 102n is electrically connected to one of the slots of the computing system 100. Therefore, the processing unit information may include information related to a specific number of processing units 102A to 102n, information related to the identification of the slot of the computing system 100 electrically connected to one of the processing units 102A to 102n, information related to the number of processing unit boards on which the processing units 102A to 102n are mounted, other information, or any combination thereof.

[0029] For example, if the computing system 100 includes eight slots (e.g., slots 0 to 7), the processing unit information may indicate that the computing system 100 includes four processing units electrically connected to slots 0, 1, 2, and 3. In another example (4S with a descent gauge), if the computing system 100 includes eight slots, the processing unit information may indicate that the computing system 100 includes four processing units electrically connected to slots 0, 4, 5, and 7. In yet another example, if the computing system 100 includes eight slots, the processing unit information may indicate that the computing system 100 includes eight processing units electrically connected to slots 0 to 7.

[0030] Step 204 of the method 200 for operating the computing system includes determining, at least in part, the current configuration of a plurality of processing units 102A to 102n of the computing system 100 based on processing unit information. Generally, a given configuration of the plurality of processing units 102A to 102n will include at least how many processing units are electrically connected to the computing system 100 and which slots these processing units are inserted into.

[0031] Step 206 of the method 200 for operating the computing system includes, at least in part, allocating resources of the computing system 100 among the plurality of processing units 102A-102n according to the current configuration of the plurality of processing units 102A-102n. The resources of the computing system 100 typically include a variety of devices and components, including one or more memory devices (e.g., memory device 108), one or more chipsets (e.g., controller hub chipset 110, northbridge chipset 112, southbridge chipset 114, etc.), one or more peripheral devices (e.g., peripheral device 116), bus segments (e.g., one or more bus segments 118) electrically connecting the processing units 102A-102n to these resources, other resources, and any combination thereof.

[0032] As described herein, BIOS 104 includes a resource table stored thereon that defines partitioning schemes for various configurations of the multiple processing units 102A to 102n. Each configuration partitioning scheme indicates how to allocate various resources of the computing system 100 among the processing units in each configuration. Generally, each configuration of processing units 102A to 102n has its own corresponding partitioning scheme. For example, if the current configuration of processing units 102A to 102n is determined to be a first configuration in step 204, this may result in resource partitioning according to the first partitioning scheme. If the current configuration is a second configuration that differs from the first configuration, it will typically result in resource partitioning according to the second partitioning scheme, which is different from the first partitioning scheme.

[0033] A second configuration that differs from the first configuration can occur in various scenarios. For example, a second configuration may be considered different from the first configuration when it includes a different number of processing units than the first configuration. In another example, a second configuration may be considered different from the first configuration when it includes the same number of processing units but with a different slot group. In yet another example, a second configuration may be considered different from the first configuration when it includes the same number of processing units as the first configuration but with a different number of processing unit boards.

[0034] However, in some implementations, there may be configurations that differ from each other, but the same partitioning scheme is defined in the BIOS 104 resource table. For example, in some implementations, all configurations with four processing units may have the same partitioning scheme, even if these four processing units are electrically connected to different slots and / or mounted on different processing unit boards.

[0035] In some implementations, partitioning the resources of the computing system 100 includes performing memory-mapped input / output (MMI / O) on all memory devices 108. This allocates the addressable space of the memory devices 108 to each processing unit 102A-102n and determines the addressable regions for accessing / operating any peripheral devices 116. In some implementations, partitioning the resources of the computing system 100 (additionally or alternatively) includes allocating each bus segment 118 to one or more of the plurality of processing units 102A-102n.

[0036] In many computing systems, during the first part of the power-on process after the computing system is powered on, the BIOS executes a POST (Power-On Post-Processing) procedure, which can be used to test various components of the computing system and set various parameters of the computing system, such as GPIO (general-purpose input / output) pin configurations and processor interconnect transmission parameters. The BIOS typically receives an indication of the computing system's identity (e.g., SKU or product name) from the BMC during the first part of the power-on procedure. In computing system 100, the BIOS 104 does not yet need to know the specific configuration of the multiple processing units 102A-102n. However, if the BIOS 104 does know that computing system 100 is a modular computing system with a variable number of processing units / processor unit boards, the BIOS 104 may still hang during the POST procedure. Therefore, in some cases, the method 200 for operating the computing system may include receiving an indication from the BMC 106 that computing system 100 is a modular computing system with a variable number of processing units and / or processing unit boards. This indication, combined with the processing unit information collected in step 202, allows for the determination of processing unit configurations and the allocation of resources. In some implementations, this instruction is received during the first part of the boot process (when the POST procedure is executed).

[0037] As described herein, the computing system 100 may include an FRU 120 coupled to a BMC 106. The FRU 120 may be configured to send the instruction (effectively used as the product name of the computing system 100) from the BMC 106 to the BIOS 104 during the first part of the power-on process. By using the FRU 120, the BIOS 104 is allowed to function properly with the modular computing system 100 without requiring any changes to the BMC 106 during manufacturing.

[0038] This can be used to facilitate UBA (Unified Board Abstraction) training and KTI (Keizer Technology Interconnect) initial training. UBA training is used for GPIO, TxEQ (transmitter equalization) tuning for Ultra Path Interconnect (UPI), PCIe (peripheral component interconnect express) bifurcation, and USB port configuration. These UBA configurations are all hardware-design dependent. For example, one SKU might set a GPIO to GPI, while another SKU might set it to GPO. Since the BIOS cannot reconfigure a GPIO to GPO, conflicts will occur due to hardware design incompatibility, leading to POST stall codes. In the UBA training examples, a 2S module can have a UBA setting based on a first hardware design, while an 8S module can have a different UBA setting based on a different hardware design; these configurations cannot be mixed. Therefore, a specific modular design FRU product name must be used, which differs from the product names of other non-modular design FRUs. If a modularly designed motherboard uses the product name of a non-modularly designed FRU during the UBA training phase, a stall code problem will occur during the UBA training phase.

[0039] KTI initial training includes configuring and training the CPU, specifically targeting UPI. During this stage, the CPU firmware (e.g., pcode) determines whether to boot in 2S / 4S / 8S mode based on hardware straps. This means that even if the CPU is installed in an 8S module, the pcode will only boot in 2S mode. The BIOS can only determine the number of CPUs based on the pcode's (CPU firmware) output. Therefore, assuming the hardware actually uses an 8S module and the hardware straps are configured for 8S module booting, if there are no UPI faults causing KTI downgrading, the BIOS will recognize the hardware as 8S boot. "KTI downgrading" means that although the hardware provides eight CPUs for BIOS training in 8S booting, due to hardware faults in some UPIs, the BIOS must disable some UPI ports and CPUs to conform to Intel's KTI training model. Therefore, how the BIOS determines the number of slots after KTI training is crucial. If the number of slots in the 8S example is downgraded to 4S, the BIOS should use the 4S resource table instead of the 8S one. Using a mismatched resource table will also cause boot failure. This example method allows the BIOS to know the actual number of slots to load the resource table, rather than automatically using a random configuration.

[0040] In some implementations, the computing system 100 is configured to re-partition resources in real time if one of the processing units 102A to 102n becomes undetectable. A processing unit may become undetectable due to a failure in the processing unit itself, the processing unit board on which it is mounted, the slot electrically connected to the processing unit, or any processor interconnects connecting the processing unit to other processing units. In these implementations, the method 200 for operating the computing system may also include optional steps 212, 214, and 216.

[0041] Step 212 includes determining that one of the processing units 102A to 102n is undetectable. In some implementations, step 212 includes receiving an indication from BMC 106 that one of the processing units 102A to 102n has become undetectable. In other implementations, BIOS 104 (and / or the processing unit executing BIOS firmware) directly determines that one of the processing units 102A to 102n has become undetectable.

[0042] Step 214 includes determining the updated configuration of the processing units, which may include receiving updated processing unit information from BMC 106 and determining the updated configuration of the remaining processing units 102A to 102n. Step 216 includes reallocating the resources of the computing system 100 based on the updated configurations of the multiple processing units 102A to 102n. Therefore, this process allows the resources of the computing system 100 that were initially allocated to now undetectable processing units to be reallocated to different processing units for their use, rather than being left unused.

[0043] In some implementations, the resource reallocation of the computing system 100 after one of the processing units 102A-102n has become undetectable includes reallocating the bus segments 118 originally allocated to the undetectable processing units 102A-102n within the remaining processing units 102A-102n. In some implementations, the resource reallocation of the computing system 100 after one of the processing units 102A-102n has become undetectable includes reallocating the addressable space of the memory devices 108 originally allocated to the undetectable processing units 102A-102n within the remaining processing units 102A-102n, so that no unused addressable space is left.

[0044] In some implementations, after one of the processing units 102A to 102n becomes undetectable, BIOS firmware can be executed for debugging. Because BIOS 104 can adjust the undetectable processing unit and reallocate resources in real time, BIOS 104 can perform a more detailed debugging process.

[0045] In these implementations, the method 200 for operating the computing system may include optional steps 222, 224, and 226. Step 222 includes determining which slot an undetectable processing unit among the processing units 102A-102n is electrically connected to. Step 224 includes determining whether any processor interconnects electrically connected to the undetectable processing unit and / or the slot of the undetectable processing unit are faulty. Step 226 includes storing an event log in a memory device of the computing system 100, which may include one of the memory devices 108, the memory device of one of the processing units 102A-102n, the BIOS 104 (e.g., a memory device storing BIOS firmware), the memory device of the peripheral device 116 (e.g., a hard disk drive, solid-state drive, etc.), or stored in any other suitable location. The event log typically includes at least the identity of the slot of the undetectable processing unit and the identity of any faulty interconnects electrically connected to the undetectable processing unit and / or the slot of the undetectable processing unit. In some cases, the event log includes a complete record of each processor interconnect electrically connected to each processing unit 102A to 102n.

[0046] This exemplary modular BIOS allows for the determination of the number of detectable CPUs and allows for comparison with the order based on product name information. The exact correct hardware configuration is known on the UPI. Therefore, the 8S has 4 UPIs, the 4S has only 3 UPIs, and the modular 2S board has only 1 UPI on its respective motherboard. If there are problems with UPI downsizing or some CPUs cannot be detected, a FRU product name mismatch can occur. For example, if the 8S has the FRU product name 8S but the number of slots is 4, it indicates a KTI downsizing problem in the tested system, and the tested system is a so-called downsized 4S. Based on previous Intel troubleshooting experience, some root causes are difficult to determine because the CPU cannot be detected, or because the BIOS ultimately only knows the number of slots, leading to problems with specific UPI ports. In the case of a downsized 4S, if the BIOS only knows 4S, it is insufficient to know whether a CPU is not installed, whether a specific UPI port cable is damaged, or whether there is a pcode problem based on issues in KTI training. This exemplary method compares the number of slots with the FRU product name to identify anomalies in the hardware configuration. Therefore, a downgraded configuration can boot successfully because the number of slots is based on the port resource table. However, this does not allow the user to know the exact root cause of the downgrade problem. Therefore, the second feature is to use the number of slots, the FRU product name, and the number of UPIs to determine if the hardware configuration is as expected. For example, if only 4 CPUs are actually detected in an 8S test system with the product name 8S FRU, then the 8S 4UPI configuration is used to report the unconnected UPI ports to Oemtype2 via a bitmap and to send critical error logs on specific UPI ports to the BMC's system event log (SEL). For the CPU, a bitmap is available before and after the BIOS disables CPU / UPI bitmap information due to so-called KTI downgrade, to determine the CPU layout. Based on this logic, these bitmaps can be used to draw a schematic diagram including the hardware configuration. If these disabled UPI ports are close to certain specific housings or sleds in a modular design platform, it can be inferred that the problem is more likely related to a specific housing or sled. If these disabled CPUs are concentrated near a specific location of a particular CPU, it can be inferred that the problem is related to a CPU that was not properly installed. More importantly, even if all CPUs and UPIs are detectable, if some UPI ports are found to have UPI Link slowdowns (e.g., some UPI channels are dropped), it can be inferred that there is a quality problem with a certain UPI cable. At this point, the supplier can be notified to improve the quality control of their UPI cables.In summary, this exemplary method helps in the triage and debugging of problems on modular platforms.

[0047] Example resource tables for 4S and 2S configurations are as follows: Figures 3A to 3B As shown. Figures 3A to 3B The resource table in the table can be used for 4S / 2S porting that is compatible with 4S / 2S configurations that are downsized. Figures 3A to 3B The resource tables display the bus port configuration and MMIO-L port configuration for each CPU in each chassis or sled. The modular product name is set to the default value. The resource tables ensure that the port configurations of the bus, MMIO-L, memory-mapped input / output-high (MMIO-H), and I / O resources used by the module are bootable under 32S / 16S / 8S / 4S / 2S. A single modular product name can be used to control multiple modular SKUs, as other features and port configurations can be determined based on the number of slots to access the appropriate resource table.

[0048] This example method can be used to handle all manufacturing scenarios involving different modular components with a single product name. Taking Intel's EGS platform as an example, it has five stable PCIe slots 0-4, labeled PE0, PE1, PE2, PE3, and PE4. The bus resources corresponding to each bus can be found in [reference needed]. Figure 4A The table shown. Figure 4AThis shows the bus numbering deployment under a 4S 2-segment configuration based on the CPU's Integrated I / O stack. Only one PE (e.g., PE1) is allocated, resulting in 91 bus numbers. Unused PEs (e.g., PE0, PE2, PE3), even though not connected to any PCIe devices, are each allocated 2 bus numbers. For PEx devices, at least one bus number must be allocated to support SR-IOV (single root I / O virtualization), so each PEx requires an additional bus number. Therefore, even unused PEs require 2 bus numbers. Additional bus number allocations are needed to support hot-plug functionality, resulting in a total of 3 bus numbers allocated. In this example, SR-IOV is enabled, but hot-plugging is disabled, so only 2 bus numbers are needed. DINO-D (Data Streaming Accelerator), DINO-I (In-memory database Analytics Accelerator), DINO-N (North Peak), and DINO-O (Out-of-Band Manageability Services Module) are Intel's silicon intellectual property (IP). Each DINO requires a configuration of 5 bus numbers, for a total of 20 bus numbers per CPU. Due to the enabling of multiple segments, 3 bus numbers are reserved, with the last slot in each segment allocated to either CPU1 or CPU3 (counting from 0). To ensure that each CPU has the same configuration, we have reserved 3 bus numbers for all CPUs. The UBOX (Utility Box) also requires a 2-bus-number allocation.

[0049] If the host detects that only two CPU sockets are in use, the BIOS will automatically switch to... Figure 4B The bus table shown. Figure 4BThis is the bus numbering deployment table for the CPU IIO stack in a 2S 2-segment configuration. In this configuration, each CPU has an allocation of 256 bus numbers. In the exemplary 2S M1 motherboard process, two PCIe cards are tested, meaning PE0 and PE1 are available for PCIe device resource allocation. In this example, PE0 is allocated 110 bus numbers, and PE1 is allocated 111 bus numbers. Both the 2S M1 motherboard process configuration and the 4S M3 server-grade configuration are compatible with the same BIOS firmware to determine the number of CPUs. Even in the case of KTI downgrading, such as 4S CPU loss due to UPI issues (i.e., the so-called "downgraded 2S configuration"), even downgraded to 2S, 4S PE1 only requires an allocation of 91 bus numbers. PE1 still has an allocation of 110 bus numbers, more than the 91 bus numbers allocated to PE1 in 4S. Therefore, allocating bus resources by the number of slots can handle both MFG configurations and KTI downgrading scenarios.

[0050] Figure 4C The table shows the MMIO-L allocation for CPU0 in segment 4S 2. In this example, the direct media interface (DMI) requires at least 88M. For stable PCIe, PE1 requires 288M, while other PEs (e.g., PE0, PE2, PE3, PE4) are allocated only 4M each. For DINO, each device requires 8M, so a total of 32M is allocated. The reserved bus has no MMIO-L resource requirement and is therefore allocated 0M. UBOX is allocated 8M of resources.

[0051] Figure 4D The table shows the MMIO-L allocation for CPU1 in the 4S 2 segment. For the exemplary 4S 2 segment, the CPU1 configuration is slightly different because... Figure 4D The table does not contain DMI. However, for the same data structure, 4M must still be allocated to comply with Intel's RC reference code rules.

[0052] Figure 4E A table summarizing the MMIO-L allocation of PE1 on an exemplary 4S 2 segment for each CPU is displayed. Figure 4F It is the MMIO-L resource allocation table for each CPU in the 2S 2 segment. Figure 4G The MMIO-L resource allocation table for CPU0 in segment 2S 2 is shown.

[0053] Therefore, the basic logic of bus allocation also applies to MMIO-L allocation. For example, for PE1, a 2S 2-segment only needs to allocate 316M of MMIO-L resources. For a 4S 2-segment, 280 or 288M is required (depending on the CPU location). Therefore, 4SPE1 can use 280M of MMIO-L resources, and even a downsized 2S has an allocation of 320M. This ensures that MMIO-L resources do not exceed the maximum value, and this method allows for handling MFG 2S M1 configurations and downsized 2S in MMIO-L allocation. The same logic for MMIO-L can be applied to MMIO-H and IO resources. Furthermore, although the examples above involve 2S and 4S, these principles can be applied to other configurations, such as 8S / 16S / 32S and other numbers of slots.

[0054] Although the disclosed embodiments have been illustrated and described with respect to one or more implementations, equivalent substitutions and modifications will be made or understood by those skilled in the art upon reading and understanding this specification and the accompanying drawings. Furthermore, while a particular feature of the invention may be disclosed only with respect to one of several implementations, such feature may be combined with one or more other features of other implementations, which may be desirable and advantageous for any given or particular application.

[0055] While various embodiments of this disclosure have been described above, it should be understood that they are by way of example only and not as limiting. Many changes may be made to the disclosed embodiments based on this disclosure without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the embodiments described above. Rather, the scope of this disclosure should be defined by the following claims and their equivalents.

[0056] Symbol Explanation

[0057] 100: Computing System

[0058] 102A, 102n: Processing units

[0059] 104: Basic Input / Output System (BIOS)

[0060] 103: Processor Interconnect

[0061] 106: Baseboard Management Controller (BMC)

[0062] 108: Memory devices

[0063] 110: Controller Hub Chipset

[0064] 112: Northbridge chipset

[0065] 114: Southbridge chipset

[0066] 116: Peripheral devices

[0067] 118: Bus segment

[0068] 120: Field replaceable unit (FRU)

[0069] 200: Methods for operating the computing system

[0070] 202, 204, 206, 212, 214, 216, 222, 224, 226: Steps

Claims

1. A computing system, comprising: Baseboard management controller (BMC); Multiple processing units are electrically connected to the BMC; and A basic input / output system (BIOS) chip, on which BIOS firmware is stored; During the power-on process of the computing system, one or more of the processing units are configured to execute the BIOS firmware to: Collect information from a processing unit; At least in part, the current configuration of the processing units is determined based on the processing unit information; and The computing system's resources are divided among the processing units, at least in part, based on their current configuration.

2. The computing system as described in claim 1, wherein, The processing unit information includes a number of processing units, an identifier of a plurality of slots in the computing system to which each of the processing units is electrically connected, a number of a plurality of processing unit boards to which the processing units are allocated, or any combination thereof.

3. The computing system as described in claim 1, wherein, The resources of the computing system include at least (i) multiple memory devices, (ii) one or more chipsets, (iii) one or more peripheral devices, (iv) one or more bus segments electrically connecting the processing units to the memory devices, the one or more chipsets and the one or more peripheral devices, or (v) any combination of (i) to (iv).

4. The computing system as described in claim 3, wherein, Dividing the one or more bus segments involves assigning each of the one or more bus segments to one or more processing units among the processing units.

5. The computing system as described in claim 4, wherein, In response to one of the processing units becoming undetectable during operation of the computing system, one or more other processing units are configured to execute the BIOS firmware to reassign the bus segment allocated to the undetectable processing unit to one of the remaining processing units.

6. The computing system as described in claim 1, wherein, The BIOS firmware stored on the BIOS chip includes a resource table that defines a partitioning scheme for the resources of the computing system for each of the multiple different configurations of the processing units.

7. The computing system as described in claim 1, wherein, The resources allocated to this computing system include: In response to the current configuration of these processing units being a first configuration, the resources are partitioned according to a first partitioning scheme; and In response to the fact that the current configuration of these processing units is a second configuration, the resources are divided according to a second partitioning scheme. The second configuration includes (i) a different number of processing units than the first configuration, (ii) the same number of processing units as the first configuration, but with different slot groups electrically connected to the processing units, or (iii) the same number of processing units as the first configuration, but with a different number of processing unit boards mounted on the processing units.

8. The computing system as described in claim 1, wherein, The partitioning of the resources of the computing system includes: partitioning the resources based on a first partitioning scheme according to the current configuration of the processing units, and wherein, in response to one of the processing units becoming undetectable during operation of the computing system, one or more other processing units are configured to execute the BIOS firmware to partition the resources based on a second partitioning scheme, which differs from the first partitioning scheme, according to an updated configuration of the processing units excluding the undetectable processing unit.

9. The computing system as described in claim 1, wherein, During a first part of the power-on process, one or more of the processing units are configured to execute the BIOS firmware to receive a first instruction from the BMC that a variable number of the processing units are electrically connected to the BMC, and wherein, during a second part of the power-on process, one or more of the processing units are configured to execute the BIOS firmware to collect processing unit information, determine the current configuration of the processing units, and allocate the resources of the computing system.

10. The computing system of claim 1, further comprising a plurality of slots and a plurality of interconnects electrically connecting each of the slots to at least one other slot, each of the processing units being electrically connected to one of the slots, and wherein, In response to one of the processing units becoming undetectable during operation of the computing system, one or more other processing units are configured to execute the BIOS firmware to: Determine which slot the undetectable processing unit is electrically connected to; Determine if any one or more of the interconnects electrically connected to the slot of the undetectable processing unit are faulty; and An event log is stored in a memory device of the computing system. The event log includes the identity of the slot of the undetectable processing unit and the identity of any faulty interconnects electrically connected to the slot of the undetectable processing unit.

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