Instruction translation method, instruction translation apparatus, system on chip, and computing device

Abstract

Embodiments of the present specification provide instruction translation methods, instruction translation devices, system on chips and computing devices, wherein the instruction translation method comprises: translating a target instruction block in a target program to a target instruction set architecture; if the target instruction block contains a jump instruction, determining a first branch instruction block to be jumped to and a second branch instruction block not to be jumped to after execution of the target instruction block, wherein the first branch instruction block and the second branch instruction block are instruction blocks under a source instruction set architecture; translating the first branch instruction block and the second branch instruction block to obtain a plurality of unexecuted instruction blocks under the target instruction set architecture, and caching the plurality of unexecuted instruction blocks for execution. The translation-execution switching operation that needs to be repeatedly performed due to frequent execution flow jumps is reduced, the performance loss caused by the switching translation and execution process is reduced, the overall translation and execution efficiency is improved, and the user experience is significantly improved.

Description

Technical Field

[0001] This specification relates to the field of electronic hardware technology, and in particular to an instruction translation method, instruction translation device, overlay system, and computing device. Background Technology

[0002] In modern computing environments, instruction set binary translation (IPC) technology is widely used in cross-architecture code execution scenarios, such as simulators, virtual machines, and compatibility layers. This technology enables direct execution of software across different architectures by translating machine code from one instruction set architecture to its corresponding code in real time, greatly improving software portability and hardware utilization.

[0003] However, each time the control flow changes during translation, execution must be paused to translate the new code block. This frequent switching leads to significant performance overhead, impacting program efficiency and consequently reducing user experience. This latency is particularly noticeable in interactive applications or high-performance scenarios.

[0004] Therefore, a more efficient method for instruction translation is urgently needed. Summary of the Invention

[0005] In view of this, embodiments of this specification provide an instruction translation method. One or more embodiments of this specification also relate to an instruction translation apparatus, a system-on-a-chip, a computing device, a computer-readable storage medium, and a computer program product, to address the technical deficiencies existing in the prior art.

[0006] According to a first aspect of the embodiments of this specification, an instruction translation method is provided, comprising: Translate the target instruction blocks in the target program to the target instruction set architecture; If the target instruction block contains jump instructions, then determine the first branch instruction block to which to jump and the second branch instruction block not to jump after the target instruction block is executed. The first branch instruction block and the second branch instruction block are instruction blocks under the source instruction set architecture. The first branch instruction block and the second branch instruction block are translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and these unexecuted instruction blocks are cached for execution.

[0007] According to a second aspect of the embodiments of this specification, an instruction translation apparatus is provided, the instruction translation apparatus including an instruction fetching unit, a translation unit, and a buffer unit; The translation unit is used to translate the target instruction blocks in the target program to the target instruction set architecture; The instruction fetch unit is used to determine, if the target instruction block contains a jump instruction, the first branch instruction block to which the target instruction block should jump and the second branch instruction block not to jump after the target instruction block is executed, wherein the first branch instruction block and the second branch instruction block are instruction blocks under the source instruction set architecture. The translation unit is also used to translate the first branch instruction block and the second branch instruction block to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and to cache the multiple unexecuted instruction blocks for execution through the cache unit.

[0008] According to a third aspect of the embodiments of this specification, a processor is provided, including the instruction translation apparatus of the second aspect.

[0009] According to a fourth aspect of the embodiments of this specification, an on-chip system is provided, comprising: The control unit and multiple on-chip components, including a processor with an instruction translation device running on the processor; The control unit is used to control and manage multiple on-chip components, the instruction translation device is used to implement the steps of the instruction translation method in the first aspect, and the processor is used to execute multiple unexecuted instruction blocks cached by the instruction translation device.

[0010] According to a fifth aspect of the embodiments of this specification, a computing device is provided, comprising: Memory and system-on-a-chip; The memory is used to store computer programs / instructions, and the system on-chip is used to execute the computer programs / instructions. When the computer programs / instructions are executed by the system on-chip, they implement the steps of the instruction translation method described above.

[0011] According to a sixth aspect of the embodiments of this specification, a computer-readable storage medium is provided that stores a computer program / instructions that, when executed by a processor, implement the steps of the above-described instruction translation method.

[0012] According to a seventh aspect of the embodiments of this specification, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the steps of the instruction translation method described above.

[0013] One embodiment of this specification translates a target instruction block in a target program to a target instruction set architecture. If the target instruction block contains jump instructions, a first branch instruction block to which the target instruction block will jump and a second branch instruction block not to jump are determined after the target instruction block is executed. The first and second branch instruction blocks are instruction blocks under the source instruction set architecture. The first and second branch instruction blocks are translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and these unexecuted instruction blocks are cached for execution. By pre-translating the first and second branch instruction blocks under the source instruction set architecture and caching them as multiple unexecuted instruction blocks under the target instruction set architecture, the repeated translation-execution switching operations required due to frequent control flow jumps are reduced, lowering the performance overhead caused by switching translation and execution processes. This improves overall translation and execution efficiency, significantly enhances user experience, effectively reduces pipeline stalls, and increases processor throughput and response speed. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating an instruction translation method provided in one embodiment of this specification; Figure 2 This is a flowchart illustrating the processing procedure of an instruction translation method provided in one embodiment of this specification; Figure 3 This is a schematic diagram of the structure of an instruction translation device provided in one embodiment of this specification; Figure 4 This is a block diagram of a system-on-a-chip provided in one embodiment of this specification; Figure 5 This is a structural block diagram of a computing device provided in one embodiment of this specification. Detailed Implementation

[0015] Many specific details are set forth in the following description to provide a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0016] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this specification. The singular forms “a,” “described,” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0017] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this specification, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0018] Furthermore, it should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in one or more embodiments of this specification are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0019] First, the terms and concepts used in one or more embodiments of this specification will be explained.

[0020] A cache unit is a high-speed, small-capacity random access memory located between the binary translator and main memory. It temporarily stores frequently accessed data and instructions to reduce the time spent accessing main memory and improve the efficiency of the binary translator. Cache units are divided into instruction cache (ICache) and data cache (DCache) to optimize instruction and data flows respectively.

[0021] Instruction Fetch Unit (IFU): Part of the binary translator, responsible for fetching the next instruction to be executed from the memory unit and sending it to the subsequent processing stage.

[0022] Program Counter (PC): A register that stores the address of the next instruction and guides the instruction fetch unit to retrieve the next instruction from where.

[0023] Dynamic Binary Translation (DBT) is a technique that translates binary code from a source instruction set architecture into equivalent code for a target instruction set architecture in real time during program execution. It enables programs to run on different hardware platforms by progressively translating and optimizing instruction blocks during execution, without requiring recompilation or modification of the source code. DBT typically combines caching mechanisms and optimization strategies to reduce translation overhead and improve execution efficiency, and is widely used in scenarios such as cross-platform compatibility, performance optimization, and migration of legacy software.

[0024] RISC-V (Reduced Instruction Set Computing-V) is an open-source reduced instruction set architecture designed to provide a modern, high-performance, and scalable infrastructure for designing processors and system-on-a-chip.

[0025] Guest program: refers to the program being translated. Usually, the instruction set of the program being translated is different from that of the host machine. For example, when translating a program written in x86 instruction set on a RISC-V chip machine, then RISC-V is the host machine, and the x86 program being translated is the guest program. In this context, the x86 instruction set is the guest instruction set. host: refers to the machine that executes the binary translator, such as a machine based on the RISC-V architecture. Translator: A program responsible for translating guest instructions into the host instruction set.

[0026] Basic Block: A basic block refers to a sequence of instructions with a single entry point and a single exit point. Jump instructions (including conditional jumps, direct jumps, indirect jumps, system calls, etc.) are exit instructions; after execution, the execution flow jumps to another location in the program. Other arithmetic and memory access instructions are non-exit instructions; after execution, their subsequent instruction sequences are executed sequentially.

[0027] With the rapid development of computer architecture, compatibility issues between different instruction set architectures have become increasingly prominent. Dynamic binary translation (DBT) technology has emerged to address this, aiming to solve cross-platform operation problems and enable programs to execute efficiently on the target instruction set architecture. DBT technology is widely used in virtualization, legacy software migration, and performance optimization, its core being how to maximize translation and execution efficiency while ensuring correctness.

[0028] Currently, the field of dynamic binary translation generally adopts a "translate as execution progresses" strategy, meaning the binary translator only translates instructions within the current execution path. This on-demand translation approach aligns with the program's actual execution path, effectively reducing unnecessary translation overhead while ensuring a high degree of consistency between the translation process and program execution. Furthermore, existing DBT technologies typically combine caching mechanisms and local optimization strategies to further improve translation and execution efficiency.

[0029] However, existing technologies are limited in that they only focus on translating the current execution path, ignoring potential optimization opportunities for paths that have not yet been executed. For example, when encountering conditional branch instructions, existing technologies typically only translate the branch path that is actually executed, while ignoring the branch paths that have not yet been executed. While this approach reduces the complexity of translation, it also prevents the optimization of instructions in unexecuted paths in advance, limiting overall performance improvements. Furthermore, when the program frequently involves branch jumps, traditional methods require repeated switching between translation and execution, resulting in additional performance overhead. This limitation in translation scope and switching overhead has become a significant bottleneck restricting further improvements in the efficiency of dynamic binary translation.

[0030] To address the aforementioned issues, this specification provides an instruction translation method, and also relates to an instruction translation device (i.e., a binary translator), a system-on-a-chip, a computing device, a computer-readable storage medium, and a computer program product, which will be described in detail in the following embodiments.

[0031] See Figure 1 , Figure 1 This is a flowchart of an instruction translation method provided in one embodiment of this specification. The method is applied to a binary translator, which runs on a processor. The binary translator includes an instruction fetch unit, a translation unit, and a cache unit, and specifically includes the following steps.

[0032] Step 102: Translate the target instruction blocks in the target program to the target instruction set architecture.

[0033] The processor is the core component of a computer system, responsible for executing instructions and processing data, and controlling other parts of the computer system, such as input / output devices, memory, and network interfaces. The processor performs a series of complex operations to complete specific processing tasks, including fetching instructions from storage, decoding instructions, executing instructions, accessing memory, and writing back results. Processors include, but are not limited to, Reduced Instruction Set Processors (RISC) and Complex Instruction Set Processors (CISP).

[0034] The target instruction block is the smallest unit of execution generated during dynamic binary translation, characterized by a single entry point and a single exit point. This means that each target instruction block has only one starting point (entry point), from which the program execution flow enters the instruction block; it also has only one ending point (exit point), where the program execution flow leaves the instruction block, proceeding to the next instruction block or jumping to other locations based on changes in control flow. This design simplifies control flow management and reduces the complexity of branch prediction.

[0035] The target program refers to a program that is currently executing and being dynamically translated during execution, rather than a program that has already been fully translated. This means that a portion of the program's code has been converted into instructions in the target instruction set architecture, while the remainder is still awaiting translation in the source instruction set architecture. In this context, the target instruction block refers to a sequence of instructions that has been successfully translated and is currently in the execution phase.

[0036] The target instruction set architecture (TFA) is the instruction set architecture supported by the target platform. It defines the instruction format, opcodes, and semantics that the processor can directly execute. The target TFA differs from the source TFA, for example, translating from ARM architecture to x86 architecture.

[0037] The source instruction set architecture is the instruction set architecture that the source program initially relies on, defining the format, opcodes, and semantics of instructions in the source program. The difference between the source instruction set architecture and the target instruction set architecture is the core issue of dynamic binary translation.

[0038] For example, during dynamic execution and translation, the binary translator first identifies the source instruction block that needs to be translated and translates it into a target instruction block under the target instruction set architecture. Once the translation is complete, the binary translator loads this target instruction block into the instruction cache for execution. The instruction fetch unit then fetches instructions starting from the entry point of the target instruction block, determines the location of the next target instruction block to be executed, and prepares to load the new instruction block to continue execution.

[0039] Step 104: If the target instruction block contains jump instructions, determine the first branch instruction block to which the target instruction block will jump and the second branch instruction block not to jump after the target instruction block is executed. The first branch instruction block and the second branch instruction block are instruction blocks under the source instruction set architecture.

[0040] The instruction fetch unit reads the instructions contained in the source program stored in the memory unit for the binary translator.

[0041] In the software implementation of the cache unit for the binary translator, the instruction blocks of the target architecture instruction set to be translated are stored in memory.

[0042] A jump instruction is a non-continuous instruction used to change the execution order of a program. Jump instructions allow the processor to skip certain instructions or jump to another location in the program to continue execution. Jump instructions are commonly used to implement logic such as conditional branches, loops, subroutine calls, and returns. For example, unconditional jump: `JMP label`, jumps to the label `label` regardless of the condition. Conditional jump: `JZ label`, jumps to the label `label` if the zero flag (Z) is 1. Subroutine call: `CALL function`, jumps to the function `function` and saves the return address. Subroutine return: `RET`, returns from the subroutine, restoring to the address of the instruction before the call.

[0043] The first branch instruction block is the block of instructions from the source instruction set architecture that needs to be executed after the target instruction block has been executed, should a jump instruction occur. The location of the first branch instruction block is determined by the target address of the jump instruction, and is usually the next logical unit on the jump path.

[0044] The second branch instruction block is the instruction block under the source instruction set architecture that needs to be executed after the target instruction block has been executed, if no jump instruction has occurred. The second branch instruction block is usually located immediately after the jump instruction and is the next logical unit on the sequential execution path.

[0045] For example, when executing a target instruction block, the binary translator first checks whether the target instruction block contains jump instructions. If it does, the translator determines the location of the first branch instruction block based on the type of jump instruction (conditional jump or unconditional jump) and the target address information. The first branch instruction block is the target after the jump from the target instruction block, and the binary translator needs to translate it into instructions under the target instruction set architecture for subsequent execution. Simultaneously, the binary translator also needs to determine the location of the second branch instruction block, i.e., the next instruction block if no jump occurs, and translate it into instructions under the target instruction set architecture.

[0046] In the embodiments described in this specification, by pre-determining the first branch instruction block to which the target instruction block will jump and the second branch instruction block not to which it will jump, the translation delay caused by changes in control flow is reduced, the processing efficiency of the jump path is optimized, thereby improving the smoothness of program execution and the response speed of dynamic translation.

[0047] Correspondingly, in one optional embodiment of this specification, step 102 includes the following specific steps: Parse the target instruction blocks in the target program that have been translated into the target instruction set architecture to obtain multiple instructions to be executed; Execute multiple instructions in sequence and record the changes in the program counter, whereby the program counter is used to record the memory address of the instruction to be executed. Accordingly, step 104 includes the following specific steps: If the change characteristics indicate that the memory address of the instruction to be executed has changed discontinuously, then the target instruction block is determined to contain a jump instruction. Obtain the jump address and non-jump address corresponding to the jump instruction from the program counter, and determine the first branch instruction block to jump to after the target instruction block is executed based on the jump address, and determine the second branch instruction block to not jump based on the non-jump address.

[0048] The program counter is a register in the binary translator that stores the address of the next instruction. It guides the instruction fetch unit to retrieve the next instruction from that address. This instruction address is the program counter value, which is the address of a memory location that points to the location where the next instruction is fetched.

[0049] In practical applications, when executing a target program, the first step is to parse the target instruction blocks that have been translated to the target instruction set architecture. This process involves reading and analyzing the contents of these instruction blocks from memory to extract a series of instructions to be executed. For example, in a dynamic binary translator, the binary translator reads instructions one by one, starting from the address pointed to by the current program counter (PC), and converts them into equivalent instructions under the target instruction set architecture. This step includes not only basic instruction translation but may also involve optimization operations such as register renaming and instruction scheduling to improve subsequent execution efficiency. Once parsing is complete, the binary translator obtains a set of instructions to be executed. Then, the binary translator executes these instructions sequentially according to their order in memory, recording the changes in the program counter in real time. These changes are crucial for determining the presence of jump instructions. If the program counter shows a discontinuous change in the memory address of an instruction, it indicates that the current target instruction block contains a jump instruction. At this point, the binary translator determines two branch paths based on the new address provided by the jump instruction: one is the path where the jump occurs (i.e., the first branch instruction block), and the other is the sequential execution path (i.e., the second branch instruction block). In this way, the binary translator can effectively manage changes in control flow, ensuring the smoothness and efficiency of program execution.

[0050] For example, when translating a target instruction block in a target program to a target instruction set architecture, the binary translator first parses the target instruction block and extracts multiple instructions to be executed. Then, the binary translator executes these instructions sequentially and records the changes in the program counter in real time. If the program counter shows a discontinuous change in the memory address of an instruction to be executed, it indicates that the current target instruction block contains a jump instruction. At this point, the binary translator obtains the jump address and non-jump address corresponding to the jump instruction from the program counter. Based on the jump address, it determines the first branch instruction block to jump to after the target instruction block is executed; based on the non-jump address, it determines the second branch instruction block to not jump to. One possible approach is to immediately update the branch prediction information once a discontinuous change is detected to facilitate the prefetching of subsequent instructions; another approach is to cache portions of both the first and second branch instruction blocks simultaneously to reduce future latency.

[0051] In the embodiments described in this specification, the target instruction block is parsed and the instructions to be executed are executed sequentially. At the same time, the changes in the program counter are monitored to determine whether there is a jump instruction. By determining whether there is a jump instruction, the binary translator can reduce the overhead of switching between translation and execution states during binary translation by translating the source program instruction block that the jump instruction may jump to in advance. Furthermore, by optimizing more source program instruction blocks at the same time, the quality of the translated target instruction set instruction block is improved, thereby increasing the execution efficiency of the translated instruction block on the processor.

[0052] Step 106: Translate the first branch instruction block and the second branch instruction block to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and cache multiple unexecuted instruction blocks for execution.

[0053] Unexecuted instruction blocks are sets of instructions from the target instruction set architecture that have undergone dynamic binary translation but have not yet been executed. These instruction blocks are generated based on the contents of the first-branch instruction block and the second-branch instruction block, and are intended for use in subsequent program execution.

[0054] Caching mechanisms are used to store translated but not yet executed instruction blocks, ensuring that these instruction blocks can be quickly loaded and executed when needed, thereby reducing latency caused by real-time translation. Caching can optimize program execution flow, especially in situations with frequent control flow changes, thus improving execution efficiency.

[0055] For example, after determining the first branch instruction block and the second branch instruction block, the binary translator first performs a dynamic binary translation of these two branch instruction blocks, converting them from the source instruction set architecture to instructions under the target instruction set architecture. After the translation is complete, two or more unexecuted instruction blocks are obtained and stored in the cache awaiting execution. Once the instruction blocks are successfully translated and cached, the processor can load the corresponding instruction blocks for execution immediately after the control flow is determined.

[0056] In the embodiments described in this specification, by translating the first branch instruction block and the second branch instruction block in advance and caching the results, the processor can respond quickly when the control flow changes, reducing the latency caused by instruction translation, improving the continuity and smoothness of program execution, and enhancing the overall system performance. This pre-translation and caching strategy is particularly suitable for applications with complex control flow, helping to improve their compatibility and operating efficiency across different platforms.

[0057] Correspondingly, in an optional embodiment of this specification, step 106 includes the following specific steps: Check if there are any unexecuted instruction blocks under the target instruction set architecture in the first branch instruction block, and check if there are any unexecuted instruction blocks under the target instruction set architecture in the second branch instruction block; If it exists, add the unexecuted instruction block to the set to be optimized; If it does not exist, add the first branch instruction block and the second branch instruction block to the set to be translated; Each instruction block in the set to be translated is translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture.

[0058] A query operation is a process by which the processor checks whether a specific instruction block has been translated into an unexecuted instruction block under the target instruction set architecture. This query typically involves searching existing records in the cache or memory to determine if a pre-translated instruction block exists.

[0059] The set to be optimized is a collection of unexecuted instruction blocks that already exist within the target instruction set architecture. These instruction blocks require further optimization to improve execution efficiency, but they have already completed the basic translation from the source instruction set architecture to the target instruction set architecture.

[0060] The set to be translated contains target instruction blocks that have not yet been translated into instructions under the target instruction set architecture. These instruction blocks need to undergo a dynamic binary translation process before they can be executed on the target platform.

[0061] In practical applications, after identifying the first and second branch instruction blocks, the next crucial step is to query these two blocks to check if they already exist in the unexecuted instruction blocks of the target instruction set architecture. This step aims to avoid repeatedly translating the same instruction blocks, thereby saving resources and speeding up processing. Specifically, the processor first queries whether a corresponding translated version of the first branch instruction block exists. If it does, the unexecuted instruction block is added to the optimization set for further optimization. The same process applies to the second branch instruction block. If the query results show that either branch instruction block has not yet been translated, it is added to the translation set, awaiting the next round of translation. It is worth noting that this query process typically relies on efficient caching mechanisms or index structures to ensure fast lookups. For example, in high-performance computing environments, hash tables can be used to accelerate the query process and reduce lookup time. Furthermore, to improve system flexibility, multi-level caching strategies can be introduced, allowing frequently used instruction blocks to be stored closer to the processor core, further reducing access latency. Through this query mechanism, the dynamic binary translator can intelligently manage the translation and optimization of instruction blocks, significantly improving the overall system response speed and execution efficiency.

[0062] For example, after determining the first branch instruction block and the second branch instruction block, the processor first queries these two branch instruction blocks to check if corresponding unexecuted instruction blocks that have already been translated into the target instruction set architecture exist. If the query result shows that an unexecuted instruction block corresponding to a certain branch instruction block already exists, then that unexecuted instruction block is added to the set to be optimized; the purpose of this is to provide a basis for further optimization in order to improve the efficiency of subsequent execution. If the query result shows that an unexecuted instruction block corresponding to a certain branch instruction block does not exist, then that branch instruction block is added to the set to be translated. For the translation process, one option is to use just-in-time (JIT) compilation technology to quickly translate each instruction block in the set to be translated; another implementation is to use a more complex optimization strategy to fully translate and optimize the instruction blocks, which, although time-consuming, can bring higher execution performance. After the translation is completed, multiple unexecuted instruction blocks are obtained, ready for use in the subsequent program execution flow.

[0063] In the embodiments described in this specification, the mechanism of querying before deciding whether translation is needed avoids repeatedly translating the same instruction blocks, thereby saving resources and speeding up processing. Furthermore, distinguishing between the set to be optimized and the set to be translated allows for flexible adjustment of optimization strategies based on actual needs, ensuring both execution efficiency and effective utilization of system resources, thus improving the overall system's response speed and performance.

[0064] Correspondingly, in one optional embodiment of this specification, translating each instruction block in the set to be translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture includes the following specific steps: Translate any instruction block within each instruction block and determine whether any instruction block contains a jump instruction; If included, then determine the third branch instruction block to which the user will jump and the fourth branch instruction block to which the user will not jump after the execution of any instruction block; Check if there is an unexecuted instruction block under the target instruction set architecture in the third branch instruction block, and check if there is an unexecuted instruction block under the target instruction set architecture in the fourth branch instruction block; If it exists, add the unexecuted instruction block to the set to be optimized; If it does not exist, add the third branch instruction block and the fourth branch instruction block to the set to be translated.

[0065] The third branch instruction block is the logical unit corresponding to the target address that the program will execute when a jump instruction is contained in a certain instruction block in the set to be translated. Its location is determined by the target address of the jump instruction and needs to be identified and prepared for subsequent processing.

[0066] The fourth branch instruction block is the next logical unit the program will continue to enter along the sequential execution path if a jump instruction is contained in an instruction block in the set to be translated, and the jump does not occur. This path usually follows the current instruction block and also needs to be identified for subsequent processing.

[0067] In practical applications, during the translation of instruction blocks in the set to be translated, the binary translator not only focuses on the translation of the current instruction block but also pays special attention to whether it contains jump instructions. Once a jump instruction is detected, the binary translator needs to further determine the third branch instruction block that might jump to after the execution of this instruction block and the fourth branch instruction block that does not jump. This process is similar to the processing of the first and second branch instruction blocks mentioned earlier, but it is recursive. That is, whenever a new branch path is found, it needs to be queried to see if it has already been translated. If the query result is negative, these new branch instruction blocks are added to the set to be translated, forming a nested translation flow. This design allows the dynamic binary translator to flexibly handle complex control flow structures, ensuring that all necessary instruction blocks are translated and ready for execution in a timely manner, no matter how complex the program's execution path is. At the same time, by maintaining a global set to be translated, the binary translator can start a new round of translation tasks at appropriate times, ensuring the effective utilization of system resources. For example, in a multi-threaded environment, different branch paths can be translated concurrently, thereby maximizing the utilization of hardware resources and shortening the overall translation time.

[0068] For example, when translating instruction blocks in the translation set, the binary translator first performs a translation operation on any instruction block and checks whether the instruction block contains a jump instruction. If a jump instruction is detected, it further determines two possible paths that the instruction block might jump to after execution: the third branch instruction block (the path when the jump occurs) and the fourth branch instruction block (the sequential execution path when the jump does not occur). Subsequently, the binary translator queries whether the third and fourth branch instruction blocks already exist in the unexecuted instruction blocks under the target instruction set architecture. If the query results show that the unexecuted instruction blocks corresponding to these branch instruction blocks already exist, they are added to the set to be optimized for subsequent optimization processing; if the query results show that these branch instruction blocks have not yet been translated, they are added to the set to be translated, waiting for the next round of translation. This process has a nested characteristic: whenever an instruction block in the translation set is translated and a new branch instruction block is found, these new branch instruction blocks are dynamically added to the set to be translated, forming a recursive translation process until all branch paths have been translated.

[0069] In the embodiments described in this specification, by explicitly distinguishing between paths where jumps occur and sequential execution paths where jumps do not occur, the binary translator can comprehensively cover all possible control flow branches, ensuring that each path is translated and cached in a timely manner. This approach not only improves support for complex control flows but also significantly reduces translation latency caused by path switching, enhancing the system's flexibility and operational efficiency.

[0070] Correspondingly, in one optional embodiment of this specification, after translating each instruction block in the set to be translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture, the following specific steps are further included: Delete each instruction block from the set to be translated and check whether the set to be translated is empty; If not, then return to translate each instruction block in the set to be translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture.

[0071] Removing instruction blocks from the translation set means removing translated instruction blocks from the set after all instruction blocks within it have been translated. This operation ensures that the set contains only unprocessed instruction blocks, avoids duplicate translations, and optimizes memory usage.

[0072] Verifying whether the set to be translated is empty involves checking if there are any unprocessed instruction blocks in the current set. This step is crucial for controlling the translation process, as it determines whether translation operations should continue.

[0073] In practical applications, after translating a specific instruction block and obtaining multiple unexecuted instruction blocks under the target instruction set architecture, the binary translator enters a cleanup phase. This involves deleting translated instruction blocks from the translation set and verifying whether the translation set is empty. This step is crucial for maintaining efficient system operation. First, deleting translated instruction blocks frees up valuable memory resources, preventing performance degradation due to excessive unused data occupying space. Second, verifying the state of the translation set determines the next step: if the set is empty, it means all instruction blocks requiring translation have been translated, and the optimization phase can begin; otherwise, it means there are still unprocessed instruction blocks, requiring a return to the translation process. To ensure the efficiency of this process, various strategies can be employed to manage the translation set. For example, elements in the set can be sorted based on the importance or expected execution frequency of the instruction blocks, prioritizing those on critical paths. Furthermore, predictive algorithms can be used to identify potentially high-priority instruction blocks in advance, enabling appropriate selection under resource constraints. Through such meticulous management and scheduling, the dynamic binary translator can maintain good performance in complex application scenarios.

[0074] For example, after translating each instruction block in the set to be translated and obtaining multiple unexecuted instruction blocks under the target instruction set architecture, the binary translator first performs a cleanup operation, that is, deleting each translated instruction block from the set to be translated. Then, the binary translator checks whether the set to be translated is empty. If the set to be translated is not empty, it means that there are still unprocessed instruction blocks, so it returns to the previous step to start a new round of translation, that is, translating each instruction block in the set to be translated again to obtain more unexecuted instruction blocks under the target instruction set architecture. This loop mechanism ensures that all instruction blocks that need to be translated are systematically processed until the entire set to be translated becomes empty. In this way, complex control flow and branch paths can be effectively managed, ensuring that each newly discovered branch instruction block is properly added to the set to be translated and eventually translated.

[0075] In the embodiments described in this specification, the binary translator implements a self-sustaining cyclic translation mechanism by deleting the processed instruction blocks and verifying whether the set to be translated is empty after each instruction block translation is completed. This mechanism not only ensures that all instruction blocks can be systematically translated into instructions under the target instruction set architecture, but also avoids repetitive work and resource waste, improving overall translation efficiency and system response speed. Furthermore, this method is particularly suitable for programs with complex branching structures, enhancing the system's flexibility and adaptability.

[0076] Correspondingly, in one optional embodiment of this specification, after deleting each instruction block from the set to be translated and verifying whether the set to be translated is empty, the following specific steps are further included: If so, based on the program counter, obtain multiple jump-related instruction blocks corresponding to the target instruction block from the set to be optimized; The target instruction block is associated with multiple jump-related instruction blocks for optimization.

[0077] After deleting each instruction block from the set to be translated and verifying that the set is empty, if the set is confirmed to be empty, it indicates that all instruction blocks requiring translation have been translated. Next, the binary translator, based on the program counter, retrieves multiple jump-related instruction blocks corresponding to the target instruction block from the set to be optimized. Jump-related instruction blocks refer to a series of instruction blocks connected to the current target instruction block via jump instructions, and these instruction blocks have direct or indirect execution path dependencies.

[0078] Optimizing the target instruction block along with multiple jump-related instruction blocks means not only optimizing individual instruction blocks but also considering the inter-references and dependencies between them, thus achieving a deeper level of optimization. This optimization method can improve the accuracy of instruction prediction, reduce jump latency, and enhance overall execution efficiency. Since there may be frequent data exchanges and control flow dependencies between jump-related instruction blocks, optimization can make these blocks execute more efficiently, resulting in better performance.

[0079] In practical applications, after confirming that the set to be translated is empty, the next step is to obtain multiple jump-related instruction blocks corresponding to the target instruction block in the set to be optimized based on the program counter, and then perform correlation optimization on them. This process emphasizes the mutual reference and dependency relationships between instruction blocks, achieving deeper optimization by comprehensively considering the instruction blocks on the entire jump chain. Since there may be frequent data exchanges and control flow dependencies between jump-related instruction blocks, optimizing only a single instruction block often fails to achieve good results. Therefore, correlation optimization becomes one of the key steps in improving system performance. For example, when performing constant propagation and folding, optimization can be performed not only on constant expressions within a single instruction block, but also by sharing and transmitting optimization information across multiple related instruction blocks, thereby eliminating more redundant operations. Furthermore, correlation optimization can help improve instruction scheduling by adjusting the execution order between different instruction blocks to reduce pipeline stalls and increase instruction throughput. It is worth mentioning that this optimization method is particularly suitable for programs with complex branching structures, enhancing not only the system's flexibility and adaptability but also significantly improving the overall efficiency and stability of program execution.

[0080] For example, after determining that the set to be translated is empty, the binary translator uses information from the program counter to identify multiple jump-related instruction blocks in the set to be optimized that are associated with the current target instruction block. The binary translator then performs association optimization on these instruction blocks. For instance, for a group of instruction blocks interconnected by jump instructions, the optimization process might adjust the instruction order to reduce the number of jumps, or merge similar code segments to reduce execution overhead. Furthermore, the binary translator might optimize register allocation and data transfer paths based on the dependencies between these instruction blocks to speed up execution. A key advantage of association optimization is its ability to transcend the boundaries of a single instruction block, considering the instructions in the entire jump chain as a whole, thereby achieving more efficient execution path planning and resource utilization.

[0081] In the embodiments described in this specification, by performing correlation optimization on the target instruction block and its associated jump instruction blocks, not only can each instruction block be optimized individually, but the mutual references and dependencies between instruction blocks can also be fully utilized to further improve the optimization effect. This approach significantly reduces latency caused by jumps, improves the accuracy of instruction prediction and execution efficiency, making the program run more smoothly and respond faster. Through this method, the system can maintain efficient execution even under complex control flows, enhancing overall performance and user experience.

[0082] Correspondingly, in an optional embodiment of this specification, after translating the first branch instruction block and the second branch instruction block, the following specific steps are further included: Check whether there are any illegal instruction blocks in the first branch instruction block and the second branch instruction block; If it exists, check if the violation instruction block contains any unexecuted instruction blocks under the target instruction set architecture; If it does not exist, determine whether the execution path of the violation instruction block is an alternative path; If so, obtain the memory address of the violation instruction block; The successor instruction block is determined based on the memory address, where the successor instruction block is the instruction block under the source instruction set architecture that is executed after the violation instruction block. Translate the subsequent instruction block.

[0083] Non-compliant instruction blocks refer to instruction blocks discovered during the translation process that do not conform to the target instruction set architecture specifications or pose potential execution risks. These instruction blocks may contain undefined operations, unsupported instruction formats, or other issues that could lead to execution failure.

[0084] Alternative paths refer to other possible paths in the program execution flow besides the main execution path, including exception handling paths and error recovery paths. These paths are typically used to handle various abnormal situations that may occur during program execution.

[0085] A successor instruction block is an instruction block within the source instruction set architecture that follows the violation instruction block in the execution order. It represents the portion of the program that continues execution, regardless of whether the current instruction block contains a violation.

[0086] In practical applications, after translating the first and second branch instruction blocks, additional verification steps are required to ensure the absence of non-compliant instruction blocks. A non-compliant instruction block refers to an instruction block discovered during translation that does not conform to the target instruction set architecture specification or poses a potential execution risk. These blocks may contain undefined operations, unsupported instruction formats, or other issues that could lead to execution failure. During verification, if a non-compliant instruction block is found, it is necessary to further check whether an unexecuted instruction block already exists under the target instruction set architecture. If no corresponding unexecuted instruction block is found, it is necessary to determine whether the execution path of the non-compliant instruction block is an alternative path. If it is an alternative path, the memory address of the non-compliant instruction block is obtained, and its successor instruction blocks are determined based on this address—that is, those instruction blocks under the source instruction set architecture that immediately follow the non-compliant instruction block in execution order. Finally, these successor instruction blocks are translated to ensure that the program can continue execution smoothly even if a non-compliant instruction block is encountered. This approach not only improves the robustness and stability of the system but also enhances its support for complex control flows, enabling the program to execute reliably under various conditions. In this way, the system can maintain efficient execution even under complex control flows, enhancing overall performance and user experience.

[0087] For example, after translating the first and second branch instruction blocks, the binary translator first checks whether there are any illegal instruction blocks in these two branch instruction blocks. If an illegal instruction block is detected, it further queries whether the illegal instruction block already exists as an unexecuted instruction block in the target instruction set architecture. If no corresponding unexecuted instruction block exists, it needs to determine whether the execution path of the illegal instruction block is an alternative path. If it is an alternative path, the memory address of the illegal instruction block is obtained, and its successor instruction blocks are determined based on this address, that is, those instruction blocks in the source instruction set architecture that immediately follow the illegal instruction block in execution order. Next, the binary translator translates these successor instruction blocks to ensure that the program can successfully execute subsequent code even when encountering illegal instruction blocks.

[0088] Regarding the processing methods in the steps, one option is to prioritize a comprehensive check and translation of all relevant instruction blocks on the path when it is determined that the violating instruction block belongs to the alternative path; another approach is to dynamically adjust the translation strategy and take different optimization measures for different types of violating instruction blocks, such as ignoring certain warnings that do not affect the final result or using specific remedial measures to correct the problem.

[0089] In the embodiments described in this specification, by identifying and processing non-compliant instruction blocks in the first and second branch instruction blocks, particularly by determining whether they are alternative paths and translating their subsequent instruction blocks, the system ensures smooth operation even in the face of potential execution risks or incompatible instructions. This approach not only improves the robustness and stability of the system but also enhances its support for complex control flows, enabling the program to execute reliably under various conditions. Furthermore, this method helps to prevent and resolve potential problems during execution in advance, thereby improving user experience and overall system performance.

[0090] One embodiment of this specification translates a target instruction block in a target program to a target instruction set architecture. If the target instruction block contains jump instructions, a first branch instruction block to which the target instruction block will jump and a second branch instruction block not to jump are determined after the target instruction block is executed. The first and second branch instruction blocks are instruction blocks under the source instruction set architecture. The first and second branch instruction blocks are translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and these unexecuted instruction blocks are cached for execution. By pre-translating the first and second branch instruction blocks under the source instruction set architecture and caching them as multiple unexecuted instruction blocks under the target instruction set architecture, the repeated translation-execution switching operations required due to frequent control flow jumps are reduced, lowering the performance overhead caused by switching translation and execution processes. This improves overall translation and execution efficiency, significantly enhances user experience, effectively reduces pipeline pauses, and increases the throughput and response speed of the binary translator.

[0091] The following is in conjunction with the appendix Figure 2 Taking the instruction translation method provided in this specification in the application of binary dynamic translation as an example, the instruction translation method will be further explained. Among other things, Figure 2 This is a flowchart illustrating the processing steps of an instruction translation method provided in one embodiment of this specification, specifically including the following steps.

[0092] Step 202: Translate the first basic block.

[0093] Step 204: Execute the translated basic block.

[0094] Step 206: Has the program ended?

[0095] If not, proceed to step 208.

[0096] Step 208: Is the ending a branch condition instruction?

[0097] If not, proceed to step 210; if yes, proceed to step 212.

[0098] Step 210: Translate the next basic block.

[0099] Step 212: Translate and execute target A.

[0100] Step 214: Translation has not yet been performed for objective B.

[0101] Step 216: Translate the basic blocks.

[0102] Specifically, the translation of the basic blocks (target A and target B) begins with traversing the entry instruction (the first instruction) of the basic block, reading each instruction contained in the translated program file one by one, and translating each instruction into a Host instruction. If a conditional branch instruction (such as a jcc type instruction in x86) or a jump instruction (such as a jmp or call instruction in x86) is encountered, it indicates that the end of the basic block has been reached. Furthermore, errors encountered during the translation process (such as illegal instructions) can also cause the translation of the basic block to end. Subsequent steps will handle different translation termination cases.

[0103] Step 218: Is there a translation error and has the basic block not yet been executed?

[0104] Specifically, during the traversal in step 216, errors encountered while translating basic blocks are recorded. Because some speculative translation branches contain unsupported instructions (e.g., x86 libc functions determine which CPU-supported instruction set branch to execute based on the instruction set support information indicated in the CPUID), illegal instructions and other issues may occur during the translation of basic blocks. In step 218, the translation error status of the current basic block is assessed. If an error occurs in the translation of the current basic block, and the current basic block has not been executed and is not part of the path to be executed, the error is ignored, and the process proceeds directly to step 226.

[0105] Step 220: Is the ending a branch?

[0106] Specifically, in step 216, encountering conditional branch instructions and other jump instructions will terminate the translation of the current basic block. In step 220, it is necessary to distinguish the reason for the termination of the current translation. If the basic block translation ends with a conditional branch instruction, then it is necessary to proceed to step 222 to determine the two jump targets of the branch instruction; otherwise, proceed directly to step 226.

[0107] Step 222: Does the branch contain any untranslated targets?

[0108] Specifically, the branch instruction in step 220 contains two targets, which need further evaluation in step 222. If either jump target has not been translated, it needs to be added to the current set S to be translated. After processing, proceed to step 226.

[0109] Step 224: Add the untranslated target to the set S to be translated.

[0110] Specifically, the untranslated targets are added to the translation set S. This step adds the translation targets found in step 222 to the translation set S, with the PC of the target location as the key of the set.

[0111] Step 226: Is the set S to be translated empty?

[0112] Specifically, determine the state of the current set S to be translated. This step checks if the set is empty. If it is empty, it means all basic blocks to be translated have been processed, and proceed to step 230; otherwise, there are still basic blocks to be translated, and the process proceeds to step 228. Step 228: Extract target C from set S and translate it.

[0113] Specifically, one basic block to be translated is selected from the set of blocks to be translated, and the translation process proceeds to step 216. The selection of a target C to be translated can be based on the order of PC size or the order in which the basic blocks were added. However, it is not limited to these orders. Step 230: Optimize all translated basic blocks.

[0114] Specifically, all previously discovered and translated basic blocks are optimized. Typical optimizations include dead instruction removal, constant propagation, and constant folding. This step is not limited to these optimizations.

[0115] Step 232: Output the translated code block.

[0116] Specifically, the basic blocks discovered and translated in steps 216 to 230 are added to the translated code cache, awaiting execution.

[0117] Step 234: Obtain the next Host code to be executed after translation.

[0118] Through steps 202-234 above, by pre-translating and optimizing branch paths under the source instruction set architecture and caching these optimized instructions for subsequent execution, the efficiency of program execution across different instruction sets is significantly improved. This method not only reduces the repeated translation-execution switching operations required due to frequent control flow jumps, thus reducing the performance loss, but also improves instruction quality and execution efficiency by pre-optimizing code paths that have not yet been executed, thereby effectively shortening the overall program execution time. Furthermore, corresponding error handling mechanisms are designed for errors that may occur during the translation process, further ensuring the stability and reliability of program execution. This optimization strategy enables dynamic binary translation to exhibit higher efficiency in cross-platform compatibility and performance optimization, greatly enhancing the user experience.

[0119] Corresponding to the above method embodiments, this specification also provides embodiments of an instruction translation device. Figure 3 A schematic diagram of an instruction translation apparatus according to one embodiment of this specification is shown. Figure 3 As shown, the instruction translation device 300 includes a translation unit 310, an instruction fetching unit 320, and a buffer unit 330; Translation unit 310 is used to translate target instruction blocks in the target program to the target instruction set architecture; The instruction fetch unit 320 is used to determine, if the target instruction block contains a jump instruction, the first branch instruction block to which the target instruction block should jump and the second branch instruction block not to jump after the target instruction block is executed, wherein the first branch instruction block and the second branch instruction block are instruction blocks under the source instruction set architecture. The translation unit 310 is also used to translate the first branch instruction block and the second branch instruction block to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and cache the multiple unexecuted instruction blocks for execution through the cache unit 330.

[0120] In the embodiments described in this specification, in the instruction translation device, when the instruction fetch unit 320 encounters a jump instruction, it pre-determines the first branch instruction block and the second branch instruction block under the source instruction set architecture. The translation unit 310 then translates these two branches, and the cache unit 330 caches them as multiple unexecuted instruction blocks under the target instruction set architecture, thereby achieving pre-translation of code paths that have not yet been executed. This method avoids the repeated translation-execution switching operations required during frequent control flow jumps, reduces performance overhead, effectively reduces pipeline stalls, improves the throughput and response speed of the instruction translation device, and significantly enhances the user experience.

[0121] The above is a schematic scheme of an instruction translation device according to this embodiment. It should be noted that the technical solution of this instruction translation device and the technical solution of the above-described instruction translation method belong to the same concept. For details not described in detail in the technical solution of the instruction translation device, please refer to the description of the technical solution of the above-described instruction translation method.

[0122] Corresponding to the embodiments of the instruction translation method described above, this specification also provides embodiments of on-chip systems. Figure 4 This specification illustrates a schematic diagram of a system-on-a-chip (SoC) 400 according to an embodiment of the present specification. The SoC 400 includes, but is not limited to, a control unit 410 and multiple on-chip components 420. The multiple on-chip components 420 include a processor 4210, on which an instruction translation device 42110 runs. The instruction translation device 42110 running on the processor 4210 performs pre-translation of a source instruction set architecture program to obtain instruction blocks of a target instruction set architecture, and then runs them on the target instruction set architecture processor.

[0123] The control unit 410 is used to control and manage multiple on-chip components 420.

[0124] The instruction translation device 42110 is used to implement the steps of the above instruction translation method, and the processor 4210 is used to execute multiple unexecuted instruction blocks cached by the instruction translation device 42110.

[0125] The system-on-a-chip (SoC) 400 is a system-on-a-chip hardware device that integrates a control unit 410 and multiple on-chip components 420. It typically integrates a control unit 410, as well as a central processing unit, a digital signal processor, a processor, and input / output interfaces (I / O), among other on-chip components 420. The SoC 400 can improve performance, reduce power consumption, and decrease physical size, making it suitable for various scenarios such as mobile devices, IoT devices, embedded systems, and edge computing devices. The specific embodiments in this application do not limit the specific implementation of the SoC.

[0126] The control unit 410 is a core component of the system-on-a-chip 400, responsible for instruction decoding, execution flow control, and coordination with multiple on-chip components 420. The control unit 410 controls and manages the workflow of multiple on-chip components 420 by sending control signals, ensuring that each on-chip component can correctly complete its tasks in a predetermined order and logic.

[0127] Multiple on-chip components 420 are various functional hardware components in the system-on-a-chip 400, which work together to complete specific tasks or functions. The multiple on-chip components 420 may include, but are not limited to, a central processor, a digital signal processor, a processor, and input / output interfaces.

[0128] The above is an illustrative scheme of a system-on-a-chip (SoC) according to this embodiment. It should be noted that the technical solution of this SoC and the technical solution of the instruction translation method described above belong to the same concept. Details not described in detail in the SoC technical solution can be found in the description of the instruction translation method described above.

[0129] Corresponding to the above-described instruction translation method and system-on-a-chip embodiments, this specification also provides embodiments of computing devices. Figure 5 A schematic diagram of a computing device 500 according to one embodiment of this specification is shown. The computing device 500 includes, but is not limited to, a memory 510 and a system-on-a-chip 520.

[0130] The memory 510 is used to store computer programs / instructions.

[0131] The system-on-chip 520 is used to execute the following computer program / instruction, which, when executed by the system-on-chip 520, implements the steps of the above-described instruction translation method.

[0132] The computing device 500 is an electronic device with computing capabilities, capable of running various software programs to perform specific functions or tasks. The computing device 500 typically includes a memory 510 and hardware devices for performing tasks. In the embodiments described in this specification, the computing device 500 includes, but is not limited to, a system-on-a-chip 520 and a memory 510. The specific embodiments of this application do not limit the specific implementation of the computing device.

[0133] The memory 510 is a component in the computing device 500 used to store data and computer programs / instructions, and is generally divided into two types: volatile and non-volatile. Volatile memory (such as RAM) loses data after power is turned off and is mainly used for temporary storage of running programs and data; non-volatile memory (such as ROM and flash memory) can retain data after power is turned off and is used to store firmware and persistent data.

[0134] The above is an illustrative scheme of a computing device according to this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the instruction translation method described above belong to the same concept. For details not described in detail in the technical solution of the computing device, please refer to the description of the technical solution of the instruction translation method described above.

[0135] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0136] The computer program / instruction includes computer program code, which may be in the form of source code, object code, executable file, or some intermediate form.

[0137] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments in this specification are not limited to the described order of actions, because according to the embodiments in this specification, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments in this specification.

[0138] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0139] The preferred embodiments disclosed above are merely illustrative of this specification. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments described herein. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification. This specification is limited only by the claims and their full scope and equivalents.

Claims

1. An instruction translation method, comprising: Translate the target instruction blocks in the target program to the target instruction set architecture; If the target instruction block contains a jump instruction, then determine the first branch instruction block to which the target instruction block will jump and the second branch instruction block not to jump after the target instruction block is executed, wherein the first branch instruction block and the second branch instruction block are instruction blocks under the source instruction set architecture; The first branch instruction block and the second branch instruction block are translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and the multiple unexecuted instruction blocks are cached for execution.

2. The method according to claim 1, further comprising, after translating the target instruction block in the target program to the target instruction set architecture: Parse the target instruction blocks in the target program that have been translated into the target instruction set architecture to obtain multiple instructions to be executed; The plurality of instructions to be executed are executed sequentially, and the changes in the program counter are recorded, wherein the program counter is used to record the memory address of the instructions to be executed; If the target instruction block contains a jump instruction, then determining the first branch instruction block to which the target instruction block will jump and the second branch instruction block not to jump after the target instruction block is executed includes: If the change feature indicates that the memory address of the instruction to be executed has changed discontinuously, then the target instruction block is determined to contain a jump instruction. The jump address and non-jump address corresponding to the jump instruction are obtained from the program counter. Based on the jump address, the first branch instruction block to be jumped to after the target instruction block is executed is determined, and based on the non-jump address, the second branch instruction block to be non-jumped is determined.

3. The method according to claim 1, wherein translating the first branch instruction block and the second branch instruction block to obtain multiple unexecuted instruction blocks under the target instruction set architecture includes: Check if the first branch instruction block contains any unexecuted instruction blocks under the target instruction set architecture, and check if the second branch instruction block contains any unexecuted instruction blocks under the target instruction set architecture; If it exists, add the unexecuted instruction block to the set to be optimized; If it does not exist, then add the first branch instruction block and the second branch instruction block to the set to be translated; Each instruction block in the set to be translated is translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture.

4. The method according to claim 3, wherein translating each instruction block in the set to be translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture includes: Translate any instruction block in each instruction block and determine whether any instruction block contains a jump instruction; If included, then determine the third branch instruction block to which the execution of any of the instruction blocks will proceed and the fourth branch instruction block to which the execution will not proceed; Check whether the third branch instruction block contains any unexecuted instruction blocks under the target instruction set architecture, and check whether the fourth branch instruction block contains any unexecuted instruction blocks under the target instruction set architecture; If it exists, the unexecuted instruction block is added to the set to be optimized; If it does not exist, the third branch instruction block and the fourth branch instruction block are added to the set to be translated.

5. The method according to claim 3, after translating each instruction block in the set to be translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture, further comprising: Delete each instruction block from the set to be translated, and verify whether the set to be translated is an empty set; If not, then return to translating each instruction block in the set to be translated to obtain multiple unexecuted instruction blocks under the target instruction set architecture.

6. The method according to claim 5, after deleting each instruction block from the set to be translated and verifying whether the set to be translated is an empty set, further comprising: If so, based on the program counter, obtain multiple jump-related instruction blocks corresponding to the target instruction block from the set to be optimized; The target instruction block and the plurality of jump-related instruction blocks are subjected to association optimization processing.

7. The method according to claim 1, further comprising, after translating the first branch instruction block and the second branch instruction block: Verify whether there are any illegal instruction blocks in the first branch instruction block and the second branch instruction block; If it exists, check whether the violation instruction block contains an unexecuted instruction block under the target instruction set architecture; If it does not exist, then determine whether the execution path of the violation instruction block is an alternative path; If so, obtain the memory address of the violation instruction block; The successor instruction block is determined based on the memory address, wherein the successor instruction block is an instruction block under the source instruction set architecture whose execution order is after the violation instruction block; The subsequent instruction block is translated.

8. An instruction translation apparatus, comprising an instruction fetch unit, a translation unit, and a buffer unit; The translation unit is used to translate the target instruction block in the target program to the target instruction set architecture; The instruction fetch unit is configured to, if the target instruction block contains jump instructions, determine a first branch instruction block to which the target instruction block will be executed and a second branch instruction block not to be executed. The first branch instruction block and the second branch instruction block are instruction blocks under the source instruction set architecture; The translation unit is further configured to translate the first branch instruction block and the second branch instruction block to obtain multiple unexecuted instruction blocks under the target instruction set architecture, and cache the multiple unexecuted instruction blocks through the cache unit for execution.

9. A processor comprising the instruction translation apparatus of claim 8.

10. A system-on-a-chip, comprising: The control unit and multiple on-chip components, the multiple on-chip components including a processor, the processor having an instruction translation device running on it; The control unit is used to control and manage the plurality of on-chip components, the instruction translation device is used to implement the steps of the method according to claims 1 to 7, and the processor is used to execute a plurality of unexecuted instruction blocks cached by the instruction translation device.

11. A computing device, comprising: Memory and system-on-a-chip; The memory is used to store computer programs / instructions, and the system-on-a-chip is used to execute the computer programs / instructions, which, when executed by the system-on-a-chip, implement the steps of the method described in claims 1 to 7.

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