Off-chip DDR cache management method, system and related device

Abstract

The application provides an off-chip DDR cache management method, system and related equipment, which comprises the following steps: reserving off-chip DDR cache units for the storage space of a data packet multi-queue engine, dividing the storage space into a plurality of equal composite address blocks and constructing a global free list; allocating an initial composite address block for each message queue and constructing a dynamic linked list with head and tail pointers saved in a hardware register; when a data packet is enqueued, if the initial composite address block is full, a new composite address block is dynamically applied from the global free list, linked to the initial composite address block and the tail pointer is updated; when a data packet is dequeued, if the data packet in the target composite address block has been read empty, the target composite address block is automatically returned to the global free list and the head pointer is updated. The application solves the problems of low storage space utilization and high expansion cost of the traditional static allocation mechanism in the non-uniform flow scene, realizes global dynamic sharing and flow adaptive allocation of the DDR cache, and has low hardware overhead.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and in particular to an off-chip DDR cache management method, system and related equipment for a data packet multi-queue engine. Background Technology

[0002] The scalable unified computing architecture employs a hardware architecture with complete decoupling between the framework layer and the computing layer, relying on a microkernel cluster (UCC) to complete parallel task computation. (See also...) Figure 1 As shown in the dashed box, the Packet Multi-Queue Engine (PQ), as the core component of the queue management unit in the UCS framework layer, enables lock-free asynchronous message interaction between the UCC and the big core, and between the hardware acceleration module and the big core. It supports batch operations and multi-queue parallel scheduling, and adapts to the multi-dimensional expansion and flexible topology requirements of the UCS framework.

[0003] The existing data packet multi-queue engine has a hierarchical caching system, which includes on-chip high-speed cache and off-chip DDR large-capacity cache. When the internal dequeue cache storage space of PQ is exhausted, the inter-core interaction data packets to be transmitted are automatically overflowed to the off-chip DDR for persistent caching. This architecture has advantages such as simple hardware logic, high link stability and strong multi-topology adaptability, and can provide a high-speed communication foundation for heterogeneous multi-core chips.

[0004] In existing technical solutions, off-chip DDR cache units adopt a static average address allocation mechanism. However, in real-world commercial scenarios, the message queues of a multi-queue data packet engine naturally exhibit traffic imbalance characteristics. For example, in network forwarding scenarios, the traffic share of the control message queue is extremely low, while the traffic share of the data forwarding message queue is extremely high; in AI inference scenarios, the traffic difference between the weight parameter transmission queue and the intermediate result cache queue is significant. The traditional static average allocation method has the following technical drawbacks: (1) Low storage space utilization: Low-traffic queues occupy fixed address space for a long time, resulting in a large amount of idle storage resources; High-traffic queues are prone to insufficient space and packet blocking, and storage resources cannot be dynamically transferred. (2) Limited chip scalability: As the UCS cluster expands, the number of PQ message queues increases accordingly. Static allocation requires a large amount of redundant DDR space to be reserved in advance, resulting in high chip storage hardware costs. (3) Poor business adaptability: Fixed address allocation cannot dynamically adjust storage space according to business traffic fluctuations, making it difficult to cope with sudden large traffic data packet transmission scenarios and resulting in weak business fault tolerance.

[0005] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0006] This invention provides an off-chip DDR cache management method, system, and related equipment for a data packet multi-queue engine. The main objective of this invention is to solve the technical problems mentioned in the background section of the prior art.

[0007] The first aspect of this invention provides an off-chip DDR cache management method for a packet multi-queue engine, comprising: The storage space reserved for the packet multi-queue engine in the off-chip DDR cache unit is divided into several equally sized composite address blocks. Each composite address block includes multiple consecutive storage units, with the last storage unit used as a linked list pointer field and the remaining storage units used as packet storage fields. All the free composite address blocks are constructed into a global free linked list, and a dynamic linked list is maintained independently for each message queue of the data packet multi-queue engine based on the global free linked list. The head pointer and tail pointer of the dynamic linked list are stored in hardware registers, and the pointers of the middle nodes of the dynamic linked list are stored in the linked list pointer field of the composite address block. When the on-chip enqueue cache unit is full, causing data packets to overflow into the off-chip DDR cache unit, the data packets are sequentially written into the data packet storage field of the initial composite address block pointed to by the tail pointer of the current message queue. If the initial composite address block is full, a new composite address block is requested from the global free list, and the physical address of the new composite address block is written into the linked list pointer field of the initial composite address block as the intermediate node pointer. The tail pointer of the current message queue is updated to point to the new composite address block, and the sequential writing of the data packets continues. When there is free space in the on-chip dequeue buffer unit, the data packets are read sequentially from the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue. If all the data packets in the target composite address block have been read, the intermediate node pointer in the linked list pointer field of the target composite address block is read to obtain the physical address of the next level composite address block. The first pointer of the current message queue is then updated to point to the next level composite address block to continue reading the data packets sequentially. The target composite address block that has been read empty is returned to the global free linked list.

[0008] In an optional embodiment of the first aspect of the present invention, a single composite address block comprises 64 consecutive storage units to match the burst transmission characteristics of the 64-byte cache line of the off-chip DDR cache unit, wherein the first 63 of the storage units are used as the data packet storage field and the last storage unit is used as the linked list pointer field, forming a 63+1 embedded composite storage structure.

[0009] In an optional embodiment of the first aspect of the present invention, the composite address blocks in the global free list are arranged in ascending order of the physical address to form a unidirectional free list; when the target composite address block that has been read empty is returned to the global free list, the target composite address block that has been read empty is attached to the tail of the global free list by tail insertion, so as to reduce the physical addressing jitter of the off-chip DDR cache unit.

[0010] In an optional embodiment of the first aspect of the present invention, sequentially writing the data packets into the data packet storage field of the initial composite address block pointed to by the tail pointer of the current message queue includes: The number of remaining free storage units in the initial composite address block pointed to by the tail pointer of the current message queue is detected in real time. If there is a free cache unit in the initial composite address block, the data packet is written sequentially to the data packet storage field of the initial composite address block, and the write position is updated by the block-incrementing hardware offset logic to maintain continuous write timing.

[0011] In an optional embodiment of the first aspect of the present invention, sequentially reading the data packets from the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue includes: Combining the hardware offset progressive reading logic, the data packets in the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue are read sequentially, and the reading offset is updated synchronously. If the target composite address block is not completely read, the sequential reading continues.

[0012] In an optional embodiment of the first aspect of the present invention, the off-chip DDR cache management method further includes: The number of composite address blocks in the global free list is monitored in real time, and a warning threshold is preset. When the number of composite address blocks in the global free list is lower than the preset warning threshold, a pre-limiting operation is performed; When all the composite address blocks in the global free list are exhausted, a forced backpressure signal is sent to the enqueue interface of the data packet multi-queue engine to suspend the writing of the data packet.

[0013] In an optional embodiment of the first aspect of the present invention, the off-chip DDR cache management method further includes: The access boundaries between the data packet storage field and the linked list pointer field are predefined, and hardware isolation of read and write permissions is achieved by configuring an address mask. This restricts the data packet read and write operations between cores to the data packet storage field, preventing abnormal data packets from flushing or tampering with the intermediate node pointers stored in the linked list pointer field.

[0014] The second aspect of the present invention provides a cache management system for implementing the off-chip DDR cache management method described in any one of the first aspects of the present invention. The cache management system includes an on-chip dequeue cache unit, an on-chip enqueue cache unit, an off-chip DDR cache unit, a dynamic address block management module, and a linked list maintenance module. The dynamic address block management module is used to divide the storage space reserved by the off-chip DDR cache unit for the data packet multi-queue engine into several equal-sized composite address blocks, construct a global free linked list, and respond to address block request instructions when writing data packets and address block reclamation instructions when reading data packets, thereby completing the global dynamic scheduling of the storage resources of the off-chip DDR cache unit. In this module, a single composite address block includes multiple consecutive storage units, with the last storage unit used as a linked list pointer field and the remaining storage units used as data packet storage fields. The linked list maintenance module is used to maintain a dynamic linked list independently for each message queue of the data packet multi-queue engine. The head pointer and tail pointer of the dynamic linked list are stored in hardware registers, and the pointers of the intermediate nodes of the dynamic linked list are stored in the linked list pointer field of the composite address block.

[0015] In an optional embodiment of the second aspect of the present invention, the cache management system is compatible with the native AXI bus and task handshake protocol of the scalable unified computing architecture, and the data packet multi-queue engine has lock-free asynchronous interaction and multi-queue parallel scheduling capabilities.

[0016] A third aspect of the present invention provides a network communication device, the network communication device comprising: a memory and at least one processor, the memory storing instructions, and the memory and the at least one processor being interconnected via a line; The at least one processor invokes the instructions in the memory to cause the network communication device to execute the off-chip DDR cache management method as described in any one of the first aspects of the present invention.

[0017] Beneficial Effects: This invention provides an off-chip DDR cache management method, system, and related devices for a multi-queue packet engine. The method includes dividing the storage space reserved for the multi-queue packet engine in the off-chip DDR cache unit into equal-sized composite address blocks; and constructing a minimal hardware linked list for each message queue, storing only the head and tail pointers in hardware registers, with the intermediate node pointers embedded within the composite address blocks. When a packet is enqueued, if the current address block is full, a new block is dynamically requested from the global free list and linked; when a packet is dequeued, if the current address block is empty, it is automatically returned to the free list. This invention solves the problems of low storage space utilization and high expansion costs in unbalanced traffic scenarios using traditional static allocation mechanisms, achieving global dynamic sharing and traffic adaptive allocation of the DDR cache with extremely low hardware overhead. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating an embodiment of a scalable unified computing architecture employing a framework layer, as exemplified by the present invention. Figure 2 This is a schematic diagram of an embodiment of an off-chip DDR cache management method for a data packet multi-queue engine, as exemplified by the present invention; Figure 3 This is a schematic diagram of an embodiment of a composite address block according to an exemplary method of the present invention; Figure 4 This is a schematic diagram of an embodiment of a cache management system according to an exemplary method of the present invention; Figure 5 This is a schematic diagram of an embodiment of a network communication device according to an example of the present invention. Detailed Implementation

[0019] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] The first aspect of this invention provides an off-chip DDR cache management method for a packet multi-queue engine. The core design idea of ​​this invention is to optimize the address allocation mechanism of the off-chip DDR cache unit while being fully compatible with the existing Scalable Unified Computing Architecture (UCS) framework, without changing the core scheduling logic of the packet multi-queue engine, and without affecting the lock-free asynchronous interaction and multi-queue parallel scheduling capabilities of the packet multi-queue engine (PQ). By relying on fixed address block partitioning and embedded pointer storage, a simplified hardware linked list is constructed to achieve global dynamic sharing of storage space and adaptive allocation of traffic. This solves the technical problems of resource idleness, low utilization, and high expansion costs under the static allocation mode, reduces the hardware cost of the chip's off-chip DDR cache, and improves the scalability of the packet multi-queue engine in large-scale cluster scenarios.

[0021] See Figure 2 The off-chip DDR cache management method of the data packet multi-queue engine includes: S100. The storage space reserved for the packet multi-queue engine in the off-chip DDR cache unit is divided into several equally sized composite address blocks. Each composite address block includes multiple contiguous storage units, with the last storage unit used as a linked list pointer field, and the remaining storage units used as packet storage fields. See also... Figure 3 In an optional embodiment of the first aspect of the present invention, a single composite address block may include 64 consecutive storage units to match the burst transmission characteristics of the 64-byte cache line of the off-chip DDR cache unit, wherein the first 63 of the storage units are used as the data packet storage field and the last storage unit is used as the linked list pointer field, forming a 63+1 embedded composite storage structure.

[0022] More specifically, for example, taking the division of 1MB space into multiple equal-sized fixed composite address blocks as an example, in this invention, the size of a single address block can be 4KB, so a total of 256 composite address blocks can be divided. To adapt to the burst transmission of DDR 64-byte cache lines, each 4KB address block is logically further subdivided into 64 64-byte storage units. Among them, the first 63 storage units (address offset 0x00 to 0xFC0) constitute a data packet storage field, which is used to cache 63 data packets exchanged between cores. The last 64-byte storage unit (address offset 0xFC0 to 0xFFF, but only its first 8 bytes are used) constitutes a linked list pointer field, which is used to store the 64-bit physical address of the next level composite address block (i.e., intermediate node pointer). This 63+1 embedded composite structure constitutes one of the core designs of this invention.

[0023] S200. Construct a global free list from all the free composite address blocks, and based on the global free list, maintain a dynamic list independently for each message queue of the data packet multi-queue engine. The head pointer and tail pointer of the dynamic list are stored in hardware registers, and the pointers of the intermediate nodes of the dynamic list are stored in the list pointer field of the composite address block.

[0024] Specifically, in this invention, after the system is powered on, the dynamic address block management module will construct a unidirectional global free list from all 256 free address blocks in ascending order of physical address (that is, the composite address blocks in the global free list are arranged in ascending order of physical address to form a unidirectional free list). The module only needs one register to store the head pointer of the free list.

[0025] Next, the 32 message queues of the data packet multi-queue engine are initialized. 32 composite address blocks are taken from the head of the global free list, and an initial composite address block is allocated to each message queue. Subsequently, in the list maintenance module, the head pointer and tail pointer of each message queue are set in the hardware register to point to the physical address of its corresponding initial composite address block. At this point, each message queue has an empty address block, ready to receive data. The remaining 224 address blocks are kept in the global free list, waiting for dynamic scheduling.

[0026] S300: When the on-chip enqueue cache unit is full, causing data packets to overflow into the off-chip DDR cache unit, the data packets are sequentially written into the data packet storage field of the initial composite address block pointed to by the tail pointer of the current message queue. If the initial composite address block is full, a new composite address block is requested from the global free list, and the physical address of the new composite address block is written into the linked list pointer field of the initial composite address block as the intermediate node pointer. The tail pointer of the current message queue is updated to point to the new composite address block, and the sequential writing of the data packets continues.

[0027] In this invention, when the on-chip enqueue buffer of the data packet multi-queue engine is full and the data packet needs to overflow to the off-chip DDR buffer, the following dynamic allocation process is executed: Write data packet: Based on the message queue to which the data packet belongs, locate the tail pointer of the queue and find the current tail composite address block.

[0028] Space check: Detect the number of remaining free storage units in the current message queue tail address block. For example, the hardware uses an in-block write offset counter to determine whether the data packet storage field (63 units in total) of the current address block is full (i.e., detect in real time the number of remaining free storage units in the initial composite address block pointed to by the tail pointer of the current message queue).

[0029] Intra-block write: If not full (there are free units), the data packet is written directly and the intra-block offset is updated. For example, a 64-byte data packet is written directly to the free unit indicated by the offset. Then the write offset is automatically incremented by 1. (That is, in this invention, if there are free cache units in the initial composite address block, the data packet is written sequentially to the data packet storage field of the initial composite address block, and the write position is updated by the intra-block hardware offset auto-increment logic to maintain continuous write timing.)

[0030] In this invention, the hardware is pre-configured with a storage domain isolation protection mechanism. The address mask mechanism ensures that write operations will not cross the boundary and pollute the final linked list pointer field. For example, the address mask strictly distinguishes between the business write operations of the first 63 units and the system write operations of the 64th unit, so as to completely avoid the business data packets from crossing the boundary and flushing the linked list pointer data (that is, in this invention, the access boundaries between the data packet storage domain and the linked list pointer field are pre-defined, and the hardware isolation of read and write permissions is achieved by configuring the address mask, so that the data packet read and write operations of inter-core interaction are restricted to the data packet storage domain, and abnormal data packets are prevented from flushing or tampering with the intermediate node pointers stored in the linked list pointer field).

[0031] Inter-block linking and allocation: If the current address block is full, a new address block is requested from the global free list. The physical address of the new block is written to the pointer field of the current block, the tail pointer of the queue is updated, and the data packet is written to the starting position of the new address block. For example, if all 63 units of the current address block are full, an address block request instruction is sent to the dynamic address block management module. The module will take a new free address block from the head of the global free list and return its physical address. Then, this new address is written to the linked list pointer field of the current (old) tail composite address block to complete the linking of the linked list nodes. Finally, the tail pointer of the message queue in the hardware register is updated to point to this new composite address block. The new data packet is then written to the first storage unit of the new address block (the position with an offset of 0).

[0032] S400. When there is free space in the on-chip dequeue buffer unit, the data packets are read sequentially from the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue. If all the data packets in the target composite address block have been read, the intermediate node pointer in the linked list pointer field of the target composite address block is read to obtain the physical address of the next level composite address block. The first pointer of the current message queue is updated to point to the next level composite address block to continue the sequential reading of the data packets. The empty target composite address block is returned to the global free linked list.

[0033] In this invention, when the on-chip dequeue buffer unit of the data packet multi-queue engine becomes idle and needs to read data packets from the off-chip DDR cache, the following dynamic recycling process is executed: Read data packets: Read the data packets inside the current queue's first address block. Based on the message queue to be read, locate the first pointer of that message queue, find the current header compound address block, and synchronously update the read offset during the reading process.

[0034] Intra-block read: If not all 63 data packets have been read, read sequentially. For example, the hardware uses an intra-block read offset counter to read data packets in the data packet storage field sequentially. Each time a data packet is read, the read offset is automatically incremented by 1. (That is, in this invention, combined with the hardware offset progressive read logic, the data packets in the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue are read sequentially, and the read offset is updated synchronously. If the target composite address block has not been completely read, read sequentially.)

[0035] Whole block reclamation determination: When the read offset reaches 63, it means that all data packets in the composite address block have been successfully read, triggering the whole block reclamation mechanism. The hardware strictly prohibits reclamation when there is still unread data in the block, thus fundamentally eliminating the generation of memory fragmentation.

[0036] Pointer update and recycling: If the current address block has been completely read, the tail pointer field is read to obtain the next level address block, that is, the linked list pointer field of the current (old) head composite address block is read to obtain the physical address of the next level composite address block. The head pointer register of the queue is updated to this new address. Then, the old address block that has just been read is returned to the dynamic address block management module, that is, the empty address block is returned to the global free linked list, and the head pointer of the queue is updated.

[0037] Free List Mounting: To reduce the address jump range of physical addressing of off-chip DDR cache units and improve bus access stability, the dynamic address block management module adopts a tail insertion method to mount reclaimed empty address blocks to the tail of the global free list (i.e., when the target composite address block that has been read empty is returned to the global free list, the tail insertion method is used to mount the target composite address block that has been read empty to the tail of the global free list, thereby reducing the physical addressing jitter of the off-chip DDR cache unit). In the process of running the system, after the business task is completed, the system will also automatically traverse the linked list nodes of the message queue, reclaim address blocks in batches and reset pointers. A whole block judgment logic is adopted, and only complete empty blocks participate in reclamation (i.e., the whole block reclamation logic is forced, and only when all data packets inside a single composite address block have been read can it be returned to the free list, prohibiting the release of half blocks, and completely eliminating memory fragmentation from the hardware level).

[0038] In an optional embodiment of the first aspect of the present invention, the off-chip DDR cache management method further includes: real-time monitoring of the number of composite address blocks in the global free list and setting a warning threshold; when the number of composite address blocks in the global free list is lower than the preset warning threshold, performing a pre-limiting operation; when all composite address blocks in the global free list are exhausted, sending a forced backpressure signal to the enqueue interface of the data packet multi-queue engine to suspend the writing of the data packet.

[0039] Specifically, to ensure system stability under extreme traffic conditions, this invention also includes an idle block threshold gradient backpressure mechanism, as follows: Monitoring and Rate Limiting: The dynamic address block management module monitors the number of free blocks in the global free list in real time. When the number falls below a preset warning threshold (e.g., 10% of the total number of blocks), the module sends a pre-limiting signal to the upstream module to appropriately slow down the queuing rate of data packets, providing a buffer for the system to cope with instantaneous traffic surges.

[0040] Forced backpressure: When all address blocks in the global free list are exhausted, the module immediately sends a forced backpressure signal to the enqueue interface of the packet multi-queue engine, completely suspending all packet overflow writes to the off-chip DDR cache until a new address block is reclaimed and released. This ensures that data loss will not occur due to lack of available space under any circumstances.

[0041] In summary, the core innovation of the off-chip DDR cache management method of the multi-queue engine for data packets in this invention lies in the following: 1. 63+1 Embedded Composite Address Block Structure: The linked list pointer is embedded at the end of the data packet block, and the independent data packet storage field and pointer field are divided. No additional SRAM is needed to store the pointer. It is naturally adapted to the high-speed burst transmission of DDR 64-byte cache line, and the access efficiency is greatly improved.

[0042] 2. Simplified hardware linked list architecture: The hardware only retains the head and tail pointers, discards all intermediate node pointer registers, and the intermediate nodes are distributed and stored inside DDR. The hardware logic is extremely simple, the timing is very easy to converge, and the resource overhead is extremely low.

[0043] 3. Dynamic storage scheduling natively integrated with the multi-queue engine for data packets: The dynamic address block mechanism is deeply coupled with PQ's multi-queue parallel scheduling, lock-free interaction, and multi-topology interconnection to achieve fully automatic hardware resource scheduling without software intervention.

[0044] 4. Intra-block offset progressive write mechanism: The hardware offset is incremented and written sequentially within a single address block to strictly maintain the data packet write sequence, naturally matching the burst read and write alignment characteristics of DDR, and eliminating bandwidth loss caused by out-of-order storage.

[0045] 5. Physical Address Ascending Order Free Linked List Mounting Mechanism: Global free address blocks are arranged in a unidirectional chain according to physical address ascending order. Reclaimed address blocks are mounted using the tail insertion method, which reduces DDR physical address jitter and improves bus access stability.

[0046] 6. Whole-block reclamation anti-fragmentation control mechanism: The hardware forces the use of whole-block reclamation logic. Only after all data packets within a single address block have been read out can it be returned to the free list, prohibiting the release of half blocks and completely eliminating memory fragmentation at the hardware level.

[0047] 7. Idle Block Threshold Gradient Backpressure Mechanism: The hardware monitors the number of global idle blocks in real time and sets a warning threshold; when the number of idle blocks is lower than the warning level, front-end backpressure flow limiting is executed to alleviate instantaneous traffic surges and avoid packet loss caused by one-time resource exhaustion.

[0048] To better illustrate the technical effectiveness of the off-chip DDR cache management method of the data packet multi-queue engine of the present invention, the following embodiments are constructed for comparative testing: Example hardware configuration: Built on a standard scalable unified computing architecture (UCS) hardware platform, including 4 micro-core clusters (UCC), a packet multi-queue engine with 32 independent inter-core interactive message queues; the length of a single packet is fixed at 64 bytes; 1MB of cache space is reserved for the packet multi-queue engine (PQ) in the off-chip DDR cache; the capacity of a single address block is 4KB, and the total number of address blocks is 256; the service scenario adopts Ethernet packet forwarding, including 4 low-traffic control queues and 28 high-traffic data forwarding queues.

[0049] Comparative Example: Traditional Static Average Allocation Scheme: Address Allocation Method: Storage space is evenly divided among 32 queues, with each queue occupying a fixed 8 address blocks; Resource Usage: Control queues are idle for extended periods, with a total of 112KB of idle space, while data forwarding queues have insufficient space; Example: Dynamic linked list allocation scheme of the present invention: Initialization configuration: Each queue is allocated 1 initial address block, and the remaining 224 blocks are included in the global free linked list; Resource scheduling logic: Low-flow queues maintain single block occupation for a long time, while high-flow queues dynamically request free address blocks, and resources are automatically tilted; Performance indicators: Storage space utilization rate is 100%.

[0050] Implementation Summary: Experiments have demonstrated that this invention solves the industry pain point of wasted off-chip DDR cache resources in unbalanced traffic scenarios without altering the core architecture of the packet multi-queue engine, worsening latency and power consumption, or affecting the lock-free asynchronous interaction capabilities of the packet multi-queue engine (PQ). This invention requires minimal hardware modifications, exhibits excellent timing convergence, and has strong mass production feasibility. Furthermore, it completely avoids the architectural defects of general-purpose hardware linked list patents, possessing extremely high engineering and commercial value.

[0051] In summary, compared with traditional static allocation schemes and general hardware linked list technology, the off-chip DDR cache management method of the data packet multi-queue engine of this invention can bring at least the following technical effects: (1) Improve storage resource utilization: Realize global dynamic flow of address blocks, and increase storage space utilization from 18% to over 90% in unbalanced traffic scenarios, completely eliminating long-term idle space; (2) Extremely low hardware resource overhead: The design method of external SRAM for general linked lists is abandoned, and only registers are used to store the head and tail pointers, with the overall hardware logic increment not exceeding 5%; (3) Reduce chip mass production costs: Under the same business throughput, the DDR physical storage space requirement is reduced by 33%, effectively reducing the SoC storage hardware cost; (4) Adaptable to all levels of chip expansion: compatible with edge lightweight chips to high-end computing power chips, and scale expansion can be completed without modifying the core architecture of the data packet multi-queue engine; (5) High real-time performance and no memory fragmentation: Fixed block allocation eliminates memory fragmentation, single DDR read and write matches standard cache line, and the latency is stable and controllable, meeting the industrial hard real-time requirements.

[0052] See Figure 4 The second aspect of the present invention provides a cache management system for implementing the off-chip DDR cache management method described in any one of the first aspects of the present invention. The cache management system includes an on-chip dequeue cache unit, an on-chip enqueue cache unit, an off-chip DDR cache unit, a dynamic address block management module, and a linked list maintenance module. The dynamic address block management module is used to divide the storage space reserved by the off-chip DDR cache unit for the data packet multi-queue engine into several equal-sized composite address blocks, construct a global free linked list, and respond to address block request instructions when writing data packets and address block reclamation instructions when reading data packets, thereby completing the global dynamic scheduling of the storage resources of the off-chip DDR cache unit. In this module, a single composite address block includes multiple consecutive storage units, with the last storage unit used as a linked list pointer field and the remaining storage units used as data packet storage fields. The linked list maintenance module is used to maintain a dynamic linked list independently for each message queue of the data packet multi-queue engine. The head pointer and tail pointer of the dynamic linked list are stored in hardware registers, and the pointers of the intermediate nodes of the dynamic linked list are stored in the linked list pointer field of the composite address block.

[0053] Specifically, the cache management system of this invention, while retaining the original on-chip enqueue cache unit and on-chip dequeue cache unit read / write logic, upgrades the hardware of the off-chip DDR cache unit inside the packet multi-queue engine, adding two lightweight functional modules without modifying the original core circuits of the packet multi-queue engine (PQ), such as message routing, queue scheduling, and DMA interaction. It adopts fixed block partitioning, embedded pointers, and simplified linked list control logic to achieve dynamic allocation, automatic reclamation, and fragment-free management of off-chip DDR cache storage space. As a core component of the queue management unit of the Scalable Unified Computing Architecture (UCS) framework layer, this invention optimizes the hardware architecture for the storage allocation logic of inter-core interactive data packets overflowing to the off-chip DDR cache in the packet multi-queue engine. It is suitable for high-density heterogeneous computing SoC chip design fields with obvious traffic imbalance characteristics, such as network packet processing, artificial intelligence inference, and industrial real-time control.

[0054] Dynamic address block management module: responsible for allocating DDR reserved storage space, generating and maintaining a global free address block linked list, responding to address block request and reclamation instructions, and completing unified scheduling of storage resources; Linked list maintenance module: maintains an independent dynamic linked list for each message queue, and adopts a very simple maintenance structure. The hardware registers only store the head and tail pointers of the queue, discarding all intermediate node pointer registers. The intermediate node pointers are all distributed and integratedly embedded in the DDR address block, without consuming expensive on-chip SRAM resources.

[0055] In an optional embodiment of the second aspect of the present invention, the cache management system is compatible with the native AXI bus and task handshake protocol of the scalable unified computing architecture, and the packet multi-queue engine has lock-free asynchronous interaction and multi-queue parallel scheduling capabilities. The cache management system of the present invention is compatible with the UCS native AXI bus and task handshake protocol, and is also compatible with point-to-point, ring, and mesh interconnection topologies. It fully inherits the lock-free asynchronous interaction and multi-queue parallel scheduling capabilities of the packet multi-queue engine, and possesses multi-cluster collaborative characteristics. Hardware upgrades can be completed without modification to the upper-layer software.

[0056] In an optional embodiment of the second aspect of the present invention, a single composite address block comprises 64 consecutive storage units to match the burst transmission characteristics of the 64-byte cache line of the off-chip DDR cache unit, wherein the first 63 of the storage units are used as the data packet storage field and the last storage unit is used as the linked list pointer field, forming a 63+1 embedded composite storage structure.

[0057] In an optional embodiment of the second aspect of the present invention, the composite address blocks in the global free list are arranged in ascending order of the physical address to form a unidirectional free list; when the target composite address block that has been read empty is returned to the global free list, the target composite address block that has been read empty is attached to the tail of the global free list by tail insertion, so as to reduce the physical addressing jitter of the off-chip DDR cache unit.

[0058] In an optional embodiment of a second aspect of the present invention, the cache management system further includes an off-chip data packet writing module, the off-chip data packet writing module being used for: The number of remaining free storage units in the initial composite address block pointed to by the tail pointer of the current message queue is detected in real time. If there is a free cache unit in the initial composite address block, the data packet is written sequentially to the data packet storage field of the initial composite address block, and the write position is updated by the block-incrementing hardware offset logic to maintain continuous write timing.

[0059] In an optional embodiment of the second aspect of the present invention, the cache management system further includes an off-chip data packet reading module, the off-chip data packet reading module being used for: Combining the hardware offset progressive reading logic, the data packets in the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue are read sequentially, and the reading offset is updated synchronously. If the target composite address block is not completely read, the sequential reading continues.

[0060] In an optional embodiment of a second aspect of the present invention, the cache management system further includes a backpressure protection module, the backpressure protection module being used for: The number of composite address blocks in the global free list is monitored in real time, and a warning threshold is preset. When the number of composite address blocks in the global free list is lower than the preset warning threshold, a pre-limiting operation is performed; When all the composite address blocks in the global free list are exhausted, a forced backpressure signal is sent to the enqueue interface of the data packet multi-queue engine to suspend the writing of the data packet.

[0061] In an optional embodiment of a second aspect of the present invention, the cache management system further includes a storage domain isolation module, the storage domain isolation module being used for: The access boundaries between the data packet storage field and the linked list pointer field are predefined, and hardware isolation of read and write permissions is achieved by configuring an address mask. This restricts the data packet read and write operations between cores to the data packet storage field, preventing abnormal data packets from flushing or tampering with the intermediate node pointers stored in the linked list pointer field.

[0062] Figure 5 This is a schematic diagram of a network communication device provided in an embodiment of the present invention. The network communication device can vary significantly due to differences in configuration or performance, and may include one or more processors 10 (central processing units, CPUs) (e.g., one or more processors) and a memory 20, and one or more storage media 30 (e.g., one or more mass storage network communication devices) for storing recording programs or data. The memory and storage media can be short-term or persistent storage. The program stored in the storage media may include one or more modules (not shown in the figure), each module including a series of instruction operations on the network communication device. Furthermore, the processor may be configured to communicate with the storage media and execute the series of instruction operations in the storage media on the network communication device.

[0063] The network communication device of this invention may further include one or more power supplies 40, one or more wired or wireless network interfaces 50, one or more input / output interfaces 60, and / or one or more operating systems, such as Windows Server, Mac OS, Unix, Linux, FreeBSD, etc. Those skilled in the art will understand that... Figure 5 The network communication device structure shown does not constitute a limitation on the network communication device. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0064] This invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the steps of the dual-microphone-based noise reduction recording method.

[0065] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system, module, or unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0066] If the integrated unit is implemented as a software functional unit or a combination of software and hardware and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer network communication device (which may be a personal computer, a server, or a network communication device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0067] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for managing off-chip DDR cache in a multi-queue packet engine, characterized in that, include: The storage space reserved for the packet multi-queue engine in the off-chip DDR cache unit is divided into several equally sized composite address blocks. Each composite address block includes multiple consecutive storage units, with the last storage unit used as a linked list pointer field and the remaining storage units used as packet storage fields. All the free composite address blocks are constructed into a global free linked list, and a dynamic linked list is maintained independently for each message queue of the data packet multi-queue engine based on the global free linked list. The head pointer and tail pointer of the dynamic linked list are stored in hardware registers, and the pointers of the middle nodes of the dynamic linked list are stored in the linked list pointer field of the composite address block. When the on-chip enqueue cache unit is full, causing data packets to overflow into the off-chip DDR cache unit, the data packets are sequentially written into the data packet storage field of the initial composite address block pointed to by the tail pointer of the current message queue. If the initial composite address block is full, a new composite address block is requested from the global free list, and the physical address of the new composite address block is written into the linked list pointer field of the initial composite address block as the intermediate node pointer. The tail pointer of the current message queue is updated to point to the new composite address block, and the sequential writing of the data packets continues. When there is free space in the on-chip dequeue buffer unit, the data packets are read sequentially from the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue. If all the data packets in the target composite address block have been read, the intermediate node pointer in the linked list pointer field of the target composite address block is read to obtain the physical address of the next level composite address block. The first pointer of the current message queue is then updated to point to the next level composite address block to continue reading the data packets sequentially. The target composite address block that has been read empty is returned to the global free linked list.

2. The off-chip DDR cache management method according to claim 1, characterized in that, Each composite address block comprises 64 consecutive storage units to match the burst transfer characteristics of the 64-byte cache line of the off-chip DDR cache unit. The first 63 storage units are used as the data packet storage field, and the last storage unit is used as the linked list pointer field, forming a 63+1 embedded composite storage structure.

3. The off-chip DDR cache management method according to claim 1, characterized in that, The composite address blocks in the global free list are arranged in ascending order of physical address to form a unidirectional free list; when the target composite address block that has been read empty is returned to the global free list, the target composite address block that has been read empty is attached to the tail of the global free list by tail insertion, so as to reduce the physical addressing jitter of the off-chip DDR cache unit.

4. The off-chip DDR cache management method according to claim 1, characterized in that, The step of sequentially writing the data packets into the data packet storage field of the initial composite address block pointed to by the tail pointer of the current message queue includes: The number of remaining free storage units in the initial composite address block pointed to by the tail pointer of the current message queue is detected in real time. If there is a free cache unit in the initial composite address block, the data packet is written sequentially to the data packet storage field of the initial composite address block, and the write position is updated by the block-incrementing hardware offset logic to maintain continuous write timing.

5. The off-chip DDR cache management method according to claim 1, characterized in that, The step of sequentially reading the data packets from the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue includes: Combining the hardware offset progressive reading logic, the data packets in the data packet storage field of the target composite address block pointed to by the first pointer of the current message queue are read sequentially, and the reading offset is updated synchronously. If the target composite address block is not completely read, the sequential reading continues.

6. The off-chip DDR cache management method according to claim 1, characterized in that, Also includes: The number of composite address blocks in the global free list is monitored in real time, and a warning threshold is preset. When the number of composite address blocks in the global free list is lower than the preset warning threshold, a pre-limiting operation is performed; When all the composite address blocks in the global free list are exhausted, a forced backpressure signal is sent to the enqueue interface of the data packet multi-queue engine to suspend the writing of the data packet.

7. The off-chip DDR cache management method according to claim 1, characterized in that, Also includes: The access boundaries between the data packet storage field and the linked list pointer field are predefined, and hardware isolation of read and write permissions is achieved by configuring an address mask. This restricts the data packet read and write operations between cores to the data packet storage field, preventing abnormal data packets from flushing or tampering with the intermediate node pointers stored in the linked list pointer field.

8. A cache management system for implementing the off-chip DDR cache management method according to any one of claims 1-7, characterized in that, The cache management system includes an on-chip dequeue cache unit, an on-chip enqueue cache unit, an off-chip DDR cache unit, a dynamic address block management module, and a linked list maintenance module; The dynamic address block management module is used to divide the storage space reserved by the off-chip DDR cache unit for the data packet multi-queue engine into several equal-sized composite address blocks, construct a global free linked list, and respond to address block request instructions when writing data packets and address block reclamation instructions when reading data packets, thereby completing the global dynamic scheduling of the storage resources of the off-chip DDR cache unit. In this module, a single composite address block includes multiple consecutive storage units, with the last storage unit used as a linked list pointer field and the remaining storage units used as data packet storage fields. The linked list maintenance module is used to maintain a dynamic linked list independently for each message queue of the data packet multi-queue engine. The head pointer and tail pointer of the dynamic linked list are stored in hardware registers, and the pointers of the intermediate nodes of the dynamic linked list are stored in the linked list pointer field of the composite address block.

9. The cache management system according to claim 8, characterized in that, The cache management system is compatible with the native AXI bus and task handshake protocol of the scalable unified computing architecture, and the data packet multi-queue engine has lock-free asynchronous interaction and multi-queue parallel scheduling capabilities.

10. A network communication device, characterized in that, The network communication device includes: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a line; The at least one processor invokes the instructions in the memory to cause the network communication device to perform the off-chip DDR cache management method as described in any one of claims 1-7.

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