Processor, task scheduling method, electronic device, storage medium

Abstract

A processor, a task scheduling method, an electronic device and a storage medium are applied to the field of data communication. The processor comprises a plurality of resource partitions, a command processor and a command processing distributor. The command processor is configured to receive a command package, analyze the command package to generate a plurality of tasks, wherein the command package carries a first identifier, and in response to the first identifier indicating that the plurality of tasks are scheduled in a first scheduling mode. The command processing distributor is configured to distribute the plurality of tasks to the plurality of resource partitions according to the number of computing unit clusters included in each resource partition, wherein the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition. In response to the first identifier indicating that the plurality of tasks are scheduled in a second scheduling mode, the command processing distributor is configured to randomly distribute the plurality of tasks to the plurality of resource partitions, wherein the plurality of resource partitions uniformly receive the plurality of tasks. The processor can realize balanced scheduling of tasks.

Description

Technical Field

[0001] The embodiments of this disclosure are applied to the field of electronic digital data processing, specifically relating to a processor, a task scheduling method, an electronic device, and a non-transitory computer-readable storage medium. Background Technology

[0002] When the parallel processor performs large model training and inference tasks, the host sends command packets to the parallel processor on the device side. The parallel processor internally consists of a command processor and a command processing distributor, which complete the command reception, parsing, splitting into tasks, and distribution in two stages, forming a hardware command scheduling path.

[0003] Current command dispatchers use uniform scheduling when distributing tasks, which leads to a mismatch between the tasks distributed and the computing resources, resulting in an imbalance in task scheduling. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a processor including multiple resource partitions, a command processor, and a command processing distributor. Each resource partition includes multiple computing unit clusters, and each computing unit cluster includes multiple computing units. The multiple computing units in a computing unit cluster are configured to jointly execute a task. The command processor is configured to receive command packets, parse the command packets to generate multiple tasks, wherein the command packets carry a first identifier. In response to the first identifier indicating that a first scheduling method is used to schedule the multiple tasks, the command processing distributor is configured to distribute the multiple tasks to the multiple resource partitions according to the number of computing unit clusters included in each resource partition, wherein the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition. In response to the first identifier indicating that a second scheduling method is used to schedule the multiple tasks, the command processing distributor is configured to randomly distribute the multiple tasks to the multiple resource partitions, wherein the multiple resource partitions receive the multiple tasks evenly.

[0005] For example, in a processor provided in at least one embodiment of this disclosure, when the plurality of tasks are scheduled in the first scheduling mode, a computing unit cluster executes at most one task during the execution of the plurality of tasks generated by the command package.

[0006] For example, in a processor provided in at least one embodiment of this disclosure, when the command processing dispatcher distributes the plurality of tasks to the plurality of resource partitions according to the number of computing unit clusters included in each resource partition, it includes performing the following operations: determining a plurality of destination resource partitions according to the number of tasks already distributed in each resource partition and the number of computing unit clusters included in the resource partition, and distributing the plurality of tasks to the plurality of destination resource partitions in sequence, wherein each destination resource partition is working normally, and at least one computing unit cluster in the destination resource partition is in an idle state capable of executing tasks.

[0007] For example, in a processor provided in at least one embodiment of this disclosure, the command processing dispatcher includes a poller, a plurality of first registers and a plurality of second registers corresponding one-to-one with the plurality of resource partitions, and the command processing dispatcher is configured to adjust the current value in the first register corresponding to each resource partition according to the number of tasks already dispatched to each resource partition and the number of computing unit clusters included in each resource partition; the command processing dispatcher is further configured to set the second register corresponding to each resource partition to a first preset value when the current value in the first register corresponding to each resource partition is a first value, and to set the second register corresponding to each resource partition to a second preset value when the current value in the first register corresponding to each resource partition is not the first value, wherein when the current value in the first register corresponding to each resource partition is the first value, it indicates that no more tasks are allowed to be dispatched to the resource partition; the poller is configured to distribute the plurality of tasks sequentially to the plurality of destination resource partitions according to the current values ​​of the plurality of second registers, wherein the current value of the second register corresponding to the plurality of destination resource partitions is the second preset value.

[0008] For example, in a processor provided in at least one embodiment of this disclosure, the command processing distributor includes multiple task pools corresponding one-to-one with the plurality of resource partitions. Each task pool is configured to cache tasks sent by the poller to the resource partition corresponding to the task pool. When the command packet is received, each first register is initialized to an initial value, wherein the initial value is less than or equal to the total number of computing unit clusters included in the resource partition corresponding to the first register. Each first register is configured to, in response to the poller sending a task to the task pool corresponding to the resource partition corresponding to the first register, decrement the current value of the first register by 1 and write the result back to the first register, wherein the first value is 0.

[0009] For example, in a processor provided in at least one embodiment of this disclosure, the processor is further configured to initialize the plurality of first registers by performing a write access to a memory-mapped input / output address and configuring the initial value of the plurality of first registers.

[0010] For example, in a processor provided in at least one embodiment of this disclosure, when the poller executes the operation of sequentially distributing the plurality of tasks to the plurality of destination resource partitions according to the current values ​​of the plurality of second registers, it includes performing the following operations: sequentially distributing tasks to the plurality of resource partitions in a preset order, wherein, during the distribution process, the current value of the second register corresponding to the currently selected resource partition is read in the preset order; in response to the current value of the corresponding second register being the first preset value, the currently selected resource partition is skipped, and tasks are distributed to the next resource partition in the preset order whose current value of the corresponding second register is not the first preset value; in response to the current value of the corresponding second register being the second preset value, the currently selected resource partition is taken as the destination resource partition, and tasks are distributed to the currently selected resource partition.

[0011] For example, in a processor provided in at least one embodiment of this disclosure, the command processing dispatcher is further configured to, in response to at least one resource partition becoming invalid or suspending the use of the at least one resource partition, set the initial value of the first register corresponding to each of the at least one resource partition to the first value.

[0012] For example, in the processor provided in at least one embodiment of this disclosure, the command processing dispatcher further includes an arbitration module and multiple task pools corresponding one-to-one with the multiple resource partitions. Each task pool is configured to cache the tasks issued by the poller to the resource partition corresponding to the task pool. The arbitration module is communicatively connected to the multiple resource partitions through a bus and is configured to poll the multiple task pools and route the tasks in the arbitration task pool to the corresponding resource partitions through the bus.

[0013] For example, in the processor provided in at least one embodiment of this disclosure, the processor is a graphics processor or a general-purpose graphics processor, each resource partition includes multiple streaming processor clusters, each streaming processor cluster includes multiple computing units, and the multiple computing units form one or more computing unit clusters.

[0014] At least one embodiment of this disclosure provides an electronic device including a processor as described in any embodiment of this disclosure.

[0015] This disclosure provides at least one embodiment of a task scheduling method applied to a processor. The processor includes multiple resource partitions, a command processor, and a command processing dispatcher. Each resource partition includes multiple computing unit clusters, and each computing unit cluster includes multiple computing units. The multiple computing units in a computing unit cluster are configured to jointly execute a task. The task scheduling method includes: receiving a command packet; the command processor parses the command packet to generate multiple tasks, wherein the command packet carries a first identifier; in response to the first identifier indicating that the multiple tasks are scheduled using a first scheduling method, the command processing dispatcher distributes the multiple tasks to the multiple resource partitions according to the number of computing unit clusters included in each resource partition, wherein during the distribution of the multiple tasks, the total number of tasks sent to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition; in response to the first identifier indicating that the multiple tasks are scheduled using a second scheduling method, the command processing dispatcher randomly distributes the multiple tasks to the multiple resource partitions, wherein the multiple resource partitions receive the multiple tasks evenly.

[0016] For example, in a task scheduling method provided in at least one embodiment of this disclosure, the command processing distributor distributes the multiple tasks to the multiple resource partitions according to the number of computing unit clusters included in each resource partition. This includes: the command processing distributor determines multiple destination resource partitions according to the number of tasks already distributed in each resource partition and the number of computing unit clusters included in each resource partition, and distributes the multiple tasks to the multiple destination resource partitions in sequence. Each destination resource partition is working normally, and at least one computing unit cluster in each destination resource partition is in an idle state capable of executing tasks.

[0017] For example, in a task scheduling method provided in at least one embodiment of this disclosure, the command processing distributor includes a poller, a plurality of first registers and a plurality of second registers corresponding one-to-one with the plurality of resource partitions. The command processing distributor determines a plurality of destination resource partitions based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in each resource partition, and distributes the plurality of tasks to the plurality of destination resource partitions sequentially. This includes: adjusting the current value in the first register corresponding to each resource partition based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in each resource partition; setting the second register corresponding to each resource partition to a first preset value when the current value in the first register corresponding to each resource partition is a first value, and setting the second register corresponding to each resource partition to a second preset value when the current value in the first register corresponding to each resource partition is not the first value, wherein when the current value in the first register corresponding to each resource partition is a first value, it indicates that no more tasks are allowed to be sent to the resource partition; and the poller distributes the plurality of tasks to the plurality of destination resource partitions sequentially based on the current values ​​of the plurality of second registers, wherein the current value of the second register corresponding to each of the plurality of destination resource partitions is the second preset value.

[0018] For example, in a task scheduling method provided in at least one embodiment of this disclosure, the poller distributes the plurality of tasks to the plurality of destination resource partitions in sequence according to the current values ​​of the plurality of second registers, including: distributing tasks to the plurality of resource partitions in sequence according to a preset order, wherein, during the traversal process, resource partitions whose corresponding second registers are the first preset values ​​are skipped, and tasks are sequentially distributed to other destination resource partitions whose corresponding second registers are not the first preset values.

[0019] For example, in a task scheduling method provided in at least one embodiment of this disclosure, the task scheduling method further includes: in response to at least one resource partition failing or suspending the use of the at least one resource partition, setting the value of the first register corresponding to each of the at least one resource partition to the first value.

[0020] At least one embodiment of this disclosure provides an electronic device, including: a storage device storing computer-executable instructions non-transitory; and a processing device configured to run the computer-executable instructions, wherein the computer-executable instructions are executed by the processing device to implement the task scheduling method according to any embodiment of this disclosure.

[0021] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the task scheduling method according to any embodiment of this disclosure.

[0022] The processor provided in at least one embodiment of this disclosure is compatible with multiple task scheduling modes, supporting both the existing second scheduling mode (uniform scheduling mode) and a new first scheduling mode. In the first scheduling mode, the command processing dispatcher can distribute tasks according to the actual computing resources in each resource partition. The total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, ensuring that the number of tasks distributed to each resource partition matches the number of computing unit clusters in that resource partition, resulting in more balanced task scheduling. Simultaneously, since the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, exclusive access and computation of the computing unit clusters can be achieved, reducing the overhead of switching contexts when the computing unit clusters are processing different tasks, and to some extent reducing programming complexity. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figure 1 This is a schematic diagram of the architecture of a parallel processor; Figure 2 A schematic diagram of resource partitioning in a general-purpose graphics processor; Figure 3 A schematic structural diagram of a processor provided for at least one embodiment of this disclosure; Figure 4 A schematic structural diagram of a command processing dispatcher provided in at least one embodiment of this disclosure; Figure 5 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure; Figure 6 A schematic diagram of the specific structure of an electronic device provided in at least one embodiment of this disclosure; Figure 7 A schematic flowchart illustrating a task scheduling method provided for at least one embodiment of this disclosure; Figure 8 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0026] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components are omitted.

[0027] Figure 1 This is a schematic diagram of the architecture of a parallel processor.

[0028] like Figure 1 As shown, when the parallel processor on the device side executes large model training and inference tasks, the host (e.g., central processing unit) sends command packets to the parallel processor. The parallel processor internally completes the command reception, parsing, splitting into tasks, and distributing to downstream execution modules in two levels: command processor and command processor dispatcher.

[0029] like Figure 1 As shown, the command processor is a front-end command processing hardware module in a parallel processor chip that faces the host side. It is responsible for receiving command packets issued by the host, parsing and validating the command packets, breaking down the high-level hardware commands into several tasks that can be executed by downstream hardware, and forwarding the split tasks to the downstream command processing distributor.

[0030] The command processing dispatcher is a downstream scheduling hardware module of the command processor. It receives the split tasks output by the command processor, performs task queue management and load scheduling, and distributes each task to downstream hardware via the bus. The downstream hardware (e.g., ...) then dispatches the tasks. Figure 1 The actual computation and memory access are performed by the resource partitions in the system.

[0031] The command processing dispatcher evenly distributes tasks to multiple resource partitions in the parallel processors. One computing unit cluster executes one task, and the individual tasks decomposed by the command processor are ultimately executed by a single computing unit cluster.

[0032] For example, a parallel processor can be a Graphic Processing Unit (GPU), a General-Purpose Graphic Processing Unit (GPGPU), a Tensor Processing Unit (TPU), a Data Processing Unit (DPU), a Neural Processing Unit (NPU), etc., and this disclosure does not impose any specific limitations on it.

[0033] The following section uses a general-purpose graphics processor as an example to introduce the specific structure of resource partitioning.

[0034] Figure 2 This is a schematic diagram of the resource partitioning structure in a general-purpose graphics processor.

[0035] exist Figure 2 The command processor and command dispatcher are not shown in the text; the relevant structures are referenced in [reference needed]. Figure 1 The description.

[0036] A general-purpose graphics processing unit (GPU) is actually an array of programmable multiprocessors. For example, a programmable multiprocessor can be a streaming processor cluster (SPC), which includes... Figure 2 The diagram shows multiple streaming processor clusters. These clusters share data through a global cache or global memory.

[0037] like Figure 2 As shown, the multiple streaming processor clusters in a general-purpose graphics processor are divided into multiple resource partitions, and each resource partition includes multiple streaming processor clusters. For example... Figure 2 As shown, a streaming processor cluster includes multiple computing units (CUs). Each computing unit (CU) is used to perform arithmetic and logical operations, such as accumulation, reduction, and regular addition, subtraction, multiplication, and division.

[0038] A computing unit comprises multiple cores (also called computing kernels or computing cores). Each computing core includes an arithmetic logic unit (ALU), a floating-point unit, etc., and is used to execute specific computational tasks. In addition, the computing unit also includes a register file (e.g., ... Figure 2 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0039] In parallel computing, computational tasks are typically executed by multiple threads. These threads are divided into multiple thread blocks before execution in the graphics processing unit (or parallel computing processor), and then dispatched via a thread block distribution module. Figure 2 (Not shown in the image) Multiple thread blocks are distributed to various computation units. All threads in a thread block must be assigned to the same computation unit for execution. Simultaneously, thread blocks are broken down into minimum execution thread bundles (or simply warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute in the same computation unit or in different computation units.

[0040] In each computing unit, the thread beam scheduling / distribution module ( Figure 2 (Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can execute concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory-executed instructions are issued to shared memory within the computing unit or further issued to intermediate-level caches, global caches, or global memory (e.g., [example cache]). Figure 2 High Bandwidth Memory (HBM) is used for read and write operations.

[0041] For example, each resource partition includes multiple computing unit clusters, and each computing unit cluster includes multiple computing units. The number of computing units in different computing unit clusters may be different. Therefore, the number of computing unit clusters in each resource partition may also be different.

[0042] like Figure 2 As shown, each streaming processor cluster includes multiple computing units. The computing units in a streaming processor cluster can be divided into one or more computing unit clusters. Each computing unit cluster includes, for example, 2, 4, 8, etc., computing units. A computing unit cluster performs the same task.

[0043] For example, in one example, each resource partition includes N streaming processor clusters, each streaming processor cluster includes M computing units, and each resource partition includes M There are N computing units. Computing units are grouped into clusters of 2, 4, 8, etc. For example, in one resource partition, every 2 computing units form a cluster, and the 2 computing units are configured to jointly execute a task sent by the command processing dispatcher; in another resource partition, every 4 computing units form a cluster, and the 4 computing units are configured to jointly execute a task sent by the command processing dispatcher.

[0044] As mentioned earlier, the command dispatcher distributes the tasks decomposed by the command processor evenly to P resource partitions in the parallel processor, where P is a positive integer. The command dispatcher has P task pools, each corresponding to one of the P resource partitions, used to cache tasks to be dispatched to the corresponding resource partitions. When a resource partition can accept a task and the bus is ready, the task is popped from the task pool and sent to the bus.

[0045] Because the available computing resources vary across resource partitions—for example, the number of computing unit clusters within each partition is not identical—and the command dispatcher distributes the tasks decomposed by the command processor evenly across P resource partitions, a mismatch can occur between the number of tasks assigned to a particular resource partition and the number of computing unit clusters within that partition, resulting in unbalanced task scheduling. For instance, a resource partition with fewer computing unit clusters may receive a large number of tasks (exceeding its total number of clusters), causing hardware overload; conversely, a resource partition with more computing unit clusters may receive fewer tasks (less than its total number), leading to some clusters being idle and wasting resources.

[0046] In addition, in some scenarios, the received command packets are split into tasks that require exclusive access and processing. However, the current task scheduling method cannot achieve this exclusive access and processing, which increases the programming difficulty and the context overhead caused by task switching.

[0047] For example, the first command package performs a data prefetching operation, and the next command package performs the prefetched data processing operation. The tasks split from the first command package are evenly distributed to P resource partitions. It is possible that the number of tasks distributed to a certain resource partition is greater than the total number of computing unit clusters in that resource partition. Therefore, at least one computing unit cluster in that resource partition needs to perform a task switch, increasing the context overhead caused by the task switch. Furthermore, since it is a data prefetching operation, a new memory space needs to be allocated during programming to store the data of the switched tasks, avoiding data overwriting and preventing errors when processing the prefetched data later. Therefore, this also increases the programming difficulty and complexity.

[0048] Moreover, in some scenarios, it may be necessary to pause the processing of a certain resource partition, such as when there is a hardware malfunction in that resource partition. However, the current task scheduling method cannot achieve this. The command processing dispatcher cannot detect whether a resource partition is unusable. In this case, the tasks sent to that resource partition cannot be processed, which affects the normal operation and data read / write logic of the chip, causing the overall chip function to malfunction and become unusable.

[0049] This disclosure provides at least one embodiment of a processor, a task scheduling method, an electronic device, and a non-transitory computer-readable storage medium.

[0050] In at least one embodiment, the processor includes multiple resource partitions, a command processor, and a command processing dispatcher. Each resource partition includes multiple computing unit clusters, and each computing unit cluster includes multiple computing units. The multiple computing units in a computing unit cluster are configured to jointly execute a task. The command processor is configured to receive command packets, parse the command packets to generate multiple tasks, wherein the command packets carry a first identifier. In response to the first identifier indicating that a first scheduling method is used to schedule the multiple tasks, the command processing dispatcher is configured to distribute the multiple tasks to the multiple resource partitions according to the number of computing unit clusters included in each resource partition, wherein the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition. In response to the first identifier indicating that a second scheduling method is used to schedule the multiple tasks, the command processing dispatcher is configured to randomly distribute the multiple tasks to the multiple resource partitions, wherein the multiple resource partitions receive the multiple tasks evenly.

[0051] The processor provided in at least one embodiment of this disclosure is compatible with multiple task scheduling modes, supporting both the existing second scheduling mode (uniform scheduling mode) and a new first scheduling mode. In the first scheduling mode, the command processing dispatcher can distribute tasks according to the actual computing resources in each resource partition. The total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, ensuring that the number of tasks distributed to each resource partition matches the number of computing unit clusters in that resource partition, resulting in more balanced task scheduling. Simultaneously, since the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, exclusive access and computation of the computing unit clusters can be achieved, reducing the overhead of switching contexts when the computing unit clusters are processing different tasks, and reducing programming complexity to some extent.

[0052] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0053] Figure 3 A schematic structural diagram of a processor provided for at least one embodiment of this disclosure.

[0054] For example, the processor can be in the form of a chip, such as a System on Chip (SOC). An SOC can integrate modules such as a command processor, command dispatcher, resource partitions, processor core, memory, and peripheral interfaces (such as UART, SPI, and GPIO interfaces) into a single chip, forming a highly integrated hardware architecture.

[0055] For example, the chip may include a central processing unit, a graphics processing unit, a tensor processor, or other large-scale integrated circuits with data processing and / or instruction execution capabilities. Alternatively, the chip may include digital circuits or digital circuit units that implement specific functions, such as field-programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs).

[0056] In addition, the chip may also include auxiliary circuit modules to ensure the stable operation of command processors, command processing dispatchers, etc.

[0057] For example, the chip provided in at least one embodiment of this disclosure may specifically be a Graphic Processing Unit (GPU), a General-Purpose Graphics Processing Unit (GPGPU), a Tensor Processing Unit (TPU), a Data Processing Unit (DPU), a Neural Processing Unit (NPU), etc., and this disclosure does not impose specific limitations on it. This disclosure does not limit the function, form, or purpose of the processor.

[0058] For example, when the processor is a graphics processing unit (GPU) or a general-purpose GPU, the specific architecture of the processor can be referred to the aforementioned... Figure 2 Related descriptions.

[0059] like Figure 3 As shown, the processor 100 includes multiple resource partitions 101, a command processor 102, and a command processing dispatcher 103.

[0060] like Figure 3 As shown, each resource partition 101 includes multiple computing unit clusters, each computing unit cluster includes multiple computing units, and the multiple computing units in a computing unit cluster are configured to jointly execute a task.

[0061] For example, in some embodiments, the processor is a graphics processing unit (GPU) or a general-purpose GPU, each resource partition includes multiple streaming processor clusters, each streaming processor cluster includes multiple computing units, and the multiple computing units form one or more computing unit clusters. In this embodiment, the specific structure of the resource partition can be referred to the foregoing. Figure 2 The relevant descriptions will not be repeated here.

[0062] certainly, Figure 3 In the example, processor 100 may also include other circuits or units, and the connection relationship between the various circuits or units is unrestricted and can be determined according to actual needs.

[0063] It should be noted that in at least one embodiment of this disclosure, the processor 100 may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited and can be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0064] For example, the processor 100 may be implemented in hardware or a combination of hardware and software, and this disclosure does not impose any specific restrictions on it.

[0065] The command processor is configured to receive command packets, parse the command packets, and generate multiple tasks.

[0066] Command packets, for example, come from the host. The command processor receives command packets from the upper-layer host, breaks down single compound commands, and outputs several independently schedulable and executable tasks for downstream hardware (computing unit clusters) to process.

[0067] The command packet carries a first identifier.

[0068] The first identifier is bound to the command package, and different command packages can be configured with different first identifiers as needed. For example, some command packages require exclusive access to execute the command package, so the first identifier they carry can be a first identifier value. When the processor detects the first identifier value, it schedules multiple tasks using the first scheduling method. For example, other command packages do not require exclusive access to execute the command package, so the first identifier they carry can be a second identifier value. When the processor detects the second identifier value, it schedules multiple tasks using the original second task scheduling method.

[0069] For example, in one example, for a command packet that performs prefetching data, the first identifier carried by the command packet can be a first identifier value, indicating that when the command packet is executed, multiple tasks are scheduled using a first scheduling method; the next command packet performs processing on the prefetched data, and the first identifier carried by the command packet can be a second identifier value, indicating that when the command packet is executed, multiple tasks are scheduled using the original second task scheduling method.

[0070] In response to a first identifier indicating that multiple tasks are scheduled using a first scheduling method, the command processing dispatcher is configured to distribute the multiple tasks to multiple resource partitions based on the number of computing unit clusters included in each resource partition.

[0071] During the distribution of multiple tasks generated by the current command package, the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition.

[0072] Therefore, when scheduling multiple tasks using the first scheduling method, the command processing dispatcher can allocate tasks based on the actual computing resources of each resource partition. The total number of tasks sent to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, ensuring that the number of tasks sent to each resource partition matches the number of computing unit clusters in that resource partition, resulting in more balanced task scheduling. Simultaneously, since the total number of tasks sent to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, exclusive access and computation of the computing unit clusters can be achieved, reducing the overhead of switching contexts when the computing unit clusters are processing different tasks, and thus reducing programming complexity to some extent.

[0073] For example, in some embodiments, during the execution of multiple tasks generated by the command package, a computing unit cluster executes at most one task. Since the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, it is possible to ensure that a computing unit cluster executes at most one task. This enables exclusive access and computation for the computing unit cluster, reduces the overhead of switching contexts when the computing unit cluster is processing different tasks, and reduces programming complexity to some extent.

[0074] In response to the first identifier indicating that multiple tasks are scheduled using the second scheduling method, the command processing dispatcher is configured to randomly distribute the multiple tasks to multiple resource partitions, wherein the multiple resource partitions receive the multiple tasks evenly.

[0075] For example, when scheduling multiple tasks using the second scheduling method, the tasks are randomly distributed to multiple resource partitions, such as in a predetermined order, with each resource partition receiving multiple tasks evenly. The number of tasks received by the multiple resource partitions is roughly the same, and the differences in computing resources between resource partitions are not considered during task scheduling.

[0076] Therefore, in at least one embodiment of this disclosure, different command packages can adopt different task scheduling methods, and are compatible with multiple task scheduling modes. It supports the original second scheduling mode of uniform task scheduling, and also provides a new first scheduling mode of task scheduling based on actual computing resources in resource partitioning. This allows the processor to freely choose a more suitable task scheduling mode when facing different command packages, thereby improving the flexibility of task scheduling.

[0077] For example, in some embodiments, when the command processing dispatcher distributes the multiple tasks to the multiple resource partitions according to the number of computing unit clusters included in each resource partition, it includes performing the following operations: determining multiple destination resource partitions based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in the resource partition, and distributing the multiple tasks to the multiple destination resource partitions in sequence, wherein each destination resource partition is working normally, and at least one computing unit cluster in the destination resource partition is in an idle state capable of executing tasks.

[0078] The target resource partition is functioning normally if it is not in a failed state or has not been suspended; and if at least one computing unit cluster in the target resource partition is in an idle state capable of executing tasks, meaning that the resource partition can still receive new tasks and can be executed by the idle computing unit cluster.

[0079] For example, in some embodiments, registers or variables can be used to record the number of tasks that have been distributed to each resource partition and the number of computing unit clusters included in the resource partition. For example, the difference between the two can be used to indicate the target resource partition, and multiple tasks can be distributed to multiple target resource partitions in sequence.

[0080] For example, in some embodiments, the command processing dispatcher includes a poller, a plurality of first registers corresponding one-to-one with a plurality of resource partitions, and a plurality of second registers.

[0081] The command processing dispatcher is configured to adjust the current value in the first register corresponding to each resource partition based on the number of tasks that have been distributed to each resource partition and the number of computing unit clusters included in the resource partition.

[0082] The command dispatcher is also configured to set the second register corresponding to each resource partition to a first preset value when the current value in the first register is the first value, and to set the second register to a second preset value when the current value in the first register is not the first value. When the current value in the first register of a resource partition is the first value, it indicates that no further tasks should be sent to the resource partition; when the current value in the first register is not the first value, it indicates that further tasks should be sent to the resource partition.

[0083] The poller is configured to sequentially distribute multiple tasks to multiple destination resource partitions based on the current values ​​of multiple second registers, wherein the current values ​​of the second registers corresponding to the multiple destination resource partitions are second preset values.

[0084] For example, the command processing dispatcher also includes an arbitration module and multiple task pools that correspond one-to-one with multiple resource partitions. Each task pool is configured to cache the tasks issued by the poller to the resource partition corresponding to the task pool. The arbitration module communicates with multiple resource partitions through a bus and is configured to poll multiple task pools, and route the tasks in the task pool that has obtained arbitration to the corresponding resource partitions through the bus.

[0085] Figure 4 This is a schematic structural diagram of a command processing dispatcher provided in at least one embodiment of the present disclosure.

[0086] like Figure 4 As shown, the command processing dispatcher 103 includes a poller 1031, a plurality of first registers 1032 corresponding one-to-one with a plurality of resource partitions 101, and a plurality of second registers 1033.

[0087] To distinguish the descriptions, such as Figure 4 As shown, multiple resource partitions 101 are represented as resource partition 101_1, resource partition 101_2, ..., resource partition 101_P, where P is a positive integer greater than 1. Multiple first registers 1032 are represented as first register 1032_1, first register 1032_2, ..., first register 1032_P. Multiple second registers 1033 are represented as second register 1033_1, second register 1033_2, ..., second register 1033_P. First register 1032_1 and second register 1033_1 correspond to resource partition 101_1, first register 1032_2 and second register 1033_2 correspond to resource partition 101_2, ..., first register 1032_P and second register 1033_P correspond to resource partition 101_P.

[0088] like Figure 4 As shown, the command processing dispatcher includes multiple task pools 1034, each corresponding to one of the multiple resource partitions 101. Each task pool is configured to cache tasks distributed by the poller 1031 to the resource partition corresponding to the task pool. For clarity, as described below... Figure 4 As shown, multiple task pools 1034 include task pool 1034_1 corresponding to resource partition 101_1, task pool 1034_2 corresponding to resource partition 101_2, ..., and task pool 1034_P corresponding to resource partition 101_P. Task pool 1034_1 is configured to cache tasks sent to resource partition 101_1 by the poller 1031, task pool 1034_2 is configured to cache tasks sent to resource partition 101_2 by the poller 1031, ..., and task pool 1034_P is configured to cache tasks sent to resource partition 101_P by the poller 1031.

[0089] For example, the command processing dispatcher is configured to adjust the current value in the first register corresponding to the resource partition based on the number of tasks that have been dispatched to each resource partition and the number of computing unit clusters included in the resource partition.

[0090] Specifically, upon receiving a command packet, each first register is initialized to an initial value. This initial value is less than or equal to the total number of computing unit clusters included in the resource partition corresponding to the first register. For example, taking first register 1032_1 as an example, assuming the total number of computing unit clusters included in resource partition 101_1 is 4, the initial value of first register 1032_1 can be set to 4, or it could be 3, etc. Setting it to 4 allows for more efficient utilization of the computing resources in the resource partition.

[0091] Each first register is configured to, in response to the poller sending a task to the task pool corresponding to the resource partition corresponding to the first register, decrement the current value of the first register by 1 and write the result back to the first register.

[0092] After initialization, whenever the poller issues a task and caches it in a task pool, the current value of the first register corresponding to the resource partition of that task pool is decremented by 1, and the result is written back to the first register.

[0093] For example, taking the first register 1032_1 as an example, assuming that after initialization, the initial value of the first register 1032_1 is 4, when the poller issues a task and caches it in the task pool 1034_1, the current value of the first register 1032_1 is decremented by 1, becoming 3. When the poller issues another task and caches it in the task pool 1034_1, the current value of the first register 1032_1 is decremented by 1 again, becoming 2. And so on.

[0094] Since the total number of tasks assigned to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, when the current value in the first register becomes 0, it means that all computing unit clusters in the resource partition corresponding to the first register have been assigned tasks, and the resource partition can no longer receive new tasks as the destination resource partition.

[0095] For example, assuming the poller has already sent 4 tasks to resource partition 101_1, when the fourth task is sent and cached in task pool 1034_1, the current value of the first register 1032_1 becomes 0, indicating that no more tasks are allowed to be sent to resource partition 101_1.

[0096] For example, when the current value in the first register corresponding to each resource partition is the first value, the second register corresponding to the resource partition is set to the first preset value. When the current value in the first register corresponding to the resource partition is not the first value, the second register corresponding to the resource partition is set to the second preset value. When the current value in the first register corresponding to each resource partition is the first value, it means that no more tasks are allowed to be sent to the resource partition.

[0097] For example, in the aforementioned embodiment, the first value is 0. Taking the first register 1032_1 and the second register 1033_1 as examples, when the current value of the first register 1032_1 becomes 0, it indicates that no more tasks are allowed to be sent to resource partition 101_1. At this time, the current value of the second register 1033_1 is set to the first preset value (e.g., set to 0). When the current value of the first register 1032_1 is not 0, it indicates that tasks can still be sent to resource partition 101_1. At this time, the current value of the second register 1033_1 is set to the second preset value (e.g., set to any non-zero number).

[0098] like Figure 4 As shown, since each task assignment updates the value of the first register and may also trigger an update of the second register, the poller needs to read the current value of the second register before each task assignment to obtain the latest value. The poller is configured to sequentially assign multiple tasks to multiple destination resource partitions based on the current values ​​of the multiple second registers. The current value of the second register corresponding to the multiple destination resource partitions is a second preset value, that is, the second register indicates whether tasks can still be assigned to the resource partitions.

[0099] For example, when the poller distributes multiple tasks to multiple destination resource partitions in sequence based on the current values ​​of multiple second registers, it includes performing the following operations: distributing tasks to multiple resource partitions in a preset order, wherein, during the distribution process, the current value of the second register corresponding to the currently selected resource partition is read in the preset order; in response to the current value of the corresponding second register being a first preset value, the currently selected resource partition is skipped, and tasks are distributed to the next resource partition whose current value of the corresponding second register is not the first preset value in the preset order; in response to the current value of the corresponding second register being a second preset value, the currently selected resource partition is taken as the destination resource partition, and tasks are distributed to the selected resource partition.

[0100] For example, the poller sends tasks to P task pools in sequence. If the current value of the second register corresponding to a certain resource partition is the first preset value, then the resource partition is skipped and the task is sent to other resource partitions in sequence.

[0101] Specifically, assuming the preset order is resource partition 101_1, resource partition 101_2, ..., resource partition 101_P, the poller sends out tasks in sequence according to this preset order.

[0102] As mentioned earlier, assuming the first register 1032_1 is initialized to 4, the initial value of the second register 1033_1 is set to the second preset value. When the task is issued for the first time, the poller 1031 sends the task to the task pool 1034_1, and then sends it to the destination resource partition 101_1; the current value of the first register 1032_1 is decremented by 1, becoming 3, while the second register 1033_1 remains at the second preset value.

[0103] Assume that the first register 1032_2 is initialized to 2, and the initial value of the second register 1033_2 is set to the second preset value. When the task is issued for the second time, the poller 1031 sends the task to the task pool 1034_2, and then sends it to the destination resource partition 101_2; the current value of the first register 1032_2 is decremented by 1, becoming 1, while the second register 1033_2 remains at the second preset value.

[0104] The task was then distributed to resource partitions 101_3, etc., which will not be elaborated here.

[0105] During the second round of distribution, the current value of the first register 1032_2 is 1, and the current value of the second register 1033_2 is the second preset value. When the poller 1031 selects resource partition 101_2 again according to the preset order, the poller 1031 sends the task to the task pool 1034_2, and then sends it to the destination resource partition 101_2. The current value of the first register 1032_2 is decremented by 1 and becomes 0, and the second register 1033_2 is set to the first preset value.

[0106] Subsequently, during the third round of distribution, when poller 1031 selects resource partition 101_2 again according to a preset order, it reads the current value of the second register 1033_2 as the first preset value. At this point, it skips resource partition 101_2 and continues reading the current value of the second register 1033_3. Assuming the current value of the second register 1033_3 is the second preset value, the task is then assigned to task pool 1034_3 for subsequent distribution to the destination resource partition 101_3. Of course, if the current value of the second register 1033_3 is also the first preset value, it skips resource partition 101_3 and continues reading the current value of the second register 1033_4, and so on.

[0107] In this embodiment, a first register is used to record the relationship between the number of tasks already distributed to each resource partition and the number of computing unit clusters included in the resource partition. The current value of the first register is used to determine whether tasks can still be distributed to the corresponding resource partition. A second register is used to directly record whether a resource partition can be used as a destination resource partition. The second register acts on a poller. Before each task distribution, the poller needs to read the current value of the second register and skip resource partitions that are no longer allowed to distribute tasks. This ensures that the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, so that the number of tasks distributed to each resource partition matches the number of computing unit clusters in that resource partition, resulting in more balanced task scheduling.

[0108] Meanwhile, since the total number of tasks assigned to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition, exclusive access and computation of the computing unit clusters can be achieved, reducing the overhead of switching contexts when the computing unit clusters are processing different tasks, and reducing programming complexity to some extent.

[0109] For example, the processor is also configured to initialize multiple first registers by performing write accesses to memory-mapped input / output addresses, thereby configuring the initial values ​​of multiple first registers. In other words, the initial values ​​of the first registers are flexibly configurable. Users can adjust the initial values ​​of the first registers according to the requirements of the current command package or the operations to be performed, so that the task scheduling is more adapted to the tasks of the command packages to be processed, and the scheduling is more balanced.

[0110] For example, the command processing dispatcher is also configured to, in response to at least one resource partition failing or suspending the use of at least one resource partition, set the initial value of the first register corresponding to each of the at least one resource partition to a first value.

[0111] For example, in some embodiments, some resource partitions may be unusable due to failure or damage; in other embodiments, it may be necessary to suspend the use of some resource partitions depending on usage. In such cases, in at least one embodiment of this disclosure, this can be achieved by setting the initial value of the first register corresponding to these resource partitions to a first value.

[0112] For example, in one scenario, the initial value of the first register corresponding to these resource partitions can be set to 0, then the second register of these resource partitions is set to the first preset value. When the poller issues tasks, it will skip these resource partitions after reading the current value of the second register, thus avoiding sending tasks to these unusable resource partitions at the scheduling level. This allows the processor to continue to function normally, effectively improving the processor's robustness and yield.

[0113] It should be noted that this disclosure is not limited thereto. For example, in some other embodiments, the first scheduling mode provided in at least one embodiment of this disclosure can also be implemented by combining hardware and software code. This disclosure does not impose any specific restrictions on this.

[0114] certainly, Figure 4 In the example, the command processing dispatcher 103 may also include other circuits or units, and the connection relationship between the various circuits or units is unrestricted and can be determined according to actual needs.

[0115] It should be noted that, in at least one embodiment of this disclosure, the command processing dispatcher 103 may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited and can be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0116] For example, the command processing dispatcher 103 can be implemented in hardware or a combination of hardware and software, and this disclosure does not impose any specific restrictions on it.

[0117] At least one embodiment of this disclosure also provides an electronic device. Figure 5 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure.

[0118] like Figure 5 As shown, the electronic device 200 includes a processor 100. Further description of the processor 100 can be found in the relevant descriptions of the foregoing embodiments, and will not be repeated here.

[0119] For example, the electronic device could be a multi-GPU system, which integrates multiple GPU cards and works together to complete large-scale parallel computing tasks. This architecture is commonly used for tasks such as artificial intelligence training, scientific computing, and high-performance graphics rendering.

[0120] For example, in some embodiments, the electronic device 200 provided in at least one embodiment of this disclosure can be a single-machine multi-card form, where multiple GPU cards are integrated in a single server or workstation, and inter-card communication is achieved through a bus (such as PCIe bus, AMD bus, etc.). For example, the electronic device 200 can also be a multi-machine multi-card form, where multiple single-machine multi-card servers are interconnected through a high-speed network to form a cluster, and each card can not only communicate with other cards in the same machine, but also interact with cards in other groups through the network.

[0121] For example, electronic device 200 can also be a TPU cluster, a multi-FPGA accelerator card system, etc., and this disclosure does not impose specific limitations on it.

[0122] For example, this electronic device 200 overcomes the limitations of single-card computing power or memory through parallel computing, and is therefore widely used in scenarios requiring large-scale data processing, high-throughput computing, or low-latency parallel tasks. Examples include deep learning and large model training, high-performance computing, large-scale data processing and AI inference, real-time rendering and visualization, and it can be applied to fields such as large model training, scientific computing, high-concurrency AI services, and real-time rendering.

[0123] Figure 6 This is a schematic diagram of the specific structure of an electronic device provided in at least one embodiment of the present disclosure.

[0124] The following is for reference. Figure 6 It illustrates a specific structural diagram of an electronic device (e.g., a terminal device or a server) 200 suitable for implementing a processor including embodiments of the present disclosure.

[0125] The electronic devices in this disclosure can include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. For example, the electronic device can be in the form of a server, used for various application scenarios such as deep learning and artificial intelligence, scientific computing, graphics rendering and video editing, virtual reality and game development, and cloud services. For example, the electronic device can be a dedicated server such as a data center or cloud computing center that is deployed for tasks such as deep learning training, large-scale data analysis, and high-performance computing.

[0126] Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0127] like Figure 6 As shown, the electronic device 200 may include a processing unit 201, such as the aforementioned processor 100, which can execute various appropriate actions and processes according to non-transitory computer-readable instructions stored in memory to achieve various functions. The processing unit 201 may also include devices with instruction optimization capabilities and / or program execution capabilities, such as a central processing unit (CPU) or a tensor processor (TPU). The CPU can be based on x86, ARM, or RISC-V architectures. The GPU can be directly integrated into the SOC, directly integrated onto the motherboard, or built into the northbridge chip of the motherboard.

[0128] like Figure 6As shown, for example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 203 and / or cache memory, etc., for example, computer-readable instructions may be loaded from storage device 208 into RAM 203 to execute computer-readable instructions. Non-volatile memory may include, for example, read-only memory (ROM) 202, hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. Various applications and various data, such as various data used and / or generated by applications, may also be stored in the computer-readable storage medium.

[0129] For example, the processing device 201, the read-only memory (ROM) 202, and the random access memory (RAM) 203 are interconnected via bus 204. Input / output (I / O) interface 205 is also connected to bus 204.

[0130] Typically, the following devices can be connected to the input / output (I / O) interface 205: input devices 206 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 207 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 208 including, for example, magnetic tape, hard disk, flash memory, etc.; and communication devices 209. Communication device 209 allows electronic device 200 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 6 An electronic device 200 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 200 may alternatively implement or have more or fewer devices. For example, the processing device 201 may control other components in the electronic device 200 to perform desired functions.

[0131] At least one embodiment of this disclosure also provides a task scheduling method. Figure 7 This is a schematic flowchart illustrating a task scheduling method provided in at least one embodiment of the present disclosure.

[0132] This task scheduling method is applied to a processor, which includes multiple resource partitions, a command processor, and a command processing dispatcher.

[0133] Each resource partition includes multiple compute unit clusters, and each compute unit cluster includes multiple compute units. The multiple compute units in a compute unit cluster are configured to jointly execute a task.

[0134] For a more detailed description of the processor's structure, please refer to the aforementioned content on processor 100, which will not be repeated here.

[0135] like Figure 7 As shown, the task scheduling method includes steps S10-S30.

[0136] In step S10, a command packet is received, and the command processor parses the command packet to generate multiple tasks.

[0137] The command packet carries a first identifier.

[0138] In step S20, in response to the first identifier indicating that multiple tasks are scheduled using the first scheduling method, the command processing distributor distributes the multiple tasks to multiple resource partitions according to the number of computing unit clusters included in each resource partition.

[0139] During the distribution of multiple tasks, the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition.

[0140] In step S30, in response to the indication of the first identifier to schedule multiple tasks using the second scheduling method, the command processing dispatcher randomly distributes the multiple tasks to multiple resource partitions, wherein the multiple resource partitions receive the multiple tasks evenly.

[0141] This task scheduling method provides multiple task scheduling modes, supporting both the existing second scheduling mode (uniform scheduling mode) and a new first scheduling mode. In the first scheduling mode, the command processing dispatcher can distribute tasks based on the actual computing resources in each resource partition. The total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in that resource partition, ensuring that the number of tasks distributed to each resource partition matches the number of computing unit clusters in that resource partition, resulting in more balanced task scheduling. Simultaneously, since the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in that resource partition, exclusive access and computation by the computing unit clusters can be achieved, reducing the overhead of switching contexts when the computing unit clusters are processing different tasks, and thus reducing programming complexity to some extent.

[0142] For example, in some embodiments, step S20 may include: the command processing dispatcher determining multiple destination resource partitions based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in the resource partition, and distributing multiple tasks sequentially to the multiple destination resource partitions, wherein each destination resource partition is working normally, and at least one computing unit cluster in the destination resource partition is in an idle state capable of executing tasks.

[0143] For example, in some embodiments, the command processing dispatcher includes a poller, a plurality of first registers corresponding one-to-one with a plurality of resource partitions, and a plurality of second registers.

[0144] For example, the command dispatcher determines multiple destination resource partitions based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in the resource partition, and distributes multiple tasks sequentially to the multiple destination resource partitions. This can include: adjusting the current value in the first register corresponding to each resource partition based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in the resource partition; setting the second register corresponding to each resource partition to a first preset value when the current value in the first register corresponding to each resource partition is a first value, and setting the second register corresponding to each resource partition to a second preset value when the current value in the first register corresponding to each resource partition is not a first value, wherein when the current value in the first register corresponding to each resource partition is a first value, it means that no more tasks are allowed to be sent to the resource partition; and the poller distributes multiple tasks sequentially to the multiple destination resource partitions based on the current values ​​of the multiple second registers, wherein the current value of the second register corresponding to the multiple destination resource partitions is the second preset value.

[0145] For example, in some embodiments, the poller distributes multiple tasks to multiple destination resource partitions in sequence according to the current values ​​of multiple second registers. This may include: distributing tasks to multiple resource partitions in a preset order, wherein during the traversal, resource partitions whose corresponding second registers have a first preset value are skipped, and tasks are sequentially distributed to other destination resource partitions whose corresponding second registers do not have the first preset value.

[0146] For example, in some embodiments, the task scheduling method further includes: in response to at least one resource partition failing or suspending the use of at least one resource partition, setting the value of a first register corresponding to each of the at least one resource partition to a first value.

[0147] For example, in some embodiments, some resource partitions may be unusable due to failure or damage; in other embodiments, it may be necessary to suspend the use of some resource partitions depending on usage. In such cases, in at least one embodiment of this disclosure, this can be achieved by setting the initial value of the first register corresponding to these resource partitions to a first value.

[0148] For more details about step S10, please refer to the description of the command processor 102 of the aforementioned processor 100. For more details about steps S20-S30, please refer to the description of the command processing dispatcher 103 of the aforementioned processor 100. These details will not be repeated here.

[0149] The task scheduling method provided in at least one embodiment of this disclosure can achieve similar technical effects to the aforementioned processor, and will not be described in detail here.

[0150] At least one embodiment also discloses an electronic device including a processing device and a storage device, the storage device including one or more computer program modules configured to non-transitory store computer-executable instructions; wherein the computer-executable instructions are stored in the storage device and configured to be executed by the processing device, and the computer-executable instructions, when run, implement the task scheduling method provided in at least one embodiment.

[0151] For example, the processing device may be a processor, such as a central processing unit (CPU), digital signal processor (DSP), image processor (GPU), general-purpose graphics processor (GPGPU), or other form of processing unit with data processing capabilities and / or instruction execution capabilities. It may be a general-purpose processor or a dedicated processor and may control other components in the electronic device to perform the desired functions.

[0152] For example, the storage device may be a memory, which may include one or more computer program products. These computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium. A processing device may execute these program instructions to implement the functions (implemented by the processing device) in at least one of the disclosed embodiments and / or other desired functions. Various application programs and various data may also be stored in the computer-readable storage medium, which is not limited in the disclosure of at least one embodiment.

[0153] For example, a structural schematic diagram of this electronic device can be referenced. Figure 6 The relevant descriptions will not be repeated here.

[0154] Figure 8 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of this disclosure. For example, such as Figure 8 As shown, storage medium 300 can be a non-transitory computer-readable storage medium on which one or more computer-readable instructions 301 can be stored non-transitory. For example, when the computer-readable instructions 301 are executed by a processor, one or more steps in the task scheduling method described above can be performed.

[0155] For example, the storage medium 300 can be used in the electronic device 200, and the storage medium 300 may include the storage device 208 in the electronic device 200.

[0156] For example, the storage medium may include a memory card for a smartphone, a cache component for a tablet computer, a hard disk for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media.

[0157] In particular, according to at least one embodiment of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, at least one embodiment of this disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such a case, the computer program can be downloaded and installed from a network via communication device 209, or installed from storage device 208, or installed from ROM 202. When the computer program is executed by processing device 201, it performs the functions defined in at least one embodiment of this disclosure.

[0158] The electronic device 200 provided in at least one embodiment of this disclosure and the task scheduling method provided in at least one embodiment of this disclosure are based on the same inventive concept and can achieve the same technical effect and the same technical purpose as the task scheduling method provided in at least one embodiment of this disclosure. For details, please refer to the relevant description above, which will not be repeated here.

[0159] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this document, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0160] The computer-readable storage medium provided in at least one embodiment of this disclosure and the task scheduling method provided in at least one embodiment of this disclosure are based on the same inventive concept and can achieve the same technical effect and the same technical purpose as the task scheduling method provided in at least one embodiment of this disclosure. For details, please refer to the relevant description above, which will not be repeated here.

[0161] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0162] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the aforementioned task scheduling method.

[0163] Computer program code for performing the operations described herein may be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0164] At least one embodiment of this disclosure also provides a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described herein are generated.

[0165] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0166] When the computer program product is executed by a computer, the computer performs any of the aforementioned task scheduling methods. The computer program product can be a software installation package; when any of the aforementioned task scheduling methods is required, the computer program product can be downloaded and executed on the computer.

[0167] The computer program product provided in at least one embodiment of this disclosure is based on the same inventive concept as the task scheduling method provided in at least one embodiment of this disclosure. It can achieve the same technical effect and the same technical purpose as the task scheduling method provided in at least one embodiment of this disclosure. For details, please refer to the relevant description above, which will not be repeated here.

[0168] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0169] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0170] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0171] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0172] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0173] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0174] The following points should be noted regarding this disclosure: (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0175] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0176] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A processor, characterized in that, Includes multiple resource partitions, command processors, and command processing dispatchers. Each resource partition comprises multiple compute unit clusters, and each compute unit cluster comprises multiple compute units. The multiple compute units in a compute unit cluster are configured to jointly execute a single task. The command processor is configured to receive command packets, parse the command packets to generate multiple tasks, wherein the command packets carry a first identifier. In response to the first identifier indicating that the plurality of tasks are scheduled using a first scheduling method, the command processing dispatcher is configured to distribute the plurality of tasks to the plurality of resource partitions according to the number of computing unit clusters included in each resource partition, wherein the total number of tasks distributed to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition. In response to the first identifier indicating that the plurality of tasks are scheduled using a second scheduling method, the command processing dispatcher is configured to randomly distribute the plurality of tasks to the plurality of resource partitions, wherein the plurality of resource partitions are configured to receive the plurality of tasks evenly.

2. The processor according to claim 1, characterized in that, When the multiple tasks are scheduled in the first scheduling mode, during the execution of the multiple tasks generated by the command package, a computing unit cluster executes at most one task.

3. The processor according to claim 1, characterized in that, When the command processing dispatcher distributes the multiple tasks to the multiple resource partitions according to the number of computing unit clusters included in each resource partition, it includes performing the following operations: Based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in each resource partition, multiple destination resource partitions are determined, and the multiple tasks are sequentially distributed to the multiple destination resource partitions. Each destination resource partition operates normally, and at least one computing unit cluster within the destination resource partition is in an idle state capable of executing tasks.

4. The processor according to claim 3, characterized in that, The command processing dispatcher includes a poller, multiple first registers and multiple second registers corresponding one-to-one with the multiple resource partitions. The command processing dispatcher is configured to adjust the current value in the first register corresponding to the resource partition based on the number of tasks that have been distributed to each resource partition and the number of computing unit clusters included in the resource partition. The command processing dispatcher is further configured to set the second register corresponding to the resource partition to a first preset value when the current value in the first register corresponding to the resource partition is a first value, and to set the second register corresponding to the resource partition to a second preset value when the current value in the first register corresponding to the resource partition is not the first value. When the current value in the first register corresponding to the resource partition is the first value, it means that no more tasks are allowed to be sent to the resource partition. The poller is configured to distribute the plurality of tasks sequentially to the plurality of destination resource partitions based on the current values ​​of the plurality of second registers, wherein the current value of the second register corresponding to the plurality of destination resource partitions is the second preset value.

5. The processor according to claim 4, characterized in that, The command processing dispatcher includes multiple task pools, each corresponding to one of the multiple resource partitions. Each task pool is configured to cache tasks sent by the poller to the resource partition corresponding to that task pool. Upon receiving the command packet, each first register is initialized to an initial value, wherein the initial value is less than or equal to the total number of computing unit clusters included in the resource partition corresponding to the first register; Each first register is configured to, in response to the poller sending a task to the task pool corresponding to the resource partition corresponding to the first register, decrement the current value of the first register by 1 and write the result back to the first register, wherein the first value is 0.

6. The processor according to claim 5, characterized in that, The processor is further configured to initialize the plurality of first registers by performing write accesses to memory-mapped input / output addresses and configuring initial values ​​for the plurality of first registers.

7. The processor according to claim 4, characterized in that, When the poller distributes the multiple tasks sequentially to the multiple destination resource partitions based on the current values ​​of the multiple second registers, it includes performing the following operations: Tasks are distributed sequentially to the multiple resource partitions in a preset order. During the distribution process, the current value of the second register corresponding to the currently selected resource partition is read according to the preset order. In response to the current value of the corresponding second register being the first preset value, the currently selected resource partition is skipped, and the task is distributed to the next resource partition whose current value of the corresponding second register is not the first preset value, according to the preset order. In response to the current value of the corresponding second register being the second preset value, the currently selected resource partition is taken as the destination resource partition, and the task is distributed to the currently selected resource partition.

8. The processor according to claim 4, characterized in that, The command processing dispatcher is further configured to, in response to at least one resource partition failing or being suspended from use, set the initial value of the first register corresponding to each of the at least one resource partition to the first value.

9. The processor according to claim 4, characterized in that, The command processing and dispatching unit also includes an arbitration module and multiple task pools corresponding one-to-one with the multiple resource partitions. Each task pool is configured to cache tasks sent by the poller to the resource partition corresponding to the task pool. The arbitration module communicates with the multiple resource partitions via a bus and is configured to poll the multiple task pools, routing the tasks in the task pool that have obtained arbitration to the corresponding resource partitions via the bus.

10. The processor according to any one of claims 1-9, characterized in that, The processor is a graphics processor or a general-purpose graphics processor. Each resource partition includes multiple streaming processor clusters, and each streaming processor cluster includes multiple computing units. The multiple computing units form one or more computing unit clusters.

11. An electronic device, characterized in that, Includes the processor as described in any one of claims 1-10.

12. A task scheduling method, characterized in that, Applied to a processor, the processor including multiple resource partitions, a command processor, and a command processing dispatcher, Each resource partition comprises multiple compute unit clusters, and each compute unit cluster comprises multiple compute units. The multiple compute units in a compute unit cluster are configured to jointly execute a single task. The task scheduling method includes: A command packet is received, and the command processor parses the command packet to generate multiple tasks, wherein the command packet carries a first identifier; In response to the first identifier indicating that the plurality of tasks are scheduled using a first scheduling method, the command processing dispatcher distributes the plurality of tasks to the plurality of resource partitions according to the number of computing unit clusters included in each resource partition, wherein during the distribution of the plurality of tasks, the total number of tasks sent to each resource partition is less than or equal to the total number of computing unit clusters included in the resource partition. In response to the first identifier indicating that the plurality of tasks are scheduled using the second scheduling method, the command processing distributor randomly distributes the plurality of tasks to the plurality of resource partitions, wherein the plurality of resource partitions are configured to receive the plurality of tasks evenly.

13. The task scheduling method according to claim 12, characterized in that, The command processing distributor distributes the multiple tasks to the multiple resource partitions according to the number of computing unit clusters included in each resource partition, including: The command processing dispatcher determines multiple destination resource partitions based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in each resource partition, and then distributes the multiple tasks sequentially to the multiple destination resource partitions. Each destination resource partition operates normally, and at least one computing unit cluster within the destination resource partition is in an idle state capable of executing tasks.

14. The task scheduling method according to claim 13, characterized in that, The command processing dispatcher includes a poller, multiple first registers and multiple second registers corresponding one-to-one with the multiple resource partitions. The command processing dispatcher determines multiple destination resource partitions based on the number of tasks already distributed to each resource partition and the number of computing unit clusters included in each resource partition, and sequentially distributes the multiple tasks to the multiple destination resource partitions, including: Adjust the current value in the first register corresponding to the resource partition based on the number of tasks that have been distributed to each resource partition and the number of computing unit clusters included in the resource partition; When the current value in the first register corresponding to the resource partition is the first value, the second register corresponding to the resource partition is set to the first preset value. When the current value in the first register corresponding to the resource partition is not the first value, the second register corresponding to the resource partition is set to the second preset value. When the current value in the first register corresponding to each resource partition is the first value, it means that no more tasks are allowed to be sent to the resource partition. The poller distributes the multiple tasks sequentially to the multiple destination resource partitions based on the current values ​​of the multiple second registers, wherein the current value of the second register corresponding to the multiple destination resource partitions is the second preset value.

15. The task scheduling method according to claim 14, characterized in that, The poller distributes the multiple tasks sequentially to the multiple destination resource partitions based on the current values ​​of the multiple second registers, including: Tasks are distributed sequentially to the multiple resource partitions in a preset order. During the traversal, resource partitions whose corresponding second register is the first preset value are skipped, and tasks are sequentially distributed to other target resource partitions whose corresponding second register is not the first preset value.

16. The task scheduling method according to claim 14, characterized in that, The task scheduling method further includes: In response to at least one resource partition becoming invalid or being suspended from use, the value of the first register corresponding to each of the at least one resource partition is set to the first value.

17. An electronic device, characterized in that, include: A storage device that stores computer-executable instructions non-transiently; Processing device, configured to run the computer-executable instructions, The computer-executable instructions are executed by the processing device to implement the task scheduling method according to any one of claims 12-16.

18. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by the processor, they implement the task scheduling method according to any one of claims 12-16.

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