Apparatus and method for independent reset and configuration recovery of bmc dual-core heterogeneous system

Abstract

The application discloses a kind of BMC dual-core heterogeneous system independent reset and configuration recovery device and method, device includes: first processor system, second processor system, configuration register monitoring module;First processor system contains first processor core and first watchdog timer hung under it;Second processor system contains second processor core and second watchdog timer hung under it;Configuration register monitoring module includes configuration latch unit, reset reason register, the configuration register monitoring module works in the clock domain independent from the clock tree of first, second processor system, the clock source of clock domain is not influenced by the clock gating and reset of first processor system and second processor system;Reset input end of configuration register monitoring module is only coupled to chip global reset signal, not coupled to any local reset signal.The application is adopted, realizes the independent reset between core and configuration fast recovery, improves system reliability and recovery efficiency.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and embedded technology, and in particular to an independent reset and configuration recovery device and method for a BMC dual-core heterogeneous system. Background Technology

[0002] The Baseboard Management Controller (BMC) is a dedicated management chip deployed on the server motherboard. It operates independently of the host CPU and operating system, and is responsible for real-time monitoring, logging, remote management, and fault recovery of the server's hardware status. As data centers increasingly demand higher reliability and security from server management, BMC chips are evolving from traditional single-core architectures to heterogeneous dual-core architectures. These typically include a security core running a real-time operating system (such as AUTOSAR) for high-security management tasks, and an application core running a general-purpose operating system (such as Linux) for upper-level management functions. In this architecture, the two processor cores handle management tasks at different security levels, working together to manage the server throughout its entire lifecycle.

[0003] Currently, reset management in BMC dual-core heterogeneous systems mainly adopts the following technical solutions: The first is a unified chip-wide reset mechanism, where when any processor core or its subsystem hangs due to a software anomaly, a watchdog timer triggers a global reset signal covering the entire chip, resetting the security core, application core, bus controller, all peripherals, and configuration registers to their default states. After the reset is released, both cores execute the complete initialization process from the beginning. The second is a hierarchical reset scheme based on an external programmable logic device (CPLD). By adding a CPLD outside the chip to receive fault signals from each subsystem, the CPLD makes the decision and resets only the faulty subsystem. In addition, for the preservation and restoration of configuration information after reset, existing technologies typically use two methods: one is to write key configuration parameters into non-volatile memory (NVM) before reset and then read them back after reset; the other is to set a write-once memory-mapped register (WMR) inside the system-on-chip (SoC) to save a small amount of static configuration information.

[0004] However, the above solution has the following shortcomings: First, the reset granularity is too coarse, making independent reset between cores impossible. Under a unified reset mechanism across the entire chip, an anomaly in one core will force another normally functioning core to restart, expanding the scope of service interruption and prolonging system recovery time. While solutions based on external CPLDs can achieve hierarchical reset, they increase system complexity, cost, and PCB area, and the reset strategy is fixed to external components, reducing chip integration and reliability.

[0005] Second, configuration information is lost after reset, resulting in low recovery efficiency. Whether it is a full chip reset or a partial reset, the configuration registers inside each subsystem are cleared or reset to default values ​​during the reset process. After the reset is released, the processor must re-execute the complete initialization process to restore the configuration item by item, resulting in a long system recovery time and making it difficult to meet the rapid self-healing requirements of high-availability servers.

[0006] Third, existing configuration saving schemes have fatal shortcomings in emergency reset scenarios: the software-based NVM writing method requires the CPU to be in a state where it can execute instructions normally before the reset. However, in emergency scenarios triggered by watchdog timer timeout, the CPU is often in an abnormal state and cannot reliably perform the write operation. In addition, the NVM write speed is slow and cannot guarantee that critical configurations will be saved before the reset signal takes effect. Although the Write-Once MMR method does not require software intervention, its storage capacity is extremely limited. It can only save a very small number of factory-set static configuration items and cannot dynamically track and latch the state of a large number of configuration registers that are constantly changing during system operation. Summary of the Invention

[0007] This application provides an independent reset and configuration recovery device for a BMC dual-core heterogeneous system. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0008] In a first aspect, embodiments of this application provide an independent reset and configuration recovery device for a BMC dual-core heterogeneous system, the device comprising: The system comprises a first processor system, a second processor system, and a configuration register monitoring module; the configuration register monitoring module is communicatively connected to both the first processor system and the second processor system; wherein... The first processor system includes a first processor core and a first watchdog timer mounted thereon; the second processor system includes a second processor core and a second watchdog timer mounted thereon; The configuration register monitoring module includes a configuration latch unit and a reset reason register. The configuration register monitoring module operates in a clock domain independent of the clock trees of the first and second processor systems. The clock source of this clock domain is not affected by the clock gating and reset of the first and second processor systems. The reset input of the configuration register monitoring module is coupled only to the chip's global reset signal and not to any local reset signal.

[0009] Optional, a watchdog timer is used to monitor the running status of the corresponding processor core. If the count times out, it outputs a timeout signal to the reset control logic unit and configuration register monitoring module of the target processor system in which it resides. The configuration register monitoring module is used to latch the current configuration register information of the target processor system into the configuration latch unit in its own independent clock domain in response to the timeout signal, and record the corresponding reset reason in the reset reason register. The reset control logic unit is used to generate a partial reset signal in response to a timeout signal, which is applied only to the target processor system to perform a partial reset, while the other processor system continues to run. After the partial reset signal is released, the reset processor core reads the reset reason register to determine the reset type. If it is a partial reset, it reads the latch configuration from the configuration latch unit and restores it directly. If it is a global reset, it executes the complete default initialization process. The chip global reset signal comes from the chip's PAD port. When it is valid, it simultaneously resets the first processor system, the second processor system, and the configuration register monitoring module, and clears the configuration latch unit and the reset reason register.

[0010] Optionally, the configuration register monitoring module is also used to track the configuration register information of the first processor system and the second processor system in real time under an independent clock domain during the independent normal operation of the first processor system and the second processor system, and update it to the configuration latch unit after cross-clock domain synchronization; The configuration register monitoring module is also used to re-track and latch the configuration register information of each processor system in real time under an independent clock domain after the global reset signal is released and the first and second processor systems have completed initialization.

[0011] Optionally, the first processor core is connected to the first peripheral group via the first bus and has an independent first reset domain; The second processor core is connected to the second peripheral group via a second bus and has an independent second reset domain.

[0012] Optionally, the configuration register monitoring module includes a configuration latch unit, latch control logic, and a reset reason register; wherein, The configuration latch unit includes a first latch register group and a second latch register group, which are used to latch the configuration information of the first processor system and the second processor system, respectively. The latch control logic is used to control the configuration latch unit to freeze and save the current configuration information when it receives the first timeout signal output by the first watchdog timer or the second timeout signal output by the second watchdog timer. The reset reason register is used to record the source of the reset. The reset reason register contains a first flag bit for indicating that the first watchdog timer has timed out, a second flag bit for indicating that the second watchdog timer has timed out, and a third flag bit for indicating that the global reset signal has been received.

[0013] Optionally, the configuration register monitoring module also includes: An independent clock management unit is used to receive the independent oscillator clock signal and provide the working clock for the configuration latch unit, latch control logic, and reset reason register; the independent oscillator clock signal is not affected by the clock gating and reset of the first processor system and the second processor system; The bus interface unit includes bus interfaces that are respectively connected to the first processor system and the second processor system, and are used to allow the first processor core and the second processor core to read data from the reset cause register and the configuration latch unit.

[0014] Optionally, the current configuration register information of the target processor system is latched into the configuration latch unit under its own independent clock domain, and the corresponding reset reason is recorded in the reset reason register, including: Upon detecting a timeout signal, the current configuration register information of the target processor system is frozen and latched into the corresponding latch register group in the configuration latch unit within 1 to 2 clock cycles of independent clock domains. At the same time, the flag bit in the reset reason register corresponding to the target processor system is set.

[0015] Optionally, a partial reset may be performed, including: A local reset signal is applied to the processor core, watchdog timer, bus controller, and peripherals within the target processor system, resetting them to their default states; among which... The local reset signal does not apply to another processor system, nor to the configuration register monitoring module.

[0016] Optionally, the latch configuration can be read from the configuration latch unit and restored directly, including: The configuration register information latched by the target processor system before reset is read from the configuration latch unit via the bus interface; the configuration register information includes clock configuration parameters, bus configuration parameters, peripheral enable configuration, and interrupt configuration. The reset processor core directly restores the hardware configuration of the corresponding subsystem based on the read configuration register information, skipping the complete default initialization process; Restore the operating system and restart the watchdog timer feeding mechanism.

[0017] Optionally, execute the full default initialization process, including: After the global reset signal is released, the first processor core reconfigures the clock, bus, peripheral enable and interrupt parameters according to the hardware default values, and reloads the operating system; The second processor core reconfigures the clock, bus, peripheral enable, and interrupt parameters according to the hardware defaults, and reloads the operating system; Neither the first processor core nor the second processor core reads the configuration from the configuration latch unit.

[0018] Secondly, an independent reset and configuration recovery method for a BMC dual-core heterogeneous system is applied to a real-time monitoring module. The method includes: The watchdog timer monitors the running status of the corresponding processor core. When the count expires, it outputs a timeout signal to the reset control logic unit and configuration register monitoring module of the target processor system in which it resides. In response to the timeout signal, the configuration register monitoring module latches the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain, and records the corresponding reset reason in the reset reason register. In response to the timeout signal, the reset control logic unit generates a partial reset signal that acts only on the target processor system to perform a partial reset, while the other processor system continues to run. After the partial reset signal is released, the reset processor core reads the reset reason register to determine the reset type. If it is a partial reset, it reads the latch configuration from the configuration latch unit and restores it directly. If it is a global reset, it executes the complete default initialization process.

[0019] The technical solutions provided in this application embodiment may include the following beneficial effects: In this embodiment, on the one hand, by setting up a configuration register monitoring module independent of the first and second processor systems, and coupling its reset input terminal only to the chip's global reset signal and not to any local reset signal, circuit-level isolation of the reset domain is achieved. In this case, when the first or second watchdog timer times out, the local reset signal generated by the reset control logic unit only acts on the corresponding target processor system, while the other processor system continues to operate normally. Therefore, this application can limit the impact of an anomaly of one core to the subsystem where that core resides, avoiding the expansion of the service interruption scope and significantly shortening the overall system recovery time. Simultaneously, this application does not require additional external components; independent inter-core reset can be achieved internally through reset signal routing isolation, reducing system complexity, cost, and PCB area, and improving chip integration and reliability.

[0020] On the other hand, during the independent operation of the first and second processor systems, the configuration register monitoring module tracks and latches the configuration register information of each processor system in real time under an independent clock domain. When the watchdog timer times out and issues a timeout signal, the configuration register monitoring module responds to the timeout signal by latching the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain. After the partial reset signal is released, the reset processor core reads the latched configuration information from the configuration latch unit and directly restores itself, skipping the complete default initialization process. This application retains the runtime configuration before reset through a hardware latching mechanism, meeting the rapid self-healing requirements of high-availability servers.

[0021] On the other hand, through the hardware latching mechanism of the configuration register monitoring module, when the watchdog timer timeout signal is triggered, the latching control logic directly freezes and latches the current configuration register information to the configuration latch unit at the hardware level. The entire process does not require the processor core to participate in executing any software instructions and is independent of whether the processor core can run reliably in abnormal states. Compared with the software-based NVM writing scheme, this application avoids the problems of not being able to perform write operations in abnormal CPU states and the slow NVM write speed preventing the saving from being completed before the reset signal takes effect. Compared with the Write-Once MMR scheme, the configuration latch unit of this application includes a first latch register group and a second latch register group, which are used to latch the configuration information of the first processor system and the second processor system, respectively. It can dynamically track and latch the constantly changing states of a large number of configuration registers during system operation, rather than being limited to a very small number of factory-set static configuration items. In addition, this application independently records the flag bits of each watchdog timer timeout and global reset through the reset reason register, making the reset source traceable and providing a reliable hardware-level basis for system fault diagnosis.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0024] Figure 1 This is a schematic diagram of the device structure of an independent reset and configuration recovery device for a BMC dual-core heterogeneous system provided in an embodiment of this application; Figure 2 This is a flowchart illustrating an independent reset and configuration recovery method for a BMC dual-core heterogeneous system provided in an embodiment of this application. Figure 3This is a schematic diagram of the watchdog timeout monitoring and signal output logic of a BMC dual-core heterogeneous system provided in an embodiment of this application; Figure 4 This is a schematic diagram of the hardware processing flow of a configuration register monitoring module after receiving a watchdog timeout signal, provided in an embodiment of this application. Figure 5 This is a schematic diagram of a local reset control logic processing flow for a target processor system provided in an embodiment of this application; Figure 6 This is a schematic diagram of a processor system configuration recovery and initialization process provided in an embodiment of this application. Detailed Implementation

[0025] The following description and accompanying drawings fully illustrate specific embodiments of this application to enable those skilled in the art to practice them.

[0026] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0027] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0028] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0029] To address the problems existing in the prior art, in this embodiment, on the one hand, a configuration register monitoring module independent of the first and second processor systems is set up, and its reset input is coupled only to the chip's global reset signal and not to any local reset signal, thus achieving circuit-level isolation of the reset domain. In this case, when the first or second watchdog timer times out, the local reset signal generated by the reset control logic unit only acts on the corresponding target processor system, while the other processor system continues to operate normally. Therefore, this application can limit the impact of an anomaly of one core to the subsystem where that core resides, avoiding the expansion of the service interruption scope and significantly shortening the overall system recovery time. Simultaneously, this application does not require additional external components; independent inter-core reset can be achieved internally through reset signal routing isolation, reducing system complexity, cost, and PCB area, and improving chip integration and reliability.

[0030] On the other hand, during the independent operation of the first and second processor systems, the configuration register monitoring module tracks and latches the configuration register information of each processor system in real time under an independent clock domain. When the watchdog timer times out and issues a timeout signal, the configuration register monitoring module responds to the timeout signal by latching the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain. After the partial reset signal is released, the reset processor core reads the latched configuration information from the configuration latch unit and directly restores itself, skipping the complete default initialization process. This application retains the runtime configuration before reset through a hardware latching mechanism, meeting the rapid self-healing requirements of high-availability servers.

[0031] On the other hand, through the hardware latching mechanism of the configuration register monitoring module, when the watchdog timer timeout signal is triggered, the latching control logic directly freezes and latches the current configuration register information to the configuration latch unit at the hardware level. The entire process does not require the processor core to participate in executing any software instructions and does not depend on whether the processor core can run reliably in abnormal states. Compared with the software-based NVM writing scheme, this application avoids the problems of not being able to perform write operations in abnormal CPU states and the slow NVM write speed preventing the saving from being completed before the reset signal takes effect. Compared with the Write-Once MMR scheme, the configuration latch unit of this application includes a first latch register group and a second latch register group, which are used to latch the configuration information of the first processor system and the second processor system, respectively. It can dynamically track and latch the constantly changing states of a large number of configuration registers during system operation, rather than being limited to a very small number of factory-set static configuration items. In addition, this application independently records the flag bits of each watchdog timer timeout and global reset through the reset reason register, making the reset source traceable and providing a reliable hardware-level basis for system fault diagnosis. The following uses exemplary embodiments for detailed description.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram of the independent reset and configuration recovery device for a BMC dual-core heterogeneous system provided in this application embodiment. The device includes: a first processor system, a second processor system, and a configuration register monitoring module; the configuration register monitoring module is communicatively connected to the first processor system and the second processor system respectively; wherein, the first processor system includes a first processor core and a first watchdog timer mounted thereon; the second processor system includes a second processor core and a second watchdog timer mounted thereon; the configuration register monitoring module includes a configuration latch unit and a reset reason register, and the configuration register monitoring module operates in a clock domain independent of the clock trees of the first and second processor systems, and the clock source of this clock domain is not affected by the clock gating and reset of the first and second processor systems; wherein, the reset input terminal of the configuration register monitoring module is only coupled to the chip global reset signal and not coupled to any local reset signal.

[0033] The first processor system is a security subsystem running a real-time operating system (such as AUTOSAR) within the BMC chip. Its first processor core is an E906 security processor core, used to perform high-security management tasks such as temperature threshold monitoring, hardware watchdog verification, and secure boot verification. The first processor system connects to the first peripheral group via the AHB bus, forming an independent first reset domain. The second processor system is an application subsystem running a general-purpose operating system (such as Linux) within the BMC chip. Its second processor core is a C908 application processor core, used to execute upper-level management functions such as the Web management interface, IPMI protocol stack, and remote virtual media. The second processor system connects to the second peripheral group via the AXI bus, forming an independent second reset domain.

[0034] The Configuration Register Monitor (CRM) is a hardware logic module independent of the first and second processor systems. Internally, it includes a configuration latch unit, latch control logic, a reset reason register, an independent clock management unit, and a bus interface unit. The configuration latch unit further includes a first latch register group and a second latch register group, used to latch key configuration register information of the first and second processor systems during operation. This key configuration register information includes, but is not limited to, clock division coefficients, bus arbitration parameters, peripheral enable bits, and interrupt routing configurations. The reset reason register is a set of readable and writable status registers containing three flag bits: the first flag bit indicates that the first watchdog timer timed out and triggered a reset; the second flag bit indicates that the second watchdog timer timed out and triggered a reset; and the third flag bit indicates that the chip global reset signal was valid and triggered a reset.

[0035] The configuration register monitoring module operates in an independent clock domain, separate from the clock trees of the first and second processor systems. The clock source for this independent clock domain comes from an independent RC oscillator inside the chip. The clock signal CLK_indep generated by this RC oscillator is not affected by the clock gating signals and reset signals of the first and second processor systems. This ensures that even if the first or second processor system experiences an abnormal hang, causing its system clock to stop oscillating or be gated off, the configuration register monitoring module can still work normally in the independent clock domain, completing the latching of configuration information and recording of the reset reasons.

[0036] The reset input of the configuration register monitoring module is coupled only to the global reset signal i_rst_n input from the chip's PAD port, and not to either the local reset signal rst_cpu0_sys of the first processor system or the local reset signal rst_cpu1_sys of the second processor system. This means that when the first processor system triggers a local reset due to the first watchdog timer timeout, the local reset signal rst_cpu0_sys only affects the processor core, AHB bus, first watchdog timer, and all peripherals within the first processor system, and will not enter the reset network of the configuration register monitoring module; similarly, when the second processor system triggers a local reset due to the second watchdog timer timeout, the local reset signal rst_cpu1_sys will not affect the configuration register monitoring module. The configuration register monitoring module is only reset when the global reset signal i_rst_n input from the chip's PAD port is valid, its internal configuration latch unit is cleared, and the reset reason register is also cleared or set to the global reset flag.

[0037] In some embodiments of this application, a first processor core is connected to a first peripheral group via a first bus and has an independent first reset domain; a second processor core is connected to a second peripheral group via a second bus and has an independent second reset domain.

[0038] The first bus is AHB (Advanced High-performance Bus), a bus protocol for interconnecting high-performance system modules. It supports high-bandwidth data transmission and is suitable for connecting high-speed peripherals and memory controllers. In this embodiment, the first processor core is an E906 security processor core, connected to the first peripheral group via the AHB bus. The first peripheral group includes various peripheral modules integrated within the first processor system, such as an SPI flash controller, I²C controller, UART serial port controller, GPIO controller, and temperature sensor interface. These peripherals support the security core in performing real-time management tasks such as hardware status monitoring, logging, and secure boot verification. The first reset domain refers to the physical logic area controlled by the local reset signal rst_cpu0_sys of the first processor system. This area includes the E906 processor core, the AHB bus controller, the first watchdog timer WDT0, and all peripheral modules in the first peripheral group. When the first watchdog timer WDT0 times out and triggers a local reset, the rst_cpu0_sys signal is valid, resetting only all modules within the first reset domain to their default state without affecting any modules in the second processor system.

[0039] The second bus is AXI (Advanced eXtensible Interface), a bus protocol designed for high-performance, high-frequency systems. It supports independent address and data channels, out-of-order transmission, and multiple concurrent transactions, making it suitable for connecting compute-intensive peripherals and high-bandwidth devices. In this embodiment, the second processor core is a C908 application processor core, connected to the second peripheral group via the AXI bus. The second peripheral group includes various peripheral modules integrated within the second processor system, such as a DDR memory controller, an Ethernet MAC controller, a USB controller, a PCIe controller, and a display controller. These peripherals support the application core in executing functions such as the Web management interface, IPMI protocol stack, remote virtual media, and KVM. The second reset domain refers to the physical logic area controlled by the local reset signal rst_cpu1_sys of the second processor system. This area includes the C908 processor core, the AXI bus controller, the second watchdog timer WDT1, and all peripheral modules in the second peripheral group. When the second watchdog timer WDT1 times out and triggers a partial reset, the rst_cpu1_sys signal is active, resetting all modules within the second reset domain to their default state without affecting any modules of the first processor system.

[0040] It should be noted that by independently dividing the first and second reset domains as described above, and combining the reset domain isolation design where the configuration register monitoring module is only reset by the global reset signal and is not affected by any local reset signal, this application achieves independent inter-core reset between the first processor system and the second processor system. When a watchdog timeout fault occurs in any subsystem, only the reset domain of that subsystem is reset, while the other subsystem continues to operate normally. This strictly limits the scope of the fault to within the faulty subsystem, avoiding the problem of expanding the scope of service interruption caused by traditional full-chip reset.

[0041] In some embodiments of this application, the configuration register monitoring module includes a configuration latch unit, latch control logic, and a reset reason register; wherein, the configuration latch unit includes a first latch register group and a second latch register group, which are used to latch the configuration information of the first processor system and the second processor system, respectively; the latch control logic is used to control the configuration latch unit to freeze and save the current configuration information when a first timeout signal output by a first watchdog timer or a second timeout signal output by a second watchdog timer is received; the reset reason register is used to record the reset source, and the reset reason register includes a first flag bit for identifying the timeout of the first watchdog timer, a second flag bit for identifying the timeout of the second watchdog timer, and a third flag bit for identifying the global reset signal.

[0042] Specifically, the configuration register monitoring module also includes: an independent clock management unit, used to receive the independent oscillator clock signal and provide the working clock for the configuration latch unit, latch control logic and reset reason register; the independent oscillator clock signal is not affected by the clock gating and reset of the first processor system and the second processor system; and a bus interface unit, including bus interfaces that are respectively connected to the first processor system and the second processor system, used for the first processor core and the second processor core to read the data in the reset reason register and the configuration latch unit.

[0043] For example Figure 1 As shown, the first processor system (cpu0_sys) includes a first processor core (such as an E906 security core), is connected to a first peripheral group via a first bus (such as an AHB bus), and runs a first operating system (such as an AUTOSAR real-time operating system). This first processor system has an independent first reset domain.

[0044] For example Figure 1 As shown, the second processor system (cpu1_sys) contains a second processor core (such as a C908 application core), connects to a second peripheral group via a second bus (such as an AXI bus), and runs a second operating system (such as a Linux operating system). This second processor system has an independent second reset domain.

[0045] For example Figure 1 As shown, the first watchdog timer (WDT0) is mounted under the first processor system (cpu0_sys) and is used to monitor the running status of the first processor core. When the WDT0 count expires, only the first processor system (cpu0_sys) is reset, and it does not affect the second processor system (cpu1_sys). When the E906 core is running normally, the software periodically performs a watchdog feed (reset) operation on WDT0; if the E906 core is hung and cannot feed the watchdog, after the WDT0 count expires, a partial reset signal rst_cpu0_sys is sent to cpu0_sys.

[0046] For example Figure 1 As shown, the second watchdog timer (WDT1) is mounted under the second processor system (cpu1_sys) and is used to monitor the running status of the second processor core. When the WDT1 count expires, only the second processor system (cpu1_sys) is reset, and it does not affect the first processor system (cpu0_sys). When the C908 core is running normally, the software periodically performs a watchdog feed operation on WDT1; if the C908 core is hung and cannot feed the watchdog, after the WDT1 count expires, a partial reset signal rst_cpu1_sys is sent to cpu1_sys.

[0047] For example Figure 1 As shown, the Configuration Register Monitor (CRM) module is independent of the first and second processor systems and has its own independent third clock domain. This module continuously monitors and latches the current values ​​of critical configuration registers in both the first and second processor systems at the hardware level. The CRM module is only reset by the global reset signal (i_rst_n) from the chip's PAD port and is unaffected by any reset signals in the first and second reset domains.

[0048] The configuration register monitoring module includes the following sub-units: 1. Independent clock management unit: Input: Independent RC oscillator clock CLK_indep; Function: Provides the operating clock for all registers and logic within the configuration register monitoring module; Feature: CLK_indep is unaffected by clock gating and reset of cpu0_sys and cpu1_sys.

[0049] 2. Configure the latch unit: cpu0_sys configuration latch register group: latches the clock configuration, AHB bus configuration, peripheral enable configuration, interrupt configuration, etc. of cpu0_sys; cpu1_sys configuration latch register group: latches the clock configuration, AXI bus configuration, peripheral enable configuration, interrupt configuration, etc. of cpu1_sys; Latch control logic: Controls latch operations according to latch mode.

[0050] 3. Reset Reason Register: bit[0]: WDT0 timeout reset flag, set to 1 when WDT0 triggers cpu0_sys reset; bit[1]: WDT1 timeout reset flag, set to 1 when WDT1 triggers cpu1_sys reset; bit[2]: Global reset i_rst_n flag, set to 1 when i_rst_n is valid; This register is only cleared by i_rst_n reset; the local reset signal does not affect this register.

[0051] 4. Bus interface unit: AHB Slave Interface: Receives read and write requests from the E906 core via the AHB bus; AXI Slave Interface: Receives read and write requests from the C908 core via the AXI bus; Interface arbitration logic: Arbitration is performed when two cores access the interface simultaneously.

[0052] In some embodiments of this application, the configuration register monitoring module is further configured to track the configuration register information of the first processor system and the second processor system in real time under an independent clock domain during the independent normal operation of the first processor system and the second processor system, and update it to the configuration latch unit after cross-clock domain synchronization; the configuration register monitoring module is further configured to re-track and latch the configuration register information of each processor system in real time under an independent clock domain after the global reset signal is released and the first processor system and the second processor system have completed initialization.

[0053] In some embodiments of this application, a watchdog timer is used to monitor the running status of the corresponding processor core. When the count times out, it outputs a timeout signal to the reset control logic unit and configuration register monitoring module of the target processor system in which it resides. The configuration register monitoring module is used to latch the current configuration register information of the target processor system to the configuration latch unit in its own independent clock domain in response to the timeout signal, and record the corresponding reset reason in the reset reason register. The reset control logic unit is used to generate a partial reset signal in response to the timeout signal, which only acts on the target processor system to perform a partial reset, while the other processor system continues to run. After the partial reset signal is released, the reset processor core reads the reset reason register to determine the reset type. If it is a partial reset, it reads the latched configuration from the configuration latch unit and restores it directly. If it is a global reset, it executes the complete default initialization process. The chip global reset signal comes from the chip PAD port. When it is valid, it simultaneously resets the first processor system, the second processor system, and the configuration register monitoring module, and clears the configuration latch unit and the reset reason register.

[0054] Specifically, the process of latching the current configuration register information of the target processor system to the configuration latch unit and recording the corresponding reset reason in the reset reason register under its own independent clock domain includes: after detecting a timeout signal, freezing and latching the current configuration register information of the target processor system to the corresponding latch register group in the configuration latch unit within 1 to 2 clock cycles of the independent clock domain; and setting the flag bit corresponding to the target processor system in the reset reason register at the same time.

[0055] Specifically, the process of performing a partial reset includes: applying a partial reset signal to the processor core, watchdog timer, bus controller, and peripherals within the target processor system to reset them to their default states; wherein, the partial reset signal does not apply to another processor system and does not apply to the configuration register monitoring module.

[0056] Specifically, the process of reading the latched configuration from the configuration latch unit and directly restoring it includes: reading the configuration register information latched by the target processor system before reset from the configuration latch unit through the bus interface; the configuration register information includes clock configuration parameters, bus configuration parameters, peripheral enable configuration, and interrupt configuration; the reset processor core directly restores the hardware configuration of the corresponding subsystem according to the read configuration register information, skipping the complete default initialization process; the operating system resumes operation and restarts the watchdog timer feeding mechanism.

[0057] In one possible implementation, for example Figure 1 As shown, taking the hang of cpu0_sys (E906 core) triggering WDT0 timeout reset as an example, the detailed process is as follows: During normal operation, the E906 core runs the AutoSAR real-time operating system and periodically executes service tasks. Within each service cycle, the E906 core performs a dog-feeding operation (write-clear register) on WDT0 via the AHB bus. The configuration register monitoring module continuously tracks and latches the configuration information of cpu0_sys in real-time latch mode under the CLK_indep clock domain. The C908 core runs the Linux operating system and operates independently, unaffected by cpu0_sys.

[0058] During the fault detection and latching phase: The E906 kernel is unable to perform the watchdog feeding operation due to software anomalies (such as infinite loops, kernel panics, etc.); the WDT0 counter continues to increment, reaching the timeout threshold; WDT0 outputs the timeout signal wdt0_timeout, which is simultaneously sent to: The reset control logic of cpu0_sys: triggers the rst_cpu0_sys partial reset signal; Configure the latch control logic of the register monitoring module: trigger the configuration latch operation; Under the CLK_indep clock domain, the configuration register monitoring module latches the current configuration information of cpu0_sys into the configuration latch unit within 1 to 2 CLK_indep cycles after detecting the wdt0_timeout signal; at the same time, bit[0] of the reset reason register is set to 1, recording the reset reason as WDT0 timeout reset; It should be noted that since the configuration register monitoring module operates in the independent clock domain CLK_indep and its reset signal is only i_rst_n, the rst_cpu0_sys local reset signal will not reset the module, and the latched configuration information is safely saved.

[0059] During the partial reset execution phase: When the rst_cpu0_sys signal is valid, all modules within cpu0_sys (E906 core, AHB bus controller, WDT0, peripherals, etc.) are reset. cpu1_sys (C908 core) is unaffected by rst_cpu0_sys and continues to operate normally. The configuration register monitoring module is unaffected by rst_cpu0_sys, and the latched configuration information and reset reason register contents remain unchanged.

[0060] During the reset, release, and configuration recovery phase: The rst_cpu0_sys signal is released (the reset duration is managed by the local reset control logic); The E906 core begins the power-on initialization process; Step A: The E906 core reads the reset reason register RST_REASON_REG in the configuration register monitoring module through the AHB bus, reads bit[0]=1, and determines that the reset type is WDT0 timeout partial reset; Step B: The E906 core reads the configuration information of cpu0_sys in the configuration latch unit through the AHB bus, including clock configuration parameters, AHB bus configuration parameters, peripheral enable configuration, interrupt configuration, etc. Step C: Based on the read configuration information, the E906 core directly restores the clock configuration, bus configuration, peripheral enable and interrupt configuration, skipping the default full initialization process; Step D: The E906 core resumes operation of the AutoSAR real-time operating system and continues to execute business tasks; Step E: The E906 core restarts the WDT0 dog-feeding mechanism to restore monitoring of cpu0_sys.

[0061] During the reset reason clearing phase: After the E906 core completes the configuration recovery, it clears bit[0] of the reset reason register through the AHB bus write operation to prepare for the next reset reason recording.

[0062] In some embodiments of this application, the specific process of executing the complete default initialization process includes: after the global reset signal is released, the first processor core reconfigures the clock, bus, peripheral enable and interrupt parameters according to the hardware default values, and reloads the operating system; the second processor core reconfigures the clock, bus, peripheral enable and interrupt parameters according to the hardware default values, and reloads the operating system; wherein neither the first processor core nor the second processor core reads the configuration from the configuration latch unit.

[0063] In one possible implementation, when the global reset signal i_rst_n of the chip's PAD port is valid: the i_rst_n signal simultaneously acts on cpu0_sys, cpu1_sys, and the configuration register monitoring module; All modules in cpu0_sys were reset, and the E906 core, AHB bus, WDT0 and all peripherals were restored to their default states. All modules within cpu1_sys were reset, and the C908 core, AXI bus, WDT1, and all peripherals were restored to their default states. The configuration register monitoring module is reset, the configuration latch unit is cleared, and the reset reason register is cleared (or set to the global reset flag). After i_rst_n is released, the E906 core and the C908 core respectively execute the complete default initialization process (without reading the configuration from the configuration latch unit, because the latch content has been cleared). After the two subsystems complete initialization, the configuration register monitoring module begins to work normally and re-latches the configuration information of each subsystem.

[0064] In some embodiments of this application, the timing of the real-time latching mode is as follows: During normal operation of cpu0_sys, the configuration latch unit tracks and updates the configuration register value of cpu0_sys at each rising edge of the CLK_indep clock. Since CLK_indep is asynchronous with the system clock of cpu0_sys, an asynchronous FIFO is used for cross-clock domain data synchronization. When the wdt0_timeout signal is valid, the latch control logic immediately freezes the update of the configuration latch unit and latches the current value; The freeze operation ensures that the configuration information of the last stable state before the reset is latched.

[0065] In some embodiments of this application, to ensure that the configuration register monitoring module is not mistakenly reset during a partial reset, the following reset domain isolation design is adopted: 1. Reset signal hierarchy: Level 1 reset (global reset): i_rst_n, originating from the PAD port, applies to all modules across the entire chip, including the configuration register monitoring module; Second-level reset (partial reset): rst_cpu0_sys (triggered by WDT0), rst_cpu1_sys (triggered by WDT1), which only apply to cpu0_sys and cpu1_sys respectively, and do not apply to the configuration register monitoring module.

[0066] 2. Reset signal routing isolation: The routing range of the rst_cpu0_sys signal is strictly limited to the reset domain of cpu0_sys and does not enter the reset network of the configuration register monitoring module. The routing range of the rst_cpu1_sys signal is strictly limited to the reset domain of cpu1_sys and does not enter the reset network of the configuration register monitoring module. The reset network of the configuration register monitoring module is only connected to i_rst_n.

[0067] 3. Cross-clock domain security design: The configuration information of cpu0_sys and cpu1_sys is synchronized to the CLK_indep clock domain via an asynchronous FIFO or a dual FF synchronizer and then latched. The wdt0_timeout and wdt1_timeout signals are synchronized to the CLK_indep clock domain via a synchronizer and then used by the latch control logic. When the E906 and C908 cores read the configuration latch unit, they perform asynchronous reading through their respective AHB / AXI bus interfaces, and the bus protocol ensures the correctness of data transmission.

[0068] In this embodiment, on the one hand, by setting up a configuration register monitoring module independent of the first and second processor systems, and coupling its reset input terminal only to the chip's global reset signal and not to any local reset signal, circuit-level isolation of the reset domain is achieved. In this case, when the first or second watchdog timer times out, the local reset signal generated by the reset control logic unit only acts on the corresponding target processor system, while the other processor system continues to operate normally. Therefore, this application can limit the impact of an anomaly of one core to the subsystem where that core resides, avoiding the expansion of the service interruption scope and significantly shortening the overall system recovery time. Simultaneously, this application does not require additional external components; independent inter-core reset can be achieved internally through reset signal routing isolation, reducing system complexity, cost, and PCB area, and improving chip integration and reliability.

[0069] On the other hand, during the independent operation of the first and second processor systems, the configuration register monitoring module tracks and latches the configuration register information of each processor system in real time under an independent clock domain. When the watchdog timer times out and issues a timeout signal, the configuration register monitoring module responds to the timeout signal by latching the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain. After the partial reset signal is released, the reset processor core reads the latched configuration information from the configuration latch unit and directly restores itself, skipping the complete default initialization process. This application retains the runtime configuration before reset through a hardware latching mechanism, meeting the rapid self-healing requirements of high-availability servers.

[0070] On the other hand, through the hardware latching mechanism of the configuration register monitoring module, when the watchdog timer timeout signal is triggered, the latching control logic directly freezes and latches the current configuration register information to the configuration latch unit at the hardware level. The entire process does not require the processor core to participate in executing any software instructions and is independent of whether the processor core can run reliably in abnormal states. Compared with the software-based NVM writing scheme, this application avoids the problems of not being able to perform write operations in abnormal CPU states and the slow NVM write speed preventing the saving from being completed before the reset signal takes effect. Compared with the Write-Once MMR scheme, the configuration latch unit of this application includes a first latch register group and a second latch register group, which are used to latch the configuration information of the first processor system and the second processor system, respectively. It can dynamically track and latch the constantly changing states of a large number of configuration registers during system operation, rather than being limited to a very small number of factory-set static configuration items. In addition, this application independently records the flag bits of each watchdog timer timeout and global reset through the reset reason register, making the reset source traceable and providing a reliable hardware-level basis for system fault diagnosis.

[0071] Please see Figure 2 This is a flowchart illustrating an independent reset and configuration recovery method for a BMC dual-core heterogeneous system, as provided in this application embodiment. Figure 2 As shown, the detection method in this application embodiment may include the following steps: S101, the watchdog timer monitors the running status of the corresponding processor core. When the count expires, it outputs a timeout signal to the reset control logic unit and configuration register monitoring module of the target processor system where it is located. For example Figure 3 As shown, Figure 3 This is a schematic diagram of the watchdog timeout monitoring and signal output logic of a BMC dual-core heterogeneous system provided in this application. First, the first processor system includes a first processor core and a first watchdog timer mounted thereon, and the second processor system includes a second processor core and a second watchdog timer mounted thereon. When either the first or second watchdog timer fails to complete its feeding operation within its respective monitoring period and its count reaches a preset timeout threshold, a timeout judgment condition is triggered. Subsequently, the corresponding watchdog timer outputs a timeout signal, which is transmitted to the reset control logic unit and configuration register monitoring module of the target processor system it resides in.

[0072] S102, in response to the timeout signal, the configuration register monitoring module latches the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain, and records the corresponding reset reason in the reset reason register; In some embodiments of this application, the specific process of latching the current configuration register information of the target processor system to the configuration latch unit under its own independent clock domain and recording the corresponding reset reason in the reset reason register includes: after detecting a timeout signal, freezing and latching the current configuration register information of the target processor system to the corresponding latch register group in the configuration latch unit within 1 to 2 clock cycles of the independent clock domain; and setting the flag bit in the reset reason register corresponding to the target processor system.

[0073] For example Figure 4 As shown, Figure 4 This is a schematic diagram of the hardware processing flow of a configuration register monitoring module provided in this application after receiving a watchdog timeout signal. First, when the watchdog timer count in the first or second processor system reaches a preset threshold and a timeout occurs, the watchdog timer immediately outputs a timeout signal. Then, the configuration register monitoring module receives the timeout signal and switches to its processing logic operating in an independent clock domain, responding quickly within 1 to 2 independent clock cycles (CLK_indep). Next, the latch control logic freezes the current configuration register information of the target processor system (i.e., the processor system corresponding to the timeout signal) in the independent clock domain to prevent changes before reset. Then, the frozen configuration information is latched into the corresponding register group (first latch register group or second latch register group) in the configuration latch unit. Simultaneously, the flag bit (first flag bit or second flag bit) corresponding to the watchdog timeout event in the reset reason register is automatically set by the hardware to record the reset reason. Finally, the reset reason recording operation is completed, providing reliable hardware data support for the processor core to quickly read the configuration and determine the reset type after a subsequent partial reset release.

[0074] S103, the reset control logic unit responds to the timeout signal and generates a partial reset signal that acts only on the target processor system to perform a partial reset, while the other processor system continues to run; after the partial reset signal is released, the reset processor core reads the reset reason register to determine the reset type; if it is a partial reset, it reads the latch configuration from the configuration latch unit and restores it directly; if it is a global reset, it executes the complete default initialization process.

[0075] In some embodiments of this application, the specific process of performing a partial reset includes: applying a partial reset signal to the processor core, watchdog timer, bus controller and peripherals in the target processor system to reset them to their default state; wherein, the partial reset signal does not apply to another processor system and does not apply to the configuration register monitoring module.

[0076] In some embodiments of this application, the specific process of reading the latched configuration from the configuration latch unit and directly restoring it includes: reading the configuration register information latched by the target processor system before reset from the configuration latch unit through the bus interface; the configuration register information includes clock configuration parameters, bus configuration parameters, peripheral enable configuration and interrupt configuration; the reset processor core directly restores the hardware configuration of the corresponding subsystem according to the read configuration register information, skipping the complete default initialization process; the operating system is restored and the watchdog timer feeding mechanism is restarted.

[0077] In some embodiments of this application, the specific process of executing the complete default initialization process includes: after the global reset signal is released, the first processor core reconfigures the clock, bus, peripheral enable and interrupt parameters according to the hardware default values, and reloads the operating system; the second processor core reconfigures the clock, bus, peripheral enable and interrupt parameters according to the hardware default values, and reloads the operating system; wherein neither the first processor core nor the second processor core reads the configuration from the configuration latch unit.

[0078] For example Figure 5 As shown, Figure 5 This is a schematic diagram of a partial reset control logic processing flow for a target processor system provided in this application. First, the reset control logic within the target processor system (i.e., the processor system experiencing a watchdog timeout) (e.g., the rst_cpu0_sys generation logic in the first processor system or the rst_cpu1_sys generation logic in the second processor system) initiates a reset request and generates a corresponding partial reset signal. Subsequently, this partial reset signal is strictly limited to its scope, only accessing and resetting its corresponding target processor system (including the target processor core, the mounted watchdog timer, and the corresponding peripheral group), without being transmitted to the chip's global reset network or other processor systems. Simultaneously, another processor system (i.e., a redundant processor system that has not experienced a fault), due to its independent reset domain design, is completely unaffected by this partial reset signal and continues to maintain normal operation, ensuring uninterrupted overall chip service. Finally, after the target processor system completes internal reset operations such as clearing register states and restoring configuration information, the partial reset signal is released (i.e., pulled high or deactivated), and the target processor system exits the reset state and restarts operation, thereby achieving closed-loop control of fault isolation and system self-healing.

[0079] Figure 6 As shown, Figure 6This is a schematic diagram of a processor system configuration recovery and initialization process after a reset, as provided in this application. First, after a partial or global reset, the processor core reads the reset cause register to obtain the trigger type of the reset. Then, the system enters the reset type determination node, dividing the process into two branches—partial reset and global reset—based on the flag status in the register. If it is determined to be a partial reset (triggered by a watchdog timer timeout), the system reads the configuration information latched before the reset from the configuration latch unit, directly restores the hardware configuration (such as clock, bus, peripheral enable, etc.), skips the complete default initialization process, directly resumes the operating system, and finally restarts the watchdog mechanism to achieve a closed-loop fault monitoring. If it is determined to be a global reset (triggered by external PAD input or power-on), the system executes the complete default initialization process, reconfigures the system parameters according to the hardware default values, and then reloads the operating system, ensuring that the system is in a known default reliable state after a global reboot. Through this differentiated recovery strategy, this application ensures fault isolation and rapid recovery while also considering the integrity and security of the global reset.

[0080] In some embodiments of this application, the configuration register monitoring module is further configured to track the configuration register information of the first processor system and the second processor system in real time under an independent clock domain during the independent normal operation of the first processor system and the second processor system, and update it to the configuration latch unit after cross-clock domain synchronization; the configuration register monitoring module is further configured to re-track and latch the configuration register information of each processor system in real time under an independent clock domain after the global reset signal is released and the first processor system and the second processor system have completed initialization.

[0081] In this embodiment, on the one hand, by setting up a configuration register monitoring module independent of the first and second processor systems, and coupling its reset input terminal only to the chip's global reset signal and not to any local reset signal, circuit-level isolation of the reset domain is achieved. In this case, when the first or second watchdog timer times out, the local reset signal generated by the reset control logic unit only acts on the corresponding target processor system, while the other processor system continues to operate normally. Therefore, this application can limit the impact of an anomaly of one core to the subsystem where that core resides, avoiding the expansion of the service interruption scope and significantly shortening the overall system recovery time. Simultaneously, this application does not require additional external components; independent inter-core reset can be achieved internally through reset signal routing isolation, reducing system complexity, cost, and PCB area, and improving chip integration and reliability.

[0082] On the other hand, during the independent operation of the first and second processor systems, the configuration register monitoring module tracks and latches the configuration register information of each processor system in real time under an independent clock domain. When the watchdog timer times out and issues a timeout signal, the configuration register monitoring module responds to the timeout signal by latching the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain. After the partial reset signal is released, the reset processor core reads the latched configuration information from the configuration latch unit and directly restores itself, skipping the complete default initialization process. This application retains the runtime configuration before reset through a hardware latching mechanism, meeting the rapid self-healing requirements of high-availability servers.

[0083] On the other hand, through the hardware latching mechanism of the configuration register monitoring module, when the watchdog timer timeout signal is triggered, the latching control logic directly freezes and latches the current configuration register information to the configuration latch unit at the hardware level. The entire process does not require the processor core to participate in executing any software instructions and is independent of whether the processor core can run reliably in abnormal states. Compared with the software-based NVM writing scheme, this application avoids the problems of not being able to perform write operations in abnormal CPU states and the slow NVM write speed preventing the saving from being completed before the reset signal takes effect. Compared with the Write-Once MMR scheme, the configuration latch unit of this application includes a first latch register group and a second latch register group, which are used to latch the configuration information of the first processor system and the second processor system, respectively. It can dynamically track and latch the constantly changing states of a large number of configuration registers during system operation, rather than being limited to a very small number of factory-set static configuration items. In addition, this application independently records the flag bits of each watchdog timer timeout and global reset through the reset reason register, making the reset source traceable and providing a reliable hardware-level basis for system fault diagnosis.

[0084] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The independent reset and configuration recovery program for the BMC dual-core heterogeneous system can be stored in a computer-readable storage medium. When executed, this program can include the processes of the embodiments of the above methods. The storage medium for the independent reset and configuration recovery of the BMC dual-core heterogeneous system can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0085] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. An independent reset and configuration recovery device for a BMC dual-core heterogeneous system, characterized in that, The device includes: The system comprises a first processor system, a second processor system, and a configuration register monitoring module; the configuration register monitoring module is communicatively connected to both the first processor system and the second processor system; wherein... The first processor system includes a first processor core and a first watchdog timer mounted thereon; the second processor system includes a second processor core and a second watchdog timer mounted thereon. The configuration register monitoring module includes a configuration latch unit and a reset reason register. The configuration register monitoring module operates in a clock domain independent of the clock trees of the first and second processor systems. The clock source of this clock domain is not affected by the clock gating and reset of the first and second processor systems. The reset input of the configuration register monitoring module is coupled only to the chip global reset signal and not to any local reset signal.

2. The apparatus according to claim 1, characterized in that, The watchdog timer is used to monitor the running status of the corresponding processor core. When the count times out, it outputs a timeout signal to the reset control logic unit of the target processor system and the configuration register monitoring module. The configuration register monitoring module is used to respond to the timeout signal by latching the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain, and recording the corresponding reset reason in the reset reason register. The reset control logic unit is used to generate a partial reset signal in response to the timeout signal, which acts only on the target processor system to perform a partial reset while the other processor system continues to run. After the partial reset signal is released, the reset processor core reads the reset reason register to determine the reset type. If it is a partial reset, it reads the latch configuration from the configuration latch unit and restores it directly. If it is a global reset, it executes the complete default initialization process. The chip global reset signal comes from the chip PAD port. When it is valid, it simultaneously resets the first processor system, the second processor system, and the configuration register monitoring module, and clears the configuration latch unit and the reset reason register.

3. The apparatus according to claim 1, characterized in that, The configuration register monitoring module is also used to track the configuration register information of the first processor system and the second processor system in real time under an independent clock domain during the independent normal operation of the first processor system and the second processor system, and update it to the configuration latch unit after cross-clock domain synchronization. The configuration register monitoring module is further configured to, after the global reset signal is released and the first and second processor systems have completed initialization, re-track and latch the configuration register information of each processor system in real time under an independent clock domain; wherein, The first processor core is connected to the first peripheral group via the first bus and has an independent first reset domain; The second processor core is connected to the second peripheral group via a second bus and has an independent second reset domain.

4. The apparatus according to claim 1, characterized in that, The configuration register monitoring module includes a configuration latch unit, latch control logic, and a reset reason register; wherein... The configuration latch unit includes a first latch register group and a second latch register group, which are used to latch the configuration information of the first processor system and the second processor system, respectively. The latch control logic is used to control the configuration latch unit to freeze and save the current configuration information when it receives a first timeout signal output by the first watchdog timer or a second timeout signal output by the second watchdog timer. The reset reason register is used to record the reset source. The reset reason register includes a first flag bit for indicating that the first watchdog timer has timed out, a second flag bit for indicating that the second watchdog timer has timed out, and a third flag bit for indicating that the global reset signal has been detected.

5. The apparatus according to claim 4, characterized in that, The configuration register monitoring module also includes: An independent clock management unit is used to receive the independent oscillator clock signal and provide the working clock for the configuration latch unit, latch control logic and reset reason register; the independent oscillator clock signal is not affected by the clock gating and reset of the first processor system and the second processor system; The bus interface unit includes bus interfaces that are respectively connected to the first processor system and the second processor system, and are used to allow the first processor core and the second processor core to read data from the reset reason register and the configuration latch unit.

6. The apparatus according to claim 2, characterized in that, The step of latching the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain, and recording the corresponding reset reason in the reset reason register, includes: Upon detecting the timeout signal, the current configuration register information of the target processor system is frozen and latched into the corresponding latch register group in the configuration latch unit within 1 to 2 clock cycles of independent clock domains. At the same time, the flag bit in the reset reason register corresponding to the target processor system is set.

7. The apparatus according to claim 2, characterized in that, The execution of a partial reset includes: The local reset signal is applied to the processor core, watchdog timer, bus controller, and peripherals within the target processor system, resetting them to their default states; wherein... The local reset signal does not act on another processor system, nor on the configuration register monitoring module.

8. The apparatus according to claim 2, characterized in that, The step of reading the latch configuration from the configuration latch unit and directly restoring it includes: The configuration register information latched by the target processor system before reset is read from the configuration latch unit via the bus interface; the configuration register information includes clock configuration parameters, bus configuration parameters, peripheral enable configuration, and interrupt configuration. The reset processor core directly restores the hardware configuration of the corresponding subsystem based on the read configuration register information, skipping the complete default initialization process; Restore the operating system and restart the watchdog timer feeding mechanism.

9. The apparatus according to claim 2, characterized in that, The execution of the complete default initialization process includes: After the global reset signal is released, the first processor core reconfigures the clock, bus, peripheral enable and interrupt parameters according to the hardware default values, and reloads the operating system; The second processor core reconfigures the clock, bus, peripheral enable, and interrupt parameters according to the hardware default values, and reloads the operating system; Neither the first processor core nor the second processor core reads the configuration from the configuration latch unit.

10. A method for independent reset and configuration recovery of a BMC dual-core heterogeneous system implemented based on the device according to any one of claims 1-9, characterized in that, The method includes: The watchdog timer monitors the operating status of the corresponding processor core. If the count times out, it outputs a timeout signal to the reset control logic unit of the target processor system and the configuration register monitoring module. In response to the timeout signal, the configuration register monitoring module latches the current configuration register information of the target processor system into the configuration latch unit under its own independent clock domain, and records the corresponding reset reason in the reset reason register. In response to the timeout signal, the reset control logic unit generates a partial reset signal that acts only on the target processor system to perform a partial reset, while the other processor system continues to run. After the partial reset signal is released, the reset processor core reads the reset reason register to determine the reset type. If it is a partial reset, the latch configuration is read from the configuration latch unit and restored directly. If it is a global reset, the complete default initialization process is executed.

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