Memory and data reliability determination method

Abstract

The application discloses a memory and a data reliability judgment method. The memory comprises a data buffer, a BCH code processing module and a CRC code processing module. The CRC code processing module is added to output an (n+1)th target cyclic redundancy check code according to the (n+1)th corrected data, so that the (n+1)th target cyclic redundancy check code and the (n+1)th corrected cyclic redundancy check code are used to judge whether the actual corrected error bit number is greater than or equal to the maximum correctable error bit number, thereby solving the problem that the data reliability is difficult to judge.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a memory and a method for judging data reliability. Background Technology

[0002] BCH (Bose-Chaudhuri-Hocquenghem) is an error-correcting coding algorithm that generates corresponding BCH codes based on parameters (n, k, t) to detect and correct errors during data transmission or storage. Here, n represents the length of the encoded codeword, i.e., the total number of bits in each coded block. k represents the number of data bits, i.e., the number of bits of original information contained in each data block. t represents the maximum number of correctable errors, i.e., the maximum number of errors that BCH encoding can detect and correct.

[0003] This error correction coding algorithm can correct errors less than or equal to t, but it cannot guarantee data reliability for errors greater than t. Summary of the Invention

[0004] This application provides a method for determining the reliability of memory and data, thereby alleviating the technical problem of difficulty in determining data reliability.

[0005] In a first aspect, this application provides a memory comprising a data buffer, a BCH code processing module, and a CRC code processing module. The data buffer stores the (n+1)th bit of data and the (n+1)th initial cyclic redundancy check (CRC) code arranged sequentially. The BCH code processing module outputs the (n+1)th corrected data and the (n+1)th corrected CRC code sequentially based on the (n+1)th bit of data and the (n+1)th initial CRC code, respectively. The CRC code processing module outputs the (n+1)th initial CRC code based on the (n+1)th bit of data and the (n+1)th target CRC code based on the (n+1)th corrected data.

[0006] Secondly, this application also provides a data reliability judgment method, which includes: obtaining the (n+1)th target cyclic redundancy check (CRC) code corresponding to the (n+1)th data and the (n+1)th corrected cyclic redundancy check (CRC) code corresponding to the (n+1)th initial CRC code, wherein the (n+1)th initial CRC code is obtained by encoding the (n+1)th data.

[0007] The memory and data reliability judgment method provided in this application can output the (n+1)th target cyclic redundancy check code based on the (n+1)th corrected data by adding a CRC code processing module. By using the (n+1)th target cyclic redundancy check code and the (n+1)th corrected cyclic redundancy check code, it is easier to determine whether the actual number of corrected errors is greater than or equal to the maximum number of correctable errors, thereby alleviating the problem of difficulty in judging data reliability. Attached Figure Description

[0008] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 This is a schematic diagram of the structure of a memory in related technologies.

[0010] Figure 2 This is a schematic diagram of the BCH code processing module in related technologies.

[0011] Figure 3 This is a schematic diagram of a first structure of a memory provided in an embodiment of this application.

[0012] Figure 4 for Figure 3 The timing diagram of the memory is shown.

[0013] Figure 5 This is a schematic diagram of a second structure of the memory provided in an embodiment of this application.

[0014] Figure 6 for Figure 5 The timing diagram of the memory is shown. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0016] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0017] Figure 1 This is a schematic diagram of the structure of a memory in related technologies. The memory includes a storage array 10, a data buffer 20, and a BCH code processing module 30 connected in sequence.

[0018] The data buffer 20 can also interact with external systems via input / output (I / O) interfaces. Data interaction is possible between the storage array 10 and the data buffer 20. Data interaction is also possible between the data buffer 20 and the BCH code processing module 30.

[0019] Among them, the BCH code processing module 30 uses the error correction coding algorithm BCH(n,k,t) to protect the data, which can correct any error less than or equal to t.

[0020] Figure 2 This is a schematic diagram of the structure of the BCH code processing module 30 in the related technology. It includes an encoding unit 31 and a decoding unit 32. The decoding unit 32 includes synodal computation, BM (Berlekamp-Massey) iterative computation, and chien search.

[0021] Figure 3 This is a schematic diagram of a first structure of a memory provided in an embodiment of this application. The memory also includes a CRC (Cyclic Redundancy Check) code processing module 40 and a selection module 50. The CRC code processing module 30 includes an encoding unit 31. The first input terminal of the selection module 50 is connected to the output terminal of the data buffer 20 and the input terminal of the CRC code processing module 40. The second input terminal of the selection module 50 is connected to the output terminal of the CRC code processing module 40 and the input terminal of the data buffer 20. The output terminal of the selection module 50 is connected to the input terminal of the encoding unit 31, and the output terminal of the encoding unit 31 is connected to the input terminal of the data buffer 20.

[0022] In some of these embodiments, such as Figure 3 As shown, the selection module 50 includes a selection switch MUX. The first input terminal of the selection switch MUX is connected to the output terminal of the data buffer 20 and the input terminal of the CRC code processing module 40. The second input terminal of the selection switch MUX is connected to the output terminal of the CRC code processing module 40. The output terminal of the selection switch MUX is connected to the input terminal of the encoding unit 31.

[0023] It should be noted that when the CRC code processing module 40 outputs the (n+1)th initial cyclic redundancy check code based on the (n+1)th bit of data, and when the encoding unit 31 outputs the (n+1)th BCH code based on the (n+1)th bit of data, the first input terminal of the selection switch MUX is connected to the output terminal of the selection switch MUX. n is an integer greater than or equal to 0.

[0024] When the encoding unit 31 outputs the target BCH code based on the (n+1)th initial cyclic redundancy check code, the second input terminal of the selection switch MUX is connected to the output terminal of the selection switch MUX.

[0025] Figure 4 for Figure 3 The timing diagram of the memory is shown. Figure 4 The following is the encoding process, which includes the following steps:

[0026] First step: Read the first bit of data to the (n+1)th bit of data (D0, D1, D2...Dn-1, Dn) sequentially from the data buffer 20 and input them into the encoding unit 31 and the CRC code processing module 40 to calculate the corresponding initial cyclic redundancy check code (CRC0...CRCr) and BCH code (BCH0...BCHm).

[0027] Wherein, BCHEN_IN is the input signal of encoding unit 31, and BCHEN_OUT is the output signal of encoding unit 31. CRC_IN is the input signal of CRC code processing module 40, and CRC_OUT is the output signal of CRC code processing module 40.

[0028] Specifically, during the t0 time period, the encoding unit 31 generates the first BCH code (BCH0) based on the first bit data (D0), and the CRC code processing module 40 generates the first initial cyclic redundancy check code (CRC0) based on the first bit data (D0).

[0029] During time period t1, encoding unit 31 generates second BCH code (BCH1) based on second data (D1), and CRC code processing module 40 generates second initial cyclic redundancy check code (CRC1) based on second data (D1).

[0030] During time period t2, encoding unit 31 generates the third BCH code (BCH2) based on the third data (D2), and CRC code processing module 40 generates the third initial cyclic redundancy check code (CRC2) based on the third data (D2).

[0031] Similarly, during the tn-1 time period, the encoding unit 31 generates the nth BCH code (BCHn-1) based on the nth data (Dn-1), and the CRC code processing module 40 generates the nth initial cyclic redundancy check code (CRCn-1) based on the nth data (Dn-1).

[0032] During the tn time period, the encoding unit 31 generates the (n+1)th BCH code (BCHn) based on the (n+1)th data (Dn), and the CRC code processing module 40 generates the (n+1)th initial cyclic redundancy check code (CRCr) based on the (n+1)th data (Dn).

[0033] The second step: At the beginning of the tn+1 time period, the CRC code processing module 40 stops calculating, and still outputs the (n+1)th initial cyclic redundancy check code (CRCr) during the tn+1 and tn+2 time periods.

[0034] During the tn+1 time period, the (n+1)th initial cyclic redundancy check (CRCr) bit is input into the encoding unit 31 through the selection module 50, and the encoding unit 31 calculates the target BCH code (BCHm) based on the (n+1)th initial cyclic redundancy check (CRCr).

[0035] Third step: At the beginning of the tn+2 time period, the coding unit 31 stops calculating and still outputs the target BCH code (BCHm) during the tn+2 time period.

[0036] During the tn+2 time period, the (n+1)th initial cyclic redundancy check (CRCr) and the target BCH code (BCHm) are written into the data buffer 20.

[0037] In summary, the data buffer 20 is used to store the first to the (n+1)th data bits arranged sequentially (D0, D1, D2...Dn-1, Dn), the (n+1)th initial cyclic redundancy check (CRCr) bit, and the target BCH code (BCHm).

[0038] Figure 5 This is a schematic diagram of a second structure of the memory provided in an embodiment of this application. For example... Figure 5 , Figure 6 As shown, the data buffer 20 is used to store the (n+1)th data (Dn) and the (n+1)th initial cyclic redundancy check (CRCr) arranged sequentially; the BCH code processing module 30 is used to output the (n+1)th corrected data (Dn') and the (n+1)th corrected cyclic redundancy check (CRC') sequentially according to the (n+1)th data (Dn) and the (n+1)th initial cyclic redundancy check (CRCr); the CRC code processing module 40 is used to output the (n+1)th initial cyclic redundancy check (CRCr) according to the (n+1)th data (Dn), and to output the (n+1)th target cyclic redundancy check (CRTm) according to the (n+1)th corrected data (Dn').

[0039] It is understood that the memory provided in this embodiment, by adding a CRC code processing module 40, can output the (n+1)th target cyclic redundancy check code (CRTm) based on the (n+1)th corrected data (Dn'). Thus, by using the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC'), it is helpful to determine whether the actual number of corrected error bits is greater than or equal to the maximum number of correctable error bits, thereby alleviating the problem of difficulty in judging data reliability.

[0040] In some embodiments, the memory further includes a comparison module 60, which is used to determine the relationship between the actual number of corrected errors of the BCH code and the maximum number of correctable errors (t) of the BCH code based on the comparison result between the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC').

[0041] It is understood that the memory provided in this embodiment, by adding a CRC code processing module 40, can determine the relationship between the actual number of corrected errors and the maximum number of correctable errors of the BCH code based on the comparison result between the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC'). This allows it to determine whether the actual number of corrected errors is greater than or equal to the maximum number of correctable errors, thus ensuring data reliability.

[0042] It should be noted that the aforementioned memory can be, but is not limited to, NAND flash memory, or other suitable memory chips such as Resistive Random Access Memory (ReRAM). Specifically, data buffer 20 only stores the (n+1)th initial cyclic redundancy check (CRC) bit; the first to nth CRC bits are not stored in data buffer 20. The number of bits preceding the first data bit and the number of bits preceding the CRC bit do not indicate their storage location or order in data buffer 20.

[0043] In some of these embodiments, such as Figure 5 As shown, the BCH code processing module 30 includes a decoding unit 32. The decoding unit 32 performs the Money search algorithm on the (n+1)th bit data (Dn) to output the (n+1)th corrected bit data (Dn'), and performs the Money search algorithm on the (n+1)th initial cyclic redundancy check code (CRCr) to output the (n+1)th corrected cyclic redundancy check code (CRC').

[0044] In some embodiments, the input of the CRC code processing module 40 is connected to the output of the decoding unit 32. The CRC code processing module 40 encodes the corrected data (Dn') of the (n+1)th bit to output the target cyclic redundancy check code (CRTm) of the (n+1)th bit.

[0045] In some of these embodiments, such as Figure 5 As shown, the comparison module 60 includes a comparison unit 61 and a storage unit 62. The comparison unit 61 is used to output the comparison result of whether the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC') are equal; the storage unit 62 is used to store the comparison result.

[0046] It should be noted that the comparison result can be that the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC') are equal or the same, or the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC') are not equal or different.

[0047] Since the comparison unit 61 can also be used to output other comparison results between other target cyclic redundancy check codes and other corrected cyclic redundancy check codes, and in some embodiments, these other comparison results are not needed, the storage unit 62 needs to selectively store each comparison result. For example, it can select and store the comparison result of whether the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC') are equal.

[0048] In some of these embodiments, such as Figure 5 As shown, the comparison unit 61 includes an XNOR gate XNOR1. The first input of the XNOR gate XNOR1 is connected to the (n+1)th target cyclic redundancy check code (CRTm), the second input of the XNOR gate XNOR1 is connected to the (n+1)th corrected cyclic redundancy check code (CRC'), and the output of the XNOR gate XNOR1 outputs the comparison result.

[0049] It should be noted that in other embodiments, the comparison unit 61 can also be an algorithm or circuit for determining whether two data are equal, such as a NOR gate, an equivalence comparator, an XOR gate, a NAND gate, an AND gate, or an OR gate, and the relationship between the actual number of corrected errors and the maximum number of correctable errors represented by the comparison result can be modified accordingly.

[0050] In some of these embodiments, such as Figure 5 As shown, the storage unit 62 includes a flip-flop JC1. The data input terminal of the flip-flop JC1 is connected to the output terminal of the XNOR gate XNOR1. The clock input terminal of the flip-flop JC1 is connected to a clock signal. The output terminal of the flip-flop JC1 outputs status data (CRC_PASS). When the XNOR gate XNOR1 outputs a comparison result, the clock signal enables the flip-flop JC1 to output the comparison result as status data (CRC_PASS).

[0051] It should be noted that the trigger JC1 can be an RS trigger, D trigger, JK trigger, or T trigger, etc., used to implement selective storage.

[0052] In some of these embodiments, such as Figure 5As shown, if the status data (CRC_PASS) is "1", it indicates that the (n+1)th target cyclic redundancy check (CRTm) bit is the same as the (n+1)th corrected cyclic redundancy check (CRC') bit, which means that the actual number of corrected errors is less than or equal to the maximum number of correctable errors. This shows that the correction of the data from the 3rd bit to the (n+1)th bit (D0, D1, D2...Dn-1, Dn) by the decoding unit 32 is effective, ensuring the reliability of these data.

[0053] In some of these embodiments, such as Figure 5 As shown, if the status data (CRC_PASS) is "0", it indicates that the (n+1)th target cyclic redundancy check code (CRTm) is different from the (n+1)th corrected cyclic redundancy check code (CRC'), which signifies that the actual number of corrected errors is greater than the maximum number of correctable errors. This indicates that the correction of the 3rd to (n+1)th data bits (D0, D1, D2...Dn-1, Dn) by the decoding unit 32 cannot guarantee the correctness of the data, thus clarifying the reliability of these data.

[0054] Figure 6 for Figure 5 The timing diagram of the memory is shown. Figure 6 The decoding process is shown below, and it includes the following steps:

[0055] The first step is to read DATA_OUT (D0, D1, D2...Dn-1, Dn, CRCr and BCHm) sequentially from the data buffer 20 during the ts period and send them to the decoding unit 32 for calculation. In some embodiments, the calculation is performed as a companion calculation, that is, the calculation is performed immediately after the data is sent to the decoding unit 32.

[0056] The second step: Perform BM iterative calculations during the tb time period.

[0057] The third step: During the time period from tc0 to tcn, D0, D1, D2...Dn-1, Dn are read out sequentially from the data buffer 20 and input into the decoding unit 32 for money search algorithm processing. The result of the money search algorithm processing is then input into the CRC code processing module 40 to calculate the corresponding corrected data and target cyclic redundancy check code respectively.

[0058] Specifically, during the tc0 period, D0 is read from the data buffer 20 and input into the decoding unit 32 for processing using the Qian search algorithm to obtain the first corrected data (D0'); then the first corrected data (D0') is input into the CRC code processing module 40 to calculate the first corrected cyclic redundancy check code (CRT0).

[0059] During the tc1 period, D1 is read from the data buffer 20 and input into the decoding unit 32 for processing using the Qian search algorithm to obtain the second corrected data (D1'); then the second corrected data (D1') is input into the CRC code processing module 40 to calculate the second corrected cyclic redundancy check code (CRT1).

[0060] During the tc2 period, D2 is read from the data buffer 20 and input into the decoding unit 32 for Qian search algorithm processing to obtain the third corrected data (D2'); then the third corrected data (D2') is input into the CRC code processing module 40 to calculate the third corrected cyclic redundancy check code (CRT2).

[0061] Similarly, during the tcn-1 time period, Dn-1 is read from the data buffer 20 and input into the decoding unit 32 for processing using the Qian search algorithm to obtain the nth corrected data (Dn-1'); then the nth corrected data (Dn-1') is input into the CRC code processing module 40 to calculate the nth corrected cyclic redundancy check code (CRTn-1).

[0062] During the tcn period, Dn is read from the data buffer 20 and input into the decoding unit 32 for processing using the Qian search algorithm to obtain the (n+1)th corrected data (Dn'); then the (n+1)th corrected data (Dn') is input into the CRC code processing module 40 to calculate the (n+1)th corrected cyclic redundancy check code (CRTm).

[0063] Fourth step: At the beginning of the tcn+1 time period, the CRC code processing module 40 stops calculating, and still outputs the (n+1)th corrected cyclic redundancy check code (CRTm) during the tcn+1 and tcn+2 time periods.

[0064] During the tcn+1 time period, the decoding unit 32 continues to process the initial cyclic redundancy check code (CRCr) of the (n+1)th bit using the Qian search algorithm to calculate the corrected cyclic redundancy check code (CRC') of the (n+1)th bit.

[0065] Fifth step: At the start of the tcn+2 time period, the decoding unit 32 stops calculating and still outputs the (n+1)th corrected cyclic redundancy check (CRC) bit during the tcn+2 time period.

[0066] During the tcn+2 time period, determine whether the (n+1)th corrected cyclic redundancy check (CRTm) bit is equal to the (n+1)th corrected cyclic redundancy check (CRC) bit:

[0067] When the (n+1)th corrected cyclic redundancy check (CRTm) is equal to the (n+1)th corrected cyclic redundancy check (CRC'), CRC_PASS = 1.

[0068] When the (n+1)th corrected cyclic redundancy check (CRTm) is not equal to the (n+1)th corrected cyclic redundancy check (CRC'), CRC_PASS = 0.

[0069] Step 6: When CRC_PASS=1, it means that the data is reliable when the actual number of corrected errors is less than or equal to the maximum number of correctable errors (t).

[0070] When CRC_PASS = 0, it means that the data is unreliable when the actual number of corrected errors is greater than the maximum number of correctable errors (t).

[0071] In some embodiments, this embodiment also provides a data reliability judgment method, which includes: obtaining the (n+1)th target cyclic redundancy check (CRC) code corresponding to the (n+1)th data and the (n+1)th corrected cyclic redundancy check (CRC) code corresponding to the (n+1)th initial CRC code, wherein the (n+1)th initial CRC code is obtained by encoding the (n+1)th data.

[0072] It is understood that the data reliability judgment method provided in this embodiment can also output the (n+1)th target cyclic redundancy check code (CRTm) based on the (n+1)th corrected data (Dn') by adding a CRC code processing module 40. By using the (n+1)th target cyclic redundancy check code (CRTm) and the (n+1)th corrected cyclic redundancy check code (CRC'), it is helpful to determine whether the actual number of corrected error bits is greater than or equal to the maximum number of correctable error bits, thereby alleviating the problem of difficulty in judging data reliability.

[0073] In some embodiments, the relationship between the actual number of corrected errors in the BCH code and the maximum number of correctable errors in the BCH code is determined based on the comparison result between the (n+1)th target cyclic redundancy check (CRC) code and the (n+1)th corrected CRC code.

[0074] It should be noted that, in this embodiment, the actual number of corrected errors in the BCH code and the maximum number of correctable errors in the BCH code are determined based on the comparison result between the (n+1)th target cyclic redundancy check (CRC) code and the (n+1)th corrected CRC code. This allows the determination of whether the actual number of corrected errors is greater than or equal to t, thus ensuring data reliability.

[0075] It should be noted that if the comparison result indicates that the (n+1)th target cyclic redundancy check code is the same as the (n+1)th corrected cyclic redundancy check code, it means that the actual number of corrected errors is less than or equal to the maximum number of correctable errors.

[0076] If the comparison result indicates that the (n+1)th target cyclic redundancy check code is different from the (n+1)th corrected cyclic redundancy check code, it means that the actual number of corrected errors is greater than the maximum number of correctable errors.

[0077] It should be noted that this data reliability assessment method can be applied to, but is not limited to, the storage field, and can also be applied to other data fields, such as the communication field.

[0078] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0079] The memory and data reliability judgment method provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory, characterized in that, The memory includes: A data buffer is used to store the (n+1)th data bit and the (n+1)th initial cyclic redundancy check code arranged sequentially, where n is an integer greater than or equal to 0; The BCH code processing module is used to output the corrected data and the corrected cyclic redundancy check code in sequence according to the (n+1)th bit data and the (n+1)th bit initial cyclic redundancy check code. A CRC code processing module is used to output the (n+1)th initial cyclic redundancy check code based on the (n+1)th bit data, and to output the (n+1)th target cyclic redundancy check code based on the (n+1)th corrected bit data.

2. The memory according to claim 1, characterized in that, The memory further includes a comparison module, which is used to determine the relationship between the actual number of corrected errors of the BCH code and the maximum number of correctable errors of the BCH code based on the comparison result between the (n+1)th target cyclic redundancy check (CRC) code and the (n+1)th corrected CRC code.

3. The memory according to claim 2, characterized in that, The comparison module includes: A comparison unit is used to output a comparison result of whether the (n+1)th target cyclic redundancy check code and the (n+1)th corrected cyclic redundancy check code are equal; A storage unit is provided for storing the comparison results.

4. The memory according to claim 3, characterized in that, The comparison unit includes an XNOR gate, the first input of which is connected to the (n+1)th target cyclic redundancy check code, the second input of which is connected to the (n+1)th corrected cyclic redundancy check code, and the output of which outputs the comparison result.

5. The memory according to claim 4, characterized in that, The storage unit includes a flip-flop, the data input terminal of the flip-flop is connected to the output terminal of the XOR gate, the clock input terminal of the flip-flop is connected to a clock signal, and the output terminal of the flip-flop outputs status data. When the XOR gate outputs the comparison result, the clock signal enables the flip-flop to output the comparison result as the state data.

6. The memory according to claim 5, characterized in that, If the status data is "1", it indicates that the actual number of corrected errors is less than or equal to the maximum number of correctable errors.

7. The memory according to claim 5, characterized in that, If the status data is "0", it indicates that the actual number of corrected errors is greater than the maximum number of correctable errors.

8. The memory according to claim 1, characterized in that, The BCH code processing module includes a decoding unit, which performs the Money Search algorithm on the (n+1)th bit data to output the (n+1)th bit corrected data, and performs the Money Search algorithm on the (n+1)th bit initial cyclic redundancy check code to output the (n+1)th bit corrected cyclic redundancy check code.

9. The memory according to claim 8, characterized in that, The input of the CRC code processing module is connected to the output of the decoding unit. The CRC code processing module encodes the corrected data of the (n+1)th bit to output the target cyclic redundancy check code of the (n+1)th bit.

10. The memory according to claim 1, characterized in that, The memory also includes a selection module, and the BCH code processing module includes an encoding unit; The first input terminal of the selection module is connected to the output terminal of the data buffer and the input terminal of the CRC code processing module. The second input terminal of the selection module is connected to the output terminal of the CRC code processing module and the input terminal of the data buffer. The output terminal of the selection module is connected to the input terminal of the encoding unit. The output terminal of the encoding unit is connected to the input terminal of the data buffer.

11. The memory according to claim 10, characterized in that, The selection module includes a selection switch. The first input terminal of the selection switch is connected to the output terminal of the data buffer and the input terminal of the CRC code processing module. The second input terminal of the selection switch is connected to the output terminal of the CRC code processing module. The output terminal of the selection switch is connected to the input terminal of the encoding unit.

12. The memory according to claim 11, characterized in that, When the CRC code processing module outputs the (n+1)th initial cyclic redundancy check code based on the (n+1)th bit data, and when the encoding unit outputs the (n+1)th BCH code based on the (n+1)th bit data, the first input terminal of the selection switch is connected to the output terminal of the selection switch.

13. The memory according to claim 12, characterized in that, When the encoding unit outputs the target BCH code based on the (n+1)th initial cyclic redundancy check code, the second input terminal of the selection switch is connected to the output terminal of the selection switch.

14. The memory according to claim 13, characterized in that, Write the (n+1)th initial cyclic redundancy check (CRC) code and the target BCH code to the data buffer.

15. The memory according to any one of claims 1-14, characterized in that, The data buffer is also used to store the first to the (n+1)th data arranged sequentially, the (n+1)th initial cyclic redundancy check code, and the target BCH code.

16. A method for judging data reliability, characterized in that, The data reliability assessment method includes: Obtain the (n+1)th target cyclic redundancy check (CRC) code corresponding to the (n+1)th data and the (n+1)th corrected CRC code corresponding to the (n+1)th initial CRC code, wherein the (n+1)th initial CRC code is obtained by encoding the (n+1)th data.

17. The data reliability judgment method according to claim 16, characterized in that, The data reliability assessment method also includes: Based on the comparison result between the (n+1)th target cyclic redundancy check (CRC) code and the (n+1)th corrected CRC code, the relationship between the actual number of corrected error bits of the BCH code and the maximum number of correctable error bits of the BCH code is determined.

18. The data reliability judgment method according to claim 17, characterized in that, The step of determining the relationship between the actual number of corrected error bits and the maximum number of correctable error bits of the BCH code based on the comparison result between the (n+1)th target cyclic redundancy check (CRC) code and the (n+1)th corrected CRC code includes: If the comparison result indicates that the (n+1)th target cyclic redundancy check code is the same as the (n+1)th corrected cyclic redundancy check code, then the actual number of corrected error bits is less than or equal to the maximum number of correctable error bits.

19. The data reliability judgment method according to claim 17, characterized in that, The step of determining the relationship between the actual number of corrected error bits and the maximum number of correctable error bits of the BCH code based on the comparison result between the (n+1)th target cyclic redundancy check (CRC) code and the (n+1)th corrected CRC code includes: If the comparison result indicates that the (n+1)th target cyclic redundancy check code is different from the (n+1)th corrected cyclic redundancy check code, then it means that the actual number of corrected error bits is greater than the maximum number of correctable error bits.

20. The data reliability judgment method according to claim 17, characterized in that, The step of obtaining the (n+1)th target cyclic redundancy check (CRC) code corresponding to the (n+1)th bit of data and the (n+1)th corrected CRC code corresponding to the (n+1)th initial CRC code includes: The (n+1)th target cyclic redundancy check code is obtained during the TCn time period; The calculation of the target cyclic redundancy check code is stopped during the TCn+1 time period, and the n+1th corrected cyclic redundancy check code is obtained.

21. The data reliability judgment method according to claim 20, characterized in that, The step of obtaining the (n+1)th target cyclic redundancy check code in the TCn time period includes: The (n+1)th bit data is processed using the Qian search algorithm to obtain the (n+1)th bit corrected data. The corrected data of the (n+1)th bit is encoded to obtain the target cyclic redundancy check code of the (n+1)th bit.

22. The data reliability judgment method according to claim 20, characterized in that, The step of stopping the calculation of the target cyclic redundancy check (CRC) code during the (TCn+1)th time period and obtaining the (n+1)th corrected CRC code includes: The (n+1)th initial cyclic redundancy check (CRC) code is obtained by performing a money search algorithm on the CRC code.

Images