Method for performing error correction using error likelihood information, and related memory controller and data storage device

Abstract

The present application relates to a method for performing error correction using error likelihood information, and a memory controller and a data storage device. The method for performing error correction includes: retrieving a codeword from a data group in the flash memory; performing a first horizontal decoding on the retrieved codeword; in response to a failure of the first horizontal decoding, performing an exclusive-OR (XOR) operation based on the retrieved codeword and parity data derived based on XOR within the data group to generate error likelihood information of the retrieved codeword; updating soft information corresponding to the retrieved codeword based on the error likelihood information; and performing a second horizontal decoding on the retrieved codeword based on the updated soft information.

Description

Technical Field

[0001] This invention relates to flash memory, and more particularly to a method for performing error repair using error probabilities information, as well as a related memory controller and data storage device. Background Technology

[0002] In modern memory systems, especially non-volatile (NV) memory such as NAND flash memory, error correction codes (ECC) are used to maintain data integrity. ECC technology can detect and correct bit errors that may occur during data storage or retrieval due to factors such as device aging, read / write interference, or other physical anomalies.

[0003] A typical ECC architecture encodes user data into codewords containing payload bits and parity bits. During data retrieval, parity bits are used to detect and correct errors based on the encoding architecture. However, all ECC architectures are limited by their existing correction capabilities. When the number of bit errors in a codeword exceeds the correction capability limit, the decoder may be unable to correct the codeword, leading to uncorrectable read errors and the potential risk of data loss.

[0004] Therefore, there is a need in the field for an improved error correction mechanism that can surpass the existing correction capabilities of conventional ECC architectures. Summary of the Invention

[0005] This invention provides an improved error correction method that utilizes a dual-decoder collaborative architecture comprising a horizontal decoder and a vertical decoder. The horizontal decoder performs ECC decoding on codewords retrieved from flash memory. Conversely, the vertical decoder operates on multiple codewords within a data group, reconstructing data and estimating errors between codewords based on an XOR-based parity check relationship (e.g., RAID-like parity check).

[0006] When a horizontal decoder cannot independently correct a codeword, a vertical decoder can be used to reconstruct the codeword or to generate error probabilities based on cross-codeword parity analysis. This error probabilities are then used to adjust the reliability index in the initial soft information of the codeword, thereby achieving secondary soft-decision horizontal decoding with a higher probability of correction. This collaborative approach significantly increases the probability of successful error correction, exceeding the existing correction capabilities of a single decoder, thus enabling adaptive multiple decoding when the memory system encounters high error rates.

[0007] An embodiment of the present invention provides a method for performing error repair in a flash memory, the method comprising: retrieving a codeword from a data group in the flash memory; performing a first level decoding on the retrieved codeword; in response to the failure of the first level decoding, performing a mutual exclusion OR operation on the retrieved codeword and a parity check data derived from mutual exclusion OR in the data group to generate error probabilities of the retrieved codeword; updating soft information corresponding to the retrieved codeword according to the error probabilities of the retrieved codeword; and performing a second level decoding on the retrieved codeword according to the updated soft information.

[0008] Embodiments of the present invention provide a memory controller for a flash memory, the memory controller comprising: a storage device, a processing unit, and an error correction code (ECC) processing circuit. The storage device is used to store program code. The processing unit is used to execute the program code such that the memory controller retrieves a codeword from the flash memory. The ECC processing circuit comprises: a horizontal decoder and a vertical decoder. The horizontal decoder is used to perform a first horizontal decoding on the retrieved codeword. The vertical decoder is used to perform a mutual exclusion OR operation on the retrieved codeword and a parity check data derived from mutual exclusion OR within the data group when the first horizontal decoding fails, to generate error probabilities for the retrieved codeword. The ECC processing circuit is further used to update soft information corresponding to the retrieved codeword based on the error probabilities; and the horizontal decoder is further used to perform a second horizontal decoding on the retrieved codeword based on the updated soft information. Attached Figure Description

[0009] Figure 1 An electronic device and a data storage device according to an embodiment of the present invention are illustrated.

[0010] Figure 2 This illustration depicts a data group stored in a non-volatile memory according to an embodiment of the present invention.

[0011] Figure 3 This illustration depicts an error repair process based on the coordinated operation of horizontal and vertical decoding, according to an embodiment of the present invention.

[0012] Figure 4 This illustration shows how the information conversion module of an embodiment of the present invention operates between the vertical decoder and the horizontal decoder.

[0013] Figure 5 A flowchart illustrating an embodiment of the error repair method for flash memory according to the present invention is shown.

[0014] [Symbol Explanation]

[0015] 10 Electronic devices

[0016] 50 Main Units

[0017] 52 processor

[0018] 54 RAM

[0019] 100 Data storage devices

[0020] 110 Memory Controller

[0021] 112 Processing Units

[0022] 112M ROM

[0023] 112C program code

[0024] 113 Internal Memory

[0025] 114 Control Logic Circuit

[0026] 118 Transmission Interface Circuit

[0027] 130 ECC processing circuit

[0028] 120 NV memory

[0029] 122_1~122_2, NMU memory units

[0030] BLK Block

[0031] SBLK Super Block

[0032] 210 Horizontal Encoder

[0033] 220 Horizontal Decoder

[0034] 230 Vertical Encoder

[0035] 240 Vertical Decoder

[0036] 250 Information Conversion Module

[0037] 300 Data Groups

[0038] C0~C127 code words

[0039] CP0~CP127 Parity Check Codes

[0040] XPD parity check code derived from XOR

[0041] Steps S11~S19, S21~S25 Detailed Implementation

[0042] Embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the inventive concept can be embodied in various different forms and should not be construed as limited to the embodiments shown. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the inventive concept to those skilled in the art. Therefore, known processes, elements, and techniques relating to some embodiments of the inventive concept will not be described. Unless otherwise stated, the same reference numerals in the drawings and written description denote the same elements and are therefore not repeated. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0043] The terms "an embodiment" or "an example" used in this specification mean that a particular feature, structure, or characteristic shown in that embodiment or example will be included in at least one embodiment of the invention. Therefore, the terms "in an embodiment" or "in an example" appearing throughout this specification do not all refer to the same embodiment. Furthermore, specific features, structures, or characteristics of the invention may be combined in any suitable combination and / or sub-combination to be implemented in one or more embodiments.

[0044] Figure 1 This diagram illustrates the architecture of an electronic device and a data storage device according to an embodiment of the present invention. As shown, the electronic device 10 includes a host device 50 and a data storage device 100. The host device 50 may include at least one processor 52 for controlling the operation of the host device 50, and a random-access memory (RAM) 54 for storing data and information required by the processor 52. Examples of the host device 50 may include (but are not limited to): smartphones, tablets, wearable devices, personal computers (such as desktop computers or laptops), image capturing devices (such as digital cameras or camcorders), game consoles, in-vehicle navigation systems, printers, scanners, or server systems. Examples of the data storage device 100 may include, but are not limited to: portable storage devices, solid-state drives, and various embedded storage devices.

[0045] In different embodiments of the present invention, the data storage device 100 may include a memory controller 110 and further include non-volatile (NV) memory 120. NV memory 120 may include one or more NV memory elements, such as a plurality of NV memory elements (MUs) 122-1-122_N. In some embodiments, NV memory 120 may be NAND flash memory, and NV memory elements 122_1-122_N may be a plurality of NAND flash memory packages or a plurality of NAND flash memory dies, but the present invention is not limited thereto.

[0046] In some embodiments, the NV memory 120 may include multiple memory blocks (BLKs), which may be grouped into multiple superblocks (SBLKs). A memory block (BLK) may be a physical block containing multiple memory cells. A superblock (SBLK) may be a unit of logical memory region used by the memory controller 110 to manage the NV memory 120. Furthermore, the composition of a superblock (SBLK) may span NV memory dies 122_1 to 122_N. A memory block (BLK) may be an array of memory cells, with multiple memory cells forming a two-dimensional or three-dimensional array structure. A memory cell may be programmed as a single-level storage cell with one bit of information, or as a multi-level storage cell with two or more bits of information (e.g., a two-level, three-level, or four-level storage cell). Additionally, a memory block (BLK) may contain multiple pages, where a page may consist of memory cells coupled to the same word line. Furthermore, a memory block (BLK) may be a unit for erase operations, while a page may be a unit for programming and read operations.

[0047] In some embodiments, each NV memory die 122_1 to 122_N is equipped with control circuitry for executing memory operation commands issued by the memory controller 110. Each NV memory die 122_1 to 122_N may contain multiple planes, each plane having multiple blocks composed of memory cells, and associated column and row control circuitry. Through multi-plane operation commands, various memory operations can be performed in parallel on different planes to perform multi-plane read, write, or erase operations.

[0048] The memory controller 110 may include a processing unit 112, a read-only memory (ROM) 112M, internal memory 113, a transmission interface circuit 118, and an error correction code (ECC) processing circuit 130. At least a portion of these circuits and components may be coupled to each other via a bus. The internal memory 113 may be implemented by one or more RAM devices. For example, the internal memory 113 may include static RAM (SRAM) and / or dynamic RAM (DRAM). The internal memory 113 may be used to provide internal storage space for the memory controller 110, such as temporarily storing information like data, addresses, commands, mapping information, variables, and / or parameters. In some embodiments, the memory controller 110 may not include DRAM. Instead, the memory controller 110 may rely on host memory buffer (HMB) technology. Using HMB technology, the memory controller 110 can utilize the host device 50's RAM 54 (e.g., DRAM) as all, part, or an extension of the internal memory 113, thereby improving the read and write performance of the data storage device 100.

[0049] Furthermore, in this embodiment, ROM 112M is used to store program code 112C, and processing unit 112 is used to execute program code 112C to control access to NV memory 120. Program code 112C may contain one or more program modules, such as boot loader code. When data storage device 100 obtains power from host device 50, processing unit 112 can initiate the initialization process of data storage device 100 by executing program code 112C. During the initialization process, microprocessor 112 can load a set of in-system programming (ISP) code from NV memory 120. Microprocessor 112 can execute ISP code, enabling data storage device 100 to perform various functions. According to one embodiment of the present invention, the ISP code may include, but is not limited to, one or more program modules related to memory access (e.g., reading, programming, and erasing), such as a read operation module, a lookup table module, a wear-leveling module, a read refresh module, a read reclaim module, a garbage collection module, and a sudden power-off recovery (SPOR) module. These modules are used to perform corresponding read, lookup table, wear-leveling, read refresh, read reclaim, garbage collection, SPOR, and other operations.

[0050] The memory controller 110 can control the reading, writing, and erasing of the NV memory 120. In addition, the memory controller 110 can simultaneously process host commands from the host device 50 to write data, and read and rewrite valid data from the NV memory 120 through garbage collection and / or wear leveling operations. The transmission interface circuit 118 may conform to specific communication specifications, such as Universal Serial Bus (USB), Secure Digital (SD) interface or its subsequent upgrades, Ultra High Speed-I (UHS-I) interface, Ultra High Speed-II (UHS-II) and its subsequent upgrades, Compact Flash (CF) interface and its subsequent upgrades, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) specification, Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Peripheral Component Interconnect Express (PCI-E), and Universal Flash Storage (UFS) specification, and may communicate with the host device 50 according to the specific communication specifications.

[0051] Typically, host device 50 may indirectly access memory device 100 by transmitting host commands and corresponding logical addresses to memory controller 110. Memory controller 110 receives host commands and logical addresses, translates host commands into memory operation commands, and further uses memory operation commands to control NV memory 120 to perform read, program, or erase operations on memory storage cells or data pages with physical addresses within NV memory 120.

[0052] In some embodiments, a logical-to-physical (L2P) address mapping table with multiple logical-to-physical (L2P) address mapping entries can be divided into multiple mapping groups. Each mapping group contains a portion of the entire L2P address mapping table for performing logical-to-physical address translation. These L2P mapping groups are permanently stored in blocks of NV memory 120 and loaded into internal memory 113 when needed. Similarly, an entity-to-logical (P2L) address mapping table with multiple entity-to-logical (P2L) address mapping entries can be divided into multiple mapping groups. Each mapping group contains a portion of the P2L address mapping table for performing entity-to-logical address translation. These P2L mapping groups are permanently stored in blocks of NV memory 120.

[0053] Figure 2 This illustration depicts a data group within an NV memory in an embodiment of the present invention. As shown, a data group 300 stored in the NV memory 120 may contain multiple codewords, such as codewords C0 to C127. Furthermore, each codeword C0 to C127 may be stored on a different page or a different superpage of the NV memory 120. For example, codeword C0 may be stored on the first page (or the first superpage) of the NV memory 120, while codeword C1 may be stored on the second page (or the second superpage). Each codeword C0 to C127 also includes parity bits CP0 to CP127 for horizontal error correction. The horizontal decoder (HD) 220 included or implemented in the ECC processing circuit 130 is used to verify and decode each codeword C0 to C127 based on the corresponding parity bits and using a specific error correction algorithm. If any codeword is determined to be erroneous, the horizontal decoder 220 will use its corresponding parity check bits to correct the erroneous bits until a predetermined error correction capability limit is reached. In different embodiments of the present invention, the horizontal decoder 220 may be a low-density parity-check code (LDPC) decoder, a Bose–Chaudhuri–Hocquenghem (BCH) decoder, a Turbo decoder, or a combination thereof, for horizontal decoding of codewords C0 to C127.

[0054] If the number of erroneous bits in one or more codewords C0 to C127 exceeds the error correction capability of the horizontal decoder 220, the parity data XPD (i.e., redundant data similar to a Redundant Array of Independent Disks (RAID) architecture) derived from exclusive-OR (XOR) operations in the data group 300 will be utilized by the vertical decoder (VD) 240 included or implemented in the ECC processing circuit 130 to attempt to generate a reconstructed version of the codeword. For example, if the number of erroneous bits in codeword C0 exceeds the error correction capability of the horizontal decoder 220, the vertical decoder 240 will perform a vertical decoding operation, which involves performing an XOR operation on the remaining codewords C1 to C127 and the XOR-derived parity data XPD to generate a reconstructed version of codeword C0. It should be noted that although Figure 2 The example shown is data group 300 containing 128 codewords and a set of parity data derived from XOR. In other embodiments, the individual number of codewords and parity data derived from XOR can be adjusted according to system design requirements.

[0055] Additionally, the ECC processing circuit 130 receives data from the host device 50 and generates each codeword C0~C127 for storage in the NV memory 120. The ECC processing circuit 130 includes or implements a horizontal encoder (HE) 210 for performing horizontal encoding on the user data according to a specific ECC encoding architecture. For example, the horizontal encoder 210 can be an LDPC encoder, a BCH encoder, a Turbo encoder, or a combination of these encoders. Furthermore, the ECC processing circuit 130 includes or implements a vertical encoder (VE) 230 for performing vertical encoding on the codewords C0~C127 to generate parity data XPD derived from XOR. For example, the vertical encoder 230 can be an XOR-based encoder (e.g., a RAID-like encoder) that generates parity data by performing an XOR operation bit-by-bit on the horizontally encoded codewords C0~C127. Note that although... Figure 2 The example shown demonstrates the generation of parity data XPD derived from XOR using 128 codewords. However, in other embodiments of the present invention, the specific number of codewords used to generate parity data derived from XOR can be adjusted according to system configuration or design requirements.

[0056] As described above, if the number of erroneous bits in codewords C0~C127 read from NV memory 120 exceeds the error correction capability limit of horizontal decoder 220, memory controller 110 will retrieve the remaining codewords from data group 300 in NV memory 120. At this time, horizontal decoder 220 will attempt to decode the remaining codewords. If the number of erroneous codewords (i.e., codewords with too many erroneous bits to be corrected by horizontal decoding) is less than or equal to the error correction capability limit of vertical decoder 240, vertical decoder 240 can be used to generate reconstructed versions of one or more erroneous codewords. However, if the number of erroneous codewords exceeds the error correction capability limit of vertical decoder 240, vertical decoder 240 will provide bit-level error likelihood information to horizontal decoder 220. This information can be used by horizontal decoder 220 for reference during soft-decision decoding, thereby improving error correction performance. See also... Figure 3 To further understand the error correction process of the present invention.

[0057] Figure 3 This illustration depicts an error recovery process based on the coordinated operation of horizontal and vertical decoding in an embodiment of the present invention. In step S11, the ECC processing circuit 130 uses the horizontal decoder 220 to perform a first horizontal decoding (e.g., LDPC decoding) on ​​the target codeword P (e.g., codeword C0) retrieved from a page of the NV memory 120. In step S12, the ECC processing circuit 130 evaluates whether the horizontal decoding of the target codeword P was successful.

[0058] If the result of a syndrome check by multiplying the target codeword P by the parity-check matrix is ​​a zero vector, indicating that no errors are detected, then decoding can be considered successful. Alternatively, if the horizontal decoder 220 can correct the detected erroneous bits within its error correction capability and converge to a valid codeword, it can also be considered successful.

[0059] In one embodiment, the horizontal decoder 220 performs soft-decision decoding based on log-likelihood ratio (LLR) data. During soft-decision horizontal decoding, the horizontal decoder 220 performs iterative message passing between variable nodes and check nodes in the coding architecture (e.g., LDPC coding). In each iteration, external information is exchanged to progressively improve the reliability estimation at the bit level, thereby gradually increasing the probability of convergence to a valid codeword.

[0060] In one embodiment, each bit in the captured target codeword P corresponds to a piece of soft information containing an LLR value. An LLR value includes a sign bit and one or more reliability bits. The sign bit represents the most likely hard-decision value for that bit; for example, a sign bit "0" indicates a higher probability that the bit is logic "0," and a sign bit "1" indicates a higher probability that the bit is logic "1." The reliability bits represent the level of confidence in the hard decision, typically determined by the magnitude of the LLR value. A higher reliability value indicates higher confidence, while a lower reliability value indicates increased uncertainty. During iterative decoding, the horizontal decoder 220 utilizes the soft information to apply higher weights to more reliable bits and adjusts the correction strategy for bits with lower reliability.

[0061] If step S12 determines that the horizontal decoding is successful, the process proceeds to step S13, where the memory controller 110 transmits the result of the horizontal decoding to the host device 50. The data transmitted by the memory controller 110 may be the uncorrected initial target codeword P (if there are no errors), or a corrected version of the target codeword P obtained after successful decoding by the horizontal decoder 220.

[0062] Conversely, if step S12 determines that horizontal decoding has failed, the process proceeds to step S14 to initiate vertical decoding. In one embodiment, horizontal decoding is determined to have failed when the horizontal decoder 220 fails to converge to a valid codeword sufficient to pass the symptom check within a predetermined maximum number of decoding iterations.

[0063] In step S14, the ECC processing circuit 130 performs vertical decoding using the vertical decoder 240. Specifically, all other codewords (e.g., codewords C1 to C127) belonging to the same data group 300 as the target codeword P are retrieved from the NV memory 120. Then, the vertical decoder 240 performs a bitwise XOR operation on the parity data derived based on XOR (e.g., XPD) and all other codewords (e.g., codewords C1 to C127) to generate a reconstructed version of the target codeword P based on the inter-codeword parity relationship within the data group 300.

[0064] If the reconstructed version of the target codeword P can directly pass the symptom check performed by the horizontal decoder 220, or if the number of its error bits falls within the error correction capability of the horizontal decoder 220, then vertical decoding is considered successful. In the latter case, although some error bits remain in the reconstructed version of the target codeword P, these error bits can be corrected by the horizontal decoder 220. At this time, the process will proceed to step S13, transmitting the data (e.g., the payload data within the codeword) of the reconstructed version or the corrected reconstructed version of the target codeword P to the host device 50. Conversely, if the reconstructed version cannot be verified or corrected successfully by the horizontal decoder 220, then vertical decoding is considered a failure, and the process will proceed to step S16.

[0065] In step S16, the ECC processing circuit 130 uses the vertical decoder 240 to generate error likelihood information (ELI) for the target codeword P. The error likelihood information can be used to indicate an estimate of the probability of an error occurring in each bit of the codeword P. The error likelihood information can also be used to adjust the initial reliability parameter of the soft information for each bit in the target codeword P. Furthermore, the ECC processing circuit 130 performs a second horizontal decoding based on the adjusted reliability parameter (i.e., the updated soft information).

[0066] In one embodiment, error likelihood information is obtained by performing a bitwise XOR operation on the captured target codeword P (e.g., codeword C0), all other codewords in the same data group (e.g., codewords C1~C127), and parity check data derived based on XOR (e.g., XPD). In one embodiment, error likelihood information may be a sequence of bits, where each bit represents the error likelihood value at the corresponding bit position in the target codeword P. In some embodiments, if a bit in the bit sequence of error likelihood information is a logic "1", it indicates that the bit at the corresponding position in the captured target codeword P is highly likely to be erroneous; in other embodiments, if a bit in the bit sequence of error likelihood information is a logic "0", it indicates that the bit at the corresponding position in the captured target codeword P is more likely to be correct. It should be noted that error likelihood information provides a probability estimate, not an absolute error detection result.

[0067] Based on the generated error probabilities, the ECC processing circuit 130 updates the soft information of the captured target codeword P. In one embodiment, the soft information of each bit captured from the NV memory 120 includes a sign bit and one or more reliability bits. The ECC processing circuit 130 updates the one or more reliability bits corresponding to each bit of the captured target codeword P bit by bit according to the generated error probabilities.

[0068] In one embodiment, to generate updated soft information for use by the horizontal decoder 220, the ECC processing circuit 130 adjusts the initial soft information determined during the capture of the target codeword P, rather than adjusting it using the modified intermediate soft information from previous iterative decoding processes (e.g., steps S11-S15). Accordingly, the horizontal decoder 220 performs a second horizontal decoding on the target codeword P using the updated soft information (i.e., a combination of the initial soft information and the error probabilities) of the captured target codeword P. In step S17, it is determined whether the second horizontal decoding was successful. If successful, the process returns to step S13, transmitting the data (e.g., payload data) in the corrected version of the captured target codeword P to the host device 50; if it still fails, the process proceeds to step S18.

[0069] In one embodiment, the ECC processing circuit 130 may include an Information Translation Module (ITM) 250, please refer to Figure 4 To gain a further understanding, as shown in the figure, the information conversion module 250 integrates (e.g., translates) the initial soft information (per bit) of the target codeword P and the error probabilities (per bit) of the target codeword P generated by the vertical decoder 240 to generate translated soft information (per bit) of the target codeword P that meets the input width requirements of the horizontal decoder 220. For example, if the initial soft information for each bit of the target codeword P is 1 sign bit plus 2 reliability bits, and the error probabilities for each bit of the target codeword P is 1 bit, then the information conversion module 250 maps the initial 2-bit reliability and 1-bit error probabilities corresponding to each bit to 2-bit translated reliability bits, so that the overall format remains 1 sign bit plus 2 reliability bits (translated reliability bits) to conform to the input format of the horizontal decoder 220.

[0070] In step S18, it will be determined whether the total number Q (including the target codeword P) of erroneous codewords extracted from the data group has decreased after going through the error repair process from steps S11 to S16.

[0071] In some cases, certain codewords in other codewords (e.g., codewords C1~C127) may be identified as erroneous codewords after being retrieved from the NV memory 120 and undergoing the vertical decoding process in step S14. Even if the erroneous bits in the target codeword P cannot be corrected in step S16, the erroneous bits of other erroneous codewords may have been corrected, thus improving the overall reliability of the data group. Therefore, this means that after several iterations of decoding in steps S11 to S16, there is a chance to successfully correct the target codeword P. Therefore, if the total number of erroneous codewords Q is reduced after step S16, the process will return to step S11, and the error repair process will be executed again, using the previously corrected codewords to assist in reconstructing or decoding the remaining erroneous codewords (including the target codeword P). Conversely, if no progress is made (i.e., the total number of erroneous codewords Q remains unchanged), the process will terminate at step S19, and the decoding of the retrieved target codeword P will be declared a failure.

[0072] Figure 5 This diagram illustrates a flowchart of an error repair method performed in a flash memory, according to an embodiment of the present invention. As shown, the error repair method includes the following steps: S21: Retrieve a codeword from a data group in the flash memory; S22: Perform a first level decoding on the captured codeword; S23: In response to the failure of the first horizontal decoding, an XOR operation is performed based on the captured codeword and a parity check data derived from exclusive-OR (XOR) in the data group to generate an error probability information of the captured codeword. S24: Update the software information corresponding to the captured codeword based on the error probability information; and S25: Perform a second horizontal decoding on the captured codeword based on the updated software information.

[0073] Since the principles and specific details of these steps have been clearly described in the above embodiments, they will not be repeated here. It should be noted that the above process can be improved by adding other additional steps, or by making appropriate modifications and / or adjustments to enhance the read performance and error recovery efficiency of the flash memory.

[0074] Embodiments of the present invention can be implemented as an apparatus, method, or computer program product. Accordingly, embodiments of the present invention may take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects, all of which are collectively referred to as "modules" or "systems" in this specification. Furthermore, embodiments of the present invention may take the form of a computer program product embodied in any tangible medium containing computer-usable program code. In terms of hardware, the present invention can be implemented by applying any of the following techniques or related combinations: individual operation logic having logic gates capable of performing logical functions according to data signals, and application-specific integrated circuits (ASICs), programmable gate arrays (PGAs), or field-programmable gate arrays (FPGAs) having appropriate combinatorial logic.

[0075] The flowcharts and block diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of program code, containing one or more executable instructions for implementing a specified logical function. It should also be noted that each block in the block diagram and / or flowchart description, and combinations of blocks in the block diagram and / or flowchart description, may be implemented by a dedicated hardware system that performs the specified function or action, or a combination of dedicated hardware and computer instructions. These computer program instructions may be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture containing means of instruction to implement the functions / actions specified in the blocks of the flowchart and / or block diagram.

[0076] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for performing error repair in a flash memory, comprising: Retrieve a codeword from a data group in the flash memory; Perform a first level decoding on the captured codeword; In response to the failure of the first horizontal decoding, an XOR operation is performed on the captured codeword and a parity check data derived from exclusive-OR (XOR) in the data group to generate an error probability information of the captured codeword. Update the software information corresponding to the captured codeword based on the error profile; and Based on the updated software information, a second horizontal decoding is performed on the extracted codewords.

2. The method as described in claim 1, characterized in that, The data group contains several other codewords, the extracted codewords, and the parity data derived based on XOR.

3. The method as described in claim 2, characterized in that, The other codewords and the extracted codeword are generated through a horizontal encoding, and the horizontal encoding is a low-density parity-check code (LDPC) encoding.

4. The method as described in claim 2, characterized in that, The parity data derived from XOR is generated through a vertical encoding that involves performing an XOR operation on all codewords within the data group.

5. The method as described in claim 2, characterized in that, Further includes: In response to the failure of the first horizontal decoding, a vertical decoding is performed on the parity data derived from XOR and the other codewords to produce a reconstructed version of the captured codeword.

6. The method as described in claim 5, characterized in that, The vertical decoding involves performing an XOR operation on the parity data derived from XOR and the other codewords.

7. The method as described in claim 5, characterized in that, The steps to generate this error message include: In response to the failure of vertical decoding, an XOR operation is performed on the captured codeword, the multiple other codewords, and the parity data derived based on XOR to generate the error probabilities.

8. The method as described in claim 1, characterized in that, The first and second horizontal decodings are LDPC decodings, with the second horizontal decoding performed in a soft-decision manner.

9. The method as described in claim 1, characterized in that, The soft information includes a sign bit and one or more reliability bits corresponding to each bit of the captured codeword, and the step of updating the soft information includes: Based on the error probabilities, update the one or more reliability bits corresponding to each bit of the captured codeword bit by bit.

10. The method as described in claim 9, characterized in that, Further includes: The error probabilities of each bit of the captured codeword, and the one or more reliability bits of each bit of the captured codeword, are translated into a translated reliability information that meets the bit width requirements of the second horizontal decoding.

11. A memory controller for a flash memory, comprising: A storage device for storing program code; A processing unit for executing program code such that the memory controller fetches a codeword from the flash memory; An error correction code (ECC) processing circuit includes: A horizontal decoder is used to perform a first horizontal decoding on the captured codeword; and A vertical decoder is used to perform an XOR operation on the captured codeword and a parity check data derived based on exclusive-OR (XOR) in the data group when the first horizontal decoding fails, in order to generate an error probability information of the captured codeword. The ECC processing circuit is further used to update a soft information corresponding to the captured codeword based on the error probabilities; and the horizontal decoder is further used to perform a second horizontal decoding on the captured codeword based on the updated soft information.

12. The memory controller as claimed in claim 11, characterized in that, The data group contains several other codewords, the extracted codewords, and the parity data derived based on XOR.

13. The memory controller as claimed in claim 12, characterized in that, The ECC processing circuit also includes a horizontal encoder for performing a horizontal encoding to generate the plurality of other codewords and the captured codeword, and the horizontal encoding is a low-density parity-check code (LDPC) encoding.

14. The memory controller as claimed in claim 12, characterized in that, The ECC processing circuit also includes a vertical encoder that performs an XOR operation on all codewords in the data group to generate the parity data derived from the XOR.

15. The memory controller as claimed in claim 11, characterized in that, When the first horizontal decoding fails, the vertical decoder further performs a vertical decoding on the parity data derived from XOR and the multiple other codewords to produce a reconstructed version of the captured codeword.

16. The memory controller as claimed in claim 15, characterized in that, The vertical decoder is used to perform the vertical decoding, which includes performing an XOR operation on the parity data derived from XOR and the plurality of other codewords.

17. The memory controller as claimed in claim 15, characterized in that, When the vertical decoding fails, the vertical decoder performs an XOR operation on the captured codeword, the multiple other codewords, and the parity data derived from XOR to generate the error probability information.

18. The memory controller as claimed in claim 11, characterized in that, The first and second horizontal decodings are LDPC decodings, and the second horizontal decoding is performed in a soft-decision manner.

19. The memory controller as claimed in claim 11, characterized in that, The soft information includes a sign bit and one or more reliability bits corresponding to each bit of the captured codeword, and the ECC processing circuit is used to update the one or more reliability bits corresponding to each bit of the captured codeword bit by bit according to the error probabilities information.

20. The memory controller as claimed in claim 19, characterized in that, The ECC processing circuit also includes: An information translation module is used to translate the error probabilities of each bit of the captured codeword, along with one or more reliability bits of each bit of the captured codeword, into translated reliability information that meets the bit width requirements of the second horizontal decoding.

21. A data storage device comprising a flash memory and a memory controller as claimed in claim 11.

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