Flash decoding parameter determination method, apparatus, device, medium and program product

Abstract

The application discloses a flash decoding parameter determination method and device, equipment, medium and program product, and relates to the technical field of memory development, comprising: constructing a corresponding distribution data set based on the soft readout information of flash samples of different manufacturers and different batches under a plurality of read-write cycle times; constructing an initial parameter space based on the value range of each decoding parameter; using the distribution data set to perform multi-distribution joint simulation on the flash samples in the initial parameter space to obtain the optimal parameter combination of the flash samples under each read-write cycle time; determining the configurable parameter range of the firmware of the flash sample according to the optimal parameter combination, and generating a dynamic lookup table for the solidification configuration and dynamic switching of the flash. Through multi-distribution joint simulation of flash of multiple manufacturers, multiple batches and multiple life points, the optimal parameter combination meeting the performance requirement and having the optimal hardware cost is screened, and the problem that the traditional solidification decoding parameter design is difficult to consider performance, efficiency and universality is solved.

Description

Technical Field

[0001] This application relates to the field of memory development technology, and in particular to a method, apparatus, device, medium and program product for determining flash memory decoding parameters. Background Technology

[0002] As NAND Flash memory process nodes continue to shrink and multi-level storage technologies such as TLC / QLC (Triple-Level Cell / Quad-Level Cell) become more widespread, memory cells face degradation issues such as threshold voltage drift and increased read noise during long-term use. This leads to a significant decrease in the reliability of soft-decision information, and the log-likelihood ratio (LLR) distribution shows a significant shift with the number of read / write cycles. Currently, Flash controllers generally use low-density parity-check codes (LDPC) for error correction. To balance hardware complexity and error correction performance, approximate decoding algorithms such as normalized minimum sum and bias minimum sum are typically chosen. The key parameters of the approximate decoding algorithm are determined through manual experience or a small number of sample tests during the design phase and then fixed in hardware.

[0003] To address the issue of degraded information read quality in flash memory, existing technologies primarily improve decoding performance through LLR optimization, reread strategy adjustment, or dynamic scaling. However, these solutions are mostly focused on specific media or single scenarios, lacking a systematic adaptation to the differences in LLR distribution across multiple vendors, batches, and read / write cycles. Since flash memory samples from different sources exhibit significantly different error correction performance under the same parameters, fixed parameter designs are prone to two types of problems: firstly, to ensure reliability in extreme scenarios, the number of iterations or redundancy needs to be excessively increased, resulting in unnecessary power consumption and latency; secondly, if the parameters cannot cover the characteristics of certain batches or lifespan ranges, insufficient error correction performance will occur, severely impacting the controller's versatility and product yield. Therefore, existing hardware-fixed decoding parameters lack a systematic design, exhibiting a difficulty in balancing performance, efficiency, and versatility, making them unsuitable for flash memory applications.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, device, medium, and program product for determining flash memory decoding parameters, aiming to solve the technical problem that existing decoding parameters for hardware fixation lack systematic design and have difficulty in balancing performance, efficiency, and versatility.

[0006] To achieve the above objectives, this application proposes a method for determining flash memory decoding parameters, the method comprising: Based on the soft readout information of each flash memory sample under multiple read / write cycles, a distributed dataset of the soft readout information is constructed; the flash memory samples include samples from multiple manufacturers and multiple batches. An initial parameter space is constructed based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode; Using the distributed dataset within the initial parameter space, multi-distribution joint simulation is performed on the flash memory sample to obtain the optimal parameter combination for the flash memory sample in each read / write cycle. The configurable parameter range of the flash sample firmware is determined based on the optimal parameter combination, and a dynamic lookup table is generated. The dynamic lookup table is used to store the decoding parameter combination corresponding to each read / write cycle number. When the firmware is configured with the dynamic lookup table, the parameter value of the decoding parameter is dynamically switched according to the actual read / write cycle number during use.

[0007] In one embodiment, the step of using the distributed dataset to perform multi-distribution co-simulation on the flash memory samples within the initial parameter space to obtain the optimal parameter combination of the flash memory samples for each read / write cycle includes: The original bit information of the flash memory sample is randomly generated, and the original bit information is encoded based on the parity check matrix of the error correction code to generate a valid codeword; Noise is added to the legal codewords based on the distribution dataset to generate a noisy distribution dataset; In the noisy distributed dataset, the noisy distributed data of the flash memory samples under each read / write cycle number is used as the input of the decoding engine. The noisy distributed data is iteratively decoded by traversing each decoding parameter combination in the initial parameter space. During the decoding process, the verification node messages of the verification matrix are scaled and corrected according to the decoding parameter combination. The variable nodes of the verification matrix and the verification nodes are updated through a hierarchical scheduling mechanism until the preset iteration termination condition is met, and the decoding result is obtained. The decoding result is compared bit by bit with the original bit information to calculate the performance quantification index for each read / write cycle; the performance quantification index includes at least one of bit error rate and frame error rate; Based on the aforementioned performance quantification metrics, the optimal parameter combination is selected from the decoding parameter combinations for each read / write cycle.

[0008] In one embodiment, the step of adding noise to the legal codewords based on the distribution dataset to generate a noisy distribution dataset includes: Based on the distribution data of each flash memory sample in the distributed dataset, a probability distribution mapping model for each flash memory sample is constructed; the probability distribution mapping model can simulate the data access noise of the flash memory sample. Using the probability distribution mapping model, noise is added to the legal codewords to generate a noisy distribution dataset.

[0009] In one embodiment, the step of selecting the optimal parameter combination from the decoding parameter combinations for each read / write cycle based on the performance quantification index includes: The performance quantification index is compared with the preset performance constraints, and candidate parameter combinations that satisfy the performance constraints are selected for each read / write cycle number. The candidate parameter combinations are filtered according to the priority strategy pre-configured for each decoding parameter to obtain the optimal parameter combination for each read / write cycle.

[0010] In one embodiment, the decoding mode includes hard decision and soft decision; after the step of adding noise to the legal codewords according to the distribution dataset to generate a noisy distribution dataset, the method further includes: For the hard decision in the decoding mode, extract the symbol information of the noisy distribution data in the noisy distribution dataset and delete the assignment information to obtain the first noisy dataset; For the soft decision in the decoding mode, the symbol information of the noisy distribution data in the noisy distribution dataset is extracted and the assignment information is retained to obtain the second noisy dataset.

[0011] In one embodiment, the step of constructing a distributed dataset of soft read information based on the soft read information of each flash memory sample under multiple read / write cycles includes: The soft read information of each flash memory sample under multiple read / write cycles is compared with the correct information, and the log-likelihood ratio of the soft read information under each read / write cycle is calculated. Based on the probability distribution of the log-likelihood ratio, a distribution dataset of the soft readout information is constructed.

[0012] Furthermore, to achieve the above objectives, this application also proposes a flash memory decoding parameter determination device, which includes: The first construction module is used to construct a distributed dataset of the soft read information based on the soft read information of each flash memory sample under multiple read / write cycles; the flash memory samples include samples from multiple manufacturers and multiple batches; The second construction module is used to construct an initial parameter space based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode; The simulation test module is used to perform multi-distribution joint simulation of the flash memory sample within the initial parameter space using the distributed dataset, so as to obtain the optimal parameter combination of the flash memory sample under each read-write cycle number. The parameter fixing module is used to determine the configurable parameter range of the flash sample firmware according to the optimal parameter combination and generate a dynamic lookup table. The dynamic lookup table is used to store the decoding parameter combination corresponding to each read / write cycle count. When the firmware is configured with the dynamic lookup table, it dynamically switches the parameter value of the decoding parameter according to the actual read / write cycle count during use.

[0013] In addition, to achieve the above objectives, this application also proposes a flash memory decoding parameter determination device, the device comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the flash memory decoding parameter determination method as described above.

[0014] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the flash memory decoding parameter determination method described above.

[0015] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the flash memory decoding parameter determination method described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: By constructing a distributed dataset based on soft readout information from flash memory samples from multiple manufacturers and batches under multiple read / write cycles, the performance distribution characteristics of flash memory from multiple manufacturers, batches, and different lifespan stages are systematically integrated. This solves the problem of poor parameter adaptability caused by insufficient sample coverage and provides comprehensive data support for subsequent parameter design. Secondly, based on the value range of each decoding parameter, an initial parameter space is constructed, clarifying the adjustable range of core decoding parameters such as normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode. This avoids the problem of fixed or overly narrow parameters in traditional designs and provides sufficient flexibility for decoding optimization. On this basis, multi-distribution co-simulation of flash memory samples is performed using the distributed dataset within the initial parameter space to obtain flash memory sample data. The optimal parameter combination for each read / write cycle count can be selected under the joint constraints of multiple vendors, multiple batches, and multiple lifespan points, simultaneously meeting performance requirements and having the optimal hardware cost, thus solving the problem of performance-efficiency imbalance. Finally, based on the optimal parameter combination, the configurable parameter range of the flash memory sample's hardware device is determined, and a dynamic lookup table is generated for dynamic switching during flash memory use based on the actual number of read / write cycles. This ensures that the hardware design is compatible with parameter requirements throughout the entire lifecycle, improving the versatility of the flash memory controller. Furthermore, by dynamically switching parameters based on the actual number of read / write cycles, the efficiency loss caused by uniformly using high-overhead parameters throughout the entire lifecycle is avoided, achieving reliable error correction with good performance at different stages of flash memory use. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating an embodiment of the flash memory decoding parameter determination method of this application. Figure 2 This is a schematic diagram of the simulation test process of the flash memory simulation test system provided in the embodiments of this application; Figure 3 A schematic diagram of the simulation process for multi-distributed co-simulation provided in this application embodiment; Figure 4 This is a schematic diagram of the module structure of the flash memory decoding parameter determination device according to an embodiment of this application; Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the flash memory decoding parameter determination method in this application embodiment.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] The main solution of this application embodiment is as follows: In integrated circuit development scenarios involving memory controllers (or flash memory controllers), considering different flash memory manufacturers, different production batches, and different read / write cycle counts, an LLR distribution dataset is constructed by collecting soft readout information from multiple flash memory samples, and an initial parameter space for decoding parameters is built. Based on multi-distribution co-simulation, the optimal parameter combination that meets performance constraints is screened, and finally, a configurable hardware design range and dynamic lookup table are generated. Through systematic design, the decoding parameters are solidified, and the decoding parameters are adaptively switched under different read / write cycle counts during actual use of the flash memory controller, thus simultaneously balancing performance, efficiency, and versatility.

[0024] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or flash memory decoding parameter determination device capable of performing the above functions. The following description uses a flash memory decoding parameter determination device as an example to illustrate this embodiment and the subsequent embodiments.

[0025] Based on this, embodiments of this application provide a method for determining flash memory decoding parameters, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the flash memory decoding parameter determination method of this application.

[0026] In this embodiment, the flash memory decoding parameter determination method includes steps S10~S40: Step S10: Based on the soft readout information of each flash memory sample under multiple read / write cycles, construct a distribution dataset of the soft readout information; the flash memory samples include samples from multiple manufacturers and multiple batches; Step S20: Construct an initial parameter space based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode; Step S30: Using the distributed dataset within the initial parameter space, perform multi-distribution joint simulation on the flash memory sample to obtain the optimal parameter combination for the flash memory sample in each read / write cycle. Step S40: Determine the configurable parameter range of the flash sample firmware based on the optimal parameter combination, and generate a dynamic lookup table; the dynamic lookup table is used to store the decoding parameter combination corresponding to each read / write cycle count, and when the firmware is configured with the dynamic lookup table, it dynamically switches the parameter value of the decoding parameter according to the actual read / write cycle count during use.

[0027] Step S10: Based on the soft readout information of each flash memory sample under multiple read / write cycles, construct a distribution dataset of the soft readout information; the flash memory samples include samples from multiple manufacturers and multiple batches.

[0028] It should be noted that soft readout information can be the raw analog or digital signal acquired during flash memory reads without hard decision processing, such as the log-likelihood ratio (LLR) value containing bit confidence. The purpose of soft readout information is to characterize the level probability characteristics read from flash memory cells under specific physical degradation states. Flash memory samples can be NAND flash memory or flash storage media produced by different manufacturers or by the same manufacturer in different batches at different times.

[0029] As an example, flash memory samples from different manufacturers and batches are collected. At each read / write cycle number node (e.g., 100, 500, 1000 times), soft read information is obtained by reading the same storage cell multiple times. The data is stored in a three-level structure of "manufacturer-batch-read / write cycle number". For example, the dataset of soft read information of the mth batch of the kth manufacturer at the rth cycle is denoted as D[k][m][r], which contains the LLR value distribution (e.g., mean, variance, probability density function) of all storage cells under this condition.

[0030] Understandably, multiple read / write cycle counts can cover the entire lifespan of each flash memory sample. The aforementioned distributed dataset can be a statistical probability matrix or a structured list containing multiple dimensions, such as a two-dimensional probability array containing measurement points corresponding to different read / write cycle counts.

[0031] Step S20: Construct an initial parameter space based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode.

[0032] Decoding parameters can be key configuration variables that affect the performance and overhead of low-density parity-check (LDPC) error correction algorithms. As an example, decoding parameters are control parameters inside flash decoding algorithms, especially parameters related to error correction decoding, such as normalization factors and bias parameters in normalized minimum sum algorithms.

[0033] The decoding parameters specifically include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode. The normalization factor can be a coefficient used to scale the check node message, balancing the information transmission strength between the variable node and the check node. The bias parameter can be a constant used to correct the check node message offset, compensating for the approximation error of the minimum sum algorithm. The number of punctures can be the number of bits deleted from the encoded codeword, improving storage efficiency. The decoding mode can be a hard decision (using only symbol information) or a soft decision (retaining confidence information) processing method.

[0034] Based on the value range of each decoding parameter, an initial parameter space is constructed. This initial parameter space contains all possible combinations of parameter values ​​within the value range of each decoding parameter. Each parameter combination contains one parameter value of all parameters, and different parameter combinations have at least one parameter with a different value.

[0035] The range of decoding parameters can be configured based on experience, or it can be automatically generated based on cluster analysis of the decoding parameter values ​​of historical mature flash memory products using machine learning algorithms. The initial parameter space of the decoding parameters is a discontinuous, high-dimensional parameter space.

[0036] Step S30: Using the distributed dataset within the initial parameter space, perform multi-distribution joint simulation on the flash memory sample to obtain the optimal parameter combination for the flash memory sample in each read / write cycle.

[0037] Multi-distributed co-simulation is a simulation method used to simultaneously evaluate the global error correction performance of a specific set of parameters in response to multiple different underlying noise distributions within a unified simulation verification architecture. It should be noted that the aforementioned hardware device can be a flash memory controller integrated into a solid-state drive or embedded storage system, such as a storage controller chip containing programmable registers. Furthermore, the aforementioned dynamic lookup table can be a state mapping table embedded in the controller's internal memory, such as a parameter configuration table written to read-only memory (ROM).

[0038] As an example, using the constructed distributed dataset, multi-distribution co-simulation is performed on flash memory samples in the initial parameter space to obtain the optimal parameter combination for each read / write cycle. Multi-distribution co-simulation can be a simulation process that simultaneously considers the LLR distribution characteristics of multiple flash memory samples, and its purpose is to verify the compatibility of various parameter combinations under diverse scenarios.

[0039] Step S40: Determine the configurable parameter range of the flash sample firmware based on the optimal parameter combination, and generate a dynamic lookup table; the dynamic lookup table is used to store the decoding parameter combination corresponding to each read / write cycle count, and when the firmware is configured with the dynamic lookup table, it dynamically switches the parameter value of the decoding parameter according to the actual read / write cycle count during use.

[0040] The configurable parameter range of the firmware for the flash memory sample is determined based on the optimal parameter combination, and a dynamic lookup table is generated based on this configurable parameter range.

[0041] The configurable parameter range can be the minimum-maximum range supported by the hardware registers, which ensures that the hardware can adapt to all optimal parameter combinations; while the dynamic lookup table can be a parameter mapping table stored in non-volatile memory, which enables the decoding parameters to switch automatically with the number of read and write cycles.

[0042] The generated dynamic lookup table can be represented as a set of configuration bit streams in a reconfigurable logic device. When the flash firmware senses that the actual number of read / write cycles of the flash memory has reached a specific threshold, it directly burns the corresponding decoding parameter hardware bit stream through dynamic local reconfiguration technology, thereby realizing dynamic switching of decoding parameters at the hardware level.

[0043] In one embodiment, the lookup table is stored in the controller's SRAM, which supports online firmware updates to adapt to the parameter requirements of new batches of flash memory.

[0044] The dynamic lookup table is specifically used to store the combination of decoding parameters corresponding to each read / write cycle count. When the flash firmware is configured with a dynamic lookup table, the parameter values ​​of the decoding parameters can be switched according to the actual read / write cycle count during use.

[0045] Understandably, in a dynamic lookup table, the relationship between the number of read / write loops and the combination of decoding parameters can be either one-to-one or many-to-one. In a many-to-one relationship, multiple read / write loop counts correspond to the same combination of decoding parameters, or a range of read / write loop counts (e.g., 100 to 200 read / write loops) corresponds to one combination of decoding parameters.

[0046] By covering soft readout information from multiple vendors, batches, and lifetimes, and combining parameter space and multi-distribution joint simulation, the selection of decoding parameters and determination of hardware fixation range can be completed automatically and systematically under the joint constraints of multiple vendors, batches, and the entire life cycle. This fundamentally solves the problems of insufficient error correction performance or excessive hardware redundancy caused by the inability of a single empirical parameter to take into account the differences in soft readout characteristics in multiple scenarios, as well as the problems of poor adaptability and performance-efficiency imbalance of traditional fixed parameters, thus improving the versatility and full life cycle error correction reliability of flash memory controllers.

[0047] In this embodiment, a distributed dataset is constructed based on soft readout information from flash memory samples from multiple manufacturers and batches under multiple read / write cycles. This systematically integrates the performance distribution characteristics of flash memory from multiple manufacturers, batches, and different lifespan stages, solving the problem of poor parameter adaptability caused by insufficient sample coverage and providing comprehensive data support for subsequent parameter design. Secondly, based on the value range of each decoding parameter, an initial parameter space is constructed, clarifying the adjustable range of core decoding parameters such as normalization factor, bias parameter, maximum iteration count, number of punctures, and decoding mode. This avoids the problem of fixed or overly narrow parameters in traditional designs, providing sufficient flexibility for decoding optimization. On this basis, multi-distribution co-simulation of flash memory samples is performed using the distributed dataset within the initial parameter space to obtain... The optimal parameter combination for each read / write cycle of the flash memory sample can be selected under the joint constraints of multiple manufacturers, multiple batches, and multiple lifespan points, simultaneously meeting performance requirements and having the optimal hardware cost, thus solving the problem of performance and efficiency imbalance. Finally, based on the optimal parameter combination, the configurable parameter range of the hardware device for the flash memory sample is determined, and a dynamic lookup table is generated for dynamic switching of the flash memory during use based on the actual number of read / write cycles. This ensures that the hardware design can be compatible with parameter requirements throughout the entire lifecycle, improving the versatility of the flash memory controller. Furthermore, by dynamically switching parameters based on the actual number of read / write cycles, the efficiency loss caused by uniformly using high-overhead parameters throughout the entire lifecycle is avoided, achieving reliable error correction with good performance at different stages of flash memory use.

[0048] In one feasible implementation, step S10 may include steps S11-S12: Step S11: Compare the soft read information of each flash memory sample with the correct information under multiple read / write cycles, and calculate the log-likelihood ratio of the soft read information under each read / write cycle. Step S12: Based on the probability distribution of the log-likelihood ratio, construct the distribution dataset of the soft readout information.

[0049] Correct information is known, error-free stored data used as a comparison benchmark. The probability distribution of the log-likelihood ratio can be the statistical law of the log-likelihood ratio (LLR) value under different conditions, used to describe noise characteristics.

[0050] When constructing the distributed dataset, the soft read information of each flash memory sample under multiple read / write cycles is compared with the correct information. The log-likelihood ratio (LLR) of the soft read information under each read / write cycle is calculated, and based on the probability distribution of the LLR, an LLR probability distribution dataset of the soft read information is constructed. Through LLR calculation and probability distribution construction, the original soft read information is transformed into standardized statistical features, providing a unified input for subsequent multi-distribution joint simulation.

[0051] For example, the constructed distributed dataset is denoted as D[k], k=1~N, where N is the total number of data batches provided by all Flash memory manufacturers. D[k] contains soft readout information C with different read / write cycle counts. k [1]~C k [M], where M is the number of measurement points for the number of read / write cycles of data records in the same batch of flash memory. C k This includes the bit error rate after the LLR obtained from the test is converted into bit information by symbol, the LLR probability distribution of erroneous bits, and the LLR probability distribution of non-erroneous bits.

[0052] The log-likelihood ratio can be a reliability metric for soft-decision decoding, such as the log-likelihood ratio (LLR) of soft readout information calculated based on the channel transition probability. Its probability distribution reflects the frequency or statistical characteristics of different log-likelihood ratio values ​​in the case of erroneous bits and non-erroneous bits.

[0053] By constructing an LLR probability distribution dataset, we achieved accurate statistical quantification of the underlying physical characteristics of flash memory. By strictly distinguishing the LLR distribution characteristics of erroneous bits and non-erroneous bits, we provided the most core and closest data support to the real physical environment of flash memory for subsequent high-precision multi-distribution joint simulation.

[0054] In one feasible implementation, step S30 may include steps S31 to S35: Step S31: Randomly generate the original bit information of the flash memory sample, and encode the original bit information based on the parity check matrix of the error correction code to generate a valid codeword; Step S32: Add noise to the legal codewords according to the distribution dataset to generate a noisy distribution dataset; Step S33: In the noisy distribution data set, the noisy distribution data of the flash memory samples under each read / write cycle number is used as the input of the decoding engine. The noisy distribution data is iteratively decoded by traversing each decoding parameter combination in the initial parameter space. During the decoding process, the verification node messages of the verification matrix are scaled and corrected according to the decoding parameter combination. The variable nodes of the verification matrix and the verification nodes are updated through a hierarchical scheduling mechanism until the preset iteration termination condition is met, and the decoding result is obtained. Step S34: Compare the decoding result with the original bit information bit by bit to calculate the performance quantification index for each read / write cycle; the performance quantification index includes at least one of bit error rate and frame error rate; Step S35: Based on the performance quantification index, select the optimal parameter combination from the decoding parameter combinations for each read / write cycle.

[0055] It should be noted that the original bit information can be a random test sequence used to simulate real user writes to flash memory, such as a binary bit stream generated by a pseudo-random number generator. The parity check matrix of the error-correcting code defines the parity check constraint relationship between the bits in the valid codeword. The valid codeword can be an encoded sequence that completely satisfies the null space constraint of the parity check matrix, such as a combination of the systematic code and parity bits after LDPC encoding. The decoding engine executes specific iterative error correction algorithms to recover the damaged original information. The check node message is used to transmit the external confidence evaluation information of the check equation for each variable bit in the bipartite graph network. The variable node represents the current probability or hard-decision state of each codeword bit.

[0056] Additionally, it should be noted that the iteration termination condition can be a preset maximum number of loop executions or a comprehensive check state where all check equations have been satisfied, such as an early stopping criterion where the adjoint is zero. Performance quantification metrics are objective measurements of the error correction effectiveness of the decoding engine, including but not limited to bit error rate (BER) or frame error rate (FER).

[0057] In one implementation, the original bit information to be stored in the flash memory sample is generated by randomly generating bits of a fixed length. The original bit information is then encoded to generate valid codewords based on the QC-LDPC check matrix. This eliminates the need for a complex generation matrix, thus simplifying the encoding hardware overhead.

[0058] Based on the distribution dataset of flash memory samples, noise is added to the legal codewords to obtain a noisy distribution dataset. After the noisy data is constructed, it is input into the parameterized LDPC decoding engine for iterative decoding processing.

[0059] During the iterative decoding process, the decoding parameter combinations in the initial parameter space are traversed. Based on the current normalization factor, bias parameter, code puncturing status, and maximum iteration count, the check node message is scaled and corrected. A hierarchical scheduling mechanism is used to efficiently update the variable node and check node information. When the termination condition is met or the maximum iteration count is reached, the final decoding result is output and compared bit by bit with the original bit information. Performance quantification indicators such as bit error rate (BER) or frame error rate (FER) are calculated, and the optimal parameter combination is selected based on these performance quantification indicators.

[0060] The noisy distribution dataset is a set of LLR distributions after the flash memory stores noise, used to restore the signal distortion during actual reading. As an example, noisy LLR values ​​are generated based on the LLR probability distribution dataset using methods such as inverse transform sampling, thus obtaining the noisy distribution dataset.

[0061] A hierarchical scheduling mechanism can be a strategy of updating nodes in groups based on rows or columns of the parity check matrix, which can be used to improve decoding convergence speed. For example, the parity check matrix can be hierarchically divided by rows, and the parity check node and variable node information corresponding to each row can be updated sequentially.

[0062] Bit error rate (BER) is the ratio of the number of erroneous bits to the total number of bits, used to quantify the reliability of a single bit; frame error rate (FER) is the ratio of the number of erroneous frames to the total number of frames, used to quantify the reliability of an entire frame. The optimal parameter combination is the decoding parameter combination that simultaneously satisfies performance constraints and has the lowest hardware cost.

[0063] By employing a standardized simulation process that closely approximates the real behavior of hardware through encoding, noise addition, decoding, and comparison, quantitative evaluation of parameter combinations is achieved. This allows for accurate prediction of the error correction performance of any parameter combination without the need for actual chip fabrication, ensuring that the optimal parameter combination simultaneously meets performance requirements and hardware efficiency. This improves the reliability and repeatability of simulation results and significantly reduces the cost and cycle of algorithm verification.

[0064] In one feasible implementation, step S32 may further include steps S321 to S322: Step S321: Based on the distribution data of each flash memory sample in the distribution dataset, construct a probability distribution mapping model for each flash memory sample; the probability distribution mapping model can simulate the data access noise of the flash memory sample. Step S322: Using the probability distribution mapping model, noise is added to the legal codewords to generate a noisy distribution dataset.

[0065] Probability distribution mapping models are mathematical models that describe the statistical relationship between LLR values ​​and actual bit values, or mathematical simulation models of channel degradation constructed based on statistical empirical distributions. Examples include noise generators based on Markov chains or lookup tables, used to simulate the noise characteristics during flash memory data access. The role of data access noise is to simulate bit flips and signal level fluctuations caused by physical interference during data writing and reading in real flash memory.

[0066] Adding noise to legitimate codewords involves perturbing the LLR value of the legitimate codewords according to a probability distribution mapping model to generate a signal close to that of actual reads. In one implementation, a corresponding LLR probability distribution mapping model is constructed based on a distribution dataset. This model can accurately simulate the corresponding storage or read noise for flash memory probability distributions from different manufacturers and batches. When adding noise, for each bit in a legitimate codeword, it is first randomly flipped according to the overall error probability (e.g., 0.005) corresponding to that measurement point, and the flipped bits are recorded. Subsequently, for the flipped bits, their LLR is assigned according to the probability requirements of the error bit distribution data, and for the unflipped bits, their LLR is assigned according to the probability requirements of the non-error bit distribution data, thereby simulating the addition of real physical noise and generating a noisy distribution dataset.

[0067] By accurately simulating flash memory noise using a probability distribution mapping model, and replacing the traditional ideal Gaussian white noise with a data-driven mapping model, the complex asymmetric channel noise of flash memory is accurately reproduced, improving the realism of the simulation and ensuring the effectiveness of the decoding parameter combination in practical applications.

[0068] In one embodiment, step S35 may further include steps S351 to S352: Step S351: Compare the performance quantification index with the preset performance constraints, and select candidate parameter combinations in which the performance quantification index satisfies the performance constraints for each read / write cycle number. Step S352: According to the priority strategy pre-configured for each decoding parameter, the candidate parameter combinations are filtered to obtain the optimal parameter combination for each read / write cycle.

[0069] It should be noted that performance constraints can be error interception thresholds that meet the commercial-grade quality standards for flash memory products, such as a threshold requiring a frame error rate strictly less than one in a thousand. Candidate parameter combinations can be feasible combinations that have been verified to successfully correct all severe noise samples under the current read / write cycles. The priority strategy is a pre-defined, fixed rule used to automatically select the optimal solution that is most hardware-friendly when faced with multiple feasible solutions that meet the performance requirements.

[0070] In other words, the performance constraint is the reliability index threshold that the flash firmware product must meet, used to filter out decoding parameter combinations that do not meet the performance requirements; the priority strategy can be a predefined parameter selection order, used to balance performance and hardware cost.

[0071] In one implementation, performance quantification metrics are compared with preset performance constraints to determine whether the corresponding decoding parameter combination meets the preset performance constraints. Specifically, after setting a set of decoding parameters, all noisy flash memory data from specified manufacturers and batches under a certain read / write cycle constraint are used as input. The decoding engine performs iterative decoding, and the decoding results are compared bit-by-bit with the original bit information to statistically analyze the performance quantification metrics. If the final statistically obtained performance quantification metrics—bit error rate BER ≤ T1 or frame error rate FER ≤ T2 (T1 and T2 are the performance thresholds specified for flash memory products, i.e., performance constraints; generally, T1 is 10 to the power of -6 and T2 is 10 to the power of -3)—then the decoding parameter combination is considered to meet the performance constraints, and this set of decoding parameters is selected as a candidate parameter combination.

[0072] Then, according to the priority strategy pre-configured for each decoding parameter, the candidate parameter combinations are screened to obtain the optimal parameter combination for each read / write cycle. As an example, the priority strategy of the decoding parameters is determined based on the degree of influence of the decoding parameters on the cost and power consumption of the flash memory hardware. The greater the influence on the cost and power consumption of the flash memory hardware, the higher the priority; conversely, the smaller the influence on the cost and power consumption of the flash memory hardware, the lower the priority.

[0073] For example, to minimize hardware requirements, the optimal parameter combination is selected based on a priority strategy. Specifically, firstly, the decoding mode is prioritized to minimize decoding power consumption and latency. On this basis, the number of punctures is then prioritized to optimize flash memory storage efficiency, because the larger the number of punctures, the smaller the encoding redundancy and the higher the effective storage efficiency. Finally, the combination with the smaller maximum number of iterations is prioritized to further reduce the average decoding latency. The reason for setting this parameter priority order from front to back is that the impact of key parameters such as decoding mode, number of punctures, and maximum number of iterations on hardware cost and power consumption decreases from large to small.

[0074] By using performance constraint filtering and priority selection, the optimal parameter combination is ensured to minimize hardware overhead while meeting reliability requirements. The stringent judgment and parameter selection mechanism based on performance constraints ensures that flash memory can perform error correction normally in all possible worst-case scenarios. The ingenious priority strategy ensures that the selected decoding parameter combination can maximize hardware energy efficiency, perfectly meeting the needs of large-scale integrated circuit design and achieving the optimal balance between performance and efficiency.

[0075] In one implementation, the decoding modes include hard decision and soft decision. After generating the noisy distribution dataset, different processing is required for the noisy distribution dataset depending on the decoding mode. Specifically, after step S32, steps S36-S37 may also be included: Step S36: For the hard decision in the decoding mode, extract the symbol information of the noisy distribution data in the noisy distribution dataset and delete the assignment information to obtain the first noisy dataset; Step S37: For the soft decision in the decoding mode, extract the symbol information of the noisy distribution data in the noisy distribution dataset and retain the assignment information to obtain the second noisy dataset.

[0076] It should be noted that hard decision is a low-power operating mode that uses only single-bit polarity information for decoding and error correction, such as the standard bit-flipping decoding mode; soft decision is a high-gain operating mode that uses multi-bit quantization information carrying confidence to perform decoding, such as the min-sum decoding mode.

[0077] Additionally, it should be noted that the symbol information can be the sign of the LLR value, representing whether the most basic Boolean logic decision of the currently read bit is 0 or 1, representing the initial judgment result of the bit; the assignment information can be the absolute value of the LLR value, which is a specific numerical value representing the degree of confidence or reliability of the above symbol information. In soft-decision mode, retaining the assignment information specifically means retaining the absolute value of the LLR as a confidence weight to improve decoding accuracy.

[0078] Furthermore, the first noisy dataset can be a collection of data containing only binary bit streams, such as a one-dimensional array that retains only the positive and negative signs. The second noisy dataset can be a collection of data containing full quantization precision, such as a floating-point or fixed-point array where each element is a multi-bit LLR value.

[0079] In one implementation, different data preprocessing branches are executed depending on whether the decoding mode configured in the currently traversed decoding parameter combination is hard decoding (hard decision) or soft decoding (soft decision). If the decoding mode is configured as hard decoding, the symbol information is extracted from the noise-added LLR data, and its amplitude (assignment) information is directly deleted. The purified symbol data is used as the first noisy dataset. If the decoding mode is configured as soft decoding, the complete noisy LLR containing the symbols and amplitudes is directly used as the second noisy dataset and input into the decoding engine for subsequent decoding processes.

[0080] By distinguishing between hard-decision and soft-decision data processing methods, it adapts to the decoding requirements of different modes, taking into account both low-power (hard-decision) and high-performance (soft-decision) scenarios. This enables the unified multi-distributed joint simulation to be compatible with the decoding mode testing requirements of different precisions, providing a possibility for finding the best balance between power consumption, latency and error correction capabilities in the future.

[0081] In one embodiment, reference is made to Figure 2 The simulation process shown, and the flash memory decoding parameter determination method provided in this application embodiment, are applied to a flash memory simulation test system, which includes a flash memory test bench, a host computer, and integrated circuit design tools. Figure 2 As shown, the flash memory test machine generates soft readout information and constructs a distributed dataset D[1]~D[N] which is input to the host. The host performs simulation tests based on the distributed dataset and the initial parameter space of the constructed decoding parameters to obtain the optimal parameter combination PP[1]~PP[M] for each read / write cycle number and generates the corresponding dynamic lookup table. Finally, the integrated circuit design tool designs and fabricates the chip based on the optimal parameter combination for each read / write cycle number, and designs and generates the flash memory error correction chip. The host will also store the dynamic lookup table generated based on the optimal parameter combination into the flash memory error correction chip so that the flash memory chip can dynamically switch the decoding parameter combination according to the actual read / write cycle number during use.

[0082] Furthermore, for the specific process of simulation testing, please refer to... Figure 3 The testing process for multi-distribution co-simulation specifically involves iterative steps based on batch size, read / write cycle count, and decoding parameter combinations. First, batch i=1 represents the noisy distribution data of the first batch of flash memory samples, and read / write cycle count r=1 represents the measurement point data of the first read / write cycle. Based on the value range of each decoding parameter, an initial parameter space is constructed, denoted as Para=Para_space_0. For example, the normalization factor... The value range is 0.5-1.0, bias parameter The value ranges from 0 to 0.5, the maximum number of iterations Imax ranges from 5 to 50, the number of holes Punc ranges from 0 to 300, and the decoding mode Mode includes hard decision and soft decision.

[0083] With i=1 and r=1, C i[r] Data is used as input for multi-distribution joint simulation. Each decoding parameter combination in the initial parameter space Para=Para_space_0 is traversed for decoding iteration processing. Decoding parameter combinations that do not meet the preset performance constraints are filtered out, and decoding parameter combinations that meet the preset performance constraints are used as candidate parameter combinations. Determine i≥N (N is the batch number of flash memory samples). If the determination is negative, i=i+1, update the batch, and use the flash memory sample data of the new batch as input for multi-distribution joint simulation again. If the determination is positive, continue to determine r≥M (M is the number of measurement points for read and write cycles). If the determination is negative, PP[r]=the optimal parameter combination in Para. Let i=1, r=r+1 to update the read and write cycles, and use the data of the new read and write cycles as input for multi-distribution joint simulation again. Until r≥M, the optimal parameter combination PP[1]~PP[r] under each read and write cycle is obtained, and the simulation is completed.

[0084] For example, if there are 30 batches of data from 3 Flash manufacturers, then N=90. If each batch of data is measured at 10 measurement points with read / write cycle counts of 0, 10k, 20k, ..., 90k, then M=10. The initial parameter space is denoted as Para_space_0, and the performance constraint is set as FER<0.0005.

[0085] Based on this, during the test simulation, the read / write loop count is first set to 0, and the data from the first batch is used as the decoding input. Assuming the overall Flash error rate for this batch is 0.005, the corresponding distribution dataset is as follows: the probability of an absolute LLR value of 1 in the erroneous bits is 0.326, the probability of an absolute LLR value of 1 in the non-erroneous bits is 0.113, the probability of an absolute LLR value of 2 in the erroneous bits is 0.361, the probability of an absolute LLR value of 1 in the non-erroneous bits is 0.423, and so on. This is used as the input for multi-distribution co-simulation. In the multi-distribution co-simulation, random information bits k are first generated, and then LDPC encoding is used to obtain a valid codeword n. For each bit in n, it is flipped with a probability of 0.005, and the flipped bits are recorded. For flipped bits, their LLR is assigned values ​​of 1, 2, ... according to the probabilities of 0.326, 0.361, ... , and for non-flipped bits, their LLR is assigned values ​​of 1, 2, ... according to the probabilities of 0.113, 0.423, ... , respectively. The addition of noise was simulated using the above method, resulting in a noisy distribution dataset.

[0086] Therefore, the first set of decoding parameter combinations is set as { , The parameters are set as follows: Imax, Punc, Mode = {0.5, 0, 5, 0, soft decision}. Then, after parameterized LDPC decoding, error correction decoding is performed. The decoded information is compared with the correct information, resulting in FER = 0.001, which does not meet the preset performance constraints. Therefore, this parameter combination is removed from the initial parameter space. The second set of parameters is set as { , ,Imax,Punc,Mode}={0.6,0,5,0,soft decision},FER=0.0004, which meets the preset performance constraints, so this set of parameter combinations is retained as candidate parameter combinations. After all parameter combinations in the initial parameter space have been traversed, the input is changed to the data of the second batch, and the above steps are repeated. After N=90 batches have been traversed, the optimal parameter combination in the initial parameter space Para is assigned to PP[1], and then the read and write loop count is switched to 10k, and the above loop of 90 batches of data is repeated to obtain PP[2],..., in this way until PP[1]~PP

[10] are obtained, then the multi-distribution joint simulation is completed.

[0087] Finally, these 10 optimal parameter combinations PP[1]~PP

[10] are input into the integrated circuit design tool for design and tape-out, and stored in the dynamic lookup table in the flash memory error correction chip obtained after tape-out. The dynamic lookup table is generated based on the above 10 optimal parameter combinations.

[0088] For a given number of read / write cycles, the soft read information of all flash memory samples from a specified manufacturer and batch under that read / write cycle number is C1[r], C2[r], ..., C N [r](r=1~M), through multi-distribution co-simulation, all candidate parameter combinations that satisfy the preset performance constraints are obtained, and the optimal parameter combination is selected from them, denoted as PP[r]. The purpose of setting the judgment conditions for performance constraints is to ensure that error correction can be performed normally even in the worst case among all possible cases, and the purpose of selecting the optimal parameter combination is to minimize the hardware requirements.

[0089] according to Figure 3 The simulation test process shown involves obtaining the optimal parameter combination for all read / write cycles. The hardware design range is then determined based on the range of these M optimal parameter combinations, allowing the hardware to dynamically use different parameter combinations for error correction and decoding based on the different read / write cycles.

[0090] In this embodiment, during the process of obtaining the optimal parameter combination through multi-distributed joint simulation, the test scope covers the characteristics of flash memory from multiple manufacturers, multiple batches, and multiple lifespan points. The test data covers the diversity of the entire life cycle of flash memory, which solves the problem of poor adaptability caused by insufficient sample coverage of traditional solidified parameters and improves the universality of decoding parameters.

[0091] Furthermore, the multi-distribution co-simulation adopts a standardized simulation process of encoding, noise addition, decoding, and comparison. By quantitatively evaluating the performance indicators of the decoding parameter combinations, it ensures that the optimal parameter combination can meet the requirements of error correction reliability while also taking into account hardware efficiency, thereby improving the repeatability and feasibility of the simulation results. On this basis, a probability distribution mapping model is used to accurately simulate flash memory storage noise, restoring signal distortion under real reading scenarios, thus ensuring the effectiveness of the parameter combination in practical applications.

[0092] For the optimal parameter combination, a selection strategy based on performance constraints and parameter priorities is employed. While ensuring that the fixed parameters meet performance requirements, the optimal values ​​of parameters with a significant impact on flash memory hardware cost and power consumption are prioritized. This achieves an optimal balance between flash memory performance and hardware overhead, reducing the power consumption and latency of the flash memory firmware (or flash memory controller). Furthermore, by combining the flash memory's decoding mode, test data is processed differently, providing a standardized input for multi-distributed joint simulations. This facilitates adaptation to the differentiated testing needs of low-power and high-performance scenarios, enhancing the versatility and adaptability of simulation testing.

[0093] This application's embodiments achieve efficient error correction for flash memory controllers in multiple scenarios through multi-vendor / multi-batch / multi-lifetime point data coverage, standardized simulation processes, accurate noise modeling, and dynamic parameter switching mechanisms. This significantly improves versatility, reliability, and energy efficiency, and can adapt to the technical challenges of rapid iteration of flash memory processes and multiple application requirements.

[0094] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the flash memory decoding parameter determination method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0095] This application also provides a flash memory decoding parameter determination device, please refer to... Figure 4 The flash memory decoding parameter determination device includes: The first construction module 10 is used to construct a distribution dataset of the soft read information based on the soft read information of each flash memory sample under multiple read / write cycles; the flash memory samples include samples from multiple manufacturers and multiple batches; The second construction module 20 is used to construct an initial parameter space based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode; Simulation test module 30 is used to perform multi-distribution joint simulation on the flash memory sample within the initial parameter space using the distributed dataset, so as to obtain the optimal parameter combination of the flash memory sample under each read-write cycle number; The parameter fixing module 40 is used to determine the configurable parameter range of the flash sample firmware according to the optimal parameter combination and generate a dynamic lookup table; the dynamic lookup table is used to store the decoding parameter combination corresponding to each read and write cycle number, and when the firmware is configured with the dynamic lookup table, it dynamically switches the parameter value of the decoding parameter according to the actual read and write cycle number during use.

[0096] In one embodiment, the simulation testing module 30 is further configured to: The original bit information of the flash memory sample is randomly generated, and the original bit information is encoded based on the parity check matrix of the error correction code to generate a valid codeword; Noise is added to the legal codewords based on the distribution dataset to generate a noisy distribution dataset; In the noisy distributed dataset, the noisy distributed data of the flash memory samples under each read / write cycle number is used as the input of the decoding engine. The noisy distributed data is iteratively decoded by traversing each decoding parameter combination in the initial parameter space. During the decoding process, the verification node messages of the verification matrix are scaled and corrected according to the decoding parameter combination. The variable nodes of the verification matrix and the verification nodes are updated through a hierarchical scheduling mechanism until the preset iteration termination condition is met, and the decoding result is obtained. The decoding result is compared bit by bit with the original bit information to calculate the performance quantification index for each read / write cycle; the performance quantification index includes at least one of bit error rate and frame error rate; Based on the aforementioned performance quantification metrics, the optimal parameter combination is selected from the decoding parameter combinations for each read / write cycle.

[0097] In one embodiment, the simulation testing module 30 is further configured to: Based on the distribution data of each flash memory sample in the distributed dataset, a probability distribution mapping model for each flash memory sample is constructed; the probability distribution mapping model can simulate the data access noise of the flash memory sample. Using the probability distribution mapping model, noise is added to the legal codewords to generate a noisy distribution dataset.

[0098] In one embodiment, the simulation testing module 30 is further configured to: The performance quantification index is compared with the preset performance constraints, and candidate parameter combinations that satisfy the performance constraints are selected for each read / write cycle number. The candidate parameter combinations are filtered according to the priority strategy pre-configured for each decoding parameter to obtain the optimal parameter combination for each read / write cycle.

[0099] In one embodiment, the decoding mode includes hard decision and soft decision; the simulation test module 30 is further configured to: For the hard decision in the decoding mode, extract the symbol information of the noisy distribution data in the noisy distribution dataset and delete the assignment information to obtain the first noisy dataset; For the soft decision in the decoding mode, the symbol information of the noisy distribution data in the noisy distribution dataset is extracted and the assignment information is retained to obtain the second noisy dataset.

[0100] In one embodiment, the first building module 10 is further configured to: The soft read information of each flash memory sample under multiple read / write cycles is compared with the correct information, and the log-likelihood ratio of the soft read information under each read / write cycle is calculated. Based on the probability distribution of the log-likelihood ratio, a distribution dataset of the soft readout information is constructed.

[0101] The flash memory decoding parameter determination device provided in this application, employing the flash memory decoding parameter determination method in the above embodiments, can solve the technical problem that existing hardware-fixed decoding parameters lack systematic design and suffer from difficulties in balancing performance, efficiency, and versatility. Compared with the prior art, the beneficial effects of the flash memory decoding parameter determination device provided in this application are the same as those of the flash memory decoding parameter determination method provided in the above embodiments, and other technical features in the flash memory decoding parameter determination device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0102] This application provides a flash memory decoding parameter determination device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the flash memory decoding parameter determination method in the above embodiment 1.

[0103] The following is for reference. Figure 5This document illustrates a schematic diagram of a flash memory decoding parameter determination device suitable for implementing embodiments of this application. The flash memory decoding parameter determination device in this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The flash memory decoding parameter determination device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0104] like Figure 5 As shown, the flash memory decoding parameter determination device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the flash memory decoding parameter determination device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the flash memory decoding parameter determination device to communicate wirelessly or wiredly with other devices to exchange data. Although flash memory decoding parameter determination devices with various systems are shown in the figures, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0105] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0106] The flash memory decoding parameter determination device provided in this application, employing the flash memory decoding parameter determination method in the above embodiments, can solve the technical problem that existing hardware-fixed decoding parameters lack systematic design and suffer from difficulties in balancing performance, efficiency, and versatility. Compared with the prior art, the beneficial effects of the flash memory decoding parameter determination device provided in this application are the same as those of the flash memory decoding parameter determination method provided in the above embodiments, and other technical features in this flash memory decoding parameter determination device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0107] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0109] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the flash memory decoding parameter determination method in the above embodiments.

[0110] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0111] The aforementioned computer-readable storage medium may be included in the flash memory decoding parameter determination device; or it may exist independently and not be assembled into the flash memory decoding parameter determination device.

[0112] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the flash memory decoding parameter determining device, cause the flash memory decoding parameter determining device to: Based on the soft readout information of each flash memory sample under multiple read / write cycles, a distributed dataset of the soft readout information is constructed; the flash memory samples include samples from multiple manufacturers and multiple batches. An initial parameter space is constructed based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode; Using the distributed dataset within the initial parameter space, multi-distribution joint simulation is performed on the flash memory sample to obtain the optimal parameter combination for the flash memory sample in each read / write cycle. The configurable parameter range of the flash sample firmware is determined based on the optimal parameter combination, and a dynamic lookup table is generated. The dynamic lookup table is used to store the decoding parameter combination corresponding to each read / write cycle number. When the firmware is configured with the dynamic lookup table, the parameter value of the decoding parameter is dynamically switched according to the actual read / write cycle number during use.

[0113] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0114] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0115] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0116] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described flash memory decoding parameter determination method. This addresses the technical problem that existing hardware-fixed decoding parameters lack systematic design and suffer from difficulties in balancing performance, efficiency, and versatility. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the flash memory decoding parameter determination method provided in the above embodiments, and will not be elaborated upon here.

[0117] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the flash memory decoding parameter determination method described above.

[0118] The computer program product provided in this application can solve the technical problem that existing hardware-fixed decoding parameters lack systematic design and suffer from difficulty in balancing performance, efficiency, and versatility. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the flash memory decoding parameter determination method provided in the above embodiments, and will not be repeated here.

[0119] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for determining flash memory decoding parameters, characterized in that, The method for determining flash memory decoding parameters includes: Based on the soft readout information of each flash memory sample under multiple read / write cycles, a distributed dataset of the soft readout information is constructed; the flash memory samples include samples from multiple manufacturers and multiple batches. An initial parameter space is constructed based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode; Using the distributed dataset within the initial parameter space, multi-distribution joint simulation is performed on the flash memory sample to obtain the optimal parameter combination for the flash memory sample in each read / write cycle. The configurable parameter range of the flash sample firmware is determined based on the optimal parameter combination, and a dynamic lookup table is generated. The dynamic lookup table is used to store the decoding parameter combination corresponding to each read / write cycle number. When the firmware is configured with the dynamic lookup table, the parameter value of the decoding parameter is dynamically switched according to the actual read / write cycle number during use.

2. The flash memory decoding parameter determination method as described in claim 1, characterized in that, The step of using the distributed dataset to perform multi-distribution joint simulation on the flash memory samples within the initial parameter space to obtain the optimal parameter combination for the flash memory samples in each read / write cycle includes: The original bit information of the flash memory sample is randomly generated, and the original bit information is encoded based on the parity check matrix of the error correction code to generate a valid codeword; Noise is added to the legal codewords based on the distribution dataset to generate a noisy distribution dataset; In the noisy distributed dataset, the noisy distributed data of the flash memory samples under each read / write cycle number is used as the input of the decoding engine. The noisy distributed data is iteratively decoded by traversing each decoding parameter combination in the initial parameter space. During the decoding process, the verification node messages of the verification matrix are scaled and corrected according to the decoding parameter combination. The variable nodes of the verification matrix and the verification nodes are updated through a hierarchical scheduling mechanism until the preset iteration termination condition is met, and the decoding result is obtained. The decoding result is compared bit by bit with the original bit information to calculate the performance quantification index for each read / write cycle; the performance quantification index includes at least one of bit error rate and frame error rate; Based on the aforementioned performance quantification metrics, the optimal parameter combination is selected from the decoding parameter combinations for each read / write cycle.

3. The flash memory decoding parameter determination method as described in claim 2, characterized in that, The step of adding noise to the legal codewords based on the distribution dataset to generate a noisy distribution dataset includes: Based on the distribution data of each flash memory sample in the distributed dataset, a probability distribution mapping model for each flash memory sample is constructed; the probability distribution mapping model can simulate the data access noise of the flash memory sample. Using the probability distribution mapping model, noise is added to the legal codewords to generate a noisy distribution dataset.

4. The flash memory decoding parameter determination method as described in claim 2, characterized in that, The step of selecting the optimal parameter combination from the decoding parameter combinations for each read / write cycle based on the performance quantification index includes: The performance quantification index is compared with the preset performance constraints, and candidate parameter combinations that satisfy the performance constraints are selected for each read / write cycle number. The candidate parameter combinations are filtered according to the priority strategy pre-configured for each decoding parameter to obtain the optimal parameter combination for each read / write cycle.

5. The flash memory decoding parameter determination method as described in claim 2, characterized in that, The decoding modes include hard decision and soft decision; after the step of adding noise to the legal codewords according to the distribution dataset to generate a noisy distribution dataset, the method further includes: For the hard decision in the decoding mode, extract the symbol information of the noisy distribution data in the noisy distribution dataset and delete the assignment information to obtain the first noisy dataset; For the soft decision in the decoding mode, the symbol information of the noisy distribution data in the noisy distribution dataset is extracted and the assignment information is retained to obtain the second noisy dataset.

6. The flash memory decoding parameter determination method as described in claim 1, characterized in that, The step of constructing a distributed dataset of soft read information based on the soft read information of each flash memory sample under multiple read / write cycles includes: The soft read information of each flash memory sample under multiple read / write cycles is compared with the correct information, and the log-likelihood ratio of the soft read information under each read / write cycle is calculated. Based on the probability distribution of the log-likelihood ratio, a distribution dataset of the soft readout information is constructed.

7. A flash memory decoding parameter determination device, characterized in that, The flash memory decoding parameter determination device includes: The first construction module is used to construct a distributed dataset of the soft read information based on the soft read information of each flash memory sample under multiple read / write cycles; the flash memory samples include samples from multiple manufacturers and multiple batches; The second construction module is used to construct an initial parameter space based on the value range of each decoding parameter; the decoding parameters include at least one of the following: normalization factor, bias parameter, maximum number of iterations, number of punctures, and decoding mode; The simulation test module is used to perform multi-distribution joint simulation of the flash memory sample within the initial parameter space using the distributed dataset, so as to obtain the optimal parameter combination of the flash memory sample under each read-write cycle number. The parameter fixing module is used to determine the configurable parameter range of the flash sample firmware according to the optimal parameter combination and generate a dynamic lookup table. The dynamic lookup table is used to store the decoding parameter combination corresponding to each read / write cycle count. When the firmware is configured with the dynamic lookup table, it dynamically switches the parameter value of the decoding parameter according to the actual read / write cycle count during use.

8. A flash memory decoding parameter determination device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the flash memory decoding parameter determination method as described in any one of claims 1 to 6.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the flash memory decoding parameter determination method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the flash memory decoding parameter determination method as described in any one of claims 1 to 6.

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