A server hard disk backplane hot plug automation test method and system

Abstract

The application discloses a kind of server hard disk backboard hot plug automation test method and system, it is related to server storage equipment reliability test technical field;The application is by being set between server mainboard and the hard disk backboard to be tested hot plug switching device, completes initialization configuration and test environment readiness confirmation, executes standardization safe hot plug access and removal control, maintains server mainboard side equipment in-place simulation state in whole process, is passively monitored native communication in high resistance state bypass mode and does not intervene bus interaction, realizes whole protection using electrical and physical dual redundancy safety mechanism, synchronously collects backboard side electrical parameter, completes abnormality judgment, system verification and batch test statistics and automatically generates test report.The application does not need to modify server native hardware and firmware, can avoid mainboard abnormal alarm and hardware damage risk, realizes test full-process automation control, improves test security, efficiency and result reliability.

Description

Technical Field

[0001] This invention relates to the field of server storage device reliability testing technology, specifically to an automated testing method and system for hot-swapping server hard drive backplanes. Background Technology

[0002] With the continuous development of cloud computing, big data, and high-performance computing industries, enterprise-level data centers have placed stringent technical requirements on the high availability and online maintainability of server systems. The server hard drive backplane is a core hub component in server storage systems, connecting the server motherboard and the storage hard drives. It undertakes core functions such as power distribution, high-speed data exchange, and device status management. The stability, reliability, and security of its hot-swappable function are fundamental to ensuring online maintenance of data center storage systems, uninterrupted replacement of faulty hard drives, and continuous business operation.

[0003] Throughout the entire server lifecycle, from R&D verification and mass production quality inspection to warehousing acceptance and maintenance testing, hot-swappable performance testing of hard drive backplanes is a core mandatory test item. This test must meet the general technical requirements of the server storage industry, with clear quantitative indicators for compliance of insertion and removal timing, accuracy of electrical parameter acquisition, security protection capabilities during the testing process, and consistency and reproducibility of test results.

[0004] Currently, the industry mainly uses two mainstream technical solutions for hot-swappable performance testing of server hard drive backplanes: The first is the commonly used manual testing solution, in which operators manually complete the entire process of backplane insertion / removal, power-on, functional verification, and power-off removal, with basic continuity testing completed using simple power-on fixtures; the second is a semi-automated testing solution for specific scenarios, which uses customized fixtures to control the timing of power on / off, and combines manual verification with the testing process.

[0005] However, both existing testing solutions have unresolved core technical defects that fail to meet the industry's core technical requirements for hard drive backplane hot-swap testing.

[0006] Manual testing methods have inherent technical limitations: the timing of manual plugging and unplugging operations is highly discrete, making it impossible to consistently follow the standard timing requirements for server hot-plugging operations. This can easily lead to problems such as excessive power-on inrush current, abnormal bus communication, and triggering of motherboard protection mechanisms. Manual operation cannot achieve synchronous, high-resolution real-time acquisition of electrical parameters during the hot-plugging transient process, and cannot fully capture key transient data such as voltage fluctuations and inrush currents at the moment of power-on and power-off. The test results can only achieve qualitative judgment of continuity and disconnection, and cannot complete a precise quantitative evaluation of the backplane hot-plugging performance. At the same time, manual operation lacks a systematic safety protection mechanism, and is prone to permanent hardware damage to the server motherboard, backplane under test, and storage hard drive due to incorrect cable insertion, incorrect insertion and unplugging sequence, or misoperation, posing serious technical safety hazards.

[0007] For semi-automated testing solutions, they have failed to overcome the core technical bottlenecks in the industry: most existing solutions require modification of the server motherboard's native Baseboard Management Controller (BMC) and Basic Input / Output System (BIOS) firmware, or intervention in the native communication bus between the motherboard and the backplane, resulting in a fundamental difference between the test environment and the actual operating environment of the server, severely distorting test results, and easily triggering server motherboard BMC alarms, system crashes, and protection mechanisms, causing unexpected interruptions to the test process; existing solutions only use a single electrical-level soft protection mechanism, lacking a dual-redundant safety design that combines physical-level passive protection and electrical-level active protection, and cannot cope with extreme scenarios such as accidental backplane detachment, loose link connections, and human error, and cannot fundamentally avoid the risk of hardware short circuit damage caused by hot-plugging; at the same time, existing solutions have failed to achieve closed-loop automated control of the entire testing process, still requiring a large amount of manual intervention, and the consistency, reproducibility, and testing efficiency of batch testing cannot meet the technical requirements of server mass production quality inspection.

[0008] In summary, existing technologies cannot achieve standardized, automated, and highly secure testing of the entire hot-swappable process of server hard drive backplanes through a dual-redundancy security protection mechanism without modifying the server's native hardware and firmware, interfering with the normal operation of the motherboard, or changing the server's native operating environment. At the same time, they cannot simultaneously ensure hardware security protection during the testing process and accurate quantitative evaluation of test results, which has become the core bottleneck restricting the development of server hard drive backplane hot-swappable performance testing technology.

[0009] Therefore, there is an urgent need in this field for an automated testing solution for hot-swapping of server hard drive backplanes that can solve the aforementioned core technical problems. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings of the prior art and provide an automated testing method for hot-swapping server hard drive backplanes, comprising the following steps: S1: Initialize and configure the logic control module of the hot-swappable adapter, and generate an initialization completion signal; S2: Receive the S0 status ready signal from the server motherboard, establish a communication connection with the server motherboard, and generate an environment ready signal after confirming that the test environment is ready. S3: Based on the initialization completion signal and the environment ready signal, the hot-swap adapter is controlled to perform safe hot-swap access control of the backplane of the hard drive under test. During the entire hot-swap process, electrical parameter data on the backplane side is collected in real time, while maintaining the device in-situ simulation state on the server motherboard side to ensure that there are no abnormal alarms on the server motherboard. The safe hot-swap access control uses the access timing control process as the standardized execution logic, and adopts a dual redundancy safety mechanism to achieve full-process safety protection. The dual redundancy safety mechanism includes active protection at the electrical level and passive protection at the physical level.

[0011] S4: Compare the collected electrical parameter data with the preset electrical safety thresholds item by item and make anomaly judgments to generate anomaly judgment results; when the anomaly judgment result indicates that the access operation is successful, send a system verification command to the server motherboard, receive and process the verification data returned by the server, and generate system verification results. S5: Based on the anomaly judgment results, system verification results, and preset test batch information, count the number of successful tests and anomalies for a single backplane, and generate a single backplane test sub-report; after the single backplane test is completed, control the hot-swap adapter to perform the safe removal control of the backplane under test, generate a replaceable prompt signal, and repeat steps S3-S4 until all batches of hard disk backplanes under test are tested, and generate a complete batch test report.

[0012] Preferably, in step S3, the specific steps of using the access timing control flow as the standardized execution logic include: S3.1: Receive a backplane insertion valid signal sent by the hot-swap adapter. The backplane insertion valid signal is generated by the hot-swap adapter after detecting the physical insertion of the backplane through the backplane-side in-place detection pin and the grounding pin is reliably connected. S3.2: Based on the backplane insertion valid signal, control the hot-swap adapter to adopt the same resistor pull-down method as the original hard drive backplane of the server under test, and simulate output a valid "backplane in place" signal to the server motherboard side. S3.3: Control the hot-swap adapter to be connected in parallel to the I2C / SGPIO communication bus on the backplane side in a high-impedance bypass mode, passively listen to the communication data sent by the server motherboard to the backplane side, and generate a power-on control signal after parsing the "Power-on enabled" command. S3.4: Based on the power-on control signal, control the power switch module of the hot-swappable adapter to turn on all power supply paths in a soft-start mode. During the power supply turn-on process, receive the voltage change data and current change data of the backplane side power input terminal uploaded by the hot-swappable adapter. S3.5: Receive the access operation completion signal sent by the hot-swappable adapter, and integrate the voltage change data and current change data into the electrical parameter data.

[0013] Preferably, in step S3, the electrical layer active protection is a power pre-shutdown safety control based on communication interruption, and its specific steps include: S3.6: The logic control module for controlling the hot-swappable adapter monitors the level status of the I2C / SGPIO communication bus on the backplane side in real time, sets a preset anti-jitter detection window, and continuously judges whether the bus is in a normal communication state. S3.7: When a communication interruption event signal is received from the logic control module, an emergency shutdown signal is generated. The communication interruption event signal is generated by the logic control module after detecting that the backplane-side communication bus level is continuously in a high-impedance state and exceeds the anti-jitter detection window. S3.8: Based on the emergency shutdown signal, control the power switch module of the hot-swap adapter to completely shut off all power paths from the server motherboard to the backplane of the hard drive under test within a preset response time. S3.9: Control the hot-swappable adapter to illuminate the safety status indicator light, and at the same time generate a communication interruption alarm message and record the time of the interruption and bus status data.

[0014] Preferably, in step S3, the physical layer passive protection is achieved through the stepped connector layout of the hot-swappable adapter and the non-standard foolproof design of the cable assembly, the specific steps of which include: S3.10: The backplane connector of the hot-swappable adapter adopts a three-level stepped layout. The first level is a power connector, the second level is a high-speed data connector, and the third level is a low-speed signal connector. Adjacent connectors have a preset installation height difference, and the installation height decreases sequentially from the third level to the first level. S3.11: The plugs of power cables, high-speed data cables and low-speed signal cables adopt different shapes of non-foolproof design, which are matched with the corresponding level of connectors and cannot be inserted into connectors of other levels. S3.12: When the power cable is not fully inserted into the first-level connector, the protruding part of its plug will physically block the insertion path of the second-level and third-level connectors; when the low-speed signal cable is not fully unplugged, its plug will physically block the unplugging path of the high-speed data cable and power cable.

[0015] Preferably, in step S3.3, the specific steps for passively monitoring the communication data sent by the server motherboard to the backplane side include: S3.3.1: The logic control module that controls the hot-swappable adapter configures its input pins to a high-impedance state and connects them in parallel to the SCL and SDA signal lines of the I2C bus on the backplane side, as well as the clock line, data line, and load line of the SGPIO bus. S3.3.2: The control logic control module synchronizes the SCL clock signal of the I2C bus, parses the address frame and data frame transmitted on the bus bit by bit, and extracts the communication data packet whose target address is the backplane address of the hard disk under test; S3.3.3: The control logic control module identifies a specific register write instruction representing "the motherboard allows the backplane to power on" from the parsed communication data packet. When the same power-on instruction is detected twice in a row, the instruction is confirmed to be valid and the power-on control signal is generated. S3.3.4: Throughout the entire monitoring process, the control logic module does not send any response signals to the bus, does not modify any data on the bus, and does not intervene in any communication process.

[0016] Preferably, in step S3.4, the specific steps for receiving the voltage change data and current change data of the backplane-side power input terminal uploaded by the hot-swappable adapter include: S3.4.1: During the initial stage of the soft-start operation of the power switch module, the change data of the 12V main power supply current value on the backplane side is collected at the first preset sampling frequency, and the peak value and duration of the power-on inrush current are recorded. S3.4.2: During the stable power supply phase after the power switch module is fully turned on, the voltage and current values ​​of the 12V main power supply, 5V main power supply and standby auxiliary power supply on the backplane side are collected at the second preset sampling frequency. S3.4.3: When a voltage fluctuation exceeds a preset voltage fluctuation threshold or a current change exceeds a preset current change threshold, the high-resolution electrical parameter change data is automatically collected at the third preset sampling frequency. S3.4.4: Integrate the soft-start phase data, stable power supply phase data, and high-resolution mutation data to generate the voltage change data and current change data.

[0017] Preferably, in step S4, the specific steps for comparing the collected electrical parameter data with preset electrical safety thresholds and performing anomaly judgment to generate anomaly judgment results include: S4.1: Extract the peak value of the power-on inrush current, the stable voltage value, the stable current value, and the voltage and current change data from the electrical parameter data; S4.2: Compare the peak value of the power-on inrush current with the preset inrush current threshold. When the peak value exceeds the threshold, generate an inrush current anomaly indicator and record the time and specific value of the anomaly. S4.3: Compare the stable voltage value with the preset normal voltage range. When the stable voltage value exceeds the normal range, generate a voltage anomaly flag and record the time and specific value of the anomaly. S4.4: Compare the stable current value with the preset normal current range. When the stable current value exceeds the normal range, generate a current anomaly flag and record the time and specific value of the anomaly. S4.5: If any exception flag exists, the access operation is determined to be abnormal, and an operation exception result is generated; if no exception flag exists, the access operation is determined to be successful, and an operation success result is generated.

[0018] Preferably, in step S4, the specific steps of sending a system verification command to the server motherboard, receiving and processing the verification data returned by the server, and generating a system verification result include: S4.6: Based on the successful operation result, send a system verification command to the server motherboard; S4.7: Receive storage device list data returned by the server motherboard, verify whether the backplane of the hard drive under test and each connected hard drive are correctly identified, and generate device identification status data; S4.8: Receive hard drive read / write performance test data returned by the server motherboard, obtain the hard drive's sequential read / write speed, random read / write speed, and IOPS data, and generate hardware performance data; S4.9: Receive BMC system log and hard disk backplane status register data returned by the server motherboard, verify whether there are communication errors, power supply errors or hardware alarm information, and generate system status data; S4.10: Integrate the device identification status data, hardware performance data, and system status data to generate a system verification result; when the system verification result is passed, execute the subsequent automated test script; when the system verification result is failed, record the error information and trigger the power-off operation.

[0019] Preferably, in step S5, the specific steps for controlling the hot-swappable adapter to perform the safe removal control of the backplane of the hard drive under test include: S5.1: Receive the single backplane test completion signal and generate a backplane removal command and a power pre-shutdown signal; S5.2: Based on the power pre-shutdown signal, control the power switch module of the hot-swappable adapter to shut down all power supply paths in a soft shutdown manner; S5.3: After receiving the power-off signal from the power switch module, continue to maintain the device in-place simulation state on the server motherboard side until the backplane physical removal completion signal from the hot-swap adapter is received. S5.4: Based on the signal indicating that the physical removal of the backplate is complete, generate a replacement prompt signal.

[0020] In addition, to achieve the above objectives, the present invention also proposes an automated testing system for hot-swapping server hard disk backplanes, used to implement the aforementioned automated testing method for hot-swapping server hard disk backplanes, including a test control host, a hot-swapping adapter, and a server motherboard that is communicatively connected to the test control host and the hot-swapping adapter respectively. The test control host is used to send control commands to the hot-swappable adapter and receive returned data. The hot-swappable adapter is located between the server motherboard and the backplane of the hard drive under test, and includes a logic control module, a power switch module, an electrical parameter acquisition module, and an in-situ simulation module. The logic control module is communicatively connected to the test control host, power switch module, electrical parameter acquisition module and in-situ simulation module, respectively. It is used to receive control commands from the test control host and configure the communication bus pins to a high impedance state to passively listen to the native communication between the server motherboard and the backplane of the hard drive under test, without intervening in the bus interaction. The power switch module is connected in series between the power link of the server motherboard and the backplane of the hard drive under test. It is used to perform soft start conduction, soft shutdown and emergency shutdown based on communication interruption detection of the power link according to the instructions of the logic control module. Together with the stepped connector structure and the non-standard foolproof structure of the hot-swappable adapter, it forms a double redundancy safety protection. The sampling terminal of the electrical parameter acquisition module is connected in parallel to the power input pin of the backplane of the hard drive under test. It is used to collect the voltage, current and ripple parameters of the backplane side in real time according to the electrical characteristics of different hot-plug stages using a multi-level adjustable sampling frequency and upload them to the logic control module. The output of the in-situ simulation module is connected to the hard drive in-situ detection pin of the server motherboard, and is used to continuously output a stable in-situ detection signal that is equivalent to the original hard drive backplane to the server motherboard during the entire hot-plugging process of the hard drive backplane being connected, running and being removed.

[0021] The beneficial effects of this invention are: 1. An independent hot-swap adapter is added between the server motherboard and the backplane of the hard drive under test, and the device on the server motherboard is kept in place throughout the hot-swap process to simulate its presence. This solves the problems in the prior art where hot-swap testing relies on manual operation, requires modification of the server motherboard's native hardware or firmware, and the motherboard is prone to misjudging the device's presence during the physical insertion and removal of the backplane, triggering abnormal alarms or even crashing, which leads to test interruption and poor versatility. This invention achieves universal testing without modifying the server's native hardware and interfaces, effectively avoids alarms and crashes caused by sudden changes in the device's state, improves the continuity and stability of batch testing, and reduces manual operation costs and risks.

[0022] 2. By configuring the communication bus pins to a high-impedance passive listening state for native communication through the logic control module, without intervening in bus interaction, and in conjunction with standardized safe hot-swappable access timing control, this solves the problems of existing test devices actively intervening in bus communication, forwarding or modifying bus data, resulting in distorted test environment, test results that fail to reflect the true working state of the backplane, and hardware damage caused by disordered access timing. It preserves the native communication environment between the server motherboard and the backplane of the hard drive under test, improving the authenticity and accuracy of test results. At the same time, through standardized access timing control, it achieves orderly and controllable power-on process of the backplane, effectively avoiding the risk of hardware damage caused by disordered access.

[0023] 3. Combining a dual-redundancy safety mechanism of active electrical protection and passive physical protection, real-time acquisition of backplane electrical parameters is achieved simultaneously throughout the entire hot-swap process. This addresses the shortcomings of traditional hot-swap testing, which offers only single-layer safety protection, covers only routine operating scenarios, struggles to handle extreme incidents such as accidental backplane detachment or loose connections, and lacks comprehensive electrical data support, making it difficult to trace the cause of anomalies. A multi-layered safety protection system is constructed, from physical operating specifications to electrical emergency backup, effectively reducing the probability of hardware damage during testing. Simultaneously, the acquisition of electrical parameters throughout the process provides quantitative data for test anomaly analysis and backplane quality assessment, further enhancing the reliability and traceability of test results. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating the steps of an automated testing method for hot-swapping of a server hard drive backplane according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating the timing control process for secure hot-plugging access as described in an embodiment of the present invention. Figure 3 This is a block diagram of the dual redundancy security protection mechanism for automated testing of server hard drive backplane hot-swapping according to an embodiment of the present invention; Figure 4 This is a system architecture diagram of an automated testing system for hot-swappable server hard drive backplanes according to an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described content is only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of this application.

[0026] The features and effects of the present invention will be further described in detail below with reference to the embodiments.

[0027] like Figure 1 As shown, this invention provides an automated testing method for hot-swapping server hard drive backplanes, comprising the following steps: S1: Initialize and configure the logic control module of the hot-swappable adapter, and generate an initialization completion signal; S2: Receive the S0 status ready signal from the server motherboard, establish a communication connection with the server motherboard, and generate an environment ready signal after confirming that the test environment is ready. S3: Based on the initialization completion signal and the environment ready signal, the hot-swap adapter is controlled to perform safe hot-swap access control of the backplane of the hard drive under test. During the entire hot-swap process, electrical parameter data on the backplane side is collected in real time, while maintaining the device in-situ simulation state on the server motherboard side to ensure that there are no abnormal alarms on the server motherboard. The safe hot-swap access control uses the access timing control process as the standardized execution logic, and adopts a dual redundancy safety mechanism to achieve full-process safety protection. The dual redundancy safety mechanism includes active protection at the electrical level and passive protection at the physical level.

[0028] S4: Compare the collected electrical parameter data with the preset electrical safety thresholds item by item and make anomaly judgments to generate anomaly judgment results; when the anomaly judgment result indicates that the access operation is successful, send a system verification command to the server motherboard, receive and process the verification data returned by the server, and generate system verification results. S5: Based on the anomaly judgment results, system verification results, and preset test batch information, count the number of successful tests and anomalies for a single backplane, and generate a single backplane test sub-report; after the single backplane test is completed, control the hot-swap adapter to perform the safe removal control of the backplane under test, generate a replaceable prompt signal, and repeat steps S3-S4 until all batches of hard disk backplanes under test are tested, and generate a complete batch test report.

[0029] In this embodiment, the hot-swappable adapter refers to an independent hardware unit located between the server motherboard and the backplane of the hard drive under test, which realizes controllable transfer of power and communication links, acquisition of electrical parameters, and simulation of in-situ status. It is the hardware execution carrier of the control instructions of this method, and does not modify the original hardware and interface definition of the server motherboard throughout the process. The core items of the initialization configuration include serial communication parameters, sampling frequency calibration, electrical safety threshold writing, power soft start / soft shutdown parameter configuration, bus monitoring mode configuration, and IO pin input / output status configuration. The maximum number of retry attempts during the initialization process is 3. An initialization completion signal is generated only after all configuration items have been verified. Otherwise, an initialization failure alarm is generated and the process is terminated. The S0 state ready signal of the server motherboard is obtained by the test control host sending a status query command to the motherboard BMC through the IPMI protocol. Only when the BMC returns the system running status as S0 normal working status, no hardware alarms, and hard disk backplane interface enable is completed, is it determined that the S0 state is ready, a communication connection is established and an environment ready signal is generated. The device in-situ simulation state refers to a stable state in which the device continuously outputs an in-situ detection signal that is completely consistent with the original hard drive backplane to the server motherboard, regardless of whether the backplane under test is physically connected, powered on, or physically removed. The in-situ simulation is started immediately after the logic control module generates the initialization completion signal, and it is terminated automatically after receiving the backplane physical removal completion signal or after the backplane removal timeout of 30 seconds. Electrical safety thresholds refer to a pre-configured set of quantitative indicators used to determine whether the electrical status of the backplane of the hard drive under test is compliant during hot-swapping. The adaptation rules for electrical safety thresholds are as follows: the inrush current threshold and the normal range of stable current are configured at 120% of the rated maximum operating current of the backplane under test, and the voltage threshold is configured according to the industry-standard tolerance range of the corresponding rated voltage. Test batch information refers to the pre-configured core configuration parameters for batch testing, such as the number of test cycles for a single backplane, the total number of backplanes under test, and the test items. A single test cycle for a single backplane ends when a single system verification result is generated. If a single backplane experiences three consecutive access failures or fails system verification, the test for that backplane will be terminated. The test trigger condition for the next backplane is the signal indicating that the previous backplane has been physically removed. The individual backplane test sub-report includes test time, backplane number, number of test cycles, number of successes, number of anomalies, anomaly type, anomaly occurrence time, electrical parameter curves, and system verification results; the batch test master report includes test result statistics, pass rate analysis, and anomaly distribution for all individual backplanes.

[0030] The preset electrical safety thresholds are set as follows: 12V main power supply inrush current threshold ≤30A, normal stable voltage range 12V±5%, normal stable current range ≤25A; 5V main power supply normal stable voltage range 5V±5%, normal stable current range ≤8A; 3.3V standby power supply normal stable voltage range 3.3V±5%, normal stable current range ≤5A; voltage fluctuation threshold is ±10% of rated voltage, current surge threshold is 50% of rated current, which can be finely adjusted according to the rated parameters of the backplane under test; This embodiment solves the technical problems of traditional hot-swap testing, such as reliance on manual operation, low testing efficiency, inaccurate electrical parameter acquisition, and easy abnormal alarms on server motherboards, by introducing an independent hot-swap adapter as the control and data acquisition carrier and combining it with the fully automated control logic of "initial configuration - environment readiness - secure access - parameter comparison - system verification - batch statistics". By continuously maintaining the simulated state in place, the drawbacks of motherboard misjudgment and triggering protection mechanisms during hot-swap are avoided. At the same time, by preset differentiated electrical safety thresholds and supporting flexible fine-tuning, it adapts to the testing needs of different specifications of hard drive backplanes. The entire process does not modify the original hardware and interfaces of the server motherboard, ensuring the universality and safety of the test. It realizes automated and standardized testing of hard drive backplane hot-swap, improves testing efficiency and accuracy, and reduces the safety risks and human errors caused by manual operation.

[0031] like Figure 2 As shown, in one feasible implementation, step S3, which uses the access timing control flow as the standardized execution logic, includes the following specific steps: S3.1: Receive a backplane insertion valid signal sent by the hot-swap adapter. The backplane insertion valid signal is generated by the hot-swap adapter after detecting the physical insertion of the backplane through the backplane-side in-place detection pin and the grounding pin is reliably connected. S3.2: Based on the backplane insertion valid signal, control the hot-swap adapter to adopt the same resistor pull-down method as the original hard drive backplane of the server under test, and simulate output a valid "backplane in place" signal to the server motherboard side. S3.3: Control the hot-swap adapter to be connected in parallel to the I2C / SGPIO communication bus on the backplane in a high-impedance bypass mode, passively listen to the communication data sent from the server motherboard to the backplane, and generate a power-on control signal after parsing the "Power-on enabled" command. S3.4: Based on the power-on control signal, control the power switch module of the hot-swappable adapter to turn on all power supply paths in a soft-start mode. During the power supply turn-on process, receive the voltage change data and current change data of the backplane side power input terminal uploaded by the hot-swappable adapter. S3.5: Receive the access operation completion signal sent by the hot-swappable adapter, and integrate the voltage change data and current change data into the electrical parameter data.

[0032] Specifically, in step S3.3, the steps for passively monitoring the communication data sent from the server motherboard to the backplane include: S3.3.1: The logic control module that controls the hot-swappable adapter configures its input pins to a high-impedance state and connects them in parallel to the SCL and SDA signal lines of the I2C bus on the backplane side, as well as the clock line, data line, and load line of the SGPIO bus. S3.3.2: The control logic control module synchronizes the SCL clock signal of the I2C bus, parses the address frame and data frame transmitted on the bus bit by bit, and extracts the communication data packet whose target address is the backplane address of the hard disk under test; S3.3.3: The control logic control module identifies a specific register write instruction representing "the motherboard allows the backplane to power on" from the parsed communication data packet. When the same power-on instruction is detected twice in a row, the instruction is confirmed to be valid and the power-on control signal is generated. S3.3.4: Throughout the entire monitoring process, the control logic module does not send any response signals to the bus, does not modify any data on the bus, and does not intervene in any communication process.

[0033] Specifically, step S3.4, which involves receiving the voltage and current change data from the backplane-side power input terminal uploaded by the hot-swappable adapter, includes the following steps: S3.4.1: During the initial stage of the soft-start operation of the power switch module, the change data of the 12V main power supply current value on the backplane side is collected at the first preset sampling frequency, and the peak value and duration of the power-on inrush current are recorded. S3.4.2: During the stable power supply phase after the power switch module is fully turned on, the voltage and current values ​​of the 12V main power supply, 5V main power supply and standby auxiliary power supply on the backplane side are collected at the second preset sampling frequency. S3.4.3: When a voltage fluctuation exceeds a preset voltage fluctuation threshold or a current change exceeds a preset current change threshold, the high-resolution electrical parameter change data is automatically collected at the third preset sampling frequency. S3.4.4: Integrate the soft-start phase data, stable power supply phase data, and high-resolution mutation data to generate the voltage change data and current change data.

[0034] In this embodiment, the specific register write instruction representing "the motherboard allows the backplane to power on" follows the IPMI 2.0 and SAS 3.0 general specifications, and the target is the 0x01 write instruction of the backplane 0x03 power-on control register; the detection interval between two consecutive valid instructions is set to 10ms for example. Only when the two detected register addresses and write values ​​are completely consistent is it determined to be a valid power-on instruction, so as to avoid false triggering caused by bus interference. If an STM32 series microcontroller is used to implement the bus monitoring function, the I2C / SGPIO pins need to be configured as ordinary GPIO input mode. The bus timing is simulated by software for monitoring. Hardware I2C slave mode is prohibited to avoid automatic sending of response signals interfering with the native communication between the motherboard and the backplane.

[0035] The backplane insertion valid signal refers to the valid trigger signal generated by the hot-swap adapter after detecting the physical insertion of the backplane and the reliable conduction of the grounding pin through the backplane side presence detection pin. The criterion for reliable conduction of the grounding pin is that the impedance between the grounding pin and the system ground is continuously lower than 10Ω. The anti-jitter detection window is set to 5ms. Only when the conduction state continues for more than the anti-jitter window will a valid backplane insertion signal be generated. The high-impedance bypass mode refers to the logic control module's bus monitoring pin being configured with a high input impedance state, connected only in parallel to the communication bus for signal monitoring, without affecting the bus level in any way or forming an electrical interaction with the bus; the connection to the backplane-side I2C / SGPIO communication bus specifically means that the logic control module's monitoring pin is connected in parallel to the midpoint of the I2C / SGPIO link between the hot-swappable adapter's motherboard-side connector and the backplane-side connector, ensuring that all native communication data sent from the server motherboard to the backplane under test can be completely monitored; Soft-start refers to a power-on method that gradually increases the MOSFET gate voltage and slowly increases the power supply path conduction current to suppress the instantaneous inrush current during power-on. The example soft-start time is configured as 124ms. The 12V, 5V, and 3.3V power supply branches adopt synchronous soft-start logic. If the inrush current exceeds the overcurrent protection threshold during the soft-start process, the soft-start is immediately terminated and all power supply paths are turned off. The first preset sampling frequency, the second preset sampling frequency, and the third preset sampling frequency are differentiated sampling frequencies configured for the electrical characteristics of different stages of hot-plugging, respectively adapting to the accuracy requirements of inrush current acquisition, normal steady-state acquisition, and abnormal change acquisition. The switching of sampling frequency is automatically triggered by the logic control module according to the operating status of the power switch module, without the need for intervention from the test control host. For example, it is set as follows: a first sampling frequency of 500kHz for inrush current acquisition in the initial stage of soft start, a second sampling frequency of 10kHz for normal data acquisition in the stable power supply stage, and a third sampling frequency of 1MHz for high-resolution acquisition in abnormal change scenarios. It can be adjusted according to the test accuracy requirements.

[0036] The trigger intervals for the three sampling frequencies are set as follows: the first sampling frequency trigger interval is from the soft-start enable signal being sent until the power supply voltage stabilizes at ±5% of the rated value for 10ms; the second sampling frequency trigger interval is the continuous operation phase when the power supply is in a steady state without any abnormalities; the third sampling frequency trigger interval is from the parameter exceeding the threshold until 50ms after the abnormal state disappears. After the trigger interval ends, the frequency automatically switches back to the second sampling frequency. The switching of the sampling frequency is triggered by a hardware interrupt of the logic control module and is not affected by software task scheduling, ensuring the integrity of the data collection for abnormal changes.

[0037] The connection operation completion signal is generated by the logic control module after detecting that the voltage of all power supply branches is stable within ±5% of the rated value for more than 20ms and there are no abnormal electrical parameters. This indicates that the electrical process of this hot-swap connection has been completed.

[0038] This embodiment solves the technical problems of traditional hot-swappable access timing, such as chaotic timing, interference with motherboard communication due to bus monitoring, excessive power-on inrush current, and insufficient accuracy of electrical parameter acquisition, by designing a standardized access timing control process and combining three core technologies: high-impedance bypass monitoring, soft-start power supply, and differentiated frequency sampling. The high-impedance bypass method ensures that the monitoring process does not affect the normal communication between the motherboard and the backplane, and the double command verification mechanism improves the accuracy of power-on command recognition and avoids false triggering. The soft-start method effectively suppresses power-on inrush current and protects the hardware safety of the backplane and motherboard. The differentiated sampling frequency adapts to the electrical characteristics of different stages of hot-swapping, ensuring high-resolution acquisition of inrush current and abnormal change data while avoiding redundant data from conventional steady-state acquisition, thus improving the efficiency and accuracy of data acquisition.

[0039] In one feasible implementation, in step S3, the electrical layer active protection is a power pre-shutdown safety control based on communication interruption, the specific steps of which include: S3.6: The logic control module for controlling the hot-swappable adapter monitors the level status of the I2C / SGPIO communication bus on the backplane side in real time, sets a preset anti-jitter detection window, and continuously judges whether the bus is in a normal communication state. S3.7: When a communication interruption event signal is received from the logic control module, an emergency shutdown signal is generated. The communication interruption event signal is generated by the logic control module after detecting that the backplane-side communication bus level is continuously in a high-impedance state and exceeds the anti-jitter detection window. S3.8: Based on the emergency shutdown signal, control the power switch module of the hot-swap adapter to completely shut off all power paths from the server motherboard to the backplane of the hard drive under test within a preset response time. S3.9: Control the hot-swappable adapter to illuminate the safety status indicator light, and at the same time generate a communication interruption alarm message and record the time of the interruption and bus status data.

[0040] In this embodiment, the anti-jitter detection window refers to a fixed-duration detection interval used to filter out instantaneous jitter interference of the bus level and determine whether the bus is in a communication interruption state, exemplarily set to 20ms; the normal communication state refers to the existence of bus clock transitions and data interactions conforming to the I2C / SGPIO protocol specifications within the detection window; the communication interruption event signal refers to the trigger signal generated by the logic control module after detecting that the I2C and SGPIO dual bus pins on the backplane side between the adapter and the backplane under test have both become high impedance, the pull-up resistors on the motherboard side clamp the corresponding bus level to a high level continuously, there is no communication activity conforming to the protocol specifications, and the duration of this state exceeds the anti-jitter detection window, indicating that the communication link between the backplane and the motherboard is physically disconnected; a valid communication interruption event signal is only generated when both the I2C and SGPIO buses simultaneously meet the above interruption determination conditions, avoiding false shutdowns caused by temporary idleness of a single bus.

[0041] This embodiment adopts an electrical-level active protection architecture of "real-time bus level monitoring - anti-jitter window anomaly judgment - microsecond-level hardware emergency shutdown - alarm information synchronous recording" and combines it with a hardware-level independently triggered execution mechanism. This solves the core technical problems of traditional hot-swap testing, such as lack of real-time hardware-level protection, slow anomaly response, and easy hardware short circuit burnout. It can cut off all power supply paths instantly in the event of accidental backplane detachment or manual unplugging, completely avoiding the safety risks caused by hot-swap, and building the first line of defense for hot-swap testing.

[0042] In one feasible implementation, in step S3, the physical layer passive protection is achieved through the stepped connector layout of the hot-swappable adapter and the non-standard foolproof design of the cable assembly, the specific steps of which include: S3.10: The backplane connector of the hot-swappable adapter adopts a three-level stepped layout. The first level is a power connector, the second level is a high-speed data connector, and the third level is a low-speed signal connector. Adjacent connectors have a preset installation height difference, and the installation height decreases sequentially from the third level to the first level. S3.11: The plugs of power cables, high-speed data cables and low-speed signal cables adopt different shapes of non-foolproof design, which are matched with the corresponding level of connectors and cannot be inserted into connectors of other levels. S3.12: When the power cable is not fully inserted into the first-level connector, the protruding part of its plug will physically block the insertion path of the second-level and third-level connectors; when the low-speed signal cable is not fully unplugged, its plug will physically block the unplugging path of the high-speed data cable and power cable.

[0043] In this embodiment, the installation height refers to the vertical distance from the connector's mating end face (i.e., the mating surface that first contacts when the plug is inserted) to the backplate mounting plane; the installation height decreases sequentially from the third level to the first level, that is, the mating end face of the third level low-speed signal connector is closest to the backplate, and the mating end face of the first level power connector is farthest from the backplate, and the mating end faces of adjacent levels form a straight step drop perpendicular to the insertion direction; The grounding pins of the three types of connectors are flush with the mating end face of the corresponding level of connector. The number of grounding pins of the first-level power connector accounts for more than 70% of the total number of grounding pins, ensuring that the grounding pins are connected before disconnecting, which meets the server hot-plug forced timing requirements. The three-tiered layout refers to the three types of connectors on the backplane side being arranged in the order of power, high-speed data, and low-speed signals, with progressively decreasing installation heights. This ensures that the pins are turned on and off according to a preset timing sequence during insertion and removal. The preset installation height difference is exemplarily set to 2mm. This difference matches the standard insertion stroke of conventional server connectors and ensures that the timing difference between the power and signal pins during hot-swapping meets the safety requirements of the motherboard during power-on and power-off. Those skilled in the art can adjust this height difference according to the timing requirements of the actual motherboard.

[0044] To complement the three-tiered layout of the backplane, the plugs of the three independent cable types employ an effective insertion travel design that matches the corresponding connector level: the effective insertion travel of the power cable plug > the effective insertion travel of the high-speed data cable plug > the effective insertion travel of the low-speed signal cable plug, and the travel difference between adjacent plug levels is exactly the same as the installation height difference of the corresponding connector. This design works synergistically with the tiered layout, and can be enforced without additional electrical control: when inserted, the power cable plug conducts first, and the low-speed signal cable plug conducts last; when removed, the low-speed signal cable plug disconnects first, and the power cable plug disconnects last, fully complying with the standard timing requirement of "power on first, signal off first, signal on last" for server hot-swapping.

[0045] The non-misfit design refers to the use of different non-standard outer contours for the plugs of different types of cables, which can only be inserted by matching the interface shape of the corresponding level of connector. For example, the plugs of power cables, high-speed data cables and low-speed signal cables adopt square, trapezoidal and round non-standard structures, respectively, which can be uniquely matched with the connectors of the corresponding level and cannot be inserted into connectors of other levels, thus eliminating the risk of incorrect cable insertion from the physical source.

[0046] The protruding part of the plug is a straight retaining edge that extends integrally from the plug housing in the corresponding direction, requiring no additional components: the retaining edge of the power cable plug extends forward along the insertion direction, covering the insertion entrance area of ​​the second and third level connectors; when the power cable is not fully inserted, the retaining edge precisely blocks the insertion path of the subsequent two level connectors; only when the power cable is fully inserted does the retaining edge move forward with the plug to expose the insertion entrance. The retaining edge of the low-speed signal cable plug extends backward in the opposite direction of insertion, covering the removal path of the first and second level connectors; when the low-speed signal cable is not fully removed, the retaining edge blocks the removal action of the first two level cables; only when the low-speed signal cable is fully removed can the first two level cables be removed normally, thus forcibly standardizing the operation sequence of power cables being inserted before removal and signal cables being inserted last and removed first; the axial extension length of the forward / reverse retaining edge is completely consistent with the effective insertion stroke of the corresponding plug, and the width of the retaining edge is 2mm larger than the width of the covered connector insertion entrance, ensuring complete obstruction of the corresponding path.

[0047] This embodiment constructs a second line of defense for hot-swap testing by combining a three-tiered ladder connector layout with a non-standard error-proof design. This solves the technical problems of incorrect connector insertion, reversed cable connections, and disordered insertion / removal sequences in traditional hot-swap testing, which can lead to motherboard or backplane hardware damage and communication anomalies. The coordinated design of the ladder layout and corresponding plug travel forces a standard hot-swap sequence through physical structure, conforming to the working logic of server hardware. The non-standard error-proof design physically eliminates the possibility of incorrect cable insertion, and the physical shielding mechanism further enhances the standardization of insertion and removal operations. It eliminates the need for manual memorization of the operation sequence, lowering the barrier to manual operation and reducing the probability of error. Combined with active electrical protection, this forms double redundancy, comprehensively improving the safety and reliability of hot-swap testing.

[0048] In one feasible implementation, step S4, which involves comparing the collected electrical parameter data with preset electrical safety thresholds item by item and performing anomaly judgment to generate anomaly judgment results, includes the following specific steps: S4.1: Extract the peak value of the power-on inrush current, the stable voltage value, the stable current value, and the voltage and current change data from the electrical parameter data; S4.2: Compare the peak value of the power-on inrush current with the preset inrush current threshold. When the peak value exceeds the threshold, generate an inrush current anomaly indicator and record the time and specific value of the anomaly. S4.3: Compare the stable voltage value with the preset normal voltage range. When the stable voltage value exceeds the normal range, generate a voltage anomaly flag and record the time and specific value of the anomaly. S4.4: Compare the stable current value with the preset normal current range. When the stable current value exceeds the normal range, generate a current anomaly flag and record the time and specific value of the anomaly. S4.5: If any exception flag exists, the access operation is determined to be abnormal, and an operation exception result is generated; if no exception flag exists, the access operation is determined to be successful, and an operation success result is generated.

[0049] In this embodiment, the anomaly identifier refers to the standardized data label generated for different types of electrical parameter anomalies, which marks the anomaly type, occurrence time, and anomaly value. The valid anomaly determination rule is: except for the inrush current, other parameters are only considered valid anomalies and corresponding anomaly identifiers are generated if the time exceeds the preset threshold for more than 100μs. The peak value of the inrush current is considered a valid anomaly if it exceeds the threshold once. An abnormal operation result refers to the judgment result that any electrical parameter exceeds the safety threshold during the hot-plug connection process. This indicates that there is a safety risk or hardware abnormality in this connection operation and it will not proceed to the subsequent system verification stage. After the abnormal operation result is generated, an emergency shutdown signal is immediately generated to control the power switch module to shut down all power supply paths, record detailed abnormal information, and decide whether to retry the connection operation based on the preset number of retries (exemplarily set to 3 times).

[0050] This embodiment solves the technical problems of incomplete electrical parameter comparison, inconsistent anomaly judgment standards, and incomplete anomaly information recording in traditional hot-swap testing by designing a standardized anomaly judgment process of "parameter extraction → item comparison → anomaly identification → result judgment". This process leads to inaccurate test results and difficulty in tracing the cause of anomalies. The item comparison method can accurately locate the anomaly of each electrical parameter, and the standardized anomaly identification clarifies the anomaly type, time, and value, providing a clear basis for subsequent anomaly analysis and hardware fault diagnosis. The rule of "any anomaly determines an operational anomaly" strictly controls the safety of hot-swap access, avoids irreversible damage to the motherboard and backplane caused by abnormal access, and unifies the test judgment standards to ensure the consistency of test results for different batches and different operators, thereby improving the standardization level and reliability of testing.

[0051] In one feasible implementation, step S4, which involves sending a system verification command to the server motherboard, receiving and processing the verification data returned by the server, and generating a system verification result, includes the following specific steps: S4.6: Based on the successful operation result, send a system verification command to the server motherboard; S4.7: Receive storage device list data returned by the server motherboard, verify whether the backplane of the hard drive under test and each connected hard drive are correctly identified, and generate device identification status data; S4.8: Receive hard drive read / write performance test data returned by the server motherboard, obtain the hard drive's sequential read / write speed, random read / write speed, and IOPS data, and generate hardware performance data; S4.9: Receive BMC system log and hard disk backplane status register data returned by the server motherboard, verify whether there are communication errors, power supply errors or hardware alarm information, and generate system status data; S4.10: Integrate the device identification status data, hardware performance data, and system status data to generate a system verification result; when the system verification result is passed, execute the subsequent automated test script; when the system verification result is failed, record the error information and trigger the power-off operation.

[0052] In this embodiment, the system verification command refers to the standardized command issued by the test control host to the server motherboard to trigger the server to perform device identification, performance testing, and status detection of the backplane and hard drives under test. The unified criteria for passing the system verification are: the device identification status data shows that all hard drives connected to the backplane under test are correctly identified by the server operating system and no devices are lost; the hardware performance data shows that the hard drive read / write performance is not less than 80% of the nominal value; and the system status data shows that there are no communication or power supply related alarms in the BMC system log and the backplane status register. If all three conditions are met, the system is deemed to have passed. The system verification result refers to the comprehensive result generated after integrating device identification status, hardware performance data, and system status data to determine whether the system-level functions of the backplane under test are normal. After generating a system verification failure result, the system verification can be re-executed according to the preset number of retries (exemplarily set to 2 times). If the retry still fails, a power-off operation is triggered, a replaceable prompt signal is generated, and the next hard drive backplane under test is tested.

[0053] This embodiment constructs a comprehensive system verification framework from three dimensions: device identification, hardware performance, and system status. This solves the technical problem of traditional hot-swap testing, which only focuses on access process security and neglects system-level functional verification, leading to incomplete testing and an inability to accurately determine the actual performance of the backplane. Device identification verification ensures the validity of the connection between the backplane and the hard drive; performance testing verifies the stability and reliability of data transmission on the backplane; and system status verification identifies potential communication and power supply anomalies. The combination of these three aspects achieves the dual verification goal of "access security + normal function." The verification results are linked with subsequent automated test scripts and power-off operations to form a closed-loop control, ensuring both the comprehensiveness and accuracy of the test, further improving the degree of automation, avoiding hardware damage caused by continuous testing under abnormal conditions, and providing a comprehensive and objective basis for judging the quality of the backplane.

[0054] In one feasible implementation, step S5, specifically controlling the hot-swap adapter to perform the safe removal control of the backplane of the hard drive under test, includes the following steps: S5.1: Receive the single backplane test completion signal and generate a backplane removal command and a power pre-shutdown signal; S5.2: Based on the power pre-shutdown signal, control the power switch module of the hot-swappable adapter to shut down all power supply paths in a soft shutdown manner; S5.3: After receiving the power-off signal from the power switch module, continue to maintain the device in-place simulation state on the server motherboard side until the backplane physical removal completion signal from the hot-swap adapter is received. S5.4: Based on the signal indicating that the physical removal of the backplate is complete, generate a replacement prompt signal.

[0055] In this embodiment, the single backplane test completion signal is generated by the test control host after the number of test cycles for a single backplane reaches the preset batch requirement, or after three consecutive abnormal terminations of the test.

[0056] Soft shutdown refers to a power-off method that gradually reduces the MOSFET gate voltage and slowly decreases the power supply path conduction current until it is completely shut off. The soft shutdown time is configured as 100ms for example. The shutdown sequence is as follows: first shut down the 12V main power supply branch, then shut down the 5V main power supply branch, and finally shut down the 3.3V standby power supply branch to avoid the reverse electromotive force impact caused by instantaneous power shutdown. If an abnormal change in the power supply branch current is detected during the soft shutdown process, an emergency shutdown is immediately triggered, and a soft shutdown abnormal alarm signal is generated and recorded simultaneously. The backplane physical removal completion signal refers to the trigger signal generated by the hot-swappable adapter after the backplane is detected to be completely removed and all pins are disconnected by the in-place detection pin, indicating that the backplane removal operation is complete. The timeout waiting time for the backplane physical removal completion signal is set to 30 seconds for example. If the signal is not received within the timeout period, the in-place simulation state will be automatically terminated and a removal timeout alarm signal will be generated. The replaceable prompt signal is achieved through the continuous flashing of the green status indicator light of the hot-swappable adapter, and the text prompts on the host computer interface of the test control host are synchronized.

[0057] The power supply is completely shut off signal, which is generated by the logic control module after detecting that the output voltage of all power supply branches has dropped to 0V for more than 10ms. It indicates that the power supply link has been completely disconnected and there is no risk of being charged.

[0058] This embodiment solves the technical problems of excessively rapid power shutdown, motherboard misjudgment, and hardware damage caused by hot-swapping during traditional hot-swapping processes by designing a safe removal process of "power pre-shutdown → soft shutdown execution → in-situ simulation maintenance → removal confirmation → prompt generation". The soft shutdown method avoids the impact of the back electromotive force generated by the instantaneous power shutdown on the motherboard and backplane, protecting hardware safety. After the power is completely shut down, the in-situ simulation state is maintained to ensure that the motherboard will not trigger abnormal alarms or enter protection mode due to backplane removal, ensuring the continuity of subsequent tests. The backplane physical removal confirmation mechanism is linked with the replaceable prompt signal to clarify the completion status of the removal operation and guide the operator to replace the next backplane, improving the efficiency and standardization of batch testing. It forms a complete hot-swapping closed loop with the access control process, further improving the full-process control of automated testing and ensuring the smooth and safe conduct of batch testing.

[0059] like Figure 4 As shown, the present invention also provides an automated testing system for hot-swapping of server hard disk backplanes, including a test control host, a hot-swapping adapter, and a server motherboard that is communicatively connected to the test control host and the hot-swapping adapter respectively. The test control host is used to send control commands to the hot-swappable adapter and receive returned data. The hot-swappable adapter is located between the server motherboard and the backplane of the hard drive under test, and includes a logic control module, a power switch module, an electrical parameter acquisition module, and an in-situ simulation module. The logic control module is communicatively connected to the test control host, power switch module, electrical parameter acquisition module and in-situ simulation module, respectively. It is used to receive control commands from the test control host and configure the communication bus pins to a high impedance state to passively listen to the native communication between the server motherboard and the backplane of the hard drive under test, without intervening in the bus interaction. The power switch module is connected in series between the power link of the server motherboard and the backplane of the hard drive under test. It is used to perform soft start conduction, soft shutdown and emergency shutdown based on communication interruption detection of the power link according to the instructions of the logic control module. Together with the stepped connector structure and the non-standard foolproof structure of the hot-swappable adapter, it forms a double redundancy safety protection. The sampling terminal of the electrical parameter acquisition module is connected in parallel to the power input pin of the backplane of the hard drive under test. It is used to collect the voltage, current and ripple parameters of the backplane side in real time according to the electrical characteristics of different hot-plug stages using a multi-level adjustable sampling frequency and upload them to the logic control module. The output of the in-situ simulation module is connected to the hard drive in-situ detection pin of the server motherboard, and is used to continuously output a stable in-situ detection signal that is equivalent to the original hard drive backplane to the server motherboard during the entire hot-plugging process of the hard drive backplane being connected, running and being removed.

[0060] In this embodiment, the test control host can be an industrial control computer or a high-performance desktop computer. It establishes a communication connection with the BMC management port of the server motherboard through a gigabit Ethernet interface. For example, the communication protocol adopts the standard IPMI2.0 or Redfish protocol to realize the issuance of system verification commands, the reading of server running status and log data. It establishes a bidirectional serial communication connection with the logic control module of the hot-swappable adapter through a USB to UART module (such as CH340). The communication parameters are configured for example as a baud rate of 115200bps, 8 data bits, 1 stop bit, and no parity bit. The command frame adopts the common format of "frame header + command code + data length + data field + checksum + frame tail" to ensure stable transmission of commands and data. The test control host has built-in automated test scripts and data processing units, which can complete test data comparison, anomaly judgment, test count statistics, and automatic generation of test reports.

[0061] The server motherboard is the original manufacturer's motherboard that is compatible with the backplane of the hard drive under test. Its native hard drive backplane interface is connected to the motherboard-side connector of the hot-swap adapter via the original manufacturer's matching high-speed SAS / SATA cable. The hard drive backplane under test is connected to the backplane-side connector of the hot-swap adapter via the matching cable. The motherboard-side connector of the hot-swap adapter uses a SAS / SATA high-speed connector that is completely consistent with the native hard drive backplane interface of the server motherboard under test. For example, a MiniSAS HD 36Pin connector is used, and the pin definitions are completely matched with the original manufacturer's standard to ensure full compatibility. The backplane-side connector adopts a three-level stepped layout. The first level is a high-current power connector, the second level is a SAS / SATA high-speed data connector, and the third level is an I2C / SGPIO low-speed signal connector. The installation height difference between adjacent connector levels is set to 2mm for example, and the installation height decreases sequentially from the third level to the first level. This physically ensures the safety of the insertion sequence of "ground pin → power pin → signal pin" and the removal sequence of "signal pin → power pin → ground pin" during hot-swapping. The plugs of power cables, high-speed data cables, and low-speed signal cables adopt different shapes of non-foolproof designs. For example, square, trapezoidal, and round plug structures can be used respectively, each uniquely matching the corresponding level of connector and preventing insertion into connectors of other levels. When the power cable is not fully inserted into the first-level connector, the protruding part of its plug will physically block the insertion path of the second and third-level connectors. When the low-speed signal cable is not fully unplugged, its plug will physically block the unplugging path of the high-speed data cable and power cable, thus eliminating the risk of accidental insertion or unplugging due to manual operation from a physical structure perspective.

[0062] The hot-swap adapter serves as the hardware carrier for implementing the aforementioned testing method. It exemplarily employs a 4-layer PCB design to adapt to the power integrity and multi-signal isolation requirements of hot-swap cyclic testing scenarios, avoiding crosstalk interference between high-current power supply, high-speed data transmission, and low-speed control signals, ensuring stable operation of the test control logic and accurate acquisition of electrical parameters. The 12V main power supply path PCB trace width is exemplarily designed according to a standard of ≥40mil / A copper thickness (1 ounce), to match the current requirements of full-load power supply and hot-swap power-on surge current of enterprise-grade hard drive backplanes, avoiding hardware damage or test data distortion caused by excessive heat generation and voltage drop under high-current conditions. SAS The / SATA high-speed differential signal line adopts a 100Ω differential impedance matching design, with the length error of the differential pair in the same group controlled within 5mil to match the impedance and timing standards of the server's original high-speed bus. This avoids communication anomalies and false alarms from the server motherboard caused by signal reflection and timing deviation, ensuring uninterrupted automated testing processes. All external interfaces of the device integrate ESD electrostatic protection devices, exemplarily using SMBJ6.5CA TVS diodes to protect signal pins and SMBJ33CA TVS diodes to protect power pins, to address the electrostatic discharge risk caused by frequent plugging and unplugging during batch cyclic testing, ensuring the long-term operational reliability of the testing system.

[0063] The logic control module, as the core control unit of the hot-swappable adapter, exemplarily adopts an STM32F407IGT6 microcontroller or an EP4CE10F17C8 FPGA chip. It can achieve basic operation with a conventional minimum system circuit known in the art. The chip's built-in firmware has preset bus monitoring and parsing, power switch control, abnormal event interrupt response, data acquisition scheduling, and uplink and downlink communication interaction logic. The firmware exemplarily adopts the FreeRTOS preemptive real-time operating system and uses a preemptive priority scheduling mechanism. The interrupt preemption priority of communication interruption and electrical parameter over-limit interruption is configured as level 0 (highest level), the bus monitoring task priority is configured as level 1, the power switch control task priority is configured as level 2, the data acquisition and upload task priority is configured as level 3, and the regular command sending and receiving task priority is configured as level 4. This ensures that abnormal interruption can be responded to first without being interfered with by other tasks, and guarantees microsecond-level response in abnormal states. Its general-purpose input / output interfaces are electrically connected to the enable control pin of the power switch module, the interrupt trigger pin of the electrical parameter acquisition module, the switch control pin of the in-situ simulation module, the in-situ detection pin on the backplane side, and the connector physical status detection pin, respectively. The serial peripheral interface is connected to the data output terminal of the electrical parameter acquisition module, and the communication rate is configured to 10MHz for example. The serial communication interface establishes bidirectional stable communication with the test control host. The I2C / SGPIO bus pins are configured as high-impedance bypass mode through 10kΩ pull-up resistors and connected in parallel to the backplane side communication bus to realize passive listening and parsing of bus data. If the STM32F407 microcontroller is used to implement the bus listening function, the I2C / SGPIO pins need to be configured as ordinary GPIO input mode, and the bus timing is simulated by software for listening. The use of hardware I2C slave mode is prohibited (it will automatically send an acknowledgment signal, interfering with the native communication between the motherboard and the backplane). For example, the monitoring logic follows the standard SAS 3.0 and IPMI specifications, parsing the address and data frames of the I2C bus bit by bit, extracting communication data packets whose target address is the standard address of the backplane of the hard drive under test, and identifying register write instructions that represent "motherboard allows backplane power-on". When the same power-on instruction is detected twice consecutively with a 10ms interval, the instruction is confirmed to be valid and a power-on control signal is generated. If the logic control module does not detect any valid communication data packets whose target address is the backplane of the hard drive under test within 500ms, it determines that the communication is interrupted and immediately triggers an emergency power-off instruction. This threshold can be flexibly adjusted according to actual test requirements, taking into account both the suppression of false shutdowns and the speed of abnormal response. Throughout the monitoring process, the logic control module does not send any response signals to the bus, does not modify any data on the bus, and does not intervene in the native communication process between the motherboard and the backplane. It only reads the bus level through a pure high-impedance input mode, without changing the impedance characteristics of the bus or the communication timing, thus minimizing the impact on the native communication environment.

[0064] The power switch module provides independent controllable switch branches for the 12V main power, 5V main power, and 3.3V standby auxiliary power output from the server motherboard. Each branch is implemented using a dedicated hot-swappable controller with soft-start function and an N-channel MOSFET power transistor. Specifically, the 12V main power branch uses an LTC4260 hot-swappable controller with an IRF3205 MOSFET, while the 5V and 3.3V branches use an LTC4261 hot-swappable controller with an IRL540 MOSFET, covering the conventional power supply requirements of the server hard drive backplane. The enable pin of the hot-swappable controller is electrically connected to the general-purpose input / output interface of the logic control module. The soft-start time is configured to 1μF via an external ceramic capacitor, corresponding to a soft-start time of approximately 124ms, effectively suppressing the backplane power-on inrush current. The hardware configuration ensures an emergency shutdown response time of ≤5μs, meeting the emergency power-off timing requirements in communication interruption scenarios. The current sensing pin of the power switch module is connected in series with a high-precision sampling resistor at the input terminal of the corresponding power branch. The sampling resistor is, for example, a high-precision milliohm resistor with a precision of 0.002Ω and 1% accuracy, which can synchronously output a real-time current sampling signal to the electrical parameter acquisition module. The power status pin is electrically connected to the logic control module and is used to report the power on, off, and fault status in real time. Each branch is configured with overcurrent, overvoltage, and overtemperature protection functions. The overcurrent protection threshold is configured through an external current sensing resistor. For example, the overcurrent protection threshold of the 12V branch is set to 35A, the 5V branch is set to 12A, and the 3.3V branch is set to 10A. The overvoltage protection threshold is, for example, set to 120% of the corresponding rated voltage. Overtemperature protection is achieved through the temperature detection function built into the hot-swap controller. For example, the protection threshold is set to 125℃. When protection is triggered, the hot-swap controller automatically turns off the MOSFET and reports a fault signal to the logic control module through the FAULT pin.

[0065] The electrical parameter acquisition module exemplarily employs an 8-channel synchronous sampling 16-bit high-precision ADC chip, ADS8688. Through the aforementioned high-precision milliohm sampling resistors corresponding to the 12V, 5V, and 3.3V power input pins of the hard drive backplane under test, it achieves synchronous real-time acquisition of voltage and current for each power path. Its sampling frequency can be configured to a three-level adjustable mode via the logic control module. Exemplarily, it is set to: a 500kHz first sampling frequency for inrush current acquisition during the initial soft-start phase, a 10kHz second sampling frequency for conventional data acquisition during the stable power supply phase, and a 1MHz third sampling frequency for high-resolution acquisition during abnormal sudden changes, fully matching the sampling requirements of the aforementioned test method. The module's overvoltage and overcurrent interrupt output pins are electrically connected to the external interrupt pins of the logic control module. When electrical parameters exceed preset thresholds, a hardware interrupt can be triggered within 1μs. The acquired raw electrical data is uploaded to the logic control module in real-time via a serial peripheral interface and then forwarded to the test control host for subsequent data processing. In this embodiment, the preset electrical safety thresholds are exemplarily set as follows: 12V main power supply inrush current threshold ≤30A, normal stable voltage range 12V±5%, normal stable current range ≤25A; 5V main power supply normal stable voltage range 5V±5%, normal stable current range ≤8A; 3.3V standby power supply normal stable voltage range 3.3V±5%, normal stable current range ≤5A; voltage fluctuation threshold is ±10% of rated voltage, and current surge threshold is 50% of rated current.

[0066] The in-situ simulation module is implemented using a combination of multiple independently configurable pull-down resistor arrays and N-channel MOSFET switches. Each array corresponds to a backplane in-situ detection pin on the server motherboard. The resistance value and accuracy of the pull-down resistors are completely consistent with the in-situ detection pull-down resistors of the original hard drive backplane of the server under test, exemplarily configured as 1kΩ±5%, ensuring that the output in-situ signal is indistinguishable from the original backplane. The MOSFET switch is exemplarily an SI2302 type N-channel MOSFET, with its gate connected in series with a current-limiting resistor and electrically connected to the general input / output interface of the logic control module. Its drain is connected to the in-situ detection pin on the motherboard, and its source is grounded through a matching pull-down resistor. The logic control module can continuously maintain the MOSFET in a saturated conduction state through a conduction control signal. During the entire process of physical hot-plugging of the backplane, regardless of whether the backplane is physically connected, powered on, or physically removed, a stable pull-down in-situ signal can be continuously output to the motherboard, completely avoiding alarms, crashes, and test interruptions caused by sudden changes in the device's in-situ status.

[0067] In this embodiment, the system verification process employs the following execution logic: After receiving the successful access operation result, the test control host sends a system verification command to the server motherboard BMC via the IPMI protocol, calling the server's built-in fio hard drive testing tool to perform read / write performance testing. The test parameters are configured as follows: sequential read / write block size 128KB, random read / write block size 4KB, queue depth 32, and test duration 30s. The test control host receives the storage device list data returned by the server, verifies that the backplane of the hard drive under test and each connected hard drive are correctly recognized by the server operating system, with no device loss, and generates device identification status data. It receives the hard drive read / write performance test data, obtains the sequential read / write speed, random read / write speed, and IOPS data, and compares them with 80% of the hard drive's nominal performance as the passing threshold to generate hardware performance data. It receives the BMC system log and hard drive backplane status register data, verifies that there are no communication errors, power supply errors, or hardware alarm information, and generates system status data. When the device identification is normal, the performance data meets the standard, and there are no system alarms, the system verification result is determined to be passed; otherwise, it is determined to be failed.

[0068] In this embodiment, the dual redundancy safety mechanism adopts a collaborative linkage logic of "electrical active protection + physical passive protection", such as... Figure 3 As shown, a layered and progressive protection chain is formed, designed for different risk scenarios throughout the entire backplane hot-swap process: Physical passive protection enforces standardized insertion and removal timing and operation sequence through structural design, eliminating human error in insertion, removal, and timing from the source, covering most common operational risks; Electrical soft protection solves the power surge problem during normal hot-swap through soft start / soft shutdown, covering normal operation scenarios after physical protection takes effect; Electrical emergency protection uses emergency shutdown based on communication interruption as a fallback protection, achieving microsecond-level rapid power-off for extreme accidental scenarios that physical protection cannot cover (such as backplane accidental detachment, link misconnection, power short circuit, etc.); The three layers of protection cooperate and complement each other, forming a complete safety system from operational specifications to normal protection to extreme fallback, reducing the risk of hardware damage.

[0069] Meanwhile, by adopting a combination design of "non-intrusive bus monitoring + full-process in-situ simulation", the hot-swapping process is fully automated without modifying the original hardware of the server motherboard or intervening in the original communication between the motherboard and the backplane. This completely avoids the server alarm and downtime problems that are easily caused by modifying the motherboard firmware and intervening in bus communication in existing technologies.

[0070] This embodiment establishes an automated testing system in which the test control host, hot-swap adapter, and server motherboard work together by adding an independent hot-swap adapter between the server motherboard and the hard drive backplane under test. This system adopts the server hard drive backplane hot-swap automated testing method described in any of the above embodiments, which can realize automated cyclic management of the entire process of hard drive backplane hot-swap, high-precision electrical parameter acquisition at all times, and multi-dimensional system-level functional verification. This system, through the collaborative hardware design of its various functional modules, fully supports the entire process of implementing the aforementioned testing methods. By employing a dual-redundancy safety design combining active electrical protection and passive physical protection, it solves the technical problems inherent in traditional hard drive backplane hot-swap testing, such as power-on shock damage, motherboard malfunction alarms and system crashes, short circuits caused by manual operation, low testing efficiency, inaccurate data acquisition, and poor batch testing consistency. Through the independent matching design of the in-situ simulation module, it achieves continuous and stable simulation of the motherboard's in-situ state throughout the entire backplane physical hot-swap process, completely avoiding test interruptions caused by sudden changes in the device's in-situ state, thus improving the safety and stability of hot-swap testing. The multi-level adjustable high-precision electrical parameter acquisition module enables high-resolution real-time acquisition of electrical parameters throughout the hot-swap process, providing reliable quantitative data support for accurate test result judgment. Simultaneously, through the fully automated management of the test control host, it achieves unmanned cyclic testing of multiple batches of hard drive backplanes without manual intervention, improving the efficiency of mass production testing and reliability verification of server hard drive backplanes, the accuracy of test results, and the safety and stability of the server hard drive backplane hot-swap testing process. Compared with the prior art, the beneficial effects of the automated hot-swappable testing system for server hard disk backplanes provided in this application are completely consistent with the beneficial effects of the automated hot-swappable testing method for server hard disk backplanes provided in the above embodiments. Furthermore, the technical features of the module execution logic, control timing, security protection mechanism, and data processing rules corresponding to each step of the testing method in the testing system described in this application are all matched with the corresponding features disclosed in the methods in the above embodiments, and will not be repeated here.

[0071] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. An automated testing method for hot-swapping server hard drive backplanes, characterized in that, Includes the following steps: S1: Initialize and configure the logic control module of the hot-swappable adapter, and generate an initialization completion signal; S2: Receive the S0 status ready signal from the server motherboard, establish a communication connection with the server motherboard, and generate an environment ready signal after confirming that the test environment is ready. S3: Based on the initialization completion signal and the environment ready signal, the hot-swap adapter is controlled to perform safe hot-swap access control of the backplane of the hard drive under test. During the entire hot-swap process, electrical parameter data on the backplane side is collected in real time, while maintaining the device in-situ simulation state on the server motherboard side to ensure that there are no abnormal alarms on the server motherboard. The safe hot-swap access control uses the access timing control process as the standardized execution logic, and adopts a dual redundancy safety mechanism to achieve full-process safety protection. The dual redundancy safety mechanism includes active protection at the electrical level and passive protection at the physical level. S4: Compare the collected electrical parameter data with the preset electrical safety thresholds item by item and make anomaly judgments to generate anomaly judgment results; when the anomaly judgment result indicates that the access operation is successful, send a system verification command to the server motherboard, receive and process the verification data returned by the server, and generate system verification results. S5: Based on the anomaly judgment results, system verification results, and preset test batch information, count the number of successful tests and the number of anomalies for a single backplane, and generate a single backplane test sub-report; After a single backplane test is completed, the hot-swap adapter is controlled to safely remove the backplane of the hard drive under test, generating a replaceable prompt signal. Steps S3-S4 are executed repeatedly until all batches of hard drive backplanes under test are tested, generating a complete batch test report.

2. The automated testing method for hot-swapping of server hard drive backplanes according to claim 1, characterized in that, In step S3, the specific steps based on the access timing control flow as the standardized execution logic include: S3.1: Receive a backplane insertion valid signal sent by the hot-swap adapter. The backplane insertion valid signal is generated by the hot-swap adapter after detecting the physical insertion of the backplane through the backplane-side in-place detection pin and the grounding pin is reliably connected. S3.2: Based on the backplane insertion valid signal, control the hot-swap adapter to adopt the same resistor pull-down method as the original hard drive backplane of the server under test, and simulate output a valid "backplane in place" signal to the server motherboard side. S3.3: Control the hot-swap adapter to be connected in parallel to the I2C / SGPIO communication bus on the backplane side in a high-impedance bypass mode, passively listen to the communication data sent by the server motherboard to the backplane side, and generate a power-on control signal after parsing the "Power-on enabled" command. S3.4: Based on the power-on control signal, control the power switch module of the hot-swappable adapter to turn on all power supply paths in a soft-start mode. During the power supply turn-on process, receive the voltage change data and current change data of the backplane side power input terminal uploaded by the hot-swappable adapter. S3.5: Receive the access operation completion signal sent by the hot-swappable adapter, and integrate the voltage change data and current change data into the electrical parameter data.

3. The automated testing method for hot-swapping server hard drive backplanes according to claim 1, characterized in that, In step S3, the electrical layer active protection is a power pre-shutdown safety control based on communication interruption, and its specific steps include: S3.6: The logic control module for controlling the hot-swappable adapter monitors the level status of the I2C / SGPIO communication bus on the backplane side in real time, sets a preset anti-jitter detection window, and continuously judges whether the bus is in a normal communication state. S3.7: When a communication interruption event signal is received from the logic control module, an emergency shutdown signal is generated. The communication interruption event signal is generated by the logic control module after detecting that the backplane-side communication bus level is continuously in a high-impedance state and exceeds the anti-jitter detection window. S3.8: Based on the emergency shutdown signal, control the power switch module of the hot-swap adapter to completely shut off all power paths from the server motherboard to the backplane of the hard drive under test within a preset response time. S3.9: Control the hot-swappable adapter to illuminate the safety status indicator light, and at the same time generate a communication interruption alarm message and record the time of the interruption and bus status data.

4. The automated testing method for hot-swapping of server hard drive backplanes according to claim 1, characterized in that, In step S3, the physical layer passive protection is achieved through the stepped connector layout of the hot-swappable adapter and the non-standard foolproof design of the cable assembly. The specific steps include: S3.10: The backplane connector of the hot-swappable adapter adopts a three-level stepped layout. The first level is a power connector, the second level is a high-speed data connector, and the third level is a low-speed signal connector. Adjacent connectors have a preset installation height difference, and the installation height decreases sequentially from the third level to the first level. S3.11: The plugs of power cables, high-speed data cables and low-speed signal cables adopt different shapes of non-foolproof design, which are matched with the corresponding level of connectors and cannot be inserted into connectors of other levels. S3.12: When the power cable is not fully inserted into the first-level connector, the protruding part of its plug will physically block the insertion path of the second-level and third-level connectors; when the low-speed signal cable is not fully unplugged, its plug will physically block the unplugging path of the high-speed data cable and power cable.

5. The automated testing method for hot-swapping of server hard drive backplanes according to claim 2, characterized in that, In step S3.3, the specific steps for passively monitoring the communication data sent from the server motherboard to the backplane side include: S3.3.1: The logic control module that controls the hot-swappable adapter configures its input pins to a high-impedance state and connects them in parallel to the SCL and SDA signal lines of the I2C bus on the backplane side, as well as the clock line, data line, and load line of the SGPIO bus. S3.3.2: The control logic control module synchronizes the SCL clock signal of the I2C bus, parses the address frame and data frame transmitted on the bus bit by bit, and extracts the communication data packet whose target address is the backplane address of the hard disk under test; S3.3.3: The control logic control module identifies a specific register write instruction representing "the motherboard allows the backplane to power on" from the parsed communication data packet. When the same power-on instruction is detected twice in a row, the instruction is confirmed to be valid and the power-on control signal is generated. S3.3.4: Throughout the entire monitoring process, the control logic module does not send any response signals to the bus, does not modify any data on the bus, and does not intervene in any communication process.

6. The automated testing method for hot-swapping server hard drive backplanes according to claim 2, characterized in that, In step S3.4, the specific steps for receiving the voltage and current change data from the backplane-side power input terminal uploaded by the hot-swappable adapter include: S3.4.1: During the initial stage of the soft-start operation of the power switch module, the change data of the 12V main power supply current value on the backplane side is collected at the first preset sampling frequency, and the peak value and duration of the power-on inrush current are recorded. S3.4.2: During the stable power supply phase after the power switch module is fully turned on, the voltage and current values ​​of the 12V main power supply, 5V main power supply and standby auxiliary power supply on the backplane side are collected at the second preset sampling frequency. S3.4.3: When a voltage fluctuation exceeds a preset voltage fluctuation threshold or a current change exceeds a preset current change threshold, the high-resolution electrical parameter change data is automatically collected at the third preset sampling frequency. S3.4.4: Integrate the soft-start phase data, stable power supply phase data, and high-resolution mutation data to generate the voltage change data and current change data.

7. The automated testing method for hot-swapping of server hard drive backplanes according to claim 1, characterized in that, In step S4, the specific steps for comparing the collected electrical parameter data with preset electrical safety thresholds and performing anomaly judgment to generate anomaly judgment results include: S4.1: Extract the peak value of the power-on inrush current, the stable voltage value, the stable current value, and the voltage and current change data from the electrical parameter data; S4.2: Compare the peak value of the power-on inrush current with the preset inrush current threshold. When the peak value exceeds the threshold, generate an inrush current anomaly indicator and record the time and specific value of the anomaly. S4.3: Compare the stable voltage value with the preset normal voltage range. When the stable voltage value exceeds the normal range, generate a voltage anomaly flag and record the time and specific value of the anomaly. S4.4: Compare the stable current value with the preset normal current range. When the stable current value exceeds the normal range, generate a current anomaly flag and record the time and specific value of the anomaly. S4.5: If any exception flag exists, the access operation is determined to be abnormal, and an operation exception result is generated; if no exception flag exists, the access operation is determined to be successful, and an operation success result is generated.

8. The automated testing method for hot-swapping of server hard drive backplanes according to claim 1, characterized in that, In step S4, the specific steps for sending a system verification command to the server motherboard, receiving and processing the verification data returned by the server, and generating a system verification result include: S4.6: Based on the successful operation result, send a system verification command to the server motherboard; S4.7: Receive storage device list data returned by the server motherboard, verify whether the backplane of the hard drive under test and each connected hard drive are correctly identified, and generate device identification status data; S4.8: Receive hard drive read / write performance test data returned by the server motherboard, obtain the hard drive's sequential read / write speed, random read / write speed, and IOPS data, and generate hardware performance data; S4.9: Receive BMC system log and hard disk backplane status register data returned by the server motherboard, verify whether there are communication errors, power supply errors or hardware alarm information, and generate system status data; S4.10: Integrate the device identification status data, hardware performance data, and system status data to generate a system verification result; when the system verification result is passed, execute the subsequent automated test script; when the system verification result is failed, record the error information and trigger the power-off operation.

9. The automated testing method for hot-swapping of server hard drive backplanes according to claim 1, characterized in that, In step S5, the specific steps for controlling the hot-swap adapter to perform the safe removal control of the backplane of the hard drive under test include: S5.1: Receive the single backplane test completion signal and generate a backplane removal command and a power pre-shutdown signal; S5.2: Based on the power pre-shutdown signal, control the power switch module of the hot-swappable adapter to shut down all power supply paths in a soft shutdown manner; S5.3: After receiving the power-off signal from the power switch module, continue to maintain the device in-place simulation state on the server motherboard side until the backplane physical removal completion signal from the hot-swap adapter is received. S5.4: Based on the signal indicating that the physical removal of the backplate is complete, generate a replacement prompt signal.

10. An automated testing system for hot-swapping server hard drive backplanes, used to perform the method described in any one of claims 1-9, characterized in that, It includes a test control host, a hot-swappable adapter, and a server motherboard that is communicatively connected to the test control host and the hot-swappable adapter, respectively. The test control host is used to send control commands to the hot-swappable adapter and receive returned data. The hot-swappable adapter is located between the server motherboard and the backplane of the hard drive under test, and includes a logic control module, a power switch module, an electrical parameter acquisition module, and an in-situ simulation module. The logic control module is communicatively connected to the test control host, power switch module, electrical parameter acquisition module and in-situ simulation module, respectively. It is used to receive control commands from the test control host and configure the communication bus pins to a high impedance state to passively listen to the native communication between the server motherboard and the backplane of the hard drive under test, without intervening in the bus interaction. The power switch module is connected in series between the power link of the server motherboard and the backplane of the hard drive under test. It is used to perform soft start conduction, soft shutdown and emergency shutdown based on communication interruption detection of the power link according to the instructions of the logic control module. Together with the stepped connector structure and the non-standard foolproof structure of the hot-swappable adapter, it forms a double redundancy safety protection. The sampling terminal of the electrical parameter acquisition module is connected in parallel to the power input pin of the backplane of the hard drive under test. It is used to collect the voltage, current and ripple parameters of the backplane side in real time according to the electrical characteristics of different hot-plug stages using a multi-level adjustable sampling frequency and upload them to the logic control module. The output of the in-situ simulation module is connected to the hard drive in-situ detection pin of the server motherboard, and is used to continuously output a stable in-situ detection signal that is equivalent to the original hard drive backplane to the server motherboard during the entire hot-plugging process of the hard drive backplane being connected, running and being removed.

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