A random excitation verification method and system for a RISC-V debugging module

Abstract

The application discloses a random excitation verification method and system of a RISC-V debugging module, and belongs to the field of integrated circuit verification. The application selects an APB bus as a register access interface, independently configures a debugging module state and a processor core state, and is decoupled from an APB register access operation; a constrained random register access excitation is issued through the APB bus, and a dynamic conversion of the debugging module state is actively triggered, so that full state coverage is realized; the access authority and functional behavior of a register are verified under each state combination; a multi-dimensional cross-coverage model is constructed, a random excitation is combined with offline analysis, directional test cases are generated for low-coverage state combinations for completion, and until full-dimensional coverage reaches 100%. The application solves the problems of low verification efficiency, incomplete scene coverage and slow coverage convergence in the prior art, and greatly improves the verification efficiency and completeness.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit verification technology, and in particular to a random stimulus verification method and system for a RISC-V debug module. Background Technology

[0002] With the increasing popularity of the RISC-V instruction set architecture, processor chips based on this architecture are widely used in fields such as the Internet of Things, artificial intelligence, and industrial control. The debug module (DM), as a key component of the processor chip used for software debugging, anomaly localization, and system simulation, directly affects the chip's debuggability and product quality through its functional correctness and robustness. Therefore, thorough, efficient, and quantifiable functional verification of the RISC-V debug module is a necessary step before mass production of the chip.

[0003] Existing RISC-V debug module verification technologies are mainly divided into two categories:

[0004] The first type of method implements register access and functional verification based on low-speed serial interfaces such as JTAG and CJTAG. This method is limited by the interface's transmission rate, resulting in long simulation times and an inability to support efficient injection of large-scale random stimuli, making it difficult to meet the verification cycle requirements of mass-produced chips.

[0005] The second type of verification scheme based on the on-chip bus uses simple blind random stimulus or fixed test cases to complete the basic register access verification. However, this type of method has the following significant defects: (1) The stimulus design lacks linkage with the debug module state and the processor core state, and cannot systematically cover the differences in access permissions and functional behavior of registers under different state combinations; (2) It lacks a multi-dimensional cross-coverage system, and the coverage indicators are scattered and single-dimensional, making it impossible to quantify the verification completeness; (3) The verification of key behaviors such as access control, illegal access, and abnormal response is insufficient, and there are a large number of verification blind spots; (4) The verification scenario is single, the robustness is poor, and the verification of complex scenarios under dynamic state transitions is missing; (5) It lacks a targeted coverage convergence strategy and only relies on random traversal without rules, resulting in slow coverage convergence and low verification efficiency.

[0006] Furthermore, in the prior art, the patent document with application publication number CN105205249A and patent title "A SOC Debugging and Verification System and its Software and Hardware Collaboration Method" describes a method for achieving software and hardware collaborative verification through a debugging module. However, its purpose is to use the debugging module as a communication bridge to solve the synchronization problem in the verification process, rather than to systematically verify the correctness of the debugging module's functionality.

[0007] Another patent document with application publication number CN115562931A and patent title "Processor Debug Module Verification Method, Apparatus, Electronic Device" proposes to carry out debug module verification after the chip front-end design is completed. However, its main innovation lies in the early verification timing and the reuse of test cases. It lacks a complete, systematic, and quantifiable verification methodology, especially in terms of stimulus generation strategy, state linkage mechanism, coverage model, and convergence strategy.

[0008] Therefore, developing a method and system that can efficiently, comprehensively, and quantitatively verify the correctness of RISC-V debug modules has become an urgent technical problem to be solved in this field. Summary of the Invention

[0009] Based on this, it is necessary to provide a random stimulus verification method and system for RISC-V debug modules to address the existing technical problems, so as to achieve full coverage verification of the legal and illegal access of all registers in all states of the debug module, and ultimately improve the completeness, efficiency and robustness of RISC-V debug module verification.

[0010] To address the problems in the existing technology, the present invention adopts the following technical solution:

[0011] A random stimulus verification method for a RISC-V debug module includes the following steps:

[0012] Step A: Select the APB bus as the register access interface, build a verification environment, and connect the RISC-V debug module to be verified as the device under test to the APB bus.

[0013] Step B: Configure the soft reset state and processor core state of the debug module independently through an external interface. This configuration process is completely decoupled from register access operations on the APB bus.

[0014] Step C: Send a constraint-generated random register access stimulus to the debug module via the APB bus, and actively trigger the dynamic state transition of the debug module through APB register write operations to achieve full state coverage of the debug module;

[0015] Step D: Input the external state configuration and APB random access stimulus into the gold model synchronously, and generate the expected results for each state combination based on the RISC-V debugging standard specification;

[0016] Step E: Under each state combination consisting of the soft reset state, processor core state, and debug module state, verify the access permissions, functional behavior, and abnormal responses of all registers of the debug module, and compare the actual output of the device under test with the expected results of the golden model. If the comparison is inconsistent, perform full-link backtracking based on the unique transaction identifier.

[0017] Step F: Collect and analyze multidimensional cross-coverage data, wherein the coverage data includes at least a three-dimensional cross-combination of debug module status, processor core status, and register read / write operations;

[0018] Step G: For the state combinations that are not covered or have low coverage, generate targeted persistent state use cases and execute them. Repeat steps B to F until full-dimensional coverage reaches 100%.

[0019] Preferably, the rules for actively triggering dynamic state transitions of the debugging module through APB register write operations in step D include:

[0020] Writing the authentication bit of the debug module control register to 0 triggers an unauthorized state;

[0021] Write the system reset bit of the debug module control register to 1 to trigger the system reset state.

[0022] Write the debug module control register to issue abstract instructions, triggering the abstract instruction execution state;

[0023] Issuing illegal commands, unauthorized access, or incorrect addresses can trigger an abnormal state in the execution of abstract commands.

[0024] Preferably, the multidimensional cross-coverage model in step F includes:

[0025] Basic dimensions: coverage of 6 core states of the debug module, coverage of 3 states of the processor core, and full register read / write coverage. The 6 core states of the debug module are: soft reset state, unauthorized state, system reset state, abstract instruction execution state, debug active state, and abstract instruction execution abnormal state.

[0026] Two-dimensional crossover: crossover coverage of debug module status and register read / write operations, and crossover coverage of processor core status and register read / write operations;

[0027] 3D cross-coverage: the 3D cross-coverage of debug module status, processor core status, and register read / write operations;

[0028] Specific dimensions: cross-coverage of legal and illegal access, and coverage of abstract instruction execution and abnormal scenarios.

[0029] Preferably, the strategy for generating directional persistent state use cases in step G includes:

[0030] When the processor reset state combination coverage is lower than a preset threshold, a processor continuous reset test case is generated.

[0031] When the coverage of abnormal state combinations in the execution of abstract instructions in the debugging module is lower than a preset threshold, a continuous exception trigger test case is generated.

[0032] When the coverage of unauthorized state combinations in the debug module is lower than a preset threshold, a persistent unauthorized state test case is generated.

[0033] Preferably, the verification of register access permissions and functional behavior in step E includes:

[0034] Read operation verification: Verify that the return value is the correctness of the actual value, 0, or reset value;

[0035] Write operation validation: Verifies the correctness of data writing, ignoring, or masking behavior;

[0036] Control function verification: Verify the correctness of pause and resume, single-step execution, and abstract instruction execution;

[0037] Unauthorized access verification: Verifies the correctness of error responses in scenarios involving illegal addresses and unauthorized access.

[0038] State consistency verification: Verify that the state remains stable and there are no abnormal jumps after the register access is completed.

[0039] Preferably, the end-to-end backtracking in step E includes: tracing external state configuration parameters, APB access sequence, access timing, and state transition triggering conditions.

[0040] A random stimulus verification system for a RISC-V debug module, built on the UVM verification architecture, includes the following functional units:

[0041] The APB random stimulus generation unit is used to generate constrained random register access stimuli based on the APB bus protocol.

[0042] An external state configuration unit is used to independently configure the soft reset state and the processor core state. This unit is completely decoupled from the APB random stimulus generation unit.

[0043] The status management unit is used to maintain the current values ​​of multiple states of the debugging module and the processor core state in real time, and to record the status change trajectory and triggering conditions.

[0044] The register model and permission rules unit is used to maintain the full register list, address mapping, access permissions, write masking rules, and state dependency behavior of the debugging module.

[0045] The APB incentive distribution and scheduling unit is used to synchronously distribute APB random incentives to the device under test and the gold model unit.

[0046] The Gold Model Unit is used to generate expected results for register access, state transitions, and function implementation based on the RISC-V debugging standard specification.

[0047] The multidimensional coverage statistics and targeted completion unit is used to collect full-dimensional coverage data, analyze low-coverage scenarios offline, and generate and drive the execution of targeted completion test cases.

[0048] The comparison, error reporting, and backtracking unit is used to complete a full-dimensional comparison between the actual results of the tested device and the expected results of the gold model, capture errors, and realize full-link error backtracking based on the unique identifier of the transaction.

[0049] Preferably, the closed-loop convergence strategy executed by the multidimensional coverage statistics and targeted completion unit includes:

[0050] a) Perform large-scale regression testing, issue APB random incentives, and automatically collect full-dimensional coverage data;

[0051] b) Perform offline coverage analysis to accurately identify scenarios with low or no coverage.

[0052] c) Generate dedicated targeted use cases for low coverage state combinations, including processor continuous reset use cases, continuous unauthorized use cases, and continuous exception triggering use cases;

[0053] d) Run targeted completion test cases, merge the coverage of random incentives with the coverage of targeted test cases, and repeat the execution until the coverage of all dimensions reaches 100%.

[0054] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a random stimulus verification method for a RISC-V debug module as described in any one of claims 1 to 6.

[0055] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the random stimulus verification method of the RISC-V debug module as described in any one of claims 1 to 6.

[0056] The beneficial effects of this invention are as follows:

[0057] 1. Significantly Improved Verification Efficiency: This invention specifically selects the APB high-speed bus to replace the low-speed JTAG / CJTAG interface, increasing register access speed by tens of times and solving the industry pain point of excessively long verification times for large-scale random verification. Combined with state-linked random excitation and automated closed-loop convergence strategies, the overall verification efficiency is improved by more than 60%, significantly shortening the chip verification cycle.

[0058] 2. Comprehensive Coverage of Verification Scenarios: This invention categorizes the six states of the debugging module into "externally fixed" and "access-triggered" types. Through a "state-linked random stimulus" strategy, it proactively covers all combinations of externally fixed and access-triggered state transitions, eliminating the state coverage blind spots in traditional blind random verification. This method can reliably discover potential defects in state association, access control, and anomaly handling.

[0059] 3. Efficient and Quantifiable Coverage Convergence: This invention constructs a multi-dimensional coverage model from the basic dimension to the three-dimensional intersection, and adopts a closed-loop strategy of "random traversal + targeted completion". This strategy accurately identifies low-coverage scenarios through offline analysis and generates targeted continuous state test cases (such as continuous reset, continuous CMDerr non-zero) for completion, ensuring that the full-dimensional intersection coverage reaches 100%, meeting the completeness requirements of mass-production chip signing. Compared with the inefficient convergence method of existing technologies that rely solely on irregular random traversal, this invention significantly shortens the time required to achieve completeness verification.

[0060] 4. Accurate and rapid problem localization: The full-link backtracking mechanism proposed in this invention can synchronously trace external state configuration, APB access sequence and state transition trajectory based on the unique identifier of the transaction, which reduces the root cause localization time by more than 80% and significantly improves debugging efficiency.

[0061] 5. High versatility and engineering value: Based on the component-based design of UVM, this invention independently separates and decouples functional units such as APB stimulus generation, external state configuration, and state transition control, making it compatible with various RISC-V debugging modules. It can be directly ported to different chip projects, providing a standardized solution for debugging module verification of RISC-V architecture chips and reducing the cost of repeated development. Attached Figure Description

[0062] Figure 1 This is a flowchart illustrating the random stimulus verification method for the RISC-V debug module of the present invention.

[0063] Figure 2 This is a block diagram of the random stimulus verification system for the RISC-V debug module of the present invention;

[0064] Figure 3 This is a schematic diagram of the dimensional structure of the multidimensional cross-coverage model of the present invention; Detailed Implementation

[0065] To further understand the features, technical means, and specific objectives and functions achieved by the present invention, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0066] This invention is built upon the UVM verification architecture, with its core being a verification strategy of "high-speed access via the APB bus + state-linked random stimulus as the primary method, supplemented by post-regression targeted completion." The overall system consists of two parts: a random stimulus verification method for the RISC-V debug module and a random stimulus verification system for the RISC-V debug module.

[0067] Terminology definition:

[0068] For ease of understanding, the key terms used in this invention are defined as follows:

[0069] Debugging module: In this invention, it refers to the hardware module in the RISC-V architecture processor used for debugging functions, abbreviated as DM.

[0070] Debug module status: includes 6 core statuses, defined as follows:

[0071] Soft reset state (non-active): The debug module is inactive and controlled by an external reset signal;

[0072] Unauthenticated status: The debug module has not been authenticated and access is restricted;

[0073] Processor core states include reset, halted, and running.

[0074] Module access status: The register access status inside the debug module, including idle, APB transaction, JTAG transaction, waiting for response, etc.

[0075] Abstract instruction states: program buffer and abstract instruction execution states, including idle, command writing, instruction execution (busy), instruction completion, instruction error (cmderr), etc.

[0076] Breakpoint / Trigger Status: The configuration and monitoring status of breakpoints and triggers, including not configured, configuring, configured, triggered, monitoring, clearing, etc.

[0077] APB: Advanced Peripheral Bus, a low-power, timing-simple on-chip bus.

[0078] UVM: Universal Verification Methodology.

[0079] I. Random stimulus verification method for RISC-V debug module

[0080] This method includes the following steps:

[0081] Step A: Bus Interface Selection and Verification Framework Construction

[0082] The APB bus was selected as the register access interface for the debug module, and the RISC-V debug module to be verified was connected to the APB bus as the device under test. The APB bus has the characteristics of high speed, low power consumption, and simple timing, which can meet the requirements of efficient injection and simulation of large-scale random stimuli.

[0083] Step B: Independent configuration of external state

[0084] The debug module's soft reset state (non-active) and processor core state (reset / halted / running) can be configured independently via an external interface. This configuration process is completely decoupled from register access operations on the APB bus, ensuring no interference and guaranteeing the stability of the state configuration.

[0085] Step C: Generation and distribution of random stimuli for state linkage

[0086] The debug module receives randomly generated register access stimuli via the APB bus, covering all parameters including random addresses (legal / illegal), random data (valid / invalid), random read / write access, and access timing. Simultaneously, dynamic state transitions of the debug module are actively triggered by APB register write operations, achieving full state coverage. The debug module has six core states: soft reset, unauthorized (not authenticated), system reset (ndmreseton going), abstract command busy, debug active (normal / active), and abstract command execution abnormal (cmderr non-zero). The active triggering rules are as follows:

[0087] a) Setting dmcontrol.authenticated = 0 triggers an unauthorized state;

[0088] b) Write dmcontrol.ndmreset = 1 to trigger the system reset state;

[0089] c) Write a command to issue an abstract instruction, triggering the abstract instruction execution state;

[0090] d) Issuing illegal instructions, unauthorized access, or incorrect addresses triggers an abstract instruction execution exception state.

[0091] Step D: Synchronization of the Golden Model and Generation of Expected Results

[0092] The external state configuration and APB random access stimulus are synchronously input into the gold model, which is built based on the RISC-V debugging standard specification. This gold model generates expected data for register access, state transition trajectories and error response results under each state combination, providing a benchmark for subsequent result comparison.

[0093] Step E: Register permission and function verification under all-state combinations

[0094] Verify the access permissions and functional behavior of all registers in the debug module under each state combination consisting of the processor core states (reset / pause / run) and the six states of the debug module. Verification dimensions include:

[0095] a) Read operation verification: Verify the correctness of the return value being the actual value / 0 / reset value;

[0096] b) Write operation verification: Verify the correctness of the data writing / ignore / masking behavior;

[0097] c) Control function verification: Verify core debugging control functions such as pause / resume, single-step execution, and abstract instructions;

[0098] d) Unauthorized access verification: Verify the correctness of behavior in scenarios such as unauthorized addresses and unauthorized access;

[0099] e) State consistency check: Verify that the state remains stable after the register access is completed.

[0100] Step F: Multidimensional cross-coverage acquisition and quantization convergence

[0101] Construct a comprehensive, multi-level cross-coverage model to achieve a quantitative assessment of validation completeness. The coverage dimensions include:

[0102] a) Basic dimensions: coverage of 6 types of debug module states, coverage of 3 types of processor core states, and full register read / write coverage;

[0103] b) Two-dimensional cross: debug module status × full register read / write operation, processor core status × full register read / write operation;

[0104] c) Three-dimensional cross: debug module status × processor core status × full register read / write operations;

[0105] d) Specific dimensions: coverage of legal / illegal access, coverage of abstract instruction execution and abnormal scenarios.

[0106] Step G: Targeted Completion and Loop Closure Convergence

[0107] A closed-loop strategy of "large-scale regression random incentives + offline coverage analysis + targeted test case completion" is adopted:

[0108] a) Perform large-scale regression tests, issue APB random stimuli, and automatically collect full-dimensional coverage data;

[0109] b) Perform offline coverage analysis to accurately identify scenarios with low or no coverage.

[0110] c) Generate dedicated targeted use cases for low-coverage state combinations, including: processor continuous reset use cases, continuous unauthorized state use cases, continuous exception triggering use cases, etc.

[0111] d) Run targeted completion test cases, merge the coverage of random incentives with the coverage of targeted test cases, and repeat the above process until the coverage of all dimensions reaches 100%.

[0112] Step H: Result Comparison and Error Backtracking

[0113] The actual output of the device under test is compared with the expected result of the golden model in all dimensions and point by point. The comparison includes register data, interface signals, and state transition trajectories. When the comparison is inconsistent, a full-link backtracking is performed based on the unique identifier of the transaction. The backtracking content includes external state configuration parameters, APB access sequence, access timing, and state transition triggering conditions to quickly locate the root cause of the error.

[0114] II. Random stimulus verification system for RISC-V debug module

[0115] This system is built on the UVM verification architecture and consists of the following eight functional units:

[0116] 1. APB Random Excitation Generation Unit: Generates constrained random register access stimuli based on the APB bus protocol, covering all dimensions of random parameters.

[0117] 2. External State Configuration Unit: Independently completes the configuration and input of soft reset state and processor core state, and is completely decoupled from the APB random stimulus generation unit.

[0118] 3. Status Management Unit: Maintains the current values ​​of the 6 types of status of the debugging module and the 3 types of status of the processor core in real time, and monitors and records the status change trajectory and triggering conditions.

[0119] 4. Register Model and Permission Rules Unit: Maintains the full register list, address mapping, access permissions, write masking rules, and state-dependent behaviors of the debugging module.

[0120] 5. APB stimulus distribution and scheduling unit: synchronously distributes APB random stimuli to the device under test and the gold model unit to ensure that the stimulus input timing is completely consistent.

[0121] 6. Golden Model Unit: Based on the RISC-V debugging standard, it generates the expected results of register access, state transition, and function implementation after receiving stimulus.

[0122] 7. Multidimensional Coverage Statistics and Targeted Completion Unit: Collects full-dimensional coverage data, analyzes low-coverage scenarios offline, generates targeted completion test cases and drives execution to achieve 100% coverage convergence.

[0123] 8. Comparison, Error Reporting and Backtracking Unit: Completes a full-dimensional comparison between the actual results of the tested device and the expected results of the gold model, captures errors and triggers error reporting, and realizes full-link error backtracking and root cause location based on the unique identifier of the transaction.

[0124] In the above method, steps A to F constitute the forward channel of "stimulus generation → state coverage → verification → analysis", and step G constitutes the reverse feedback channel of "low coverage identification → targeted completion → regression verification". The forward channel mainly uses random stimuli to achieve broad coverage, while the reverse channel mainly uses targeted use cases to achieve deep completion. The two form a closed-loop iteration until convergence.

[0125] This embodiment uses a processor debugging module based on the RISC-V architecture as the verification object. The verification environment is built on the UVM architecture and uses the APB bus as the high-speed access interface for registers.

[0126] I. Setting up the implementation environment

[0127] 1. Core Architecture: The verification platform is built based on the UVM standard architecture and includes functional modules such as the APB bus functional model (BFM), external state configuration unit, state management unit, golden model unit, multi-dimensional coverage statistics unit, and comparison and backtracking unit. All units adopt a component-based design.

[0128] 2. Test Device (DUT): RISC-V debug module, which supports a configurable number of processor cores (configured to 4 cores in this embodiment).

[0129] 3. Interface Configuration: The register access interface is the APB bus with a clock frequency of 100MHz; an independent external status input interface is set for configuring the soft reset state and the processor core running / paused / reset state; the debug function interface includes pause / resume, single-step execution and other function outputs.

[0130] 4. Construction of the Golden Model: The Golden Model unit is implemented in SystemVerilog based on the RISC-V Debug Specification (RISC-V Debug Specification 0.13 or 1.0) and accurately models all register behaviors, state transition conditions, permission rules and functional behaviors defined in the specification.

[0131] 5. Verification Toolchain: Verification code is written using SystemVerilog hardware description language; Synopsys VCS tools are used for simulation compilation, execution, and coverage data acquisition; Verdi tools are used for waveform viewing, online debugging, and transaction tracing; and the coverage analysis function built into VCS is used for offline report generation.

[0132] II. Implementation Core Steps

[0133] Step 1: Configure DUT and Environment Parameters

[0134] Instantiate the RISC-V debug module at the UVM top level and set the total number of processor cores to 4 through configuration parameters. Configure the APB bus clock frequency to 100MHz.

[0135] Step 2: Independent configuration of external state

[0136] The processor core states (reset / halted / running) and soft reset states (non-active) are randomly configured through an external state configuration unit. In this embodiment, a constrained randomization method is used: in the processor core states, reset accounts for 20%, halted for 30%, and running for 50%. All state configurations are directly input to the DUT through independent signal ports, and are completely decoupled from register read / write operations on the APB bus in terms of timing, without affecting each other.

[0137] Step 3: APB Random Excitation Generation and Distribution

[0138] The APB bus functional model generates full-dimensional random register access stimuli according to constraints:

[0139] a) Address constraints: The effective address width is 7 bits. [31:9] and [1:0] are fixed to 0. The legal addresses [8:2] are DM register addresses defined in the RISC-V debugging specification, such as 0x10 and 0x11. The rest are illegal addresses, accounting for 20%.

[0140] b) Read / write constraints: Read operations account for 50%, and write operations account for 50%;

[0141] c) Data constraints: Boundary values ​​(all 0s, all 1s, etc.) account for 10%, and regular random values ​​account for 90%. For control registers, further constraints are required based on their functions. For example, the legal values ​​for the command register [31:24] are 0, 1, and 2, and the rest are illegal values.

[0142] d) Timing constraints: back-to-back transmission, random idle period insertion, etc.

[0143] Step 4: Precise Triggering and Monitoring of State Transitions

[0144] Dynamic state transitions in the debug module are triggered by write operations to the APB register. The core triggering rules are as follows:

[0145] a) Setting dmcontrol.authenticated = 0 triggers an unauthorized state;

[0146] b) Write dmcontrol.ndmreset = 1 to trigger the system reset state;

[0147] c) Write commands to issue abstract instructions (such as commands to access processor core registers), trigger the execution status of abstract instructions, and monitor their busy signals;

[0148] d) Issuing an illegal abstract instruction or unauthorized access triggers an abnormal state in the execution of the abstract instruction (cmderr is non-zero).

[0149] The status management unit monitors the transition trajectory of the six types of debugging module states in real time. Each state transition records the triggering conditions, transition time, and duration, and stores them in the transaction database.

[0150] Step 5: Functional verification under all-state combinations

[0151] In each state combination (6 states for the debug module × 3 states for the processor core = 18 main combinations), read and write operations are performed on all registers of the debug module, and the expected results are compared using the Golden Model Unit. In this embodiment, approximately 2 million random register access operations are performed.

[0152] Step 6: Coverage Convergence and Targeted Completion

[0153] a) Large-scale regression testing: Automated regression testing with random stimuli was run continuously for 72 hours, automatically collecting functional and code coverage data. After the first regression test, the three-dimensional cross-coverage (debug module state × processor core state × full register access operations) reached approximately 67%.

[0154] b) Low Coverage Point Analysis: Analyze coverage reports to accurately identify uncovered state combinations. This embodiment identifies the following low coverage scenarios:

[0155] • Combining {processor state = reset, debug module state = abstract command busy, operation = write register}, coverage is 0%;

[0156] • Combining {processor state = halted, debug module state = cmderr non-zero, operation = read register}, coverage is 12%;

[0157] • Combine {processor state = running, debug module state = not authenticated, operation = write register}, coverage 8%.

[0158] c) Targeted Completion Verification: Dedicated targeted test cases are generated for low-coverage points. The specific generation logic is as follows: extract the uncovered {state, register, operation} triples, generate the register write sequence required to reach that state according to the state transition path, and then execute the target operation in that state. This embodiment generates the following three types of targeted test cases:

[0159] • Use case of continuous execution of abstract instructions: Write a command to execute an abstract instruction, backpressure the return of the abstract instruction result, keep busy high, and randomly access the registers of the debug module;

[0160] • Persistent Unauthorized State Use Case: Persistently maintain the debug module in an unauthorized state (after writing dmcontrol.authenticated=0, the constraint cannot be written to dmcontrol.authenticated=1), and perform various register accesses;

[0161] • Continuous exception triggering use case: Issue an illegal abstract instruction, triggering the cmderr non-zero state to not be cleared, and perform register access in this state.

[0162] d) Convergence and Loop Closure: After running the targeted completion test cases, the coverage of random incentives and the coverage of targeted test cases are merged. In this embodiment, a total of 4 rounds of "regression + targeted completion" iterations were executed, with a total running time of approximately 120 hours. Finally, the three-dimensional cross coverage reached 100%, and the full-dimensional coverage achieved 100% convergence.

[0163] Step 7: Result Comparison and Error Location

[0164] The actual results of the DUT, including register values, register reads, state transition signals, functional responses, and exceptions, are compared with the expected results of the Golden Model across all dimensions. The comparison strategy is as follows: comparison is performed immediately after each transaction (one APB access), and non-blocking background comparison is performed in parallel in two modes.

[0165] When discrepancies occur, the system traces back the external state configuration value associated with the transaction, the five transactions before and after the APB access sequence, and the state transition trajectory (the 10 most recent state transition records) based on the transaction's unique identifier to quickly pinpoint the root cause of the error. This embodiment identified and fixed 12 core defects, including state transition deadlocks, read / write access control vulnerabilities, multi-state arbitration logic flaws, and anomaly cleanup failures.

[0166] Table 1: Typical Cases of Anomaly Detection

[0167] Unauthorized write {DM status = Unauthorized, Core status = Running} Write control register dmcontrol Write operations are masked, register values ​​remain unchanged. The write operation was successful, and the register value was modified. The authentication signal is not enabled due to the permission check logic. deadlock {DM state = Abstract instruction execution in progress, Core state = halted} Issue new abstract instructions Returns a busy error response, and the status remains unchanged. The DUT is unresponsive and stuck in the busy state. The state machine did not handle the new request correctly in the busy state. Abnormal cleanup failed {DM state = Abstract Instruction Execution Exception State, Core state = Running} Write cmderr to clear bits Clear the cmderr bit to zero and restore the state. The cmderr bit remains 1, and the state has not been restored. The clear logic is not properly connected to the state machine.

[0168] The implementation results of this invention in the verification of RISC-V debug modules are as follows:

[0169] 1. Comprehensive coverage: Achieves 100% coverage of all 6 states, all registers, and all operation types of the debugging module, while also covering all configuration combinations of single-core and multi-core (2-core, 4-core, 6-core) systems, with no blind spots in any verification scenarios.

[0170] 2. Functional correctness assurance: Through full-scenario verification, 12 types of core defects are accurately captured and repaired to ensure that all functions of the debugging module fully comply with the RISC-V debugging standard specifications.

[0171] 3. Significantly improved verification efficiency: The stimulus injection efficiency of the APB bus at a clock frequency of 100MHz is more than 100 times higher than that of the traditional JTAG (approximately 10MHz). The UVM modular architecture and the constraint-randomized coverage convergence strategy reduce the overall verification cycle from an average of 6 months in the traditional method to 3 months, a reduction of 50%.

[0172] Table 2: Comparison of APB and JTAG single register access times

[0173] APB 100 10 2 20 JTAG 25 (≤ APB / 4) 40 50 2000

[0174] Conclusion: Under these conditions, the APB bus provides more than 100 times the stimulus injection efficiency of JTAG.

[0175] 4. High reusability of the verification environment: The verification platform supports multi-core configurations, and all functional units are modularly designed. This environment has been successfully ported to three different RISC-V processor projects (including embedded MCU, AI, and industrial control projects), with an average porting workload of no more than two person-weeks.

[0176] 5. Meet mass production approval requirements: Achieve 100% coverage across all dimensions and a rigorous defect discovery-repair-closed-loop process, verifying completeness and robustness to meet the approval standards for chip mass production tape-out.

[0177] The performance data is based on a comparison with traditional JTAG interface (10MHz clock frequency) and blind random excitation method.

[0178] The random stimulus verification method and system for RISC-V debug modules provided by this invention can be applied to the design verification stage of various processor chips based on the RISC-V architecture (including but not limited to IoT chips, AI acceleration chips, industrial control chips, mobile processors, etc.), and has clear industrial applicability.

[0179] This invention selects the APB bus as the high-speed access interface for the debug module. Through a random stimulus strategy that actively and randomly switches the debug module state during register access, combined with a closed-loop convergence mechanism of regression coverage analysis and targeted test case completion, it achieves full coverage verification of all registers' legal and illegal accesses in all states of the debug module, ultimately improving the completeness, efficiency, and robustness of RISC-V debug module verification.

[0180] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A random stimulus verification method for a RISC-V debug module, characterized in that, Includes the following steps: Step A: Select the APB bus as the register access interface, build a verification environment, and connect the RISC-V debug module to be verified as the device under test to the APB bus. Step B: Configure the soft reset state and processor core state of the debug module independently through an external interface. This configuration process is completely decoupled from register access operations on the APB bus. Step C: Send a constraint-generated random register access stimulus to the debug module via the APB bus, and actively trigger the dynamic state transition of the debug module through APB register write operations to achieve full state coverage of the debug module; Step D: Synchronously input the external state configuration and APB random access stimulus into the gold model, and generate the expected results for each state combination based on the RISC-V debugging standard specification; Step E: Under each state combination consisting of the soft reset state, processor core state, and debug module state, verify the access permissions, functional behavior, and abnormal responses of all registers of the debug module, and compare the actual output of the device under test with the expected results of the golden model. If the comparison is inconsistent, perform full-link backtracking based on the unique transaction identifier. Step F: Collect and analyze multi-dimensional cross-coverage data, wherein the coverage data includes at least a three-dimensional cross-combination of debug module status, processor core status, and register read / write operations; Step G: For uncovered or low-coverage state combinations, generate and execute targeted persistent state use cases. Repeat steps B to F until full-dimensional coverage reaches 100%.

2. The method according to claim 1, characterized in that, The rules for actively triggering the dynamic transition of the debug module state through APB register write operations in step D include: Writing the authentication bit of the debug module control register to 0 triggers an unauthorized state; Write the system reset bit of the debug module control register to 1 to trigger the system reset state. Write the debug module control register to issue abstract instructions, triggering the abstract instruction execution state; Issuing illegal commands, unauthorized access, or incorrect addresses can trigger an abnormal state in the execution of abstract commands.

3. The method according to claim 1, characterized in that, The multidimensional cross-coverage model in step F includes: Basic dimensions: coverage of 6 core states of the debug module, coverage of 3 states of the processor core, and full register read / write coverage. The 6 core states of the debug module are: soft reset state, unauthorized state, system reset state, abstract instruction execution state, debug active state, and abstract instruction execution abnormal state. Two-dimensional crossover: crossover coverage of debug module status and register read / write operations, and crossover coverage of processor core status and register read / write operations; 3D cross-coverage: the 3D cross-coverage of debug module status, processor core status, and register read / write operations; Specific dimensions: cross-coverage of legal and illegal access, and coverage of abstract instruction execution and abnormal scenarios.

4. The method according to claim 1, characterized in that, The strategy for generating directed persistent state use cases in step G includes: When the processor reset state combination coverage is lower than a preset threshold, a processor continuous reset test case is generated. When the coverage of abnormal state combinations in the execution of abstract instructions in the debugging module is lower than a preset threshold, a continuous exception trigger test case is generated. When the coverage of unauthorized state combinations in the debug module is lower than a preset threshold, a persistent unauthorized state test case is generated.

5. The method according to claim 1, characterized in that, The verification of register access permissions and functional behavior in step E includes: Read operation verification: Verify that the return value is the correctness of the actual value, 0, or reset value; Write operation validation: Verifies the correctness of data writing, ignoring, or masking behavior; Control function verification: Verify the correctness of pause and resume, single-step execution, and abstract instruction execution; Unauthorized access verification: Verifies the correctness of error responses in scenarios involving illegal addresses and unauthorized access. State consistency verification: Verify that the state remains stable and there are no abnormal jumps after the register access is completed.

6. The method according to claim 1, characterized in that, The full-link backtracking in step E includes: tracing external state configuration parameters, APB access sequence, access timing, and state transition triggering conditions.

7. A random stimulus verification system for a RISC-V debug module, characterized in that, Built on the UVM verification architecture, it includes the following functional units: The APB random stimulus generation unit is used to generate constrained random register access stimuli based on the APB bus protocol. An external state configuration unit is used to independently configure the soft reset state and the processor core state. This unit is completely decoupled from the APB random stimulus generation unit. The status management unit is used to maintain the current values ​​of multiple states of the debugging module and the processor core state in real time, and to record the status change trajectory and triggering conditions. The register model and permission rules unit is used to maintain the full register list, address mapping, access permissions, write masking rules, and state dependency behavior of the debugging module. The APB incentive distribution and scheduling unit is used to synchronously distribute APB random incentives to the device under test and the gold model unit. The Gold Model Unit is used to generate expected results for register access, state transitions, and function implementation based on the RISC-V debugging standard specification. The multidimensional coverage statistics and targeted completion unit is used to collect full-dimensional coverage data, analyze low-coverage scenarios offline, and generate and drive the execution of targeted completion test cases. The comparison, error reporting, and backtracking unit is used to complete a full-dimensional comparison between the actual results of the tested device and the expected results of the gold model, capture errors, and realize full-link error backtracking based on the unique identifier of the transaction.

8. The system according to claim 7, characterized in that, The closed-loop convergence strategy executed by the multidimensional coverage statistics and targeted completion unit includes: a) Perform large-scale regression testing, issue APB random incentives, and automatically collect full-dimensional coverage data; b) Perform offline coverage analysis to accurately identify scenarios with low or no coverage. c) Generate dedicated targeted use cases for low coverage state combinations, including processor continuous reset use cases, continuous unauthorized use cases, and continuous exception triggering use cases; d) Run targeted completion test cases, merge the coverage of random incentives with the coverage of targeted test cases, and repeat the execution until the coverage of all dimensions converges to 100%.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the random stimulus verification method of the RISC-V debug module as described in any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the random stimulus verification method of the RISC-V debug module as described in any one of claims 1 to 6.

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